ARM-THE WORLD’S MOST POPULAR

MICROCONTROLLER –ARCHITECTURE
AND ASSEMBLY LANGUAGE
PROGRAMMING
 History of the ARM Processor

 ARM stands for ‘Advanced RISC Machine’.

 The first ARM processor actually was meant to be
the ‘Acorn RISC Machine’ as it was manufactured
by Acorn Computers Ltd., Cambridge, England, in
1985. ARM1
 ARM2 in 1987 commercially available.
 ARM2, ….., ARM 7
 ARM8, ARM9, …, ARM11
 CORTEX
 The ARM Core

 What is meant by the ‘core’?

 The core is the ‘processing unit’ or the ‘computing
engine’.

 It has all the computing power, and this aspect is

decided by the architecture, which represents the
basic design of the processor.
 The ARM Microcontroller

 It is ARM core with peripherals added to it.

 THE RISC ARCHITECTURE

 These apply to most of the instructions of ARM, but

not necessarily to all.
 i) Instructions are of the same size, that is, 32 bits
 ii) Instructions are executed in one cycle
 iii) Only the load and store instructions access
memory
 Advanced Features

 Thumb
 MMU and MPU
 Cache
 Debug interface
 Embedded ICE macrocell
 Fast muliplier
 Enhanced instructions
 Jazelle DBX (Direct Bytecode eXecution)
 Vector floating point unit
 Synthesizable
Early naming convention for ARM
Features of the architecture variants of ARM
 Features of ARM which make it special

 Data bus width

 Computational capability
 Low Power
 Pipelining
 Multiple Register instructions
 DSP Enhancements
 ARM Architecture

OPERATING MODES OF ARM

Register Set
Register in the user mode
CPSR
INTERRUPT VECTOR TABLE
 Programming the ARM processor

 Can be done in Assembly or C

 We use the Keil RVDK for programming and
simulation
Data Processing Unit
Data Alignment

Memory bank
Data Alignment
Assembly Language Programming
Instruction Set
 Data Processing Instructions

ARM is a RISC processor, one of the features of which is that it performs

computations, on data which are in registers only.

MOV and MVN-Examples

Shift and Rotate

Ex ROL :
32-n,
32-4=28
Combining MOV and Shift
 Conditional Execution

MOV R3, R5, LSL #3, there is a logical operation involved, that is, the left
shift operation.

MOVS R3, R5, LSL #3, this is executed, and find the N and C flags to
be set.
Arithmetic Instructions
Logical Instructions
 Compare Instructions

Flag settings after a compare instructions

Multiplication
 Assembly Language Programming

There are two items used therein—instructions and directives.

Directives –AREA, ENTRY and END -Examples

Anything written after the END directive will be ignored by the assembler.
General Structure of an assembly Language Line

Some points to keep in mind are listed as follows:

i. Instructions, pseudo-instructions and directives must be
preceded by a white space, such as a space or a tab, even if
there is no label.
ii. Instruction mnemonics and register names can be written in
uppercase or lowercase, but not mixed.
iii.Labels are symbols that represent addresses. The address
given by a label is calculated during assembly.
 Directives for Defining data

Data which is used in a program can be bytes or words or half words.

The EQU directive -Examples

EQU is used to equate a numeric constant to a label. The constant may be data
or address. Examples are as follows:
Constants allowed
 The RN directive-for naming registers

Suppose we need to use R0 for loading the value of X, and R1 for

loading Y, we use the directive RN as follows:
 Assembly Programs

Solution
Branch Instructions
Branch instruction usage -examples
 Subroutines/Procedures –using the Link register

 There is a form of the branch instruction which is BL

standing for
‘Branch and Link’.
 When a BL instruction is encountered, the PC value
is changed to that of the target, but the old PC value
is copied to the LR register.
 At the end of the procedure, the LR value can be
copied back to the PC.
Solution
Load and Store Instructions
Solution
Solution
 Indexed Addressing modes

 Pre-indexed
 Post-indexed
Pre-indexed Addressing

Observe the instruction LDR R0, [R7, #4].

 Here R7 is the base register and the effective address is R7 + 4.

 The data at this effective address is copied to R7.

Next, see the instruction STR R1, [R5, R6, LSL #2].

 The effective address = R5 +R6 left shifted twice.

Post-indexed Addressing
The effective address calculation is done after the execution of the specific
instruction has been done.

The instruction LDR R0, [R4], #4

 Here the data pointed by the content of R4 is first copied to R0.

 After that, the content of R4 is changed to R4 + 4.

 Readonly and Read/Write Memory

 The two memory areas defined by the compiler are

‘Readonly’ for code, and ‘Read/write’ for data.
 Usually this corresponds to ROM and RAM in a
physical system.
 RAM is used for intermediate results, for temporary
storage, etc., as this is volatile memory.
 In the readonly memory, data is written using
directives like DCD, DCW, etc.
 From there, it is copied to readwrite memory using
load and store instructions.
Multiple Register Load and Store

The LDM instruction

Operations on the base register
Using LDM and STM
 Stacks

 Maybe LIFO or FIFO

 Maybe ascending or descending
 Maybe Empty/Full
 Only PUSH and POP are defined as operations
 ARM uses LDM and STM instructions for stack
operations
 The stack pointer (SP) is used to access the stack top