8086sys.

txt
Instruction set of the 8086/8088 in systematical order
source: mcs-86 product description, Intel corporation, June 1978
AMD, MOS microprocessors and peripherals 1983 data book (for 186,286)
19880607/wjvg

100010dw mmregr/m MOV reg/mem to/from reg

1100011w mm000r/m MOV imm to reg/mem
1011wreg datadata dataifw1 MOV imm to reg
1010000w addr-low addrhigh MOV mem to acc
1010001w addr-low addrhigh MOV acc to mem
10001110 mm0srr/m MOV reg/mem to seg reg
10001100 mm0srr/m MOV seg reg to reg/mem

11111111 mm110r/m PUSH reg/mem

01010reg PUSH reg
000sr110 PUSH seg reg
011010s0 datadata dataifs0 PUSH imm (186)
01100000 PUSHA (186, push all)

10001111 mm110r/m POP reg/mem

01011reg POP reg
000sr111 POP seg reg
01100001 POPA (186, pop all)

1000011w mmregr/m XCHG reg/mem with reg

10010reg XCHG reg with acc

1110010w portport IN/INW to AL/AX from fixed port

1110110w IN/INW to AL/AX from variable port

1110011w portport OUT/OUTW to AL/AX to fixed port

1110111w OUT/OUTW to AL/AX to variable port

11010111 XLAT (xlate byte to AL)

10001101 mmregr/m LEA
11000101 mmregr/m LDS
11000100 mmregr/m LES
10011111 LAHF
10011110 SAHF
10011100 PUSHF
10011101 POPF

000000dw mmregr/m ADD reg/mem with reg to either

100000sw mm000r/m datadata dataif01 ADD imm to reg/mem
0000010w datadata dataifw1 ADD imm to acc

000100dw mmregr/m ADC reg/mem with reg to either

100000sw mm010r/m datadata dataif01 ADC imm to reg/mem
0001010w datadata dataifw1 ADC imm to acc

001010dw mmregr/m SUB reg/mem with reg to either

100000sw mm101r/m datadata dataif01 SUB imm from reg/mem
0010110w datadata dataifw1 SUB imm from acc

000110dw mmregr/m SBB reg/mem with reg to either

100000sw mm011r/m datadata dataif01 SBB imm from reg/mem
0001110w datadata dataifw1 SBB imm from acc

001110dw mmregr/m CMP reg/mem and reg

100000sw mm111r/m datadata dataif01 CMP imm with reg/mem
0011110w datadata dataifw1 CMP imm with acc

1111111w mm000r/m INC reg/mem

01000reg INC reg

1111111w mm001r/m DEC reg/mem

01001reg DEC reg

1111011w mm011r/m NEG

00110111 AAA
00100111 DAA
00111111 AAS
00101111 DAS

1111011w mm100r/m MUL

1111011w mm101r/m IMUL reg/mem
011010s1 mmregr/m datadata dataifs0 IMUL imm (186)

1111011w mm110r/m DIV reg/mem

1111011w mm111r/m IDIV reg/mem

11010100 00001010 AAM

11010101 00001010 AAD
10011000 CBW
10011001 CWD

110100vw mm000r/m ROL reg/mem

110100vw mm001r/m ROR reg/mem
110100vw mm010r/m RCL reg/mem
110100vw mm011r/m RCR reg/mem
110100vw mm100r/m SHL/SAL reg/mem
110100vw mm101r/m SHR reg/mem
110100vw mm111r/m SAR reg/mem

1100000w mm000r/m datadata ROL reg/mem by count (186)

1100000w mm001r/m datadata ROR reg/mem by count (186)
1100000w mm010r/m datadata RCL reg/mem by count (186)
1100000w mm011r/m datadata RCL reg/mem by count (186)
1100000w mm100r/m datadata SHL/SAL reg/mem by count (186)
1100000w mm101r/m datadata SHR reg/mem by count (186)
1100000w mm111r/m datadata SAR reg/mem by count (186)

001000dw mmregr/m AND reg/mem and reg to either

1000000w mm100r/m datadata dataif01 AND imm to reg/mem
0010010w datadata dataifw1 AND imm to acc

100001dw mmregr/m TEST reg/mem and reg to either

1111011w mm000r/m datadata dataif01 TEST imm and reg/mem
1010100w datadata dataifw1 TEST imm and acc

000010dw mmregr/m OR reg/mem and reg to either

1000000w mm001r/m datadata dataif01 OR imm to reg/mem
0000110w datadata dataifw1 OR imm to acc

001100dw mmregr/m XOR reg/mem and reg to either

1000000w mm110r/m datadata dataif01 XOR imm to reg/mem
0011010w datadata dataifw1 XOR imm to acc

1111011w mm010r/m NOT

1111001z REP (z for CMP and SCA)

1010010w MOVW/MOVB
1010011w CMPW/CMPB
1010111w SCAW/SCAB
1010110w LODW/LODB
1010101w STOW/STOB
0110110w INW/INB DX (186)
0110111w OUTW/OUTB DX (186)

11101000 disp-low disphigh CALL direct within segment

11111111 mm010r/m CALL indirect within segment
10011010 offslo offshi seglo seghi CALL direct intersegment
11111111 mm011r/m CALL indirect intersegment

11101001 disp-low disphigh JMP direct within segment

11101011 dispdisp JMP direct within segment short
11111111 mm100r/m JMP indirect within segment
11101010 offslo offshi seglo seghi JMP direct intersegment
11111111 mm101r/m JMP indirect intersegment

11000011 RET within segment

11000010 data-low datahigh RET within segment adding imm to sp
11001011 RET intersegment
11001010 data-low datahigh RET intersegment adding imm to sp

01110100 dispdisp JE/JZ

01111100 dispdisp JL/JNGE
01111110 dispdisp JLE/JNG
01110010 dispdisp JB/JNAE
01110110 dispdisp JBE/JNA
01111010 dispdisp JP/JPE
01110000 dispdisp JO
01111000 dispdisp JS
01110101 dispdisp JNE/JNZ
01111101 dispdisp JNL/JGE
01111111 dispdisp JNLE/JG
01110011 dispdisp JNB/JAE
01110111 dispdisp JNBE/JA
01111011 dispdisp JNP/JPO
01110001 dispdisp JNO
01111001 dispdisp JNS

11100010 dispdisp LOOP

11100001 dispdisp LOOPZ/LOOPE
11100000 dispdisp LOOPNZ/LOOPNE
11100011 dispdisp JCXZ

11001000 data_low datahigh llllllll ENTER (186)

11001001 LEAVE (186)

11001101 typetype INT with type specified

11001100 INT with type 3
11001110 INTO
11001111 IRET

01100010 mmregrm BOUND reg,reg/mem (286)

11111000 CLC
11110101 CMC
11111001 STC
11111100 CLD
11111101 STD
11111010 CLI
11111011 STI
11110100 HLT
10011011 WAIT
11011xxx mmxxxr/m ESC
11110000 LOCK

001sr110 SEGMENT override prefix

00001111 00000000 mm000r/m SLDT st lo desc tabl reg (286)

00001111 00000000 mm001r/m STR st task reg (286)
00001111 00000000 mm010r/m LLDT ld lo desc tabl reg (286)
00001111 00000000 mm011r/m LTR ld task reg (286)

00001111 00000000 mm100r/m VERR verify read acc (286)

00001111 00000000 mm101r/m VERW verify write acc (286)

00001111 00000001 mm000r/m SGDT st gl desc tabl reg (286)

00001111 00000001 mm001r/m SIDT st int desc tabl reg (286)
00001111 00000001 mm010r/m LGDT ld gl desc tabl reg (286)
00001111 00000001 mm011r/m LIDT ld int desc tabl reg (286)

00001111 00000001 mm100r/m SMSW st mach stat word (286)

00001111 00000001 mm110r/m LMSW ld mach stat word (286)

00001111 00000010 mmregr/m LAR ld acc rights (286)

00001111 00000011 mmregr/m LSL ld segm lim (286)
00001111 01100011 mmregr/m ARPL adj req priv lev (286)

d:
0 from
1 to

w:
0 byte
1 word

mm:
00 disp=0, except if r/m=110 then ea=disphigh:disp-low
01 disp=disp-low sign extended to 16 bits
10 disp=disphigh:disp-low
11 r/m is reg field

r/m:
000 ea=BX+SI+disp
001 ea=BX+DI+disp
010 ea=BP+SI+disp
011 ea=BP+DI+disp
100 ea=SI+disp
101 ea=DI+disp
110 ea=BP+disp, except if mm=00 then ea=disphigh:disp-low
111 ea=BX+disp

sw:
01 16 bits of imm data form the operand
11 an imm data byte is sign extended to form the 16-bit operand

v:
0 count=0
1 count in CL

x don't care
z is used for string primitives for comparison with zf flag

w reg:
0 000 AL
0 001 CL
0 010 DL
0 011 BL
0 100 AH
0 101 CH
0 110 DH
0 111 BH

1 000 AX
1 001 CX
1 010 DX
1 011 BX
1 100 SP
1 101 BP
1 110 SI
1 111 DI

sr:
00 ES
01 CS
10 SS
11 DS

flags = -:-:-:-:OF:DF:IF:TF:SF:ZF:-:AF:-:PF:-:CF

From: Jaap van Ganswijk <ganswijk@xs4all.nl>

To: Herve Marechal <marechal@limsi.fr>
Subject: Re: About microprocessor

At 11:27 AM 5/20/96 +0200, you wrote:

>Hello,
>Please, could you tell me where I can get complete info about the
>instruction set of i386 processor ? (mnemonics, and opcodes). I don't
>care if it's 486, pentium or newer.
>But I do want both names and hexadecimal codes of instructions.
>Thank you very much, I've spent an hour without finding!

Have you found:

../chipdir/iset/

It has the 8086 instruction set. The 386 instruction set is based on this
one with a prefix byte of 0x66 to change the operand size to 32 bits
and 0x67 to change the addressing size to 32 bits.
When you use 32 bits addressing, the coding of the addressing modes
changes...

There are PDF's of the Pentium databook on the Intel CD-ROM

called 'Intel Architecture Labs'.
See '../chipdir/ext/cdrom.html', to get this free CD-ROM.
Or look at the Intel-site for this CD-ROM or the PDF's...

Perhaps it's better to buy a regular databook however...

(Available in book stores or from Intel distributors.)

I think, there is also an overiew of the instruction set in Denmark at:

http://www.imada.ou.dk/~jews/PInfo/intel.html - Processor Information: Intel