5 4 3 2 1

RokuTV Athens South America

Block Diagram

D D

C C

B B

A A

Athens - CH Design
Title
Block Diagram
Size Document Number Rev
B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 1 of 26

5 4 3 2 1
 5 4 3 2 1

UT02 (Page 23) TUNER_3V3

+12V_Panel
D
Vout = 3.3V (250mA) D
UL01(Page 16) Iout = 300mA
SOC_PANEL_ON PMOS LDO
JY4953 CW1117CB-3.3V
+1.0_VDDC_CPU
+12V_STANDBY +5V_Normal
UE05 (Page 5) (600mA)
Vout = 1.0V
+12V_PWR UE01 (Page 4) Iout = 2A
CONE1(Page 4) Vin = 12V DC-DC
12V Main Power (3.6A) EN PG PGOOD to RESET Circuit
Power Board EN Vout = 5.22V TMI3411P
Iout = 4A
AMP_12V0 DC-DC UE06 (Page 5)
TMI3244T Vout = 1.0V +1.0V_VDDC
Iout = 4A PG
(3.17A)
EN DC-DC
MP2147
C
UA01 (Page 20) +5V_USB
C

AD82088 UU01 (Page17)

Audio AMP Pwr Dist (1.5A)
2 x 10W USB_EN Switch, 1.5A
SY6288C3AAC

B
UE02 (Page 4) +3.3V_Standby
B

Vin = 12V UE03 (Page 6)

Vout = 3.32V +3.3V_Standby Vout = 1.51V PG +1.5V_DDR
Iout = 3A Iout = 2A
DC-DC (2.4A) DC-DC
TMI3253T TMI3411P (1.35A)

CONU1 (Page 24)

Enabled in Suspend Mode WiFi Module
1.1A max UE04 (Page 6)
MOD_VTERM
25mA Suspend (OPTIONAL)
1.2V
+3.3V_Normal 100mA
LDO
SOC_PS_ON
QE01(Page 4) (600mA) (100mA) AZ1117CH-1.2TRG1
PMOS
A JY3415E or SI3415 A
EN
CH CONFIDENTIAL
Title
Power Tree
Size Document Number Rev
B 00294345 4
Power-On sequence diagram and timing requirements shown on Sheet 6
Date: Monday, August 02, 2021 Sheet 2 of 26

5 4 3 2 1
 5 4 3 2 1

+3.3V_Standby +3.3V_Standby
+3.3V_Standby

+3.3V_Standby RS01 RS02

4.7K 10K RS03
10K
US01
High Active Reset Out

2
3 2
2.2K RS04 1 MMBT3906LT1 VDD RESETn NC/0 RS05
D 13 RST_INHn QS01 SOC_RESET 13 D

Inhibit Reset from power regulators during Suspend 1

3
GND QS02
APS803S-29 or SGM803B-SXN3LG
4.7K RS17
MMBT3904
SOC_RESET requirement
RS06
100 Open Drain Required 5ms high after all power stable.

VDDC_CPU or VDDC
Populate if
can cause RESET U1 is an
Active Low
5 10K RS07 reset out.
VDDCPU_PGOOD
TLV803S

5 10K RS08 CS01

VDDC_PGOOD
0.1uF/10V
SOC_RESET requirement Low Active Reset In/Out
VDDC 2ms after 1.5V stable. SOC_RESETn 13
C C
CS02
0.1uF/16V
RS09
+3.3V_Standby 100

RS10
4.7K
Reset_key CS03
1uF/10V
33 RS11 Raw Reset Button to SoC
Reset Button
SW can cause RESET
1

2 2
DM13 DM11 CS04 33 RS12
RST_BTNn 13
KEY4 KEY3 TT0541SB 0.1uF/16V
NC/Power Power

4 3 5 NC/TT0541SB
1

4 3 5

Reserve NA +3.3V_Standby
B B

RS13
4.7K
Reset Latch State/Clear
13 33 RS14
RST_BTNn_LATCH
CS05
0.01uF/50V RS15
2

RST_BTNn_LATCH 4.7K
0 = RST_BTN DS01
1 = AC PWR ON/Internal Reset 1N4148W
1
2

MMBT3906LT1 1
QS03
3

QS04
MMBT3904
A A
RS16
4.7K
Athens - CH Design
Title
System RESET
Size Document Number Rev
B 00294345 4

Date: Tuesday, August 03, 2021 Sheet 3 of 26

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 5 4 3 2 1

Main Power Input 12V VCC12V = High Current Supply

Normal 3.3V Power
WIDE TRACES +3.3V_Standby

D
+3.3V_Normal
QE01
CONE1
PS_ON PS_ON S D
1 16 15 BL_PDIM 1 BL-ADJUST
14 16 15 13 BKL_EN 1
14 13 BL-ON/OFF CE03 G CE04
12
12 11
11 Feedback to Main supply to indicate 0.1uF/16V RE02 CE06 JY3415E or SI3415-TP
10 9 0.022uF/50V

G
D
10 9 (1= Full power; 0 = Suspend) 4.7K 0.1uF/16V D
1 8 7
6 8 7 5

S
6 5 RE03
GND1 4 3
4 3 1K 47K RE04 1K RE05
2 1
2 1 +12V_PWR +12V_Standby AMP_12V0
CON16_2.5mm

1
PS_ON 47K RE07 QE02
+12V MMBT3904
BL_PDIM CE01 CE05
14,16 BL_PDIM CE26 +
CE07
BKL_EN NC/1uF/10V
16 BKL_EN 470uF/16V 0.1uF/16V NC/10uF/16V

13 SOC_PS_ON 100 RE17 PS_ON

Added CE06and CE07 to provide for Power-On sequence adjustment

Make sure See Sheet 6 for Power-On Sequence and Timing

C
header is C
keyed
If Main Power >15V change 5V SMPS & 3.3V SMPS
Normal 5V SMPS Suspend 3.3V SMPS
Set to 5.22V
+12V_Standby
+3.3V_Standby
47K_1% RE09
PS_ON 1K RE10 +5V_Normal
+12V_Standby CE12
CE08 CE09 CE10 CE11 NC/0.1uF/16V
0.1uF/16V 10uF/16V 10uF/16V 0.1uF/16V

CE13 CE14 CE15 CE16 RE12 RE11

10uF/16V 10uF/16V 0.1uF/16V 15pF/50V 56K_1% CE17 56K_1%
TMI3253T
15pF/50V
TMI3244T +3.3V_Standby
+5V_Normal RE16
3 4
3 4 RE18 +3.3V_Standby Imax = 3A 4.7uH/Irise 3.7A,Isat 5A
VIN VFB
5.1K_1%
VIN VFB
+5V_Normal Imax = 4A 4.7uH/Irise 3.7A,Isat 5A
LE01
2.2K_1%
2
LE02
1 2 5
2 1 2 5 SW EN
B SW EN B
RE13 CE20 CE25 CE22 1 6
CE21 RE14
1 6 10K_1% 47uF/6.3V 47uF/6.3V 22uF/6.3V GND VBST RE15
CE62 0.1uF/16V 18K_1%
CE61 CE18 CE38 CE19 GND VBST 12K_1%
UE02
22uF/6.3V 0.1uF/16V UE01
22uF/6.3V 22uF/6.3V 22uF/6.3V
CE23

CE24

0.1uF/16V

0.1uF/16V
TMI: Vout = 0.765 x (1+(R1/R2))=5.217V 3.32V
5.25V 10%, 16V, 0402, X5R

TMI: Vout = 0.765 x (1+(R1/R2))=3.328V

GROUND RETURN PATH IS CRITICAL ON 2-LAYER DESIGN

A A

Athens - CH Design
PLACE AWAY FROM HEADPHONE AMPLIFIER Title
Main Power, 5V SMPS, 3.3VSMPS

Follow TI Layout Recommendations. Document Number Rev

Size
B 00294345 4

Date: Wednesday, September 08, 2021 Sheet 4 of 28

5 4 3 2 1
 5 4 3 2 1

+5V_Normal +1.0V_VDDC_CPU Power (600mA)

MAX=720mA
2.7-5.5V input +1.0V_VDDC_CPU
CE39
10uF/6.3V RE24 UE05 LE04 2.2uH/Irise 2.95A,Isat 4.1A
4.7K 4 3 1 2
VIN SW
D D
CE43 CE40 CE41 CE42
15pF/50V RE25 22uF/6.3V
DDR_1V5_PGOOD NC/0 RE26 1 6 10uF/6.3V
EN FB Rt 10K_1% 10uF/6.3V
CE44 RE27 33_1%
0.1uF/16V 2A
2 5 3 RE28
GND PG VDDCPU_PGOOD
100K_1% RE29
TMI3411P 100K_1%

Vout = 0.6 x (1+ Rt/Rb)

Rb RE30
20K_1%
RE31
20K_1% RE32
20K_1%

120K Ohms
13 VID1
C C

120K Ohms
13 VID0

VID0/VID1=Hi-Z: 0.901V
VID0=Low/VID1=Hi-Z: 0.951V
VID0/VID1=Low: 1.001V

+3.3V_Normal
VDDC Enable based on 3.3V and
1.5V to ensure 1mSec power
RE50 sequence timing. UE06
VDDC_PGOOD 3
4.7K
7 Imax Saturation = 9A
PG
B DDR_1V5_PGOOD 10K RE51 5 1
Imax Temperature = 5.1A
LE05 1.0uH
VDDC Imax = 4A +1.0V_VDDC
B
6 DDR_1V5_PGOOD EN SW 9 1 2
+5V_Normal SW Bourns
CE45 RE52 8 2 CE54 CE55 CE56
0.1uF NC/4.7K 13 VIN OUT RE43 75K 1% 10uF 22uF 22uF
VIN 4 NC CE47
RAMP RE53 13K 1%
CE59
10uF
CE58 CE60
0.1uF/16V VDDC_FB
Rt
10uF 3
FB
Sense at SoC Core
RE54 RE44 RE45
6 150K_1% 820k_1%
MODE/VCON
10K Rb
GND

CE46 Vout = 0.6x (1+ Rt/Rb)

0.1uF VID2=Hi-Z: 0.95V
MP2147 VID2=Low: 1.001V
10

RE48
220K_1%

13 VID2

A A

Athens -CH Design

Title
SMPS, VDDC Power, VDDC _CPU
GROUND RETURN PATH IS CRITICAL ON 2-LAYER DESIGN Size Document Number Rev
PLACE AWAY FROM HEADPHONE AMPLIFIER Custom00294345 4

Date: Friday, September 03, 2021 Sheet 5 of 28

5 4 3 2 1
 5 4 3 2 1

+3.3V_Standby
DDR_1V5 High Efficiency SMPS
2.7-5.5V input
Imax Temperature = 1uH/Irise 3.4A,Isat 5.9A +1.5V_DDR
CE28 CE36 UE03 LE03 1uH DDR_1V5 Imax = 2A
D RE19 4 3 1 2 D
22uF/6.3V0.1uF/16v 100K VIN SW Bourns
CE30 CE37 CE31
CE29 RE20 22uF/6.3V
1
EN FB
6 15pF/50V Rt 15K_1% 22uF/6.3V 0.1uF/16V

CE32 RE22
0.1uF/16V
240_1%
2 5 5
GND PG DDR_1V5_PGOOD
RE21
TMI3411P 10K_1%

Rb
Vout = 0.6 x (1+ Rt/Rb)=1.514V

C C

GROUND RETURN PATH IS CRITICAL ON 2-LAYER DESIGN

Follow TI Layout Recommendations.

B B

A A

Athens - CH Design
Title
SMPS1.5V
Size Document Number Rev
B 00294345 4

Power-On sequence and timing requirements for Athens Date: Thursday, July 29, 2021 Sheet 6 of 26
5 4 3 2 1
 5 4 3 2 1

+1.0V_VDDC_CPU U8F

1.5A/60mils V13 A13 100mA/20mils

V14 VDDC_CPU1 AVDD_MOD_VTERM
D V15 VDDC_CPU2 +3.3V_Normal D
CM61 VDDC_CPU3
CM29 CM33 CM15 CM18 CM26 V16 K11 CM19 CM23
V17 VDDC_CPU4 AVDD_LDO_A +1.0V_VDDC
NC/22uF/6.3V 22uF/6.3V 10uF/6.3V 0.1uF/16V 0.1uF/16V 0.1uF/16V VDDC_CPU5 CM28 0.1uF/16V 10uF/6.3V
W13
W14 VDDC_CPU6 H3 2.2uF/10V +3.3V_Standby
W15 VDDC_CPU7 3V3_STANDBY3
W16 VDDC_CPU8 G2
W17 VDDC_CPU9 3V3_STANDBY2
VDDC_CPU10
3V3_STANDBY1
G1 +1.2 _MOD_VTERM is
R11 CM25 CM35 CM17 CM65 CM66 only used when we use a
R12 VDDC1 10uF/6.3V
VDDC2 10uF/6.3V panel that needs CML mode
T11 0.1uF/16V NC/10uF/6.3V NC/1uF/10V
T12 VDDC3
P15 VDDC4
P16 VDDC5
+1.0V_VDDC 3.7A/100mils P17 VDDC6 +3.3V_Normal
P18 VDDC7
R13 VDDC8
R14 VDDC9
CM27 CM32 CM20 CM22 CM31 CM36 CM21 R15 VDDC10 AH8
22uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 0.1uF/16V 0.1uF/16V 0.1uF/16V R16 VDDC11 VDDP2
R17 VDDC12 AG8 CM24 CM30 CM34
VDDC13 VDDP1 CM01
R18
R19 VDDC14 AB25 0.1uF/16V 0.1uF/16V 10uF/6.3V
C
2.2uF/10V
T13 VDDC15 AVDD_EMMC_3318_1 C

T14 VDDC16 AB24

T15 VDDC17 AVDD_EMMC_3318_2 150mA,20mil
T16 VDDC18
T17 VDDC19
T18 VDDC20
T19 VDDC21
VDDC22 B21
+1.0V_VDDC NC31
N13 A22
P13 DVDD_DDR1 NC32
P14 DVDD_DDR2
+1.0V_VDDC DVDD_DDR_RX_A
USE Internal LDO N14
DVDD_DDR_RX_B
N12
P12 AVDDL_MOD1
AVDDL_MOD2 F1 DVDD_NODIE
DVDD_NODIE(CAP)
+1.5V_DDR
250mA/25mils H27 CM02
K14 AVDD_DDR_A(CAP) AG4 1uF/10V
CM67 CM16 L14 AVDD_DDR_A1 GND1
CM64
10uF/6.3V M14 AVDD_DDR_A2
10uF/6.3V 0.1uF/16V M13 AVDD_DDR_A3
AVDD_DDR_A4
B B
295mA/30mils A24
K12 AVDD_DDR_B(CAP)
L12 AVDD_DDR_B1 AC28
CM03 CM04 L11 AVDD_DDR_B2 AVDD_DDR_DRAM_A(CAP)
CM05 CM06 AVDD_DDR_B3 +1.5V_DDR
M11 CM07
10uF/6.3V 1uF/10V 10uF/6.3V AVDD_DDR_B4 0.1uF/16V
0.1uF/16V
+1.5V_DDR J25
AVDD_DDR_DRAM_A11 J26
B27 AVDD_DDR_DRAM_A21 L21
B28 AVDD_DDR_DRAM_A1 AVDD_DDR_DRAM_A31
+1.5V_DDR AVDD_DDR_DRAM_A2
+1.5V_DDR A16
AVDD_DDR_DRAM_B11 CM08
+1.5V_DDR
A27 0.1uF/16V
B26 AVDD_DDR_DRAM_B1 H17
CM09 AVDD_DDR_DRAM_B2 AVDD_DDR_DRAM_B21
AVDD_DDR_VBP_A_SM
AVDD_DDR_VBP_A_SM G28 N15
0.47uF/10V CM11 AVDD_DDR_VBN_A_SM AVDD_DDR_VBP_A AVDD_DDR_VBP_A1
+1.5V_DDR J27 N16
CM10 AVDD_DDR_VBN_A_SM AVDD_DDR_VBN_A AVDD_DDR_VBN_A1
AVDD_DDR_VBP_B_SM A25 J14
AVDD_DDR_VBN_B_SM B25 AVDD_DDR_VBP_B AVDD_DDR_VBP_B1 K13
CM12 0.47uF/10V 0.47uF/10V AVDD_DDR_VBN_B AVDD_DDR_VBN_B1
AVDD_DDR_VBP_B_SM
A A
0.47uF/10V R817
CM13
CM14
AVDD_DDR_VBN_B_SM Athens - CH Design
0.47uF/10V
Title
SOC Power
0.47uF/10V
Size Document Number Rev
B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 7 of 26

5 4 3 2 1
 5 4 3 2 1

U8G

A2 L8
A23 GND_1 GND155 M8
GND2 GND154

D
Heat Sink HS1
B13
B22
B23
GND3
GND4
GND5
GND153
GND152
GND151
M9
M10
M19
D
B24 M20
Heat-sink(Asink80X60) C7 GND6 GND150 M21
1 C15 GND7 GND149 M23
C21 GND8 GND148 M24
C22 GND9 GND147 N4
C24 GND10 GND146 N8
C27 GND11 GND145 N9
2 C28 GND12 GND144 N10
D3 GND13 GND143 N11
O-RSAGC-6000X5000X900-1-CH GND14 GND142
D13 N19
D15 GND15 GND141 N20
D19 GND16 GND140 N21
S3 S4 D21 GND17 GND139 N22
D22 GND18 GND138 N23
D23 GND19 GND137 P8
D24 GND20 GND136 P9
E6 GND21 GND135 P11
E13 GND22 GND134 P19
E15 GND23 GND133 P20
GND24 GND132
Hole E19
E20
E21
GND25
GND26
GND27
GND131
GND130
GND129
P21
P22
R8
E23 R9
E24 GND28 GND128 R10
C GND29 GND127 C
9

E25 T3
GND30 GND126

9
9

8 1 E26 T9
F2 GND31 GND125 T10
7 2 8 1 8 1 8 1
F10 GND32 GND124 U9
6 3 7 2 7 2 7 2
F13 GND33 GND123 U10
6 3 6 3 6 3
F15 GND34 GND122 U11
H1 GND35 GND121
5

PAD H2 H3 H4 F17 U12

GND36 GND120
5

4
5

PAD PAD PAD F18 U13

F19 GND37 GND119 U14
F20 GND38 GND118 U15
F21 GND39 GND117 U16
F23 GND40 GND116 U17
F24 GND41 GND115 U18
F26 GND42 GND114 U19
G3 GND43 GND113 U23
M1 M2 M3 GND44 GND112
TP_T_C30 TP_T_C30 TP_T_C30 G6 U24
G7 GND45 GND111 U25
G8 GND46 GND110 V8
G9 GND47 GND109 V9
G10 GND48 GND108 V10
M4 M5 M6 GND49 GND107
TP_T_C30 TP_T_C30 G15 V11
TP_T_C30 GND50 GND106
G17 V12
G18 GND51 GND105 V18
G19 GND52 GND104 W8
B B
G20 GND53 GND103 W9
G21 GND54 GND102 W10
G22 GND55 GND101 AA2
G24 GND56 GND100 AB14
G25 GND57 GND99 AC10
G26 GND58 GND98 AD4
H4 GND59 GND97 AD5
H13 GND60 GND96 AD6
H14 GND61 GND95 AD10
H15 GND62 GND94 AD26
H16 GND63 GND93 AE2
H18 GND64 GND92 AE4
H19 GND65 GND91 AE7
H20 GND66 GND90 AE9
H21 GND67 GND89 AE10
H25 GND68 GND88 AE16
H26 GND69 GND87 AE25
J7 GND70 GND86 AF3
J8 GND71 GND85 AF8
J9 GND72 GND84 AF9
J10 GND73 GND83 AF13
J12 GND74 GND82 AH9
K9 GND75 GND81 AH16
A K10 GND76 GND80 AH25 A
K27 GND77 GND79
GND78
Athens - CH Design
R817
Title
SOC GND
Size Document Number Rev
B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 8 of 26

5 4 3 2 1
 5 4 3 2 1

U8B

AD9 23
NAND_AD4 IP_T TUNER_INP
AF28 AD8 23
NAND_AD3 EMMC_IO0 / EMMC_D0 / NAND-D4 IM_T TUNER_INM
AE28 AF7 23
NAND_AD2 EMMC_IO1 / EMMC_D1 / NAND-D3 IFAGC_T TUNER_AGC
AE27
NAND_AD5 AF27 EMMC_IO2 / EMMC_D2 / NAND-D2 AC7
NAND_AD6 AG28 EMMC_IO3 / EMMC_D3 / NAND-D5 IP_S AC8
NAND_AD7 AG27 EMMC_IO4 / EMMC_D4 / NAND-D6 IM_S AD7
D NAND_AD0 AD27 EMMC_IO5 / EMMC_D5 / NAND-D7 QP_S AE8 D
NAND_AD1 AE26 EMMC_IO6 / EMMC_D6 / NAND-D0 QM_S AG6
AH27 EMMC_IO7 / EMMC_D7 / NAND-D1 IFAGC_S
NAND_CEZ 0 RM15 AF26 EMMC_IO8 / EMMC_DS / NAND-DQS AC17
NAND_REZ 0 RM16 AH26 EMMC_IO9 / EMMC_CMD / NAND_CEZ PCM2_IRQA_N / DISEQC_OUT AE18
NAND_RBZ AG26 EMMC_IO10 / EMMC_CLK / NAND_REZ PCM2_RESET/ DISEQC_IN
EMMC_IO11 / EMMC_RSTN / NAND_RBZ AC11
TGPIO2 / SCK1 TUNERI2C_SCL 23
AB11 23
NAND_CLE 0 TGPIO3 / SDA1 TUNERI2C_SDA
RM08 AG25
NAND_ALE 0 RM09 AF25 EMMC_IO14 / NAND_CLE
NAND_WEZ 0 RM10 AG24 EMMC_IO15 / NAND_ALE
NAND_WPZ AF24 EMMC_IO16 / NAND_WEZ
EMMC_IO17 / NAND_WPZ

AH18
AF18 TS2_CLK / SDIO_D0 AH17
AA26 PCM_A0 TS2_SYNC / SDIO_D1 AF17
PCM_A1 TS2_VLD / SDIO_D2 SOC_PANEL_ON 16
AF19 AG17 SOC_BL_ON 16
AA27 PCM_A2 TS2_D0 / SDIO_D3
AB27 PCM_A3
AF23 PCM_A4
C PCM_A5 C
AE24 AC18
AG23 PCM_A6 PCM2_CE_N/SDIO_CLK AD17
AF21 PCM_A7 PCM2_CD_N/SDIO_CMD
AG22 PCM_A8 AD19
AF20 PCM_A9 TS0_D0 AB19
AB26 PCM_A10 TS0_D1 AE21
AD24 PCM_A11 TS0_D2 AB20
AD25 PCM_A12 TS0_D3 AC20
AC24 PCM_A13 TS0_D4 AD20
PCM_A14 TS0_D5 AE20
AE23 TS0_D6 AC22
AH21 PCM_D0 TS0_D7 AB18
+3.3V_Normal AH22 PCM_D1 TS0_CLK AC19
Y26 PCM_D2 TS0_VLD AB22
Y27 PCM_D3 TS0_SYNC
W28 PCM_D4
CM39 CM40 W27 PCM_D5
CM38
10uF UM2 AF22 PCM_D6 T28
0.01uF/50V 0.01uF/50V
L1 A1 PCM_D7 TS1_D0 U26
L2 L1 A1 A2 TS1_D1 R27
L9 L2 A2 A9 AG19 TS1_D2 T27
L10 L9 A9 A10 AD23 PCM_CD_N TS1_D3 V26
M1 L10 A10 B1 AC25 PCM_CE_N TS1_D4 U27
M2 M1 B1 B9 AD22 PCM_IORD_N TS1_D5 W26
B B
M9 M2 B9 B10 AG21 PCM_IOWR_N TS1_D6 V27
M10 M9 B10 AC23 PCM_IRQA_N TS1_D7 R26
M10 D3 AG20 PCM_OE_N TS1_CLK T26
G3 D3 D6 Y28 PCM_REG_N TS1_VLD R28
G4 G3 D6 D7 AG18 PCM_RESET TS1_SYNC
G5 G4 D7 D8 AB23 PCM_WAIT_N
G6 G5 D8 E3 PCM_WE_N AD18
G7 G6 E3 E4 PCM2_WAIT_N
G8 G7 E4 E5
H3 G8 E5 E6
H5 H3 E6 E7
H6 H5 E7 E8 R817
H7 H6 E8 F3
J3 H7 F3 F4
J5 J3 F4 F5
J5 F5 F6
NAND_WPZ C3 F6 F7 +3.3V_Normal
WP# F7 F8
RM13 NAND_CEZ C6 F8
1K CE# H8
NAND_CLE D5 VCC2 J6
NAND_ALE C4 CLE VCC3
ALE H4 NAND_AD0
A NAND_WEZ C7 I/O0 J4 NAND_AD1 A
NAND_REZ D4 WE# I/O1 K4 NAND_AD2
RE# I/O2 K5 NAND_AD3
I/O3 NAND_AD4
C5
VSS I/O4
K6 Athens - CH Design
K3 J7 NAND_AD5
VSS1 I/O5 Title
K8
VSS2 I/O6
K7 NAND_AD6
NAND_AD7
RM14 SOC NAND
J8 4.7K
I/O7
C8 NAND_RBZ Size Document Number Rev
RB# B 00294345 4
TC58NVG2S0HBAI4 or FS33ND04GS108BF10 Date: Wednesday, July 14, 2021 Sheet 9 of 26
5 4 3 2 1
 5 4 3 2 1

D D

U8A

240 1% RM17
AC26
ZQ_A

240 1% RM18
AC27
ZQ1_A

240 1% RM19
G27
ZQ_B
KGD1 KGD2
+1.5V_DDR F28 DDR3 2GBIT DDR3 2GBIT
ZQ1_B
C C

NC/240_1% RM21
RM20 KGD3
1K 1%
DRAM_VREF_A M28
DRAM_VREF_A
DDR3 4GBIT
DRAM_VREF_B
DRAM_VREF_B D27
RM22 CM41 DRAM_VREF_B
1K 1% 0.1uF/16V CM42
1000pF/50V
CM43
NC/0.1uF/16V
+1.5V_DDR
NC/1K RM23
A-RSTZ N28
A-RST
+1.5V_DDR
NC/1K RM24 B-RSTZ D26
CM44 B-RST
+1.5V_DDR NC/0.1uF/16V

B B

RM25
All components are NC but TP1 L28
1K 1%
keep in design IO_CAL_A_PLR
DRAM_VREF_A
TP2 F27
IO_CAL_B_PHR

RM26 CM45 CM46

1K 1% 0.1uF/16V 1000pF/50V

R817

A A

Athens - CH Design
Title
DRAM
Size Document Number Rev
B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 10 of 26

5 4 3 2 1
 5 4 3 2 1

SW_CONFIG1, SW_CONFIG2 U8E

functionality is to be defined
in the future. All designs BOARD_ID0 W2 T1 18
D RIN0P TN ETH_TN D
must implement the 4.7K BOARD_ID1 V3
GIN0M TP
T2
ETH_TP 18
BOARD_ID2 V2 R1
pulldowns for the default BOARD_ID3 U3 GIN0P RN R3
ETH_RN 18
configuration. BIN0P RP ETH_RP 18
BOARD_ID4 R5
BOARD_ID5 P6 HSYNC0 P4
VSYNC0 USB_CTRL USB_EN 17
F14
CID N5
+3.3V_Normal DM_P0 USB_P0_DM 17
BOARD_ID6 Y2 P5
RIN1P DP_P0 USB_P0_DP 17
BOARD_ID7 Y1
SW_CONFIG1 W3 GIN1M
SW_CONFIG2 W1 GIN1P N7
BIN1P DM_P1 USB_P1_DM 17
N6 17
DP_P1 USB_P1_DP
M6 24
DM_P2 WiFi_USB_DM
M7 24
DP_P2 WiFi_USB_DP
RM27
NC/4.7K RM28
NC/4.7K 33 RM29 CM47 0.047uF/50V U6
19 RCA_CVBSIN CVBS0 N3 24
SW_CONFIG1 IRIN IR_IN
RM30 CM48 0.047uF/50V T6
75 VCOM
SW_CONFIG2 AH7 15pF/50V CM49
C XTAL_IN C
TP3 T7 AG7
68 RM33 CVBSOUT1 CVBS_OUT1 XTAL_OUT YM1
RM32 RM34 4 3
RM31 4.7K 75
4.7K 1 2

R817 24MHz,CL=12pF
15pF/50V CM50

NOTE:晶
体频
偏需 要 小 于30 P P M
） *2
C1=C2=（CL-Cs

B B

+3.3V_Normal See BOARD_ID spreadsheet

Board_ID Board ID[7:0] = 00000100 (DVT2)
external resistors required
RM37 RM38 RM39 RM40 RM41 RM42 RM43 RM44
NC/4.7K NC/4.7K NC/4.7K NC/4.7K NC/4.7K 4.7K NC/4.7K NC/4.7K

BOARD_ID7
BOARD_ID6
BOARD_ID5
BOARD_ID4
BOARD_ID3
BOARD_ID2
BOARD_ID1
BOARD_ID0

RM45 RM46 RM47 RM48 RM49 RM50 RM51 RM52

4.7K 4.7K 4.7K 4.7K 4.7K NC/4.7K 4.7K 4.7K
A A

Athens - CH Design
Title
SOC RGB/CVBS/USB/EPHY
Size Document Number Rev
B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 11 of 26

5 4 3 2 1
 5 4 3 2 1

RCA_AU_LIN 19
RCA_AU_RIN 19
CM51 CM52
2.2uF/10V 2.2uF/10V

U8C

21 AF14
D HDMIA-RX0N A_RX0N D
21 AG14
HDMIA-RX0P A_RX0P
21 AF15 AE5
HDMIA-RX1N A_RX1N LINEIN_L0
21 AG15 AF5
HDMIA-RX1P A_RX1P LINEIN_R0
21 AF16
HDMIA-RX2N A_RX2N
21 AG16 AE6
HDMIA-RX2P A_RX2P LINEOUT_L0
21 AH13 AF6
HDMIA-RXCKN A_RXCN LINEOUT_R0
21 AG13
HDMIA-RXCKP A_RXCP
21 AD11 AF4 19
HDMIA-SCL DDCDA_CK EARPHONE_OUTL HP_AU_LOUT
21 AD12 AH4 19 Note: This circuits can
HDMIA-SDA DDCDA_DA EARPHONE_OUTR HP_AU_ROUT
AE11
21 HDMIA-HOTPLUG
AC12 HOTPLUGA AG5 CM53 CM54
couple noise into the
21 HDMIA-Detect HOTPLUGA_HDMI20_5V VAG audio outputs.
AH5 0.1uF/16V 10uF/6.3V
AG10 VRM_ADC LM01
21 HDMIB-RX0N B_RX0N Close to MST IC
21 AF11 AUVRM
HDMIB-RX0P B_RX0P CUST_ID0 +3.3V_Normal
21 HDMIB-RX1N
AG11
B_RX1N I2S_OUT_MCK
K2
Top Layer FB/120 with wide trace
AF12 H2 CUST_ID1 33 RM53
21 HDMIB-RX1P B_RX1P I2S_OUT_BCK AMP_I2S_BCLK 20,24
AG12 K3 CUST_ID2 33 RM54
21 HDMIB-RX2N B_RX2N I2S_OUT_WCK AMP_I2S_WCLK 20,24
AH12 J2 CUST_ID3 33 RM55
21 HDMIB-RX2P B_RX2P I2S_OUT_SD0 AMP_I2S_DATA 20,24
21 AG9
HDMIB-RXCKN B_RXCN
21 AF10 RM56 RM57
HDMIB-RXCKP B_RXCP 3.3V
21 AC13 4.7K 4.7K
HDMIB-SCL DDCDB_CK +3.3V_Normal
21 AD13
HDMIB-SDA DDCDB_DA
21 AB13
HDMIB-HOTPLUG HOTPLUGB
C 21 HDMIB-Detect
AB12
HOTPLUGB_HDMI20_5V I2S_OUT_SD1
J3 33 RM98 AMP_I2C_SCL 20 OPTICAL C
K4 33 RM99
22 HDMIC-RX0N
AB2
AB3 C_RX0N
I2S_OUT_SD2
CM62 CM63
AMP_I2C_SDA 20
RM69 SPDIF OUT
22 HDMIC-RX0P C_RX0P 10R
AC2 SPDIF
22 HDMIC-RX1N C_RX1N 33pF/50V 33pF/50V
22 AC3
HDMIC-RX1P C_RX1P
22 AD2 L1 19 UX1 GQ-022-SMT
HDMIC-RX2N C_RX2N SPDIF_IN HP_MUTEn SPDIF_OUT SPDIF_OUT_B
22 AD3 L2 100 RM58 3
HDMIC-RX2P C_RX2P SPDIF_OUT VINPUT
22 AA3 2
HDMIC-RXCKN C_RXCN VDD
22 AB1 K6 CM55 1
HDMIC-RXCKP C_RXCP I2S_IN_BCK GND

4
5
W7 K5 33pF/50V CM59 CM58

1
22 HDMIC-SCL DDCDC_CK I2S_IN_WCK
22 V7 K7 RM59 DM12
HDMIC-SDA

4
5
V6 DDCDC_DA I2S_IN_DIN0 L4 10K 0.1uF/16V 2.2uF/10V
22 HDMIC-HOTPLUG HOTPLUGC I2S_IN_DIN1
22 U4 L5 NCTT0541SB
HDMIC-Detect HOTPLUGC_HDMI20_5V I2S_IN_DIN2

2
22 AF1
HDMID-RX0N D_RX0N
22 AF2
HDMID-RX0P D_RX0P
22 AG1
HDMID-RX1N D_RX1N
22 AG2 B17
HDMID-RX1P D_RX1P DMIC_BCK
22 HDMID-RX2N
AG3
D_RX2N DMIC_SD0
C18 Customer ID[3:0] = 0101 (Changhong) +3.3V_Normal
22 HDMID-RX2P
AH2
AE1 D_RX2P DMIC_SD1
B18
B19
Customer ID[3:0] 0000 = (Roku) Customer_ID
22 HDMID-RXCKN D_RXCN DMIC_SD2 USE CUSTOMER SPECIFIC ID
22
22
HDMID-RXCKP
AE3
W5 D_RXCP external resistors required
HDMID-SCL DDCDD_CK
B 22 W6 RM61 RM63 B
HDMID-SDA DDCDD_DA
22 Y4 4.7K 4.7K
HDMID-HOTPLUG HOTPLUGD
22 Y7 AA5
HDMID-Detect HOTPLUGD_HDMI20_5V MICIN1 AA6
MICCM1 CUST_ID0
100 RM64 AD14 MICIN0
AB5
AB6 CUST_ID1
Requires Only 4 Resistors
22,21 HDMI-CEC CEC0 MICCM0 CUST_ID2
CUST_ID3 Use Assigned Value Here
21 1uF/10V CM56 AE15
HDMI-ARCN HDMIRX_ARCTXN
1uF/10V CM57
21 AD15 RM65 RM67
HDMI-ARCP HDMIRX_ARCTXP 4.7K 4.7K

R817

CUSTOMER_ID

A A

Athens - CH Design
Title
SOC HDMI and Audio
Size Document Number Rev
B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 12 of 26

5 4 3 2 1
 5 4 3 2 1

+3.3V_Standby

U8D

RM70
10K RM72 C1 14
MOD_TX_P00 VBY0N
10K 24 AH3 C2 14
WiFi_WAKE_HOST GPIO0_PM / PWM_PM1 / SD_CDZ / PM_SPI_DI MOD_TX_N00 VBY0P
21 LOG_TX N2 B1 14
GPIO1_PM / PM_TX / PM_SPI_DO MOD_TX_P01 VBY1N
21 R2 B2 14
LOG_RX GPIO5_PM / PM_RX / PM_SPI_CK MOD_TX_N01 VBY1P
24 AC4 B3 14
D WiFi_RSTn GPIO6_PM / PM_SPI_CZ1 MOD_TX_P02 VBY2N D
A3 14
MOD_TX_N02 VBY2P
C3 14
GPIO2_PM M2 MOD_TX_P03 VBY3N
3 B4 14
RST_INHn GPIO9_PM M1 GPIO2_PM (CHIP_CONFIG) MOD_TX_N03 VBY3P
C4 14
+3.3V_Normal GPIO10_PM Y3 GPIO9_PM (CHIP_CONFIG) MOD_TX_P04 VBY4N
24 B5 14
HOST_WAKE_WIFI GPIO10_PM (CHIP_CONFIG) MOD_TX_N04 VBY4P
A5 14
MOD_TX_P05 VBY5N
C5 14
MOD_TX_N05 VBY5P
A6 14
MOD_TX_P06 VBY6N
4 P2 B6 14
SOC_PS_ON PWR_CTRL MOD_TX_N06 VBY6P
+12V_Standby RM97 RM71 24 V5 C6 14
LED_PWM_ON PWM_PM MOD_TX_P07 VBY7N
NC/4.7K NC/4.7K 3 H6 B7 14
SOC_RESET RESET MOD_TX_N07 VBY7P
B8
MOD_TX_P08 C8
B20 MOD_TX_N08 B9
14 MI2C_SCL DDCR_CK MOD_TX_P09
RM73 14 A20 A9
(Vx1) MI2C_SDA DDCR_DA MOD_TX_N09
10K_1% C9
(PMIC) MSTV_SCL J4 MOD_TX_P10 A10
MSTV_SDA J5 DDCA_CK MOD_TX_N10 B10
DDCA_DA MOD_TX_P11 C10
DET MOD_TX_N11 B11
MOD_TX_P12_LOCKN VBY_LOCKn 14
RM74 24 SAR0 AC5 C11 14
SAR0 MOD_TX_N12_HTPDN VBY_HTPDn
100K_1% 24 SAR1 Y8 B12
AC9 SAR1 MOD_TX_P13_OSD_LOCKn C12
3 RST_BTNn
1

AB9 SAR2 MOD_TX_N13_OSD_HTPDn

C SAR5 Used for A/V Mute and NAND WP during power fail 3 RST_BTNn_LATCH SAR3 C
SAR5_VDET H5
VPLUGIN
F4
RM75
Adjust for 1V DM03 CM60 NC1 F3
nominal
10K_1% set point 330pF/50V NC2 F5
NC3
based on main MM5Z3V3 5 VID0 U5
VID0 NC4
F6
P7 E2
supply voltage 5 VID1
P3 VID1 NC5 E3 CFG[2:0] = [ PM9 : PM10 : PM2 ]
5 VID2 VID2 NC6 D2 3b'011 = ROM boot + NAND
NC7 D1
SoC ADC Pin Protection NC8 E5 +3.3V_Standby
- Must be Populated - 33 RM76 E14 NC9 E4
16 LD_SPI_MISO LD_SPI_MISO / SPI2_DI / SPI_DO_DEMURA NC10
16 LD_SPI_CSZ 33 RM77 D17 D4 4.7K RM78 GPIO9_PM
33 RM79 E17 LD_SPI_CS / SPI2_CK NC11 D5 GPIO10_PM 4.7K RM80
16 LD_SPI_MOSI LD_SPI_MOSI / SPI1_DI / SPI_DI_DEMURA NC12
33 RM81 D14 D6 GPIO2_PM 4.7K RM82
16 LD_SPI_CLK LD_SPI_CK / SPI1_CK / SPI_CK_DEMURA NC13
E18 D7
GPIO0 / SPI_CS_DEMURA NC14 E7
ARM-EJTAG
NC15 F7 +3.3V_Standby
NC16
MSTV Tool
+3.3V_Normal E8
NC17 E9
NC18 D8
NC19 D9
NC20 D10
RM84 RM85 RM86 RM87 RM88 RM89 NC21 E10 RM90 RM91 NC/HEADER2mm_4
B B
33 NC/4.7K 4.7K 4.7K 4.7K 4.7K NC22 F11 4.7K 4.7K
CONM1 NC23
U2 E11 CONM2
AB4 PM_GPIO7 NC24 D11
1 2 LD_SPI_CSZ H1 PM_GPIO8 NC25 D12 MSTV_SCL 33 RM92 1
3 4 LD_SPI_MISO M4 PM_GPIO11 NC26 E12 MSTV_SDA 33 RM93 2
5 6 33 RM94 LD_SPI_CLK PM_GPIO12 NC27 F12 3
7 8 LD_SPI_MOSI NC28 4
9 10 NC/33 RM95 3
SOC_RESETn
C13 14
TCON0 PANEL_WPn
A14
TCON1 B14
HEADER_2X5/NC AD16 TCON2 C14
GPIO9 TCON3 TCON3 14
B15 17
TCON4 USB_OCn
AC16
GPIO10 M3
GPIO11/TCON6 AMP_MUTEn 20
L3 19
GPIO12/TON7 HP_DET

A19 16
PWM0 SOC_BL_PDIM
C17
PWM1 C19
PWM2
A A
D18
TESTPIN

Athens - CH Design
Title
R817 SOC Vx1 and PM
Size Document Number Rev
B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 13 of 26

5 4 3 2 1
 5 4 3 2 1

Connections are INVERSE of AUO P550QVN01.0 panel input, so a flex cable will work.
If a IDP ribbon cable is used, it must invert 1-51 etc.

PANEL_VCC
4K Vx1 to TCON
VD_P

1
1 FPC-51
CL15 CL18 2 1 FFC1
D
NC/10uF/16V 0.1uF/16V 3 2 D

4 3
5 4
6 5
7 6
RL51 8 7
9 8 +3.3V_Normal
0R 9 +3.3V_Normal
Input Data Format [1:0] : 10
‘ 00’ =Mode1 , ’ 01’ =Mode2, 11 10 +3.3V_Normal
’ 10’ =Mode3 , ’ 11’ =Mode4 11
注意 : 0=高 电 平/1 = 低 电 平 12
RL41 NC/10K 13 12
PWM_IN 14 13
+3.3V_Normal RL40 NC/4.7K 14
Data format 0 PWM_OUT 15 RL23
Data format 1 G+Mode 16 15 RL22 NC/4.7K
RL42 NC/4.7K 16 RL36
RL43 NC/10K G+/3D_EN 17 NC/4.7K
T_SDA 17 NC/4.7K
RL52 NC/33 18
13 MI2C_SDA RL53 NC/33 T_SCL 19 18
13 MI2C_SCL 19
13 NC/100 RL24 T_WP 20 T_WP LD_EN
PANEL_WPn 20 Bit_SEL_1
Bit SEL:‘ H’ or NC= 10bit(D) , ‘ L’ = 8
i
b
t Bit_SEL_1 21
NC/100 RL25 LD_EN 22 21
13,14 TCON3 22
AGP or NSB 23
Bit_SEL 24 23 RL26 RL27
MOD_TX_N12 24 RL37 NC/4.7K NC/4.7K
25
MOD_TX_P12 26 25
27 26
27 NC/10K
0.1uF CL20 V_TX0N 28
13 VBY0N V_TX0P 28
13 VBY0P 0.1uF CL19 29
30 29
0.1uF CL21 V_TX1N 31 30 +3.3V_Normal +3.3V_Normal
13 VBY1N 31
0.1uF CL22 V_TX1P 32
13 VBY1P 32
33
0.1uF CL23 V_TX2N 34 33
C 13 VBY2N 34 C
0.1uF CL24 V_TX2P 35 RL28 RL29
13 VBY2P 35
36 NC/4.7K NC/4.7K
0.1uF CL34 V_TX3N 37 36
13 VBY3N 37
0.1uF CL25 V_TX3P 38
13 VBY3P 38
39 T_SDA T_SCL
0.1uF CL26 V_TX4N 40 39
13 VBY4N 40
0.1uF CL27 V_TX4P 41
13 VBY4P 41
42 RL31
0.1uF CL29 V_TX5N 43 42 RL30 NC/4.7K
13 VBY5N 43
0.1uF CL28 V_TX5P 44 NC/4.7K
13 VBY5P 44
45
0.1uF CL30 V_TX6N 46 45
13 VBY6N 46
13 VBY6P 0.1uF CL31 V_TX6P 47
48 47
0.1uF CL32 V_TX7N 49 48
13 VBY7N 49
13 VBY7P 0.1uF CL33 V_TX7P 50
51 50
+3.3V_Normal 52 51
53 52
53

RL32 RL33
10K 10K

13 VBY_HTPDn 33 RL34

13 VBY_LOCKn 33 RL35 LG G+ panel use

B B
SOC_ADJ RL38 NC/0R PWM_IN
13 SOC_BL_PDIM

PANEL I2C 4,16 BL_PDIM

BL_PDIM RL39 NC/0R PWM_OUT

CLEARLY LABEL EACH LD_EN

PORT IN SILKSCREEN ‘ L’ : Non division, ‘ H’ 2 divis
n
o
i
ON BOARD
Switched I2C access
direct to panel gamma and
SAMSUNG panel use PWM_IN RL44 0R
vcom controll
+3.3V_Normal RL45 NC/4.7K G+/3D_EN RL46 NC/0R
+3.3V_Normal RL47 NC/4.7K AGP or NSBRL48 NC/0R
RL49 NC/4.7K Bit_SEL RL50 NC/0R
+3.3V_Normal

A A

Athens - CH Design
Title
Vx1 Panel
Size Document Number Rev
Custom 00294345 4

Date: Wednesday, July 14, 2021 Sheet 14 of 26

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Athens - CH Design
Title
P2P and Vx1 Chart
Size Document Number Rev
B 4
00294345
Date: Wednesday, July 14, 2021 Sheet 15 of 26
5 4 3 2 1
 5 4 3 2 1

Change to SMPS if Power Input > +12V

+12V_Standby

UL01 Panel Power Control

1 8 Use only if main supply is max 12V
D 2 S1 D11 7 D
CL01 CL02 G1 D1 VD_P
3 6
RL01 4 S2 D22 5
10uF/16V CL03
0.1uF/16V RL21 150K G2 D2
10K NC/0.22uF/16V ME4953/JY4953
CL13 10n/50V

DL01 RL02
1N4148W 150K

QL01
9 SOC_PANEL_ON 4.7K RL03
MMBT3904
RL04 CL09 <- Requires >=12V Collector/Base voltage
4.7K
NC/0.1uF/16V

C C

100 RL10 100 RL09 BRI_ADJ

9 SOC_BL_ON BKL_EN 4 13 SOC_BL_PDIM BL_PDIM 4

CL10
0.1uF/16V

RL15 RL16
4.7K 4.7K

B B

SOC LOCAL DIMMING and/or DE-MURA

CONNECTIONS
LD_SPI_CSZ is SPI CSn for LOCAL DIMMING

CLEARLY LABEL EACH

PORT IN SILKSCREEN
ON BOARD

A A

LD_SPI_MOSI, LD_SPI_MISO, LD_SPI_CLK, DEMURA_CSn = DEMURA SPI Athens - CH Design

Title
SMPS, VDDC Power, VDDC _CPU
Size Document Number Rev
B 00294345 4

Date: Wednesday, July 21, 2021 Sheet 16 of 26

5 4 3 2 1
 5 4 3 2 1

USB Current Limit Detection / Switch

1.2A LIMIT TOTAL for 1 USB Port
>1.5A LIMIT TOTAL for 2 USB Ports

D D
+3.3V_Normal
+5V_Normal

RU01
10K

SY6288C3AAC or TP6063F
CU01 CU13
USB_OCn 13
0.1uF/16V +5V_USB
10uF/6.3V
5 1
in out

RU28
11 USB_EN 100 4 3
en oc

gnd
1.5A Active low
CU02
UU01

2
10uF/6.3V

RU02
10K
Current Limit = 1.5A
C C

EN and OC pins required

USB Ports 5V_USB1 +5V_USB

USB-A-01
USB1
Route as differential pairs @ 90ohms USB1D-

1
RU03 1 + CU03
USB1_DM1 \/ 0 2 220uF/16V
11 USB_P0_DM

1 1

1
USB1_DP1 0 3 Al Elect, 16V, 20%, SMT
11 USB_P0_DP

1
DU06 4 CU04 CU05
RU04 DU05 NC/22uF/6.3V 0.1uF/16V
USB1D+

5
6
TT0541SB
TT0541SB 5V_USB3

2
+5V_USB

1
B
USB2.0 Host B

1
GND15
(Type A Connector) NC/USB-A-02
USB3

12
11
USB3D-
RU07 NC/0 5 1
USB1_DM1 6 2 P2_DM

1 1
USB1_DP1 7 3 P2_DP
8 4
RU08 NC/0

1
1

1
5V_USB2 +5V_USB USB3D+

10
9
USB-A-01 DU11 DU10
USB2
Route as differential pairs @ 90ohms USB2D-
NC/TT0541SBGND17

1
RU05 1 + CU09 NC/TT0541SB
USB2_DM2 \/ 0 P2_DM 2 220uF/16V

2
2
11 USB_P1_DM
1

1 1

USB2_DP2 0 P2_DP 3 Al Elect, 16V, 20%, SMT

11 USB_P1_DP
1

DU04 4 CU08 CU10

RU06 DU01 NC/22uF/6.3V 0.1uF/16V
USB2D+ Add double layers usb interface
5
6

TT0541SB
1

TT0541SB
compatible with USB2
2

A A

GND16
OPTIONAL Athens - CH Design
USB2.0 Host Title
USB
(Type A Connector) Size Document Number Rev
B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 17 of 26

5 4 3 2 1
 5 4 3 2 1

TD+ PW01
1
D TD+ 8 D
TD+ 1
TD-
TD- 1 7 NC
TD-
5 2
TDCT CH_GND
1 4
RD+ DCT RDCT
1 9
RD+ 6 GND1 10
RD+ GND2
RD- 3
RD-
RD-
1
MDI_TP RJ45
11 ETH_TP

MDI_TN
C 11 ETH_TN C

MDI_RP
11 ETH_RP LWM1
TD+

1
MDI_RN YLM1206F2SF-101-A

1
11 ETH_RN MDI_TP 1 2 1 LW3 2
0.1uF/25V CW01 1 2 2
2 4
4
MDI_TN 1 2 4 3
UW02

3
MDI_RN 1 10 0.1uF/25V CW03 4 3
Line-1 NC4 YCM0805F2SF-801-N TD-

3
B B
MDI_RP 2 9
Line-2 NC3 LWM2
3 8 RD+

1
GND GND
MDI_TN YLM1206F2SF-101-A

1
4 7
Line-3 NC2 MDI_RP 1 2 1 LW4 2
MDI_TP 5 6 0.1uF/25V CW05 1 2 2
Line-4 NC1 2 4
4
NC/TT0534SP
MDI_RN 1 2 4 3

3
0.1uF/25V CW07 4 3
YCM0805F2SF-801-N RD-

3
A Athens - CH Design A

Title
RJ45
Size Document Number Rev
Custom 00294345 4

Date: Wednesday, July 14, 2021 Sheet 18 of 26

5 4 3 2 1
 5 4 3 2 1

CVBS Video Input RCA_CVBSIN 11

1
TT0541SB
AV-V CY02
1 NC/33pF/50V

DY01
AV1 10 Support 2Vrms Audio

2
D 1 D
2
into connector on
9 AL_1

1
3 10K RY02 RCA_AU_LIN 12
4
8
5 RY03
6 AV-L 18K CY03
7 330pF/50V
11
AV-1-3PKM-0A102

1
1 10K RY04 RCA_AU_RIN 12
GND18
RY05
AV-R 18K CY06
330pF/50V
CVBS Audio Input

12 HP_MUTEn

C LO_MUTEn an HP_MUTEn
driven low by PMU if
RY06
4.7K
RY25 CY07 AD22653 DISCRETE HEADPHONE AMP C

100 1uF/6.3V
SAR5 below threashold.
TI DRV632 and ESMT AD22653 are Pin Compatible HP_L
RY07 10K RY08 100 L_TIP

1
1
CY08
100pF/50V RY09 DY02 CY09
NC/47K RY23
12 CY10 10uF/16V RY10 10K RY11 24K NC/TT0541SB
HP_AU_LOUT 1K 1200pF/50V

Phone1

2
CY11
680pF/50V HP_R 2

7
5
UY1 RY12 100 R_TIP
Set Gain <= -1.0

Mute

VSS
+INR

-INR

OUTR

GND

CN

1
1
3
CY12 DY03 CY13 4
For improved noise floor
OUTL
1uF/10V RY24 1

GND
+INL

VDD
UVP
-INL

CP
NC/TT0541SB 1K 1200pF/50V

B CLICK / POP ELIMINATION CY14 AD22653-QH14NAR

GND19 PHONEJACK
B
14

13

12

11

10

2
680pF/50V 1

12 CY15 10uF/16V RY13 10K RY14 24K

HP_AU_ROUT
CY16
+3.3V_Normal 100pF/50V +3.3V_Normal
<Description 2>
RY15 10K
ROKU need to change config as below：
RY16 NC/47K RY18 1= Headphone installed
3.9K_1% RY17 47k
0 = No Headphones
+3.3V_Normal
LY1
RY19 10K RY20 1K HPJ_DET
13 HP_DET
120@100MHz_450mA CY17
CY18 RY21 CY19 CY20 2.2uF/10V
100pF/50V 3.3K_1%
0.1uF/16V
10uF/6.3V

A A

Athens - CH Design
Title
Analog A/V ports
Size Document Number Rev
B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 19 of 26

5 4 3 2 1
 5 4 3 2 1

33 RH01 12
HDMIA-Detect HDMIA_5V
33 RH02 12
HDMIA-HOTPLUG
RH03 RH04
200 1.2K
LH01
12 RH05
HDMI-ARCN 10uH/3mA LH02
23 10uH/3mA NC/10K
GND4 22 RH06 RH07 RH08
2 4 18 16
GND3 21 47K 47K
GND2 5.1K
D 1 3 19 17 20 D
GND1 RH09
5.1K
19 HDMIA_HPDET
HOT_PLUG_DETECT 18 HDMIA_5V
5V_SUPPLY 17
CEC_GROUND 16 HDMIA_SDA_R 100 RH10
TMDS-SDA HDMIA-SDA 12
15 HDMIA_SCL_R 100 RH11
TMDS-SCL HDMIA-SCL 12
14 12
HEC_DATA_N HDMI_CEC HDMI-ARCP
13 12
HDMI-CEC HDMI-CEC
12 12
TMDS_DATA_CLK_N HDMIA-RXCKN
11 Populate R239 for
TMDS_DATA_CLK_SHIELD 10
TMDS_DATA_CLK_P HDMIA-RXCKP 12
TMDS_DATA_0_N
9
HDMIA-RX0N 12 certification test
8
TMDS_DATA_0_SHIELD 7
TMDS_DATA_0_P HDMIA-RX0P 12
6 12
TMDS_DATA_1_N HDMIA-RX1N
5
TMDS_DATA_1_SHIELD 4
TMDS_DATA_1_P HDMIA-RX1P 12
3 12
TMDS_DATA_2_N HDMIA-RX2N
2
TMDS_DATA_2_SHIELD 1
TMDS_DATA_2_P HDMIA-RX2P 12

1
UH03 UH04
HDMI TYPE A 1.4+
1

1
1 10 1 10
C DH03 DH05 CH1 NC1 CH1 NC1 C
CON,HDMI,SMT,R/A,19P DH01 CH01 DH04 2 9 2 9
HDMI1 3 CH2 NC2 8 3 CH2 NC2 8

NC/TT0541SB

NC/TT0541SB
NC/TT0541SB
NC/TT0541SB
4 GNDGND 7 4 GNDGND 7
0.1uF/16V
HDMI1 + ARC 5 CH3 NC3 6 5 CH3 NC3 6

2
CH4 NC4 CH4 NC4
2

2
NC/TT0534SP NC/TT0534SP
HDMIA + ARC

ARC/eARC
HDMIA and HDMIB can be used for JTAG access if needed

33 RH12 12
HDMIB-Detect
B 23 B
GND4 22 RH13 RH14
2 4 18 16
GND3 21 47K 47K
1 3 19 17 GND2 20
GND1
19 HDMIB_HPDET 33 RH15
HOT_PLUG_DETECT HDMIB-HOTPLUG 12
18 HDMIB_5V
5V_SUPPLY 17
CEC_GROUND 16 HDMIB_SDA_R 100 RH16
TMDS-SDA HDMIB-SDA 12
15 HDMIB_SCL_R 100 RH17
TMDS-SCL HDMIB-SCL 12
14
HEC_DATA_N 13
HDMI-CEC 12
TMDS_DATA_CLK_N HDMIB-RXCKN 12
11
TMDS_DATA_CLK_SHIELD 10
TMDS_DATA_CLK_P HDMIB-RXCKP 12
9 12
TMDS_DATA_0_N HDMIB-RX0N
8
TMDS_DATA_0_SHIELD 7
TMDS_DATA_0_P HDMIB-RX0P 12
6 12
TMDS_DATA_1_N HDMIB-RX1N
5
TMDS_DATA_1_SHIELD 4
TMDS_DATA_1_P HDMIB-RX1P 12
3 12
TMDS_DATA_2_N HDMIB-RX2N
2
TMDS_DATA_2_SHIELD 1
TMDS_DATA_2_P HDMIB-RX2P 12
A A
1

UH01 UH02
HDMI TYPE A 1.4+
DH06 DH08 DH09 DH10 1 10 1 10
CON,HDMI,SMT,R/A,19P 2 CH1 NC1 9 2 CH1 NC1 9 Athens - CH Design
NC/TT0541SB

CH2 NC2 CH2 NC2

NC/TT0541SB

NC/TT0541SB
NC/TT0541SB

HDMI2 CH02 3 8 3 8
GNDGND GNDGND Title
4
5 CH3 NC3
7
6
4
5 CH3 NC3
7
6
HDMI_RX_PORTS A&B
0.1uF/16V
HDMI2
2

CH4 NC4 CH4 NC4

NC/TT0534SP Size Document Number Rev
NC/TT0534SP B 4
HDMIB 00294345
Date: Wednesday, July 14, 2021 Sheet 21 of 26
5 4 3 2 1
 5 4 3 2 1

REMOVE HDMIC for 3 HDMI only Implementation

33 RH20 12
HDMIC-Detect
23
2 4 18 16
GND4 22 RH21 RH22
GND3 21 47K 47K
1 3 19 17 GND2 20
D GND1 D
19 HDMIC_HPDET 33 RH23
HOT_PLUG_DETECT HDMIC-HOTPLUG 12
18 HDMIC_5V
5V_SUPPLY 17
CEC_GROUND 16 HDMIC_SDA_R 100 RH24
TMDS-SDA HDMIC-SDA 12
15 HDMIC_SCL_R 100 RH25
TMDS-SCL HDMIC-SCL 12
14
HEC_DATA_N 13 HDMI_CEC
HDMI-CEC HDMI-CEC 12,21
12 12
TMDS_DATA_CLK_N HDMIC-RXCKN
11
TMDS_DATA_CLK_SHIELD 10
TMDS_DATA_CLK_P HDMIC-RXCKP 12
9 12
TMDS_DATA_0_N HDMIC-RX0N
8
TMDS_DATA_0_SHIELD 7
TMDS_DATA_0_P HDMIC-RX0P 12
6 12
TMDS_DATA_1_N HDMIC-RX1N
5
TMDS_DATA_1_SHIELD 4
TMDS_DATA_1_P HDMIC-RX1P 12
3 12
TMDS_DATA_2_N HDMIC-RX2N
2
TMDS_DATA_2_SHIELD 1
TMDS_DATA_2_P HDMIC-RX2P 12

1
UH07 UH08
HDMI TYPE A 1.4+
DH11 DH13 DH14 DH15 1 10 1 10
CON,HDMI,SMT,R/A,19P 2 CH1 NC1 9 2 CH1 NC1 9
C CH2 NC2 CH2 NC2 C
HDMI4
NC/TT0541SB
CH04 3
GNDGND
8 3
GNDGND
8
HDMI Debug Port PM_TX/PM_RX

NC/TT0541SB

NC/TT0541SB

NC/TT0541SB
4 7 4 7
0.1uF/16V 5 CH3 NC3 6 5 CH3 NC3 6
HDMI4
2

2
CH4 NC4 CH4 NC4
NC/TT0534SP NC/TT0534SP
HDMIC HDMI_LOG_RX RH18 100 LOG_RX 13
HDMI_LOG_TX RH19 100 LOG_TX 13
CH06 CH03

NC/15pF/50V NC/15pF/50V

33 RH26 12
HDMID-Detect
23
GND4 22 RH27 RH28
B 2 4 18 16 B
GND3 21 47K 47K
1 3 19 17 GND2 20
GND1
19 HDMID_HPDET 33 RH29
HOT_PLUG_DETECT HDMID-HOTPLUG 12
18 HDMID_5V
5V_SUPPLY 17
CEC_GROUND 16 HDMID_SDA_R 100 RH30
TMDS-SDA HDMID-SDA 12
15 HDMID_SCL_R 100 RH31
TMDS-SCL HDMID-SCL 12
14 HDMI_LOG_TX
HEC_DATA_N 13 HDMI_CEC
HDMI-CEC 12
TMDS_DATA_CLK_N HDMID-RXCKN 12
11
TMDS_DATA_CLK_SHIELD 10
TMDS_DATA_CLK_P HDMID-RXCKP 12
9 12
TMDS_DATA_0_N HDMID-RX0N
8
TMDS_DATA_0_SHIELD 7
TMDS_DATA_0_P HDMID-RX0P 12
6 12
TMDS_DATA_1_N HDMID-RX1N
5
TMDS_DATA_1_SHIELD 4
TMDS_DATA_1_P HDMID-RX1P 12
3 12
TMDS_DATA_2_N HDMI_LOG_RX HDMID-RX2N
2
TMDS_DATA_2_SHIELD 1
TMDS_DATA_2_P HDMID-RX2P 12
1

A UH05 UH06 A
HDMI TYPE A 1.4+
DH16 DH18 DH19 DH20 1 10 1 10
CON,HDMI,SMT,R/A,19P 2 CH1 NC1 9 2 CH1 NC1 9
HDMI3 CH05 3 CH2 NC2 8 3 CH2 NC2 8
GNDGND GNDGND Athens - CH Design
NC/TT0541SB

NC/TT0541SB

NC/TT0541SB

NC/TT0541SB

4 7 4 7
CH3 NC3 CH3 NC3 Title
HDMI3 w/Debug Port 0.1uF/16V 5 6 5 6 HDMI_RX_PORTS C&D
2

CH4 NC4 CH4 NC4

NC/TT0534SP NC/TT0534SP
Size Document Number Rev
HDMID w/Debug Port B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 22 of 28

5 4 3 2 1
 5 4 3 2 1

Si2151 TUNER close to tuner

4
UT02
TUNER_3V3
CW1117CB-3.3V

ADJ
OUT
IN
+5V_Normal
+3.3V_TUNER TUNER_3V3
CT05 0.250A

1
D CT04 D
CT07
1200pF/50V 1 2
0.01uF/50V 1200pF/50V CT06 LT01
1200pF/50V
120@100MHz_450mA
CT27 CT28
CT03 CT02 CT01 0.1u/16V
10u/6.3V 10u/6.3V 0.1u 10u/6.3V
TUNER_1.8V

CT08 CT09
1uF/6.3V
CT10
1200pF/50V LT02 1200pF/50V
Verify Regulator Thermal Performance
270nH

17

15

7
+3.3V

+3.3V

+3.3V

+1.8V
RF 18
NC
LT03
75 ohm Line 270nH CT25
SB1 \/ 19 DIF+ IN+
1

RF_REF TUNER_INP 9
IEC FEMALE
CT12 CT13
RT03
C 0.1uF/16V C
0 RT02 11 220 IF_OUT+
20 LIF_P
RF_IP 10 220
47pF/50V
CT14 39pF/50V 22 LIF_N IF_OUT-
LT07 CT16 RF_IN CT18
180pF/50V RT04
270nH DT1 CT26 CT17 DIF- IN-
TUNER_INM 9
BAV99 33pF/50V 33pF/50V
LT10 13
39pF/50V XTAL_I/RCLK 0.1uF/16V
LT11
180nH 14 Place Close to
270nH XTAL_O
MediaTek SoC
24
GPIO1
LT12 1
Consider heavy trace width for IF routing
270nH GPIO2

5 IFAGC_T1 100 RT05

AGC1
4 CT20
3 AGC2 0.01uF/50V
YT2 24MHz,CL=8pF SCL
B 4 3 2 B
SDA

GND(EPAD)
1 2 23 12
ADDR XOUT

GND

GND

GND

GND
Close to Tuner
Xtal Requirements

16

21

25
24Mhz +/- 100ppm UT01
TUNER_3V3
CL=8pF Address = Si2151_A10
0xC0/0xC1

TUNER_3V3 CT21
TUNER_3V3
0.1uF/16V

RT06
RT07 RT08 10K
4.7K 4.7K
9 0 RT09
TUNER_AGC
A A
9 100 RT10 CT22
TUNERI2C_SCL
0.22uF/50V
100 RT11
9 TUNERI2C_SDA Athens - CH Design
CT23 CT24 Title
47pF/50V 47pF/50V TUNER
Close to MediaTek SoC
Size Document Number Rev
B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 23 of 26

5 4 3 2 1
 5 4 3 2 1

AMP_PWR AMP_12V0

D D
Snabber circurt to reduce voltage overshoot
4PIN-2.54mm
CA32 CA31 CA01 CA02 + CA03 + CA04 LA02 6045/22uH CONA2L
10uF/16V 10uF/16V 0.1uF/16V 0.1uF/16V 220uF/16V 220uF/16V
L+ 2 3
CA05 1 23 4
470pF/50V 14
CA12 CA20 L-
Capacitors Rated 50V
UA01 RA04 0.22uF/50V 1000pF/50V
+3.3V_Normal 10R
1 2
LA06 14 24 CA06 22nF/50V CA18 Close to Speaker
120@100MHz_450mA CA07 CA08 23 VDDR BST_LA 22 LOUT+
1uF/16V 0.1uF/16V VDDL LA 20 LOUT- 0.22uF/50V
LB 19 CA11 22nF/50V
CONA1 mount for DVT1,DVT2. BST_LB
RA05 0R 9 21 RA07
CONA1 10 DVDD GNDL CA10 CA21
DGND 10R
M-TJC10-8A-CH
18 CA13 22nF/50V 0.22uF/50V 1000pF/50V
BST_RA 17
1
2
3
4
5
6
7
8

+3.3V_Normal CA09 1uF 11 RA 15 CA19

VREG RB 13 CA14 22nF/50V
BST_RB 470pF/50V
16 LA03
I2S_SCLK 4 GNDR audio_out
C 12,24 AMP_I2S_BCLK C
I2S_LRCLK 3 BCLK 6045/22uH
12,24 AMP_I2S_WCLK I2S_SDIN LRCIN
12,24 AMP_I2S_DATA 5
SDATA 8 LA04

1
SDATAO
CONA3R
6 6045/22uH R+
12 AMP_I2C_SDA SDA
12 AMP_I2C_SCL 7 CA25 1 3
CA15 CA16 CA17 SCL 12 470pF/50V 2 13 4
GVDD CA29 CA30 CA26 CA22 R- 24
NC/33pF/50V NC/33pF/50V +3.3V_Normal 1uF/16V 0.1uF/16V CON4-2.0
NC/33pF/50V RA01 15K 1 25 RA08 0.22uF/50V 1000pF/50V
/ERROR GND PAD1 ROUT+ 10R
12 AMP_MUTEn RA10 1K 2 ROUT-
/PD

/ERROR=1 Address:0x31 RA02 CA24 Close to Speaker

AD82088-QG24NRT
4.7K CA33
NC/1000pF/50V 0.22uF/50V
RA09
10R CA27 CA23

0.22uF/50V 1000pF/50V

CA28
470pF/50V

LA05
B B
Snabber circurt to reduce voltage overshoot 6045/22uH

I2C Address = 0x30 L+ 1L+

L- 1L-
R- 1R-
R+ 1R+

Follow ESMT Layout Recommendations.

NOTES:
* Do not place Voltage Regulators close to AD82088 if possible
* Voltage GND return path and filter capacitor placement is crucial
* Poor GND implementation may result in noise in Audio

A A

Athens - CH Design
Title Block Diagram
Athens

Size Document Number Rev

Custom 00294345 4

Date: Wednesday, July 14, 2021 Sheet 23 of 25

5 4 3 2 1
 5 4 3 2 1

+3.3V_Standby
LED / IR HEADER +3.3V_Standby

KEYPAD
RK20 RK01
Header 1K 1K RK02
4.7K
SAR1 is primary feature for 5 buttons or less
1K RK03 11
D IR_IN D
SAR0 = 2 Key (Mute, Input) +3.3V_Standby

NC/TT0541SB
KEY1 1K RK04
SAR0 13
CK01

DK06
KEY0 1K RK05 13 33pF/50V
SAR1
1

SAR1 = 5 Key (Power, CH-, CH+, VOL-, VOL+) RK06 RK26

CK03 RK08

2
DK05 1K 4.7K
4.7K
1nF/50V
NCTT0541SB IR_IN_DB
2

LED_G NC/1K RK09 LED_CATHODE NC/0R RK21

QK01 4.7K RK10

MMBT3904 4.7K RK25
QK02
LED_PWM_ON 13
MMBT3904
CK11
NC/47pF/50V
+3.3V_Standby

C +3.3V_Standby CK04 LED1 C

STB_3V3 2.2uF/10V
HMF0602HR02CC Populate as needed
NC/PH-6AW 2 1LED_R 240 RK22 LED_CATHODE for LED default = ON

1
1 when AC power applied.
1

2
3 IR_IN_DB
4 LED_G
LED_R
1

8 5 KEY0_1 0/NC RK23 KEY0 SW981

6
4 1 KEY0
1

7 NCTT0541SB
1 3 2
GND14
CONK1 DK01
KEY0-in
WiFi Route as differential pairs @ 90ohms
1 POWER
Module \/
2

IR_in +3.3V_Standby WiFi_USB_D-

1
WiFi_USB_D+
LED-G
Header +3.3V_Standby
IR971

1
TT0541SB TT0541SB
4
GND1 CU22
1
GND CU21 22uF/6.3V
47uF/6.3V DU07 DU08
IR_IN_DB

2
2 3
VS IR
B 47pF/50V RU27 B
4.7K

12
R-SDR438-TR-CH CK10
RK24 +3.3V_Standby 1
2 WiFi_USB_D+ 2.2 RU21
WiFi_USB_DP 11
3 WiFi_USB_D- 2.2 RU22
1uF/10V 100R WiFi_USB_DM 11
4 STB_3V3
CK09 5 STB_3V3
6 STB_3V3
7 WiFi_WAKE-HOST 33 RU23
HOST_WAKE-WiFi WIFI_WAKE_HOST 13
8 33 RU24
HOST_WAKE_WIFI 13
9 WiFi-RSTn 33 RU25 13
WIFI_RSTn
10
CU30 CU31 RU26
FFC-10 4.7K

11
CONU1 NC/4.7pF/50V NC/4.7pF/50V

A A

Athens - CH Design
Title
Board to Board
Size Document Number Rev
B 00294345 ROKU CONFIDENTIAL 4

Date: Tuesday, August 03, 2021 Sheet 24 of 26

5 4 3 2 1
 5 4 3 2 1

HDMI 1
+ARC
RXA

D
DC-DC POWER SLC HDMI 2 D

NAND
512MB RXB

DIF/AGC/I2C Tuner
Si2151
LDIM
LD_SPI
R817
BGA 19x19
Vx1 Connector

C MCP DDR3 2Gbx2 & 4Gbx1 C

2133MHz

PHONE
LINEOUT0 LineOut

JACK
Driver
MOD_TX TPA6139

PHONE
HP OUT

JACK
HP OUT Driver
DRV632

B I2S_Output B

CVBS0

A/V Input
Audio AMP
TAS5805

Optial RXD
Tx RJ-45 RXC
USB P0 USB P1 HDMI 4 HDMI 3
+UART
A A
WiFi
SPDIF_OUT USB Port0 USB Port1 Athens - CH Design
USB Port2 Title
Layout Diagram
Size Document Number Rev
B 00294345 4

Date: Wednesday, July 14, 2021 Sheet 25 of 26

5 4 3 2 1
 5 4 3 2 1

REVISION CHANGES CHANGHONG CHANGES

2020-Feb5th (A1) Initial Release 2021-April15th (A1)
Used the previous Camden and Malone design. page3：change KEY3/DM11/DS01 PCB footprint,Compatible with key4,same with BR malone 50inch
2020-April8th (A2) Updated Panel Power Control Circuit, populating C131, C134, C136, FB5 page4：change 12V power connector CONE1(delete 24V),delet SOC_BL_ADIM,change RE03/CE07/RE04/CE06/RE10/LE01/LE02/RE12/RE18
/RE11/RE16 value,Add CE01/CE26/ CE27/CE18/CE38/CE20/CE25/CE21/CE22,QE01 3415 to TITAN and MCC brand,pls check CHRO-395/416
2020-May5th (A3) Added C255 and C254, both are NC
page5: change value LE04/CE43/RE25/RE27/RE30/RE28/RE31/RE29/RE32;change VDDC DC-DC to 4A TLV62095
2020-May20th (A3) Reverse signal directions of AMP_I2S_DATA on FFM conenctor. FF_SPI_MISOand FF_SPI_INTn
D from the SoC page6：change UE03 1.5V_DDR to 2A TLV62569PDDC,change value:UE04/CE34/CE33/CE35 D
page7: Add CM61,same with BR Malone
2020-July 14th (A4) Moved Debug Port to HDMI D
page8：
change heat sink and add hole
Fixed the Wifi_USB_DP and Wifi_USB_DM off page connectors on page 24 page9: delete ATSC3.0,change RM14 to 4.7K,delete LD_TX/LD_RX/SAT_DISEQC_OUT/TS0_D0/TS1_D0~TS1_SYNC
2020-July 29th (A5)
page10: change KGD1/KGD2/KGD3 to not component
2020-Sept22nd (A6) Removed all FF connections and connector. Removed LNB Signals (only designed for Global) page11：change YM1 crystal
page12: delete AMP_RESETn/FF_BOARD_DETn/AMP_I2S_MCLK,change optical Footprint,change LM01 to 120Ω @100MHZ,change CM55 to 47pF;
2021- Jan 21st(7) Updated regulators U4, U5, U6 and Remove Lineout AMP and lineout NETS RM56/RM57 to 4.7K,RM53/RM54/RM55 to 33Ω ,change CH Customer_ID

page13：
delet SOC_BL_ADIM,change RM70/RM72 to 10K,RM97/RM71 to NC,DM03 to 3.3V,RM73/RM75 to 10K,RM74 to 100K for low standby
2021-April 7th (8) Page 2 Diagram amended to reflect amplifier power arrangement change power consume,same with malone
Usman Page 4 Amplifier power arrangement changed page14: add RL36~RL84， VB1 sequence part is changed according to Changhong standard and compatible with t-conless part.
Page 5 +1.05V_VDDC_CPU net-name changed (was +1.05_VDDC_CPU) SW needs to add three control ports to write t-conless build,pls check PANEL_WPn/MI2C_SDA/MI2C_SCL for T-CONLESS wirting
Page 16 Replaced N1 with Q12
Page 17 Replace UD1 with U13 page16: simplify SOC_BL_ON和 ，Add DL01/RL21/CL13,delete local dimming connector
SOC_BL_PDIM design,change value RL01/RL02/UL01
Page 23 R272 changed to 0R
page17: deleteFB6,CU01/CU02 to 6.3V,TVS to Unipolar,Compatible with USB3，USB 1.5A power switch add TITAN,pls check CHRO-432
page18: change network transformer design,same with malone
page19: change AV and headphone connector （ROKU need to reverse for default setting),LY1 to 450mA/0402
page20: change to ESMT AD82088
page22/23: add CH06,all of TVS to NC
page23: add CT01/CT02/LT01/CT03/CT27/CT28，RF testing point,delete SAT-TUNERI2C_SCL/SAT-TUNERI2C_SDA
Page24: key&IR part change,7002N to 3904,CK05 to 47uF,LED_PWM_ON need to default LOW
North American : add CONK2
Latin America key&IR on board : Add CK09/CONK1/DK01/IR971/LED1/RK21/RK22/RK23/SW981/DK02/DK03

C C
2021-April 19th (A2)

page3：Add RS17
page4：delete DE01, CE27 change to ceramic capacitor
page12：add RM98/RM99/CM62/CM63
page14：correct VBY2P and VBY3N sequence
page16：
CL10 need to SMT
page17：
add RU28, delete CU06/CU07/CU11/CU12, close DU01/DU04/DU05/DU06 to USB port
page19：delete RY01/CY01/CY04/CY05,change RY03/RY05 to 12K,DY02/DY03 to NC,add RY25
page22/23：delete DH02/DH07/DH12/DH17
page23：change RT06 position to front of RT09
delete CK07/CK08/RK12
page24：

2021-April 28th (A3)

page5：mount CE44, change High screen to Hi-Z

page6：delete CE33/CE34/CE35/UE04
page7：Add CM64/CM65/CM66/CM67 because of MTK reference layout has much more capacitors, delete RM01/RM02
page11：change YM1 tolerance
page12： Add DM12,change CM55 to 33pF
page13：delete T-CONLESS I/O MOD_TX_P08/MOD_TX_N08 and so on, also delete DEMURA_CSn,GST_VST,TCON2
page14：delete T-CONLESS part
page16：change RL04 to 4.7K
page19：change RY03/RY05 to 18K
B page23：delete RT12/RT13/LT06/CT15/CT11/CT19/RT14/RT15 for easy layout, otherwise these component cannot close to SOC, B
change YT2 tolerance
page24：Add CU30/CU31
page24：delete N.A IR&KEY connector CONK2/DK07/CK02
page24: add RK21/CK10
page03: addDM13 to NC
page06：change LE03 to 1uH,RE22 to 240Ω
page07：change CM64 from NC to be fitted
page04：changeRE09 to 47K，RE1 5 t o 12K

2021-Jul 14th (A4)

page11：change board ID to0x04 DVT2
page12：Fit CM62/CM63
page16：change RL01/RL02 from 47K to 150K,CL13 to 10nF,keep the same with T-CON spec.requested
page9：delete SKTM1
page24:add RK25/RK26/QK02 for jira-216 issue.
page04:delete CE27(NC) for more place to LE01
2021-Jul 29h (A4)

page04：change LE01/LE02 to 4.7uH,change UE01 to TMI3244T/UE02 to TMI3253T,fit CE16/CE17,RE12 to 56K,RE18 to 2.2K

page05:change UE06 to MP2147,CE47 to NC,delete CE57,add RE54=10k,CE46 to 0.1uF,RE27 to 33Ω ,RE43 to 75K,RE53 to 13K,RE44 to 150K,
RE45 to 820K,RE48 to 220K,UE05 to TMI3411P
page06:change UE03 to TMI3411P
page24:change CK03 position to 1nF,change RK02 position,RK03 to 1K,CK01 to 33pF, meet CH's new standard,add CK11

A A

Athens - CH Design
Title
Revisions
Size Document Number Re v
Custom00294345 4

Date: Friday, August 20, 2021 Sheet 26 of 26

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