Tunneling Field

Effect Transistors
Rahim Esfandyarpour
June 12, 2012
Submitted as coursework for PH250,
Stanford University, Spring 2012

Quantum Tunneling
The Schrödinger formulation of
quantum mechanics presents an
interesting phenomenon where a particle
tunnels through an energy barrier,
similar to evanescent wave coupling of
electromagnetic waves. One
interpretation of this duality involves the
Heisenberg uncertainty principle, which
defines a limit on how precisely the
position and the momentum of a particle
can be known at the same time. This
implies that there are no solutions with a Fig. 1: Top: Schematic of a tunnel transistor
(TFET) architecture; Bottom: Energy band
probability of exactly zero (or one). diagram illustrating the TFET ON and OFF
Hence, the probability of a given state conditions.
particle's existence on the opposite side
of an intervening barrier is non-zero, and such particles will appear - with no
indication of physically transiting the barrier - on the 'other' side with a frequency
proportional to this probability.

Band-to-Band Tunneling
In TFETs tunneling of interest is band-to-band tunneling. For band-to-band tunneling
to occur, an electron in the valence band of semiconductor tunnels across the band gap
to the conduction band without the assistance of traps. The band gap acts as the
potential barrier that the particle tunnels across. An electron travels from the valance
band to the conduction band without the absorption or emission of photon in direct
tunneling. A tunneling particle acquires a change in momentum by absorbing or
emitting a phonon in the indirect tunneling process. In indirect semiconductors whose
gamma-centered direct band gap EΓ, is much greater than their indirect band gap,
EG indirect tunneling is the main tunneling process. The direct tunneling process is
negligible in indirect band gap materials like silicon because the transmission
probability decreases rapidly with increasing barrier height. The electron tunneling
through the band gap is akin to particle tunneling through a potential barrier, and the
most probable tunneling path the smallest barrier. For direct tunneling, the
requirement for conservation of perpendicular momentum causes an increase in the
tunneling. A particle with some perpendicular momentum in the valence band must
tunnel to state with the same perpendicular momentum in the conduction band, which
results in a longer tunneling path. In the indirect tunneling process, the phonon does
impart or absorb a change in the momentum of the particle. Therefore, the electron,
phonon interaction of the indirect tunneling process decouples the perpendicular
momentum of valence band and conduction band. An electron in the valence band can
tunnel to any state in the conduction band such that energy and perpendicular
momentum are conserved:

(1)

Where β is the wave vector of the phonon. Under the continuum approximation, β can
be any value so that kc⊥ is independent of kv⊥. However, the energy imparted for a
momentum transfer from Γ-valley maximum to the X-valley minimum by a transverse
acoustic phonon is approximately 18 meV. [1] Because this energy is quite small, the
approximation is made that no change in total energy occurs with the phonon
interaction, and the term ℏωβ is neglected. In field effect transistors, tunnelling occurs
with barriers of thickness around 1-3 nm and smaller in which the gate is controlled
via quantum tunnelling rather than by thermal injection, reducing gate voltage from
∼1 volt to 0.2 volts and reducing power consumption by up to 100x. If these
transistors can be scaled up into VLSI chips, they will significantly improve the
performance per power of integrated circuits.

Tunneling FET transistors

The tunnel field-effect transistor (TFET) belongs to the family of so-called steep-
slope devices that are currently being investigated for ultra-low-power electronic
applications. [2] A key feature of the TFET, which is critical for low-power switching,
is the possibility for an inverse sub threshold slope, S, below the limit of 60 mV/dec
for normal FETs. [3]
 (2)

The fundamental challenge for realizing commercially competitive TFETs is a limited

on-current level, which is typically addressed by creating higher doping levels and
abrupt doping profiles. [4] Fig. 1 shows a schematic of an n-channel TFET
architecture which incorporates a highly doped p+ source region, a near intrinsic
channel region and n+ drain region.

TFET is simply a gated p-i-n diode, which is operating under reverse bias condition.
In a MOSFET the source of carrier injection mechanism is thermal injection but a
TFET utilizes band-to-band tunneling as a source carrier injection mechanism. Fig. 1
shows the band diagrams of the n-channel TFET in the OFF and ON states. In the
OFF state, there is a wide potential barrier between the source and the channel, as a
result no tunneling is occurring. Only a very small leakage current exists. But when
the gate voltage exceeds the threshold voltage, the potential barrier between the
channel and the source becomes narrow enough to allow a significant tunneling
current, which is called ON state. Because of the different source carrier injection
mechanism in the TFET compare to a MOSFET, it can achieve sub-60-mV/dec S
(where S is the sub threshold slope) [3]. Wang et al. [5] showed the feasibility of the
TFET for low-power applications; some interesting studies have been reported. Zhang
et al. [6] provided a theoretical analysis that the S value of TFETs can be reduced
below 60 mV/dec.

TFET is an ambipolar device, it will show p-type behavior with dominant hole
conduction and n-type behavior with dominant electron conduction. But this
ambipolarity can be suppressed by designing an asymmetry in the doping level or
profile, or by restricting the movement of one type of charge carrier using
Heterostructures. In principle, because of the asymmetry TFETs can achieve much
higher ION-IOFF ratio over a given gate voltage swing compared to the MOSFETs,
making the TFET architecture an attractive vehicle to implement low supply voltage
(VDD) digital logic circuits. When a TFET is in its off state (Fig. 1 left), the valence
band edge of the channel is located below the conduction band edge of the source, so
BTBT is suppressed, leading to very small TFET off-state currents that are dictated by
the reverse-biased p-i-n diode. Applying a negative gate voltage pulls the energy
bands up.

A conductive channel opens as soon as the channel valence band has been lifted above
the source conduction band because carriers can now tunnel into empty states of the
channel. Because only carriers in the energy window ΔΦ can tunnel into the channel,
the energy distribution of carriers from the source is limited; the high-energy part of
the source Fermi distribution is effectively cut off, as shown in Fig. 2 (left). Thus the
electronic system is effectively 'cooled down', acting as a conventional MOSFET at a
lower temperature. This filtering function is the reason why we are able to achieve an
S of below 60mV per decade (Fig. 2 right). However, the channel valence band can be
lifted by a small change in gate voltage, and the tunneling width can effectively be
reduced by the gate voltage. S in a TFET is not constant, As a consequence of the
BTBT mechanism, but it depends on the applied gate-source bias, as indicated in Fig.
2 (right), increasing with the gate-to-source bias. In a TFET S remains below 60 mV
per decade over several orders of magnitude of drain current and that's why you have
a better voltage scaling of a TFET than a MOSFET. One challenge in TFETs is to
realize high on currents because ION critically depends on the transmission probability,
TWKB, of the inter band tunnelling barrier. This barrier can be approximated by a
triangular potential, as indicated by the grey shading in Fig. 2 (left), so T can be
calculated using the Wentzel-Kramers-Brillouin (WKB) approximation:

(3)

Where m* is the effective mass and Eg is the bandgap. Here, λ is the screening
tunnelling length and describes the spatial extent of the transition region at the source-
channel interface; it depends on the specific device geometry. In a TFET, at constant
drain voltage, VD, the VG increase reduces λ and increases the energetic difference
between the conduction band in the source and the valence band in the channel (ΔΦ),
so that in a first approximation the drain current is a super exponential function of V G.
As a result, in contrast to the MOSFET, the point subthreshold swing of the TFET is
no longer a constant but strongly depends on V G. The smallest subthermal values
occur at the lowest gate voltages. A high on current requires a high transparency of
the tunnelling barrier, thus maximizing TWKB, which in the best case should be
unity. Eqn. (3) suggests optimized design approaches to boost the on current. WKB
approximation works properly in direct bandgap semiconductors, such as InAs, but
has limited accuracy for Si and Ge structures or when quantum effects and phonon
assisted tunnelling become dominant.
 Optimization of Tunneling
FETs
The goals for TFET optimization are to
simultaneously achieve the highest
possible ION, the lowest Savg over many
orders of magnitude of drain current, and
the lowest possible IOFF. To outperform
Fig. 2: Left: Schematic energy band profile for CMOS transistors, the target parameters
the off state (dashed blue lines) and the on for TFETs are: ION in the range of
state (red lines) in a p-type TFET. In the on hundreds of milliamperes; Savg far below
state electrons in the energy window, ΔΦ 60 mV per decade for five decades of
(green shading), can tunnel from the source current; ION/IOFF > 105; and VDD < 0.5 V.
conduction band into the channel valence
Because S decreases with the VG, TFETs
band. Electrons in the tail of the Fermi
distribution cannot tunnel because no empty are naturally optimized for low-voltage
states are available in the channel at their operation. To realize a high tunnelling
energy (dotted black line), so a slope of less current and a steep slope, the transmission
than 60 mV decade can be achieved. [7] probability of the source tunnelling barrier
should become close to unity for a small
change in VG. The WKB approximation suggests that the bandgap (E g), the effective
carrier mass (m*) and the screening tunnelling length (λ) should be minimized for high
barrier transparency. Whereas Eg and m* depend solely on the material system, λ is
strongly influenced by several parameters, such as the device geometry, dimensions,
doping profiles and gate capacitance. A small λ results in a strong modulation of the
channel bands by the gate. This requires a high-permittivity (high K) gate dielectric
with as low an equivalent oxide thickness as possible. Furthermore, the body
thickness of the channel should be minimized, showing in the best case one-
dimensional electronic transport behavior. The abruptness of the doping profile at the
tunnel junction is also important. To minimize the tunnelling barrier, the high source
doping level must fall off to the intrinsic channel in as short a width as possible. This
requires a change in the doping concentration of about 4-5 orders of magnitude within
a distance of only a few nanometres. Increasing the source doping reduces λ and may
lead to a slightly smaller energy barrier at the tunnel junction because of bandgap
narrowing. However, the energy filtering effect described above becomes effective
only if the Fermi energy in the source is not too large. [7]

Double Gate Tunneling FETs

In an integrated DG-CMOS/DG-Tunnel-FET process, the Tunnel FETs will benefit
from the added gate, such that the current will be at least doubled. In this way, the
ON-current is boosted, while the OFF-current, still in the femtoamperes or
picoamperes range, increases by the same factor but remains extremely low. It is
worth noting that, for ultrathin siliconon-insulator (SOI) MOSFETs, some reports
suggest that this improvement can be even higher when volume inversion takes place.
[8]

Temperature Dependence of Tunneling FETs

The temperature and voltage dependence of the GIDL effect in MOSFETs under low
electric field is investigated. The dependency of the GIDL current on the electric field
E can be expressed as

(4)

The parameter are given by A ∝ EG-7/4 and B ∝ EG3/2, with the band-gap energy EG.
From Eqn. (4) the GIDL current is derived to be very weak dependent on the
temperature. However a second effect exists at low electric field. Under low electric
field the GIDL current can be described by the Shockley-Read-Hall (SRH) model,
which has strong temperature dependence. Under higher electric field the GIDL
current is dominated by Band-to-Band tunneling which has weak temperature
dependence. Due to the comparable physical principle of the GIDL current and the
TFET, Eqn. (4) can be used to separate the SRH part of the TFET characteristic from
the Band-to-Band tunneling part. Hence, starting from a gate-to-source voltage of
approximately -1V the Band-to-Band tunneling is the dominant mechanism. Like for
the MOSFET the temperature dependency is changing with the voltage applied. For
the MOSFET the zero temperature coefficient point can be used for digital circuit
design to make the system performance independent of the temperature. For the TFET
the voltage where the change of the temperature dependence occurs is outside the
useable range. Hence, the combination of the MOSFET and the TFET can be used to
compensate for temperature effects. For analog circuits the temperature dependence
has to be verified in more detail. Obviously, the temperature effect of the TFET is
more comparable to the bipolar device. This may allow novel topologies for a "band-
gap"-like voltage reference circuit. [9]

High-k gate dielectric Tunneling FETs

An improved on-current and decreased subthreshold swing can be obtained by the
careful choice of a gate dielectric. Kathy Boucart Et al. compared 3 nm physical
thickness of Si3N4 and two high-k dielectrics with dielectric constants of 21 and 29
with SiO2. In addition to improved Ion, both the point and average subthreshold swing
improve as the result of the better gate coupling given by a high-k dielectric. The off
current is less than 1 fA for all materials. The on-current of a Tunnel FET does not
increase merely proportionally to the increase in the gate capacitance, as it would for a
conventional MOSFET. Their numerical simulation shows the Tunnel FETs
subthreshold swing continues to improve as the gate dielectric permittivity increases.
The swing for the conventional MOSFET hits its 60 mV/decade limit at room
temperature and cannot improve further. While high-k dielectrics have advantages for
device characteristics, when put directly in contact with a silicon channel, they can
lead to defects at the semiconductor/dielectric interface. Although Tunnel FETs might
be less sensitive to changes in channel mobility than MOSFETs since the transport
through the tunnel junction dominates over any scattering in the channel, standard
CMOS fabrication techniques require an interfacial layer between the high-k dielectric
and the silicon channel. High-k dielectrics bring additional challenges such as the
limitations of soft and hard dielectric breakdown. Depending on the characteristics of
fabricated high-k dielectric layers, it may be necessary to limit applied gate voltages.
[10]

Conclusion
Today TFETs represent the most promising steep-slope switch candidate, having the
potential to use a supply voltage significantly below 0.5 V and thereby offering
significant power dissipation savings. Because of their low off currents, they are
ideally suited for low-power and low-standby-power logic applications operating at
moderate frequencies. Other promising applications of TFETs include ultralow-power
specialized analog integrated circuits with improved temperature stability and low-
power SRAM.

The biggest challenge is to achieve high performance (high I ON) without degrading
IOFF, combined with an S of less than 60 mV per decade over more than four decades
of drain current. This requires the additive combination of the many technology
boosters which are available or under research.

© Rahim Esfandyarpour. The author grants permission to copy, distribute and display
this work in unaltered form, with attribution to the author, for noncommercial
purposes only. All other rights, including commercial rights, are reserved to the
author.

References
[1] H. Holonyak, Jr. et al., "Direct Observation of Phonons During Tunneling in
Narrow Junction Diodes." Phys. Rev. Lett. 3, 167 (1959).
[2] B. Ganjipour et al., "Tunnel Field-ffect Transistors Based on InP-GaAs
Heterostructure Nanowires," ACS Nano 6, 3109 (2012).

[3] W. Y. Choi et al., "Tunneling Field effect Transistors (TFETs) with Subthreshold
Swing (SS) Less Than 60 mV/dec", IEEE Electron Device Lett. 28, 743 (2007).

[4] J. I. Pankove, Optical Processes in Semiconductors (Dover, 2010).

[5] P.-F. Wang et al., "Complementary Tunneling Transistor for Low Power
Applications," Solid State Electron. 48, 2881 (2004).

[6] Q. Zhang, W. Zhao and A. Seabaugh, "Low-Subthreshold-Swing Tunnel

Transistors," IEEE Electron Device Lett. 27, 297 (2006).

[7] A. M. Ionescu and H. Riel, "Tunnel Field-Effect Transistors as Energy-Efficient

Electronic Switches", Nature 479, 329 (2011).

[8] F. Balestra et al., "Double-Gate Silicon-on-Insulator Transistor With Volume

Inversion: A New Device With Greatly Enhanced Performance," IEEE Electron
Device Lett. 8, 410 (1987).

[9] T. Nirschi et al., "The Tunneling Field Effect Transistor (TFET): The Temperature
Dependence, the Simulation Model, and Its Application," Proc. Intl. Symp. on
Circuits and Systems ICAS 3, 713 (2004).

[10] K. Boucart and A. M Ionescu, "Double-Gate Tunnel FET With High-κ Gate
Dielectric," IEEE Trans. Elect. Dev. 54, 1725 (2007).
Effect of Step Gate Work Function on InGaAs p-TFET for Low
Power Switching Applications
Sayed Md Tariful Azam,1,2 Abu Saleh Md Bakibillah,3,* Md Tanvir Hasan,2 and Md Abdus Samad
Kamal4,*
Bruno Romeira, Academic Editor and Antonio Di Bartolomeo, Academic Editor
Author information Article notes Copyright and License information Disclaimer

Associated Data
Data Availability Statement

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Abstract

In this study, we theoretically investigated the effect of step gate work

function on the InGaAs p-TFET device, which is formed by dual material
gate (DMG). We analyzed the performance parameters of the device for
low power digital and analog applications based on the gate work
function difference (∆ϕS-D) of the source (ϕS) and drain (ϕD) side gate
electrodes. In particular, the work function of the drain (ϕD) side gate
electrodes was varied with respect to the high work function of the
source side gate electrode (Pt, ϕS = 5.65 eV) to produce the step gate
work function. It was found that the device performance varies with the
variation of gate work function difference (∆ϕS-D) due to a change in the
electric field distribution, which also changes the carrier (hole)
distribution of the device. We achieved low subthreshold slope (SS) and
off-state current (Ioff) of 30.89 mV/dec and 0.39 pA/µm, respectively, as
well as low power dissipation, when the gate work function difference
(∆ϕS-D = 1.02 eV) was high. Therefore, the device can be a potential
candidate for the future low power digital applications. On the other
hand, high transconductance (gm), high cut-off frequency (fT), and low
output conductance (gd) of the device at low gate work function
difference (∆ϕS-D = 0.61 eV) make it a viable candidate for the future low
power analog applications.
Keywords: p-TFET, gate work function, dual material gate, InGaAs, low
power switching
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1. Introduction

The band-to-band tunneling transport mechanism of tunnel field effect

transistors (TFETs) allows the device to operate on low supply voltage
(VDD) and to overcome the subthreshold slope limit (SS ≥ 60 mV/dec) of
traditional metal oxide semiconductor field effect transistors (MOSFETs),
which makes TFET a potential candidate for the future low power
devices [1,2,3,4,5]. TFETs have lower power consumption in digital
circuits and have higher sensitivity and transconductance per unit of
current in analog circuits compared to the conventional MOSFETs
[1,3,6,7,8]. In particular, low and direct bandgap III–V materials have
attracted a lot of attention for TFET devices, due to their inherent
material properties (such as direct band gap, high electron mobility, and
low exciton binding energy) as compared to Si [2]. They have also higher
tunneling efficiency due to their shorter tunneling distance and lower
phonon emission. Among these materials, ternary III–V materials have a
higher degree of compositional dependency, allowing designers to fine-
tune the material properties to meet their requirements [9,10].
Moreover, nowadays, InGaAs is a very suitable material for TFET devices
leading to open new opportunities to make the compact integrated
circuits for next generation electronic as well as optoelectronic/photonic
applications [2].

Unlike n-TFETs, p-TFETs (usually n-i-p doping structure) with III–V

materials have built-in issues [2]. Due to the low conduction band
density of states of III–V materials, a heavily n-doped source of p-TFETs
induces large conduction band degeneracy, which causes exponential tail
from Fermi distribution and thus, SS is increased. The optimal source
doping should be lower than n-TFETs while focused on steep SS. On the
other hand, reduced source doping results in a lower electric field at the
tunnel junction, which reduces drain current (ID). To date, the counter
effect of doping on ID and SS has been subsidized by using
heterostructure or a heavily counter doped pocket between the source
and channel regions to achieve steep SS and high ID with high Ion/Ioff,
similar to n-TFETs (for complementary switching) [10,11,12,13]. In line
with this expectation, the dual material gate (DMG) design is a leading
contender for achieving steep SS and high ID, because it combines the
advantages of dual-material-gate and double-gate structures.

The DMG design was first proposed by Wei Long to suppress the short
channel effect of MOSFET devices [14], where it was shown that in DMG
devices instead of a single metal gate, two metal gates are positioned
laterally on the gate region and the gate contact on the source side has
higher work function than the gate contact on the drain side. The DMG
structure reduces the electric field on the drain region and hence, the
electric field is distributed, which increases channel efficiency. The
distributed electric field and higher peak on the source side of the
channel accelerate the charge carriers more rapidly, which makes DMG
devices a potential candidate for high-speed applications. The DMG
design is investigated in various recent devices, e.g., a DMG design in
CNT-FET is reported in [15], the applicability of DMG devices for digital
applications using gate-all-around (GAA) and GaN are reported in
[16,17] and the applicability of DMG devices for subthreshold analog/RF
applications are reported in [18,19]. The DMG designs are also explored
for TFETs [20,21,22,23,24].

However, to the best of our knowledge, no DMG design for the InGaAs p-
TFET device has been reported. For this paper, we investigated the DMG
design on an InGaAs p-TFET device in terms of the step gate work
function produced by the work function difference between the source
and drain side gate electrodes. The work function of the drain side gate
electrodes was regulated with reference to the high work function of the
source side gate electrodes to generate the step gate work function. Our
approach of using dual material gate with different work functions was
inspired by our previous work [17], where the performance of sub-10-
nm GaN-based DG-MOSFETs with different gate work function
combinations were investigated and it was found that the short-channel
effects (SCEs) can be significantly reduced using gates made of dual
materials. We inspected the device’s suitability for low-power digital and
analog applications by analyzing capacitance and performance
parameters. The results show improvements in Ion, Ioff, Ion/Ioff, SS, and DIBL
over the reported data in this domain [23]. The paper is organized as
follows. Section 2 describes the device structure and Section 3 provides
the computation methods. Section 4 presents the results of transfer
characteristics, output characteristics, and physical properties of the
device. Section 5 gives the capacitance characteristics of the device and
device level performance parameters for low power digital and analog
applications. Finally, Section 6 draws the conclusion.
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2. Device Structure

In this paper, a double gate p-TFET device has been studied using dual
material gate structure to improve the device performance. The
structure of the proposed p-type InGaAs DMG-TFET device is illustrated
in Figure 1, where the source, channel, and drain lengths are 5 nm, 20
nm, and 5 nm, respectively [5]. We considered gate width as 1 µm. For
the proposed device, a channel thickness of 10 nm and a physical gate
oxide (HfO2, ε = 22 ε0) thickness of 3 nm were used. Our study mainly
exploited a 2D simulation setup with cross-sectional view of the
proposed p-TFET device structure, where x- and y-axes are defined along
the channel length and channel thickness, respectively. The doping
concentrations, i.e., acceptor (NA) and donor (ND) of source and drain
regions were considered as 1 × 1019 cm−3 (ND) and 5 × 1018 cm−3 (NA),
respectively. In the channel region light, doping concentration of 1 ×
1016 cm−3 (ND) was used.
Figure 1

Schematic structure of the proposed double gate p-InGaAs TFET device.

The formation of step gate work function requires two types of gate
electrodes, e.g., high and low work function electrodes on the source side
(ϕS) and the drain side (ϕD), respectively. In this work, we considered the
same length for both electrodes, i.e., LϕS = LϕD = 10 nm. Since a high work
function source side gate electrode improves carrier efficiency in
channel under the ϕS region [20,24], we considered ϕS = 5.65 eV (Pt). On
the other hand, low work function gate electrodes such as Ni, Mo, and W
were employed in the ϕD region. In the literature, the gate electrodes on
the source are denoted as the tunneling (control) and auxiliary (screen)
gates, respectively [22,23,24]. The device performance is analyzed in
terms of step gate work function induced by the difference in work
function (∆ϕS-D) between the source side (ϕS) and the drain side (ϕD) gate
electrodes. The differences in work function (∆ϕS-D) considered in this
study are given in Table 1.

Table 1
Work function combinations and differences considered in this study.
Source Side Electrode, ϕS (eV) Drain Side Electrode, ϕD (eV) Work Function Difference, ∆ϕS-D (eV)

Pt (5.65) Ni (5.04) 0.61

Source Side Electrode, ϕS (eV) Drain Side Electrode, ϕD (eV) Work Function Difference, ∆ϕS-D (eV)

Mo (4.95) 0.70

W (4.63) 1.02

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3. Computational Methods

We conducted all simulations using Silvaco ATLAS TCAD [25] and the
simulation setup was adopted from our previous work [5] and Kim et al.
[9]. The carrier distribution was calculated using the Fermi model. To
compute the carrier recombination, we used the Shockley–Read–Hall
(SRH) and auger recombination models, as well as the bandgap
narrowing model that describes the high doping effect on the bandgap.
Low field mobility due to doping density was taken into account by the
concentration dependent mobility model, while field velocity saturation
was taken into account by the field dependent mobility model. We
considered quantum effects using the density gradient quantum
moments model [5,9]. To tunnel through the bandgap using trap states,
we used the trap assisted tunneling model with phonon scattering effect.
A nonlocal band-to-band tunneling model was used to explain nonlocal
interband tunneling effect. The on-state (source-to-channel) and off-
state (drain-to-channel) tunneling were considered as separate
tunneling regions. The tunneling probability T(E) is calculated as

T(E) =exp⎛⎝⎜−42m∗−−−−√E32/g3|e|ℏξ⎞⎠⎟

(1)

where
 m∗
is the effective mass,

Eg
is the bandgap energy,

ξ
is the electric field, and

ℏ
is the reduced Planck constant. The simulations were performed at room
temperature (300 K). In this paper, Ion and Ioff are considered as drain
current (ID) at VDD = VGS = −0.5 V and VDD = −0.5 V, VGS = 0 V, respectively.
The DIBL and SS were calculated at constant ID of 1 × 10−9 A/µm. The
simulations were also carried out at a frequency of 1 MHz.
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4. Results and Discussion

The transfer characteristics of the device for differences in work

functions are shown in Figure 2a. It is found that for the lowest work
function difference (∆ϕS-D = 0.61 eV), the device exhibits the highest
Ion (83.2 µA/µm) and Ioff (28.3 pA/µm). The inset figure of Figure 2a
shows that Ion decreases linearly from 83.2 µA/µm to 38.9 µA/µm when
the work function difference is increased from ∆ϕS-D = 0.61 eV to ∆ϕS-D =
1.02 eV. Figure 2b shows the output characteristics of the device at VGS =
−0.5 V, where the ID-VDD curve shows that the increasing rate of drain
current (ID) with respect to drain voltage (VDD) is higher for ∆ϕS-D = 0.61 eV
and ∆ϕS-D = 0.7 eV compared to ∆ϕS-D = 1.02 eV, which means that
saturation is not reached yet for ∆ϕS-D = 1.02 eV. Delayed saturation
characteristics of ∆ϕS-D = 1.02 eV can be improved by higher source
doping that reduces the source depletion [26]. On the other hand, higher
source doping increases SS of the device and introduces Fermi tail.

Figure 2

(a) Transfer characteristics (ID-VGS) at VDD = −0.5 V; inset shows Ion as a function of work
function difference (∆ϕS-D) and (b) output characteristics (ID-VDD) at VGS = −0.5 V.

The band profiles of the device for both off-state (VDD = −0.5 V, VGS = 0 V)
and on-state (VDD = VGS = −0.5 V) are shown in Figure 3. In a p-TFET, the
on-state negative gate bias shifts the bands up to align the conduction
band of the source region with the valence band of the channel region,
allowing holes to tunnel from the conduction band to the valence band.
In other words, the electron tunnels from the valence band of the
channel region to the conduction band of the source region. In this
condition, the potential of the high work function gate electrode is higher
than the potential of the low work function gate electrode for the same
applied negative gate bias and the effect is reflected in the channel
region. It is found that in the ϕS region, a high work function gate
electrode Pt causes both the conduction band and the valence band to
have a high potential in all ∆ϕS-D conditions. On the contrary, both the
conduction band and the valence band have lower potential in the
ϕD region (under the low work function electrode) than in the ϕS region,
and their potential varies according to the work function of the gate
electrodes. As a result, the energy bands of device in the channel region
show step-like (or undulated) features. Furthermore, a lower potential in
the ϕD region indicates that carriers in that region have less energy.
Hence, the drain to channel tunneling probability is low in the off-state.

Figure 3

Conduction band (CB) and valance band (VB) profiles along the channel—dot line: off-state
(VDD = −0.5 V, VGS = 0 V), solid line: on-state (VDD = VGS = −0.5 V).

The fluctuation of Ioff, Ion/Ioff, SS, and DIBL as a function of gate work
function difference (∆ϕS-D) is shown in Figure 4a,b. When the work
function difference is increased from 0.61 eV to 1.02 eV, Ioff reduces on
logarithmic scale from 28.3 pA/m to 0.39 pA/m. As a result, at ∆ϕS-D =
1.02 eV, the highest Ion/Ioff ratio of 9.94 × 107 is obtained. It is also
observed that SS drops with an increase in ∆ϕS-D. The lowest SS of 30.89
mV/dec is achieved for ∆ϕS-D = 1.02 eV. The highest SS of 37.84 mV/dec is
observed when ∆ϕS-D = 0.61 eV, which is still less than the traditional SS
limit of 60 mV/dec. Unlike SS, the DIBL of the device increases with the
increase of ∆ϕS-D. We found approximately the same DIBL for ∆ϕS-D = 0.61
eV and ∆ϕS-D = 0.7 eV, which are 49.25 mV/V and 49.81 mV/V,
respectively. In the case of ∆ϕS-D = 1.02 eV, the highest DIBL of 59.41
mV/V is achieved.

Figure 4

(a) Ioff and Ion/Ioff and (b) SS and DIBL as a function of work function difference (∆ϕ S-D).

The surface potential of the device in the off-state (VDD = −0.5 V, VGS = 0 V)
and on-state (VDD = VGS = −0.5 V) is shown in Figure 5. The negative drain
bias and gate bias reduce the surface potential in the drain and channel
regions, respectively, while the surface potential in the grounded source
region remains higher. However, in the channel region, the surface
potential varies according to the work function difference (∆ϕS-D). Hence,
the highest and lowest surface potentials in the channel region,
respectively, are caused by high work function difference (∆ϕS-D = 1.02
eV) and low work function difference (∆ϕS-D = 0.61 eV). The surface
potential of single material gate devices remains constant through the
channel region according to their work function. However, the surface
potential of dual material gate devices introduces a step-like feature in
the channel region according to their respective work functions [16,23].
Figure 5

Surface Potential along the channel—dot line: off-state (VDD = −0.5 V, VGS = 0 V), solid line:
on-state (VDD = VGS = −0.5 V).

As shown in Figure 5, a high work function electrode has a strong impact

in the ϕS region. As a result, the surface potential dips in the middle of
the ϕS region, forming a trough. On the other hand, a low work function
in the ϕD region increases surface potential in the middle of ϕD region,
creating a crest that shades the ϕS region from the high drain bias (VDD)
effect. As a result, the surface potential difference between the ϕS and
ϕD regions forms the step-like feature in the channel region. When ∆ϕS-D =
0.61 eV and 0.7 eV, the surface potential in the crest is lower than the
trough surface potential; therefore, it is approximately constant (small
gradient) around the metal junction. However, when ∆ϕS-D = 1.02 eV, the
crest and trough surface potentials are approximately the same, and the
surface potential becomes constant (flat) around the metal junction.

Figure 6a,b show the electric field and hole velocity of the device,
respectively. The high electric field in the tunnel junction of the source
and channel region is nearly the same in all circumstances due to the
same ϕS electrode. The electric field fluctuates with ϕD in the drain
region, with the largest peak occurring at the channel–drain junction for
a high work function difference (∆ϕS-D = 1.02 eV). The work function
difference between two electrodes raises negative peaks around the
junction [23,24], as shown in the inset of the figure. It is found that a low
work function difference (∆ϕS-D = 0.61 eV) has the lowest negative peak.
On the contrary, a high work function difference (∆ϕS-D = 1.02 eV) has the
two highest negative peaks. The opposite potential trend appears at the
transition of the two gates is responsible for negative electric field peaks
[24]. Since the carrier velocity (here, majority carriers are holes) are
proportional to the electric field, in Figure 6b, the hole velocity imitates
the peaks of the electric field curves. Like the electric field, hole velocity
is high at the source–channel junction and nearly constant in all
circumstances. The hole velocity drops around the junction of two
electrodes and has negative peaks. Then, the velocity increases again
towards the drain.

Figure 6

(a) Electric Field; inset shows zoomed electric field at the circled region and (b) Hole
velocity along the channel at on-state (VDD = VGS = −0.5 V).

The on-state hole concentration contour plots of the device for different
cases are shown in Figure 7. In Figure 7a, the hole concentration in the
ϕS region is higher than the ϕD region for ∆ϕS-D = 0.61 eV. In Figure 7b, the
hole concentration becomes confined in the ϕS region for ∆ϕS-D = 0.7 eV. It
is found that the hole concentration in the ϕD and drain regions are lower
than the previous case. In these two cases, holes are distributed from the
ϕS region to the drain region. However, in Figure 7c, holes are more
confined in the ϕS region near the metal junction, and poorly distributed
in the ϕD and drain regions when ∆ϕS-D = 1.02 eV. Note that, in all cases,
the hole concentration in the ϕS region is higher on semiconductor–
dielectric material interface than the middle of the channel (along y-
axis). On the contrary, in the ϕD region, holes are only distributed in the
middle of the channel (along y-axis). When compared to the electric
fields of the device in Figure 6a, it appears that the electric field
decreases as hole confinement increases in the ϕS region. The device’s
performance parameters for digital and analog applications are
examined in the next section.

Figure 7

Hole concentration contours at on-state (VDD = VGS = −0.5 V) for (a) ∆ϕS-D = 0.61 eV, (b) ∆ϕS-D =
0.7 eV, and (c) ∆ϕS-D = 1.02 eV.
Go to:

5. Performance Parameter Analysis

5.1. Capacitance Analysis

We started by examining the device’s C-V curves for different gate work
functions (as shown in Figure 8), as capacitance characteristics are
crucial in analyzing both digital and analog device performance.
In Figure 8a, a high work function electrode (Pt) on the ϕS region results
in a high gate-to-source (CGS) capacitance. On the other hand, low work
function materials on the ϕD region reduce gate-to-drain (CGD)
capacitances in all circumstances. Hence, we achieved a negligible miller
effect, which has been a significant concern for TFET devices [27], and
reduced output voltage overshoot and undershoot is expected in large-
signal transient response in all circumstances. Moreover, Figure 8a
shows that for ∆ϕS-D = 1.02 eV, both gate-to-source (CGS) and gate-to-drain
(CGD) capacitances are higher than the other two cases. Figure 8b depicts
the total (gate) capacitance (CGG~CGS + CGD), which exhibits the similar
characteristics, with the highest and lowest total (gate) capacitance (C GG)
being ∆ϕS-D = 1.02 eV and ∆ϕS-D = 0.61 eV, respectively. The total (gate)
capacitance (CGG) remains approximately the same when ∆ϕS-D = 0.61 eV
and ∆ϕS-D = 0.7 eV.

Figure 8

(a) Dot line: Gate-to-Drain (CGD) and solid line: Gate-to-Source (CGS) capacitance (b) total
capacitance (CGG) as a function of Gate Voltage (VGS) at VDD = −0.5 V.

5.2. Digital Performance Parameters

To investigate the device’s digital performance, different parameters

were considered, e.g., intrinsic speed (τ = CGGVDD/Ion), leakage power (Pleak =
nIoffVDD), dynamic power (Pdyn = 0.5 × nIonVDDα), total power (Ptotal = Pleak +
Pdyn), dynamic energy (Edyn = 0.5 × nCGGV2DDα), leakage energy (Eleak =
n2IoffVDDτ), and total energy (Etotal = Eleak + Edyn). The logic depth n = 50 and
activity factor α = 2% were used [28]. The calculated values of these
parameters are listed in Table 2.

Table 2
Digital performance parameters.
∆ϕS-D (eV)

Parameters 0.61 0.7 1.02

τ (ps) 2.22 2.55 5.07

Pleak (µW/µm) 7.09 × 10−4 4.53 × 10−5 9.77 × 10−6

Pdyn (µW/µm) 20.8 18.2 9.71

Ptotal (µW/µm) 20.8 18.2 9.71

Eleak (aJ/µm) 78.6 × 10−3 5.77 × 10−3 2.47 × 10−3

Edyn (aJ/µm) 46.2 46.4 49.2

Etotal (aJ/µm) 46.2 46.4 49.2

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It is found that the highest gate capacitance (CGG) at ∆ϕS-D = 1.02 eV results
in ~2 times higher intrinsic speed (τ). The leakage power (Pleak) is
proportional to Ioff and therefore, Pleak dissipation at ∆ϕS-D = 1.02 eV is
~13.78 × 10−3 times lower than at ∆ϕS-D = 0.61 eV. In addition, the lowest
Ion at ∆ϕS-D = 1.02 eV results in the lowest dynamic power (Pdyn). Therefore,
∆ϕS-D = 1.02 eV has the lowest total power (Ptotal) dissipation. A high gate
capacitance (CGG) of ∆ϕS-D = 1.02 eV slightly increases the dynamic energy
consumption (Edyn) of the device than other cases of ∆ϕS-D. In spite of the
highest intrinsic speed (τ) at ∆ϕS-D = 1.02 eV, the lowest Ioff of the device
gives the lowest leakage energy consumption (Eleak). The result shows
that the dynamic component of power and energy of the device play the
key role in total power (Ptotal) dissipation and energy (Etotal) consumption
of the device for different ∆ϕS-D. Since the low power device is the
primary concern for modern digital applications, with the lowest power
dissipation at ∆ϕS-D = 1.02 eV (about half of the other two cases and
slightly higher energy consumption), the high work function difference
model fits well for digital application requirements.

5.3. RF Performance Parameters

The device’s RF performance was measured in terms of

transconductance (gm = ID/VGS), output conductance (gd = dID/dVDD), cut-off
frequency (fT = gm/2πCGG), and transconductance generation factor (TGF =
gm/ID). Figure 9a,b shows the transconductance (gm) and cut-off frequency
(fT) of the device for different ∆ϕS-D as a function of gate voltage (VGS).
In Figure 9a, the inset figure shows the output conductance (gd) as a
function of ∆ϕS-D at VGS = −0.5 V. High transconductance (gm) ensures high
amplification and high cut-off frequency (fT) is the key parameter for
high-speed applications to analyze the device’s gain [29]. The highest
drain current (ID) at ∆ϕS-D = 0.61 eV results in the highest
transconductance gm (426.29 µS/µm), which is ~1.605 times higher than
∆ϕS-D = 1.02 eV. The lowest output conductance (gd) and highest
transconductance (gm) of ∆ϕS-D = 0.61 eV result in the highest voltage gain
(Av = gm/gd), as seen in the inset of Figure 9a. The lowest gate capacitance
(CGG) and highest transconductance of the device at ∆ϕS-D = 0.61 eV also
gives the highest cut-off frequency fT = 183.72 GHz, which is 1.71 times
higher than at ∆ϕS-D = 1.02 eV. Figure 9c depicts the device’s
transconductance generation factor (TGF) as a function of drain current
(ID), which is a key parameter for low power analog subthreshold
applications [30]. It is referred to as the transconductance-to-current
ratio (gm/Id) as well as device efficiency in the literature [29]. It measures
the efficiency of the device to convert current (power) into
transconductance (speed) [31]. Due to steep SS of the device at ∆ϕS-D =
1.02 eV, the TGF is also found to be steep. Here, all cases match the
traditional FET limit (38.5 µS/µA) for the same drain current (ID). In the
subthreshold region, ∆ϕS-D = 0.61 eV has higher TGF than ∆ϕS-D = 0.7 eV
and lower TGF than ∆ϕS-D = 1.02 eV. In capacitive load circuits, a lower
TGF implies lower input drivability, which indicates higher power
dissipation. On the other hand, higher TGF costs in terms of linearity of
the device [30]. With the highest transconductance (gm), voltage gain (Av),
and cut-off frequency (fT), the device at ∆ϕS-D = 0.61 eV can be a suitable
candidate for future low-power analog applications.

Figure 9

(a) Transconductance (gm), (b) cut-off frequency (fT) as function of Gate Voltage (VGS), and
(c) transconductance to current ratio (gm/Id) as function of drain current (Id) at V DD = −0.5
V; inset shows output conductance (gd) at VDD = VGS = −0.5 V as a function of work function
difference (∆ϕS-D).
Go to:

6. Conclusions

In this paper, we have investigated the effect of step gate work function
on the InGaAs p-TFET device based on the gate work function difference
(∆ϕS-D) of the source (ϕS) and drain (ϕD) side gate electrodes. Firstly, we
have analyzed the transfer and output characteristics, and physical
properties of the device. The results show that the work function
difference (∆ϕS-D) changes the electric field on the channel by creating a
potential difference in energy bands between the ϕS and ϕD regions. We
achieved the lowest SS (30.86 mV/dec), Ioff (0.39 × 10−12 A/µm), and
minimum Ion/Ioff ratio (9.97 × 107) for high work function difference ∆ϕS-
D = 1.02 eV. Finally, we have explored the digital and analog performance

parameters at the device level. It is found that the device with a high
work function difference ∆ϕS-D = 1.02 eV dissipates the least amount of
power and consumes the least amount of leakage energy, making it
suitable for digital applications. On the other hand, a low work function
difference ∆ϕS-D = 0.61 eV results in the lowest output conductance
gd (29.4 µS/µm), maximum transconductance gm (426 µS/µm), and cut-off
frequency fT (184 GHz). At ∆ϕS-D = 0.61 eV, the lowest gd and highest
gm produce the largest voltage gain, which is an important parameter in
analog applications. The findings reveal that the InGaAs p-TFET can be
used for both low-power digital and analog applications by tuning the
step gate work function of the device. From the above discussion, we can
conclude that InGaAs TFETs will be suitable for future low-power
integrated switching circuit applications.

Go to:

Author Contributions

Conceptualization, S.M.T.A., A.S.M.B. and M.T.H.; methodology, S.M.T.A.

and A.S.M.B.; validation, A.S.M.B. and M.T.H.; formal analysis, S.M.T.A.;
investigation, M.A.S.K.; data curation, S.M.T.A.; writing—original draft
preparation, S.M.T.A.; writing—review and editing, A.S.M.B., M.T.H. and
M.A.S.K.; visualization, S.M.T.A.; supervision, A.S.M.B., M.T.H. and
M.A.S.K.; project administration, A.S.M.B. and M.A.S.K. All authors have
read and agreed to the published version of the manuscript.

Go to:

Funding

This research was supported by the authors’ institutions without

involving any external funding.

Go to:
Data Availability Statement

Not applicable.

Go to:

Conflicts of Interest

The authors declare no conflict of interest. The funders had no role in the
design of the study; in the collection, analyses or interpretation of data;
in the writing of the manuscript, or in the decision to publish the results.

Go to:

Footnotes

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published

maps and institutional affiliations.

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References
1. Datta S., Bijesh R., Liu H., Mohata D., Narayanan V. Tunnel transistors for energy
efficient computing. IEEE Int. Reliab. Phys. Symp. 2013:6A.3.1–6A.3.7.
doi: 10.1109/IRPS.2013.6532046. [CrossRef] [Google Scholar]
2. Lu H., Seabaugh A. Tunnel field-effect transistors: State-of-the-art. IEEE J. Electron
Devices Soc. 2014;2:44–49. doi: 10.1109/JEDS.2014.2326622. [CrossRef] [Google
Scholar]
3. Datta S., Liu H., Narayanan V. Tunnel FET technology: A reliability
perspective. Microelectron. Reliab. 2014;54:861–874.
doi: 10.1016/j.microrel.2014.02.002. [CrossRef] [Google Scholar]
4. Fischer I.A., Bakibillah A.S.M., Golve M., Hahnel D., Isemann H., Kottantharayil A.,
Oehme M., Schulze J. Silicon tunneling field-effect transistors with tunneling in line
with the gate field. IEEE Electron Device Lett. 2012;34:154–156.
doi: 10.1109/LED.2012.2228250. [CrossRef] [Google Scholar]
5. Azam S.M.T., Bakibillah A.S.M., Kamal M.A.S. Performance Evaluation of InGaAs
Dielectric Engineered Tunnel Field-Effect Transistors. J. Nano Res. 2019;59:149–
160. doi: 10.4028/www.scientific.net/JNanoR.59.149. [CrossRef] [Google Scholar]
6. Sedighi B., Hu X.S., Liu H., Nahas J.J., Niemier M. Analog Circuit Design Using
Tunnel-FETs. IEEE Trans. Circuits Syst. I Regul. Pap. 2014;62:39–48.
doi: 10.1109/TCSI.2014.2342371. [CrossRef] [Google Scholar]
7. Biswas A., Luong G.V., Chowdhury M.F., Alper C., Zhao Q.T., Udrea F., Mantl S.,
Ionescu A.M. Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic
Analog Functions. IEEE Trans. Electron Devices. 2017;64:1441–1448.
doi: 10.1109/TED.2017.2665527. [CrossRef] [Google Scholar]
8. Settino F., Lanuzza M., Strangio S., Crupi F., Palestri P., Esseni D., Selmi L.
Understanding the potential and limitations of tunnel FETs for low-voltage
analog/mixed-signal circuits. IEEE Trans. Electron Devices. 2017;64:2736.
doi: 10.1109/TED.2017.2689746. [CrossRef] [Google Scholar]
9. Kim Y.J., Yoon Y.J., Seo J.H., Lee S.M., Cho S., Lee J.H., Kang I.M. Effect of Ga fraction
in InGaAs channel on performances of gate-all-around tunneling field-effect
transistor. Semicond. Sci. Technol. 2014;30:015006. doi: 10.1088/0268-
1242/30/1/015006. [CrossRef] [Google Scholar]
10. Knoch J., Appenzeller J. Modeling of high-performance p-type III-V
heterojunction tunnel FETs. IEEE Electron Device Lett. 2010;31:305–307.
doi: 10.1109/LED.2010.2041180. [CrossRef] [Google Scholar]
11. Verhulst A.S., Verreck D., Pourghaderi M.A., Van de Put M., Soree B., Groeseneken
G., Collaert N., Thean A.Y. Can p-channel tunnel field-effect transistors perform as
good as n-channel? Appl. Phys. Lett. 2014;105:043103.
doi: 10.1063/1.4891348. [CrossRef] [Google Scholar]
12. Verreck D., Verhulst A.S., Sorée B., Collaert N., Mocuta A., Thean A., Groeseneken
G. Improved source design for p-type tunnel field-effect transistors: Towards truly
complementary logic. Appl. Phys. Lett. 2014;105:243506.
doi: 10.1063/1.4904712. [CrossRef] [Google Scholar]
13. Huang J.Z., Long P., Povolotskyi M., Klimeck G., Rodwell M.J. P-type tunnel FETs
with triple heterojunctions. IEEE J. Electron Devices Soc. 2016;4:410–415.
doi: 10.1109/JEDS.2016.2614915. [CrossRef] [Google Scholar]
14. Long W., Ou H., Kuo J.M., Chin K.K. Dual-material gate (DMG) field effect
transistor. IEEE Trans. Electron Devices. 1999;46:865–870.
doi: 10.1109/16.760391. [CrossRef] [Google Scholar]
15. Orouji A.A., Arefinia Z. Detailed simulation study of a dual material gate carbon
nanotube field-effect transistor. Phys. E Low-Dimens. Syst. Nanostruct. 2009;41:552–
557. doi: 10.1016/j.physe.2008.10.005. [CrossRef] [Google Scholar]
16. Djeffal F., Lakhdar N., Yousfi A. An optimized design of 10-nm-scale dual-
material surrounded gate MOSFETs for digital circuit applications. Phys. E Low-
Dimens. Syst. Nanostruct. 2011;44:339–344.
doi: 10.1016/j.physe.2011.09.007. [CrossRef] [Google Scholar]
17. Mehedi I.M., Alshareef A.M., Islam M.R., Hasan M.T. GaN-based double-gate (DG)
sub-10-nm MOSFETs: Effects of gate work function. J. Comput.
Electron. 2018;17:663–669. doi: 10.1007/s10825-017-1119-z. [CrossRef] [Google
Scholar]
18. Chakraborty S., Mallik A., Sarkar C.K. Subthreshold performance of dual-material
gate CMOS devices and circuits for ultralow power analog/mixed-signal
applications. IEEE Trans. Electron Devices. 2008;55:827–832.
doi: 10.1109/TED.2007.914842. [CrossRef] [Google Scholar]
19. Kundu A., Koley K., Dutta A., Sarkar C.K. Impact of gate metal work-function
engineering for enhancement of subthreshold analog/RF performance of underlap
dual material gate DG-FET. Microelectron. Reliab. 2014;54:2717–2722.
doi: 10.1016/j.microrel.2014.08.009. [CrossRef] [Google Scholar]
20. Saurabh S., Kumar M.J. Novel attributes of a dual material gate nanoscale tunnel
field-effect transistor. IEEE Trans. Electron Devices. 2010;58:404–410.
doi: 10.1109/TED.2010.2093142. [CrossRef] [Google Scholar]
21. Lv Y., Huang Q., Wang H., Chang S., He J. A numerical study on graphene
nanoribbon heterojunction dual-material gate tunnel FET. IEEE Electron Device
Lett. 2016;37:1354–1357. doi: 10.1109/LED.2016.2597155. [CrossRef] [Google
Scholar]
22. Noor S.L., Safa S., Khan M.Z.R. Dual-material double-gate tunnel FET: Gate
threshold voltage modeling and extraction. J. Comput. Electron. 2016;15:763–769.
doi: 10.1007/s10825-016-0816-3. [CrossRef] [Google Scholar]
23. Vishnoi R., Kumar M.J. Compact analytical model of dual material gate tunneling
field-effect transistor using interband tunneling and channel transport. IEEE Trans.
Electron Devices. 2014;61:2264–2270.
doi: 10.1109/TED.2014.2315294. [CrossRef] [Google Scholar]
24. Zhang A., Mei J., Zhang L., He H., He J., Chan M. Numerical study on dual material
gate nanowire tunnel field-effect transistor; Proceedings of the IEEE International
Conference on Electron Devices and Solid-State Circuit (EDSSC); Bangkok, Thailand.
3–5 December 2012; pp. 1–5. [Google Scholar]
25. SILVACO . ATLAS User’s Manual. SILVACO; Santa Clara, CA, USA: 2014. [Google
Scholar]
26. Rajamohanan B., Mohata D., Ali A., Datta S. Insight into the output characteristics
of III-V tunneling field effect transistors. Appl. Phys. Lett. 2013;102:092105.
doi: 10.1063/1.4794536. [CrossRef] [Google Scholar]
27. Mookerjea S., Krishnan R., Datta S., Narayanan V. On enhanced Miller capacitance
effect in interband tunnel transistors. IEEE Electron Device Lett. 2009;30:1102–
1104. doi: 10.1109/LED.2009.2028907. [CrossRef] [Google Scholar]
28. Zhang Q., Seabaugh A. Can the interband tunnel FET outperform Si CMOS?;
Proceedings of the IEEE Device Research Conference; Monterey, CA, USA. 15–19
September 2008; pp. 73–74. [Google Scholar]
29. Kondekar P.N., Nigam K., Pandey S., Sharma D. Design and Analysis of Polarity
Controlled Electrically Doped Tunnel FET With Bandgap Engineering for Analog/RF
Applications. IEEE Trans. Electron Devices. 2016;64:412–418.
doi: 10.1109/TED.2016.2637638. [CrossRef] [Google Scholar]
30. Sarkar A., Das A.K., De S., Sarkar C.K. Effect of gate engineering in double-gate
MOSFETs for analog/RF applications. Microelectron. J. 2012;43:873–882.
doi: 10.1016/j.mejo.2012.06.002. [CrossRef] [Google Scholar]
31. Madan J., Chaujar R. Interfacial charge analysis of heterogeneous gate dielectric-
gate all around-tunnel FET for improved device reliability. IEEE Trans. Device Mater.
Reliab. 2016;16:227–234. doi: 10.1109/TDMR.2016.2564448. [CrossRef] [Google
Scholar]