5 4 3 2 1

Table of Contents Revisions

2 Notes and Block Diagram Rev Description Date Approved

3 S32K144 MCU XA Initial Release APR-13-2016 O. Romero

4 OpenSDA interface A Prototype Production APR-14-2016 O. Romero
5 Power Supply/SWD AX1 Development AUG-16-2016 O. Romero
6 I/O Headers B 2nd Release SEP-02-2016 O. Romero
B1 Update BOM DEC-16-2016 O. Romero
C Update BOM MAR-1-2018 A. Gonzalez

D D

C C

S32K144EVB-Q100

B B

A A
Automotive Product Group
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: ____ IUO: ____ PUBI: _X___

Designer: Drawing Title:
Osvaldo Romero
S32K144EVB-Q100
Drawn by: Page Title:
Osvaldo Romero TITLE PAGE
Approved: Size Document Number Rev
APPROVER C SCH-29248 PDF: SPF-29248 C

Date: Monday, March 19, 2018 Sheet 1 of 6

5 4 3 2 1
 5 4 3 2 1

1. Unless Otherwise Specified:

All resistors are in ohms, 1% and 5 %
All capacitors are in uF, 10% , 20 % and 5%
All voltages are DC
All polarized capacitors are aluminum electrolytic

2. Interrupted lines coded with the same letter or letter

combinations are electrically connected.
D D
3. Device type number is for reference only. The number
varies with the manufacturer.

4. Special signal usage:

_B Denotes - Active-Low Signal
<> or [] Denotes - Vectored Signals
5. Interpret diagram in accordance with American
National Standards Institute specifications, current
revision, with the exception of logic block symbology.

C C

B B

A A

ICAP Classification: CP: ___ IUO: ____ PUBI: _X___

Drawing Title:
S32K144EVB-Q100
Page Title:
Notes and Block Diagram
Size Document Number Rev
C SCH-29248 PDF: SPF-29248 C

Date: Monday, March 19, 2018 Sheet 2 of 6

5 4 3 2 1
 5 4 3 2 1

VDD_MCU VREFH

D D

C129 C131 C140 C141 C142 C143 C144 C133 C146 C137 C147 C148
10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF DNP DNP DNP DNP 0.1uF

11

10

38

61

87

12
13
U17

VDDA

VDD1

VDD2

VDD3

VDD4

VREFH
VREFL
79
P[6] PTA0 PTA0/ADC0_SE0/ACMP0_IN0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3 PTD0 P[6]
78 4 0 R156
P[6] PTA1 PTA1/ADC0_SE1/ACMP0_IN1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0 PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/FXIO_D0/TRGMUX_OUT1/HDPIN RGB_BLUE P[6]
73 3
P[6] PTA2 PTA2/ADC1_SE0/FTM3_CH0/LPI2C0_SDA/EWM_OUT/LPUART0_RX PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/FXIO_D1/TRGMUX_OUT2/HDPIN PTD1 P[6]
72 71
P[6] PTA4 P[6] PTA3 PTA3/ADC1_SE1/FTM3_CH1/LPI2C0_SCL/EWM_IN/LPUART0_TX PTD2/ADC1_SE2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/TRGMUX_IN5 PTD2 P[6]
R122 0 98 70
P[4,5] JTAG_TMS/SWD_DIO_PTA4 PTA4/ACMP0_OUT/EWM_OUT/JTAG_TMS/SWD_DIO PTD3/ADC1_SE3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/TRGMUX_IN4/NMI PTD3 P[6]
97 69
P[4,5,6] RST_TGTMCU_B PTA5/TCLK1/JTAG_TRST/RESET PTD4/ADC1_SE6/FTM0_FLT3/FTM3_FLT3 PTD4 P[6] PTD6 P[6]
58 33 R130 0
P[6] PTA6 PTA6/ADC0_SE2/ACMP1_IN0/FTM0_FLT1/LPSPI1_PCS1/LPUART1_CTS PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/TRGMUX_IN7 PTD5 P[6] LIN_RX P[5]
57 32
P[6] PTA7 PTA7/ADC0_SE3/ACMP1_IN1/FTM0_FLT2/RTC_CLKIN/LPUART1_RTS PTD6/ACMP0_IN7/LPUART2_RX/FTM2_FLT2 PTD7 P[6]
100 31 R131 0
P[6] PTA8 PTA8/LPUART3_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3 PTD7/ACMP0_IN6/LPUART2_TX/FTM2_FLT3 LIN_TX P[5]
99 42
P[6] PTA10 P[6] PTA9 PTA9/LPUART3_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2/FTM1_FLT3 PTD8/LPI2C1_SDA/FTM2_FLT2/FTM1_CH4 PTD8 P[6]
R123 0 92 41
P[5] JTAG_TDO PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO/NOETM_TRACE_SWO PTD9/LPI2C1_SCL/FTM2_FLT3/FTM1_CH5 PTD9 P[6]
91 36
P[6] PTA11 PTA11/FTM1_CH5/FXIO_D1 PTD10/FTM2_CH0/FTM2_QD_PHB PTD10 P[6]
90 35
P[6] PTA12 PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS PTD11/FTM2_CH1/FTM2_QD_PHA/LPUART2_CTS PTD11 P[6]
89 34
P[6] PTA13 PTA13/FTM1_CH7/CAN1_TX/LPI2C1_SCLS PTD12/FTM2_CH2/LPI2C1_HREQ/LPUART2_RTS PTD12 P[6]
88 25
P[6] PTA14 PTA14/FTM0_FLT0/FTM3_FLT1/EWM_IN/FTM1_FLT0/BUSOUT PTD13/FTM2_CH4/LPUART3_RX/RTC_CLKOUT PTD13 P[6] PTD15 P[6]
83 24 R154 0
P[6] PTA15 PTA15/ADC1_SE12/FTM1_CH2/LPSPI0_PCS3/LPSPI2_PCS3 PTD14/FTM2_CH5/LPUART3_TX/CLKOUT PTD14 P[6] RGB_RED P[6]
82 22
P[6] PTA16 PTA16/ADC1_SE13/FTM1_CH3/LPSPI1_PCS2 PTD15/FTM0_CH0/HDPIN PTD16 P[6]
P[6] PTA17 62 21 R155 0 RGB_GREEN P[6]
PTA17/FTM0_CH6/FTM3_FLT0/EWM_OUT PTD16/FTM0_CH1/HDPIN 20
PTD17/FTM0_FLT2/LPUART2_RX PTD17 P[6]
54
P[6] PTB0 PTB0/ADC0_SE4/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3
53 94
P[6] PTB1 PTB1/ADC0_SE5/LPUART0_TX/LPSPI0_SOUT/TCLK0 PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/FTM1_FLT2/HDPIN PTE0 P[6]
48 93
P[6] PTB2 PTB2/ADC0_SE6/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3 PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/FTM1_FLT1/HDPIN PTE1 P[6]
P[6] PTB3 47 85 PTE2 P[6] PTE4 P[6]
28 PTB3/ADC0_SE7/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2 PTE2/ADC1_SE10/LPSPI0_SOUT/LPTMR0_ALT3/FTM3_CH6/LPUART1_CTS 18 R137 0
P[6] PTB4 PTB4/ACMP1_IN2/FTM0_CH4/LPSPI0_SOUT/TRGMUX_IN1/HDPIN1 PTE3/FTM0_FLT0/LPUART2_RTS/FTM2_FLT0/TRGMUX_IN6/ACMPX_OUT1 PTE3 P[6] SBC_CAN_RX P[5]
27 9
P[6] PTB5 PTB5/FTM0_CH5/LPSPI0_PCS1/TRGMUX_IN0/ACMPX_OUT2/HDPIN2 PTE4/BUSOUT/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/EWM_OUT PTE5 P[6]
16 8 R136 0
P[6] PTB6 PTB6/XTAL/LPI2C0_SDA PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN SBC_CAN_TX P[5]
15 84
P[6] PTB7 PTB7/EXTAL/LPI2C0_SCL PTE6/ADC1_SE11/LPSPI0_PCS2/FTM3_CH7/LPUART1_RTS PTE6 P[6]
P[6] PTB8 77 59 PTE7 P[6]
76 PTB8/FTM3_CH0 PTE7/FTM0_CH7/FTM3_FLT0 26
P[6] PTB9 PTB9/FTM3_CH1/LPI2C0_SCLS PTE8/ACMP0_IN3/FTM0_CH6 PTE8 P[6] PTE9 P[6]
75 23 R529 0
PTB14 P[6] PTB10 PTB10/FTM3_CH2/LPI2C0_SDAS PTE9/FTM0_CH7/LPUART2_CTS LIN_SLP P[5]
R124 0 74 6
P[6] SBC_SCK P[6] PTB11 PTB11/FTM3_CH3/LPI2C0_HREQ PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4/TRGMUX_OUT4 PTE10 P[6]
68 5
P[5] PTB15 P[6] PTB12 PTB12/ADC1_SE7/FTM0_CH0/FTM3_FLT2/CAN2_RX PTE11/LPTMR0_ALT1/FTM2_CH5/FXIO_D5/TRGMUX_OUT5 PTE11 P[6] PTE12 P[6]
P[6] SBC_MISO R125 0 P[6] PTB13 67 19 PTE13 P[6]
66 PTB13/ADC1_SE8/FTM0_CH1/FTM3_FLT1/CAN2_TX PTE12/FTM0_FLT3/LPUART2_TX 7 R532 0
P[5] PTB16 PTB14/ADC1_SE9/FTM0_CH2/LPSPI1_SCK PTE13/LPSPI2_PCS2/FTM2_FLT0 SBC_LIMP P[5]
R126 0 65 17
P[6] SBC_MOSI PTB15/ADC1_SE14/FTM0_CH3/LPSPI1_SIN PTE14/FTM0_FLT1/FTM2_FLT1 PTE14 P[6]
64 2
P[5] PTB17 PTB16/ADC1_SE15/FTM0_CH4/LPSPI1_SOUT PTE15/LPUART3_CTS/LPSPI2_SCK/FTM2_CH6/FXIO_D2/TRGMUX_OUT6 PTE15 P[6]
R129 0 63 1
P[6] SBC_CS PTB17/FTM0_CH5/LPSPI1_PCS3 PTE16/LPUART3_RTS/LPSPI2_SIN/FTM2_CH7/FXIO_D3/TRGMUX_OUT7 PTE16 P[6]
P[5]
40
P[6] PTC0 PTC0/ADC0_SE8/ACMP1_IN4/FTM0_CH0/FTM1_CH6
C 39 C
P[6] PTC1 PTC1/ADC0_SE9/ACMP1_IN3/FTM0_CH1/FTM1_CH7
30
P[6] PTC4 P[6] PTC2 PTC2/ADC0_SE10/ACMP0_IN5/FTM0_CH2/CAN0_RX
R127 0 29
P[4,5] JTAG_TCLK/SWD_CLK P[6] PTC3 PTC3/ADC0_SE11/ACMP0_IN4/FTM0_CH3/CAN0_TX
P[6] PTC5 96
R128 0 95 PTC4/JTAG_TCLK/SWD_CLK/ACMP0_IN2/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB
P[5] JTAG_TDI PTC5/FTM2_CH0/RTC_CLKOUT/LPI2C1_HREQ/FTM2_QD_PHB/JTAG_TDI
81
P[6] PTC6 PTC6/ADC1_SE4/LPUART1_RX/CAN1_RX/FTM3_CH2
R161 0 80
P[4] UART_RX PTC7/ADC1_SE5/LPUART1_TX/CAN1_TX/FTM3_CH3
56
P[6] PTC7 P[6] PTC8 PTC8/LPUART1_RX/FTM1_FLT0/LPUART0_CTS
R162 0 55
P[4] UART_TX P[6] PTC9 PTC9/LPUART1_TX/FTM1_FLT1/LPUART0_RTS
52
P[6] PTC10 PTC10/FTM3_CH4/TRGMUX_IN11
51
P[6] PTC12 P[6] PTC11 PTC11/FTM3_CH5/TRGMUX_IN10
R152 0 50
P[6] BTN0 PTC12/FTM3_CH6/FTM2_CH6/LPUART3_CTS
49
P[6] PTC13 PTC13/FTM3_CH7/FTM2_CH7/LPUART3_RTS
R153 0 46
P[6] BTN1 PTC14/ADC0_SE12/FTM1_CH2/TRGMUX_IN9
45
P[6] PTC14 P[6] PTC15 PTC15/ADC0_SE13/FTM1_CH3/TRGMUX_IN8
R164 0 44
P[6] ADC0_SE12 P[6] PTC16 PTC16/ADC0_SE14/FTM1_FLT2/CAN2_RX/LPI2C1_SDAS
43
P[6] PTC17 PTC17/ADC0_SE15/FTM1_FLT3/CAN2_TX/LPI2C1_SCLS

VSS1

VSS2

VSS3

VSS4
PS32K144HFT0VLLT

14

37

60

86
MCU Current Measurement
Power Supply Selection SWD Connector - S32K144 Programming
VDD
VDD_MCU VREFH
P3V3 P5V0 VDD DNP DNP DNP R103 0 R109 DNP AREF P[6]
J10 TP4 TP9 TP16 Note: VREFH can be selected from R99 DNP

C
VDD VDD_MCU 1 R63 DNP TP34TP31 R121 the following 3 options: C43 C145
R117 0 2 R56 330 PWR_LED VDD 10K - Option 1(default): VREFH = 10uF 0.1uF D7
3 J14 VDD_MCU, place R103, dnp R99, R109
R64 0 and D7. DNP

A
1 2 - Option 2: VREFH = 3.0V from D7,
JTAG_TMS/SWD_DIO_PTA4 P[3,4]
HDR TH 1X3 D3 3 4 place D7 and R99, dnp R103 and
JTAG_TCLK/SWD_CLK P[3,4]

A
2
1

DNP DNP DNP DNP GREEN 5 6 R119 0 R109.

JTAG_TDO P[3]
TP17 TP1 TP32 7 8 R120 0 - Option 3: VREFH=AREF, place R109,
JTAG_TDI P[3]
B 9 10 dnp R103,R99 and D7. B
RST_TGTMCU_B P[3,4,5,6]
J15

C
HDR 1X2 TH HDR 2X5
DNP

A A

ICAP Classification: CP: ___ IUO: ____ PUBI: _X___

Drawing Title:
S32K144EVB-Q100
Page Title:
S32K144 MCU
Size Document Number Rev
D SCH-29248 PDF: SPF-29248 C

Date: Monday, March 19, 2018 Sheet 3 of 6

5 4 3 2 1
 5 4 3 2 1

D OpenSDA Interface D

V_TGTMCU V_TGTMCU
Reset P3V3_SDA P3V3_SDA
U1
C19 C3 C2 C4
R3 R4
U8 P3V3_SDA 10.0K 0.1UF 4.7uF 1 8 4.7uF 0.1UF 180K
VCCA VCCB
SDA_RST_TGTMCU_J_B 2 7
P3V3_SDA TP500 TP_2102_A 3 A1 B1 6 TP_2102_B TP501
R42 U9 P3V3_SDA A2 B2
1 10.0K 74LVC2G14GF,132 4 5
VDD1 GND OE LVLRST_EN
SDA_SWD_EN_B_R 1 A1 Y1 6 SDA_SWD_EN P3V3_SDA
C12 C6 C7 NTSX2102GU8H
10uF 1.0UF 0.1UF 7 2 5 1-2: Default. J104 R1 4.7K
VDDA GND VCC
2-3: Reset signal direct to the MCU, HDR TH 1X3
P3V3_SDA 3 A2 Y2 4 SDA_SWD_OE to use when OpenSDA is not powered. RST Push Button
R49 C10 Bypass
8 0 0.1UF SW5
VSSA

1
2
3
12 SDA_JTAG_TCLK
JTAG_TCLK/SWD_CLK/EZP_CLK/TSI0_CH1/PTA0/UART0_CTS/UART0_COL/FTM0_CH5 13 SDA_JTAG_TDI R39 1 2 SW1_RST_B V_TGTMCU
JTAG_TDI/EZP_DI/TSI0_CH2/PTA1/UART0_RX/FTM0_CH6 14 SDA_JTAG_TDO 3 4 D1
10.0K R2
JTAG_TDO/TRACE_SWO/EZP_DO/TSI0_CH3/PTA2/UART0_TX/FTM0_CH7 15 SDA_JTAG_TMS C1 C A SDA_RST_LED
P3V3_SDA JTAG_TMS/SWD_DIO/TSI0_CH4/PTA3/UART0_RTS/FTM0_CH0 16 SDA_SWD_EN_B 1000pF
NMI/EZP_CS/TSI0_CH5/PTA4/FTM0_CH1/LLWU_P3 EVQ-P2402W
330 OHM
11 SDA_SWD_OE_B_R RED
VBAT

TP6
SDA_EXTAL R32
Target MCU
L1
Interface
8

USB_MICRO_AB P5V_SDA SDA_VOUT33 P5V_SDA 17 Y1 8.00MHZ 0

1 2 EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0 18 SDA_XTAL 1 3
Signals
SHELL3

SHELL4

6 XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1 Output to system

1 P5V0_SDA_USB_CONN_VBUS 330 OHM 5 VREGIN C20 C23 J105 from Level shifter
SDA_USBSHIELD

VBUS VOUT33

2
2 SDA_USB_CONN_DN R25 33 SDA_USB_DN 4 22PF 22PF
D- USB0_DM HDR 1X2 TH
10 3 SDA_USB_CONN_DP R21 33 SDA_USB_DP 3 DNP DNP DNP
SHELL5 D+ 4 TC_SDA_USB_ID_TP USB0_DP
ID 5
SHELL2

SHELL1

GND P5V_SDA TP12 TP10 TP11 20 SDA_SWD_OE_B

ADC0_SE8/TSI0_CH0/PTB0/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/LLWU_P5

2
1
SDA_RST_TGTMCU_B SDA_RST_TGTMCU_J_B
2

21 R5 0
PESD5V0R1BSF

PESD5V0R1BSF

PESD5V0R1BSF

TC_EXTAL_TP ADC0_SE9/TSI0_CH6/PTB1/I2C0_SDA/FTM1_CH1/FTM1_QD_PHB RST_TGTMCU_B P[3,5,6]

D17 D19 D18 10 DNP
J7 C11 C9 TC_XTAL_TP 9 EXTAL32
XTAL32
7

10uF 2.2UF R57 P3V3_SDA

4.7K

L2
1

SDA_RST 19 R15 V_TGTMCU

C 1 2 RESET 4.7K C
U4
R62 TP8 TP7 1 6
330 OHM 10.0K SDA_RX_EN 5 VCCA VCCB
22 SDA_SPI0_RST_B DIR
2 ADC0_SE15/TSI0_CH14/PTC1/SPI0_PCS3/UART1_RTS/FTM0_CH0/I2S0_TXD0/LLWU_P6 23 SDA_SPI0_CS UART1_RX_TGTMCU_R 3 4 UART1_RX_TGTMCU_BUF R24 0 UART1_RX_TGTMCU
VSS1 ADC0_SE4B/CMP1_IN0/TSI0_CH15/PTC2/SPI0_PCS2/UART1_CTS/FTM0_CH1/I2S0_TX_FS UART1_TX_TGTMCU_R A B UART_RX P[3]
24
CMP1_IN1/PTC3/SPI0_PCS1/UART1_RX/FTM0_CH2/I2S0_TX_BCLK/LLWU_P7 25 UART1_RX_TGTMCU_R
PTC4/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT/LLWU_P8 26 SDA_SPI0_SCK R16 2
PU/PD LOGIC: PTC5/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/CMP0_OUT/LLWU_P9 27 SDA_SPI0_SOUT 10.0K GND
SERIAL INTERFACE CMP0_IN0/PTC6/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/I2S0_MCLK/LLWU_P10 28 SDA_SPI0_SIN
IS ALWAYS RESET
WHEN USB PORT
IS DISCONNECTED
CMP0_IN1/PTC7/SPI0_SIN/USB_SOF_OUT/I2S0_RX_FS
P3V3_SDA P5V_SDA
74LVCH1T45
Isolation Output to system
from Level shifter

P3V3_SDA V_TGTMCU
Resistors

A
33 R12 R14 U2
EPAD D2 4.7K
220
LED GREEN DNP 7 8
UART1_TX_TGTMCU_R 6 VCCA VCCB 1 UART1_TX_TGTMCU_BUF R18 0 UART1_TX_TGTMCU
SDA_SPI0_SIN 5 1A 1B 2 UART_TX P[3]
SDA_LED_R 4 2A 2B 3
GND DIR

C
29 SDA_LED 74LVC2T45GM,125
PTD4/SPI0_PCS1/UART0_RTS/FTM0_CH4/EWM_IN/LLWU_P14 30 SDA_USB_P5V_SENSE Output to system
ADC0_SE6B/PTD5/SPI0_PCS2/UART0_CTS/UART0_COL/FTM0_CH5/EWM_OUT 31 POWER_EN from Level shifter
ADC0_SE7B/PTD6/SPI0_PCS3/UART0_RX/FTM0_CH6/FTM0_FLT0/LLWU_P15 32 VTRG_FAULT_B
PTD7/CMT_IRO/UART0_TX/FTM0_CH7/FTM0_FLT1 P3V3_SDA V_TGTMCU

R20 U7
10.0K 1 6 J106
DNP SDA_SWD_OE R35 0 SDA_SWD_OE_R 5 VCCA VCCB HDR 1X2 TH
DIR DNP

1
2
SDA_SPI0_SOUT 3 4 SWD_DIO_TGTMCU_BUF SWD_DIO_TGTMCU
A B JTAG_TMS/SWD_DIO_PTA4 P[3,5]
R31 R30
10.0K 4.7K 2 SWD_CLK_TGTMCU_BUF
GND JTAG_TCLK/SWD_CLK P[3,5]
MK20DX128VFM5 HW Designer: Rafael del Rey

1
2
74LVCH1T45
J8
HDR 1X2 TH
DNP

P3V3_SDA V_TGTMCU
U10
R47 1 6 Open SDA Ope SDA
SDA_SWD_EN 0 SDA_SWD_EN_R 5 VCCA
DIR
VCCB
Input Power Power Outputs
B SDA_SPI0_SCK 3 4 B
A B i path
R51 R52
P3V3_SDA i path SDA_VOUT33
2
OpenSDA Interface JTAG Connector PWR Switch 10.0K 4.7K
GND

1
2
(To enable 5v from P3V3_SDA
74LVCH1T45
Note: You can power openSDA
USB connector) 3.3VDC, 10mA should be provided with your own power supplies
to this rail (P3V3_SDA) J9 HDR 1X2 TH by replacing this rail
in order to power openSDA (SDA_VOUT33)
V_TGTMCU
P5V_SDA P5V_SDA Isolation and level shift stage PU/PD LOGIC (DIR PIN):
BUFFER IS TRISTATED WHEN module
DNP
with your 3.3V power supply rail
P3V3_SDA P3V3_SDA R60 SHORTING HEADER ON BOTTOM LAYER
(for 1.8 to 5V compatibility) P3V3_SDA IS UNPOWERED

i path
Jumper is shorted by a cut-trace
10.0K on bottom layer. Cutting the trace
C15 will effectively isolate the on-board
MCU from the OpenSDA P5V_SDA_PSW
debug interface.
C18 C8 18PF U11 ACTIVE HIGH
4.7uF 4.7uF R77 DNP 1 6
10.0K 10.0K VIN VOUT
P3V3_SDA R70 MIC2005_CSLEW 5 4 VTRG_FAULT_B SDA_VOUT33 can provide up to 120mA
J12 CSLEW FAULT of power at 3.3VDC to your system
DNP
1 2 SDA_JTAG_TMS VTRG_EN 3 2
3 4 SDA_JTAG_TCLK ENABLE GND P5V_TRG_SDA can provide up to 450mA
SDA_JTAG_TDO (per USB spec) of power at 5VDC
C26 5 6 MIC2005-0.8YM6 to your system
0.1UF 7 8 SDA_JTAG_TDI R68 C25 R69
9 10 SDA_RST 15K 0.1UF 1.0K

HDR 2X5 I/O Poer

POWER_EN i path Input
V_TGTMCU SH1
VDD
V_BRD is supported
from 1.8V to 5V

0 Power should be provided

to this rail for the logic
related to your platform I/O

SDA_SPI0_RST_B R41 0 SDA_SWD_EN

DNP
SDA_SPI0_CS R38 0 SDA_SWD_OE

DNP
{For Enablement Purposes Only}

A A

ICAP Classification: CP: ___ IUO: ____ PUBI: _X___

Drawing Title:
S32K144EVB-Q100
Page Title:
OpenSDA interface
Size Document Number Rev
D SCH-29248 PDF: SPF-29248 C

Date: Monday, March 19, 2018 Sheet 4 of 6

5 4 3 2 1
 5 4 3 2 1

CAN Physical Layer

3.3V LDO Power Supply
VIN D13 PNS40010ER P5V_SDA_PSW P5V_SBC
J107 TP14 TP13
A C 1 P5V0 U15 P3V3
2 1 5
D
3 VIN VOUT D
TP38 D9 PNS40010ER TP36 2
J16 VBATT VSUP HDR TH 1X3 R169 0 GND
1 A C 3 4
3 C22 C21 R170 0 EN BYP C59 C24
2 C128 C47 C29 0.1uF 10uF DNP 0.01UF 10uF
22uF 0.1uF 0.01uf SPX3819M5-L-3-3
CON PWR 3
SH1
SH2

P5V_SBC TP15 3
PHPT61003PY Q1 2
R535 2.2 5 1 20mOhm Resistor
in layout
C27
6.8uF
P5V_SBC VSUP

4
R537

15
R536

6
TP24 TP502 TP19 TP22 U19 TP20 TP21 TP27 TP25 TP23 TP33 10k
4.7K 5 14

VEXCC

VEXCTRL
DNP V1 BAT
8 7 U32 P5V_SBC
P[5] SBC_RST RST RXD SBC_CAN_RX_LS P[5] VDD
2 SBC_CAN_TX_LS P[5] P5V_SBC
11 TXD 1 8
P[5] SBC_LIMP_LS LIMP VCCA VCCB
CAN 13
V2
SCK
SDI
10
3
SBC_SCK_LS
SBC_MOSI_LS
P[5]
P[5] P[5] SBC_RST R565 DNP 0 2
A1 B1
7 R563 DNP 0 RST_TGTMCU_B P[3,4,5,6]
J13 9 3 6
CAN_HI SDO SBC_MISO_LS P[5] A2 B2
1 18 20 SBC_CS_LS P[5]
2 17 CANH SCS 4 5

GND4
GND3
GND2
GND1
R92 60.4 CAN_LO
3 CANL 12 GND OE R562 4.7K

EP
WAKE
2
1

4
J109 C536 UJA1169TK/F NTSX2102GU8H

4
1
21

19
16
HDR 1X4 RA HDR 1X2 TH 6.8uF

3
1
R98 60.4
C40 SW9 P5V_SBC U33 VDD
2
1

C 4700 PF EVQ-P2402W 1 6 C
J108 R564 4.7K 5 VCCA VCCB
HDR 1X2 TH DIR
R566 0 3 4
P[5] SBC_LIMP_LS A B SBC_LIMP P[3]
DNP

4
2
2
GND

74LVCH1T45

LIN Physical Layer Level Shifters

MASTER OPTION
P5V_SBC U29 VDD
PMEG3050EP VSUP P5V_SBC U30 P5V_SBC 1 6
D6 P5V_SBC VDD 5 VCCA VCCB
C A 1 8 R559 4.7K DIR
B
Note: Place R530 VCCA VCCB 3 4 B
only after R529 U28 P[5] SBC_MISO_LS A B SBC_MISO P[3]
R538 R530 2 7
TP35 TP37 has been VDD P[5] SBC_CAN_TX_LS A1 B1 SBC_CAN_TX P[3]
R171 R80 4.7K 4.7K P5V_SBC P5V_SBC P[5] SBC_CAN_RX_LS 3 6 SBC_CAN_RX P[3]
2K 2K DNP removed. 1 8 A2 B2 2
VCCA VCCB GND
7

U21 4 5
1 2 7 GND OE R560 4.7K
LIN_RX_LS P[5] P[5] LIN_RX_LS LIN_RX P[3]
VBAT

RXD 3 A1 B1 6 74LVCH1T45
P[5] LIN_TX_LS A2 B2 LIN_TX P[3]
3 NTSX2102GU8H
VBATT TP18 8 NC1 4 4 5 R558 4.7K
NC2 TXD LIN_TX_LS P[5] GND OE
J11 P5V_SBC
1 LIN 6
2 LIN 2 NTSX2102GU8H
LIN_SLP P[3]
GND

3 SLP C538
4 C17 U26 0.1UF U31 VDD
220PF TJA1027T/20 P5V_SBC VDD P5V_SBC 1 6
VCCA VCCB
5

HDR 1X4 RA 1 8 5
VCCA VCCB DIR
P[5] SBC_SCK_LS 2 7 SBC_SCK P[3] P[5] SBC_CS_LS 3 4 SBC_CS P[3] C537
3 A1 B1 6 A B 0.1UF
P[5] SBC_MOSI_LS A2 B2 SBC_MOSI P[3]
4 5 2
GND OE R556 4.7K GND

74LVCH1T45
NTSX2102GU8H

A A

ICAP Classification: CP: ___ IUO: ____ PUBI: _X___

Drawing Title:
S32K144EVB-Q100
Page Title:
Power Supply/SWD/Reset
Size Document Number Rev
C SCH-29248 PDF: SPF-29248 C

Date: Monday, March 19, 2018 Sheet 5 of 6

5 4 3 2 1
 5 4 3 2 1

P[3] PTA11
P[3] PTA17
P[3,6] PTD10
P[3,6] PTD11
P[3] PTD12 PTE4 P[3]
P[3] PTD5 PTE5 P[3] VDD
P[3,6] PTD3 PTA12 P[3]
P[3] PTE3 PTA13 P[3]

P[3] PTD15
P[3] PTD16 PTC16 P[3]
P[3,6] PTD0 PTC17 P[3]
P[3,6] PTE8 PTD3 P[3,6]
P[3] PTC12 PTD1 P[3]
D P[3] PTC13 D
P[3] PTE7
P[3] PTA14
NOTE:
J1,J2,J3 and J4: Arduino UNO
compatible headers.
J5 and J6: Arduino Mega
compatible headers.

20
18
16
14
12
10

16
14
12
10

20
18
16
14
12
10
8
6
4
2

8
6
4
2

8
6
4
2
J2 J1 J6
CON 2X8 CON_2X10
CON_2X10

9
7
5
3
1

9
7
5
3
1
19
17
15
13
11

19
17
15
13
11
P[3,6] PTA3 R539 0 DNP

9
7
5
3
1
15
13
11
Xtal
P[3,6] PTA2 R540 0 DNP
PTD0 P[3,6]
P[3,6] PTE10 R567 0 SH13 0 PTD2 P[3]
NOTE: R568 0
PTA2 and PTA3 I2C via LPI2C P[3,6] PTE11 PTD9 P[3] PTB6_XTAL
P[3] AREF PTD8 P[3] P[3,6] PTB6 R84 0
PTE10 and PTE11 I2C via FLEXIO R88 0
PTC8 P[3] P[3,6] PTB7
P[3] PTB2 PTC9 P[3]

PTB7_EXTAL
P[3] PTB3 PTD17 P[3]
GND P[3] PTB4 PTE12 P[3]
P[3] PTB5 PTA8 P[3] R91 1.0M
NOTE: J2-15.
R134, place it by deafult for extra P[3] PTD14 PTA9 P[3]
GPIO/PWM. P[3] PTD13
Y3 8MHZ
R135, place it and remove R134 to have 1 2
CMP functionality.
P[3,6] PTE8 R135 0 DNP
NOTE: J2-13. R134 0 Note J5-1:
R133, place it by deafult for extra P[3] PTC11 R167 place it by defualt for
R132 0 DNP NOTE: J4-9, J4-11 C126 C127
GPIO/PWM. P[3,6] PTC3 R146, and R147 placed by deafult, ADC channel.
R133 0 12PF 12PF
R132, place it and remove R133 to have P[3] PTC10 remove and place R544 and R543 for R168 place it and remove R167
CMP functionality. P[3] PTB11 I2C functionality with FLEXIO or when using FSL BLDC shield.
P[3] PTB10 place PTA2 and PTA3 for LPI2C . Note J5-3:
P[3] PTB9 R165 place it by defualt for
P[3] PTB8 ADC channel.
P[3,6] PTA3 SH12 0
SH11 0 R544 0 DNP R166 place it and remove R165
C P[3,6] PTA2 PTE11 P[3,6] C
when using FSL BLDC shield.
R542 0 DNP PTA2 P[3,6]
P[3]
P[3]
P[3,6]
PTE6
PTE2
PTC0 R146
R147
0
0
R543
R541
0 DNP
0 DNP
PTE10 P[3,6]
PTA3 P[3,6] R168
R167
0 DNP
0
PTD11 P[3,6]
Potentiometer VDD
P[3] PTA6 PTA15 P[3]
P[3] PTB1
P3V3 P5V0 P[3] PTB0 R166 0 DNP PTD10 P[3,6]
P[3] PTB12 R165 0 PTA16 P[3]

1
R13 TP5
P[3] PTD4 PTA1 P[3]
PTA0 P[3]
2
PTA7 P[3] ADC0_SE12 P[3]
VDD VIN PTB13 P[3]
PTC1 P[3,6] 5K
P[3,4,5] RST_TGTMCU_B VIN PTC2 P[3,6] C5

3
0.1UF

C49
10uF
11
13
15

11
13
15

11
13
15
17
19
1
3
5
7
9

1
3
5
7
9

1
3
5
7
9
J3 J4 J5
CON 2X8 CON 2X8 CON_2X10

VDD

2
4
6
8
10
12
14
16
18
20
2
4
6
8

2
4
6
8
10
12
14
16

10
12
14
16

P[3,6] PTB6 R81 0 DNP PTC15 P[3]

P[3,6] PTB7 R90 0 DNP PTD6 P[3]
P[3] PTE0 PTD7 P[3]
P[3] PTE9 PTE1 P[3]
P[3] PTC5
P[3] PTC4
P[3] PTA10 R545 0 DNP PTE13 P[3]
P[3] PTA4 R546 0 DNP PTE14 P[3]
PTE15 P[3]
B P[3] PTC7 PTE16 P[3] B
P[3] PTC6
P[3] PTB17
P[3] PTB14
P[3] PTB15
P[3] PTB16
P[3] PTC14
P[3,6] PTC3

User Buttons VDD VDD

Touch Pads RGB Led
SW3 SW2 VDD
C533 R533 0 PTC3 P[3,6] C535 R534 0 PTC0 P[3,6]
1 2 1 2 10pF 10pF D11
3 4 3 4
EVQ-P2402W EVQ-P2402W R525 R528 A1 C1 LEDRGB_RED R97 RGB_RED P[3]
BTN1 P[3] BTN0 P[3] 4.7K 4.7K TP30 220

A2 C2 LEDRGB_GREEN R96 RGB_GREEN P[3]

R74 R44 TP29 220
10.0K C28 10.0K C16
0.1UF 0.1UF A3 C3 LEDRGB_BLUE R95
SW7 SW8 RGB_BLUE P[3]
TP28 220
R172 0 1 R527 01
P[3,6] PTC1 P[3,6] PTC2
LED RED/GRN/BL
Electrode Electrode

A A

ICAP Classification: CP: ___ IUO: ____ PUBI: _X___

Drawing Title:
S32K144EVB-Q100
Page Title:
I/O Headers
Size Document Number Rev
C SCH-29248 PDF: SPF-29248 C

Date: Monday, March 19, 2018 Sheet 6 of 6

5 4 3 2 1