SL. NO.

Questions
1 Why latches are called a memory devices?
2 Which of the following is an application of Combinational Circuit?
In a combinational circuit, the output at any time depends only on the
3
_______ at that time.

4 In a sequential circuit, the output at any time depends

5 What does the triangle on the clock input of a any Flip Flop mean?

6 Why Latch has Two Stable States?

7 When a active high is applied to the Set line of an SR latch, then

When both inputs of SR latches are low, the latch is in ___________
8 condition.
9 What is the Full form of SR latch?

10 When is the Flip-Flop said to be transparent?

If both inputs of an SR Flip Flop are low,what will happen when the clock
11 goes high?

12 Which one of the following is the application of an SR flip-flop?

13 One disadvantage of the SR flip-flop is

14 Which of the Following is not correct for the D Flip Flop?

15 What is the Output condition of JK Flip Flop when inputs J= 0 & K= 0?

16 Which of the following is not generally associate with Flipflops?
Which of following is an ADVANTAGE of an Asynchronous Counter
17
Circuit?
18 Which of the following is the alternative name for 4-bit Binary Counter?

19 The modulus of a counter is

A decade counter with a count of zero (0000) through nine (1001) is
20
known as
21 Which of the following is NOT the alternate name for BCD Counter?
22 Which of the following is a valid state in an 8421 BCD counter?
23 A 3-bit binary counter has a maximum modulus of
24 A 5-bit binary counter has a maximum modulus of
25 A modulus-12 counter must have
A 4-bit ripple counter consists of flip-flops that each have a propagation
26 delay from clock to Q output of 12 ns. For the counter to recycle from
1111 to 0000, it takes a total propogation delay of _______________.
 Which of the following IC is the synchronous, presettable, 4-bit binary
27 counter?
A 4-bit binary up/down counter is in the binary state of zero. The next
28
state in the DOWN Counter mode is ___________.
29 Three cascaded modulus-10 counters have an overall modulus of
30 Which of the following MOD Counter is widely used in Digital Clock?
31 Which type of the Counter or Shift Register is used in Automatic Parking
Control
Which ofCircuit?
the following type of shift register is similar to Multiplexing
32
Technique?
The output frequency of single flip-flop will be ________ of input
33
frequency of flip-flop.
34 To enter a byte of data serially into an 8-bit shift register, there must be
To parallel load a byte of data into a shift register with a synchronous
35
load, there must be
With a 100 kHz clock frequency, eight bits can be serially entered into a
36 shift register in
37 With a 1 MHz clock frequency, eight bits can be parallel entered into a
shift register
38 Identify The IC number for Bidirectional Universal Shift Register
39 A modulus-8 ring counter requires
40 A modulus-8 Johnson counter requires
41 A DAC is a
42 A type of Error associated with digital to analog converters (DACs) is:
43 In troubleshooting a DAC, we check its performance characteristics, such
as______________

44 What is gain error in a DAC

A Binary weighted digital to analog converter has an input resistor of

45 100kΩ. What will be current through the resistor, if the resistor is
connected to a 5V Source?
46 In a binary weighted DAC, the lowest-value resistor corresponds to

47 As Compared to binary weighted digital to analog DAC converter , the

major advantage of the R/2R ladder digital to analog (DAC) is

Which term applies to the maintaining of a given signal level until the
48
next sampling

49 In analog to digital converter (ADCs) sample - and - hold circuits are

designed to

50 What is the Purpose of Sample and Hold Circuit?

51 The most common ADC seen in telecommunications based on audio

signals is
 Identify from the following performance parameter of ADC in which suits
52 the definition of no. of samples per second.
53 The quantization process
54 Aliasing results in
55 The dual slope analog to digital conver finds extensive use in _____
56 A digital voltmeter uses a

57 What is the Primary disadvantage of the Flash analog to digital converter

(ADC)?

58 What is the Conversion time of flash converter?

59 In a flash Analog to Digital convertor,the output of each comparator is

connected to an input of a ______________
60 The throughput of a flash ADC is measured in
61 The main advantage of the successive - approximation A/D converter
over the counter - ramp A/D converter is its:

62 The ADC0808 is an example of a _____________

63 Memory is a/an ___________

64 A flip flop stores __________
65 A register is able to hold __________ of information
Which of the following parameter of memory defines the section of
66
memory in a single memory array?
Which of the following parameter of memory defines the group of chips
67 that make up a memory module that stores data in units such as words
or bytes?
Which of the following parameter of memory defines the maximum
68 number of bits that can be read or written into the memory at a time?
Which of the following parameter of memory defines the time taken by
69 RAM to complete read/write operation from the instant that an address
is sent to the memory?
Which of the following parameter of memory defines the sum of access
70 time & additional time required before a second access can commence in
case of RAM ONLY?
71 Data stored in an electronic memory cell can be accessed at random and
on demand using __________
72 A ROM is defined as __________
73 Why are ROMs called non-volatile memory?
74 Which type of ROM has to be custom built by the factory?
75 CD-ROM refers to __________
76 Which of the following memories are magnetic memory type?
77 Which of the following memory is an example of sequential access
memory?
 78 The full form of PROM is __________
79 Which of following processes matches for Fusing process in PROM?

80 Which of the following best describes EPROMs?

81 The full form of EPROM is __________

Which type ROM can be used to erase the contents by an electrical
82
signal?
83 Which of the following is NOT an application of SRAM?
84 How many no. of transistors are used in fabricating a SRAM Chip?
85 Which of the following operations are performed by SRAM?
86 Which of the following operations are performed by DRAM?
87 Which of the following devices used in fabricating a Dynamic RAM ICs?
88 Which of the following features best defines about Dynamic RAM?

89 What is the disadvantage of MOS capacitor in DRAM?

With which of the following two memory devices, NVRAM Chip is
90 formed?
91 Which of following is the most widely used type of NVRAM?

Which of the following type of NVRAM stores the information in the

92 form of voltage in a capacitor?

When both the AND and OR are programmable, such PLDs are known as
93 __________

Which of the following approach in digital circuit design work with fixed
94 functions?

Which of the following design approach in digital circuits offers HIGHEST

95
RELIABILITY?
Which of the following design approach in digital circuits will NOT
96
provide Design Flexibility?
Which of the following design approach in digital circuits will have Design
97
Security Issues?
98 The full form of PLD is __________
99 The evolution of PLD began with __________
100 For reprogrammability, PLDs use __________
101 Why antifuses are implemented in a PLD?
Which of the following is the type of Factory Programmable Logic
102
Devices?
103 Which of the following is NOT the type of Field Programmable Logic
Devices?
104 The full form of PLA is _____________.
105 Which of the following combination best defines Programmable Logic Arra

106 PAL refers to ____________

107 Which of the following design versions are NOT available in PAL devices?

108 Which of the following combination best defines Programmable Array Logi

109 If a PAL has been programmed once ____________

110 Which of the following output is generated from PAL circuit?
111 Which of the following is/are the basic element/s of FPGA?
112 FPGA stands for __________
113 Which of the following is a reprogrammable gate array?
114 How FPGA differs from PLD?
115 Which o fthe following display devices are NOT the type of Digital Displays
116 In 7 segment display, how many LEDs are used?
117 In seven segment display, which of the following component is used to
construct seven segments?

118 In a Common Anode Seven Segment Display, which of the segment LEDs
are ON for displaying decimal digit '0'?
In a Common Anode Seven Segment Display, which of the segment LED
119 will be OFF for displaying decimal digit '6'?

Which of the following type of Alphanumeric Display conatins LED

120
aligned in the form of Matrix?
121 Which of the following factor is NOT an ADVNATGE of Multiplexed Display
122 The full form of LCD is ____________
123 Select the operating voltage range for LCDs.
124 What is backplane in LCD?
125 Which of the following type of LCD is used in Watches & Calculators?
126 Which of following DO NOT describe Active Matrix LCD?
127 Which of following advantages is related to Active Matrix LCD?
 Choice 1 Choice 2 Choice 3 Choice 4
It has capability to store 8 It can store single bit of It has internal None of the above
bit of Data Data memory of 4 bit
Counter Circuits Latch Circuits Encoder Circuit Shift Register Circuits

past output values intermediate values present input values clock pulses

past output values intermediate values

both past output and presentpresent
input input values

Level Enabled edge-triggered Both None

a latch works on the a latch works on the a latch works on the
a latch works on the
principal of bistable principal of monostable principal of astable principal of oscillator
multivibrator multivibrator multivibrator
Q' output goes HIGH None Q output goes LOW Q output goes HIGH
Set No change Reset Invalid
SET RESET SET READY SET RESTART START RESET
When the Q output is when the output follows when you can see
through the IC None
opposite the input the input
packaging
No change will occur in The output will
An invalid state will exist the output toggle The output will reset

transistion pulse generator astable oscillator racer switch debouncer

It has only a single
It has no enable input It has a RACE condition It has no clock Input input
Q output follows the Only one of the The output
The Output toggles if one of compliment follows
the input is held high Input D when the enable input can be high at the input when
is high a time
enabled
Set Reset Toggle No change
Hold Time Propogation Delay Time Interval time setup time
High Propogation Delay Produces Decoding Error Prone to Glitches Simple Circuit Design
MOD-10 Counter MOD-6 Counter MOD-16 Counter MOD-4 Counter
the actual number of the number of times the number of logic
the number of flip-flops it recycles in a
states in its sequence gates used
second
an ASCII counter a binary counter A BCD counter an octal counter
4-bit Binary Counter Decade Counter Divide by 10 Modulus of 10
Counter Counter
1010 1011 1111 1000
3 6 8 16
5 8 16 32
12 flip-flops 3 flip-flops 4 flip-flops synchronous clocking

12 ns 24 ns 36 ns 48 ns
 IC 7490 IC 7493 IC 74160 IC 74163

(0001)2 (1111)2 (1101)2 (1110)2

30 100 1000 10000

MOD-5 MOD-9 MOD-10 MOD-30
Up-Down Counter Bidirectional Shift Universal Shift Ring Counter
Register Register
SISO SIPO PISO PIPO
divide by 2 divide by 4 divide by 8 divide by 16
one clock pulse two clock pulses four clock pulses eight clock pulses
one clock pulse for each one clock pulse for
one clock pulse eight clock pulses
1 in the data each 0 in the data
80 μs 8 μs 80 ms 100 ms
in the propagation in the propagation
1 μs 8 μs delay time of EIGHT delay time of ONE
flip-flops flip-flop
IC 7495 IC 74164 IC 74194 IC 74195
8 Flip-flops 4 Flip-flops 12 Flip-flops 5 Flip-flops
8 Flip-flops 4 Flip-flops 12 Flip-flops 5 Flip-flops
digital-to-analog computer digital analysis calculator data accumulation digital-to-analog
converter converterand
nonmonotic
nonmonotonic error incorrect output codes offset error offset error
nonmonotonicity differential nonlinearity low and high gain all of the above
more or less input
error in the slope of the voltage is required
missing codes output staircase for the first step None
waveform than what is
specified
50μA 5mA 500μA 50mA
the highest binary weighted the
input
lowest binary weighted input the first input the last input
The Virtual Ground is
Its Operation is elimated and the
It only uses two different it has a fewer part of the much easier to circuit is therefore
resistor values same number of inputs analyse easier to understand
and troubleshoot
shannon frequency
Holding Aliasing stair-stepping
sampling
stabilize the input sample and hold the
Sample and hold the output stabilize the comparator D/A converter
of the binary counter during threshold voltage during analog signal during staircase waveform
the conversion process the comparison process the conversion during the
process conversion process
Tp hold a voltage To hold a voltage
To hold data after
constant so an ADC has constant so a DAC
To keep temporary memory time to produce an has time to produce multiplexer has
selected an output
output an output
flash ADC successive approximation sigma-delta ADC dual slope ADC
ADC
 Aliasing Quantization Error Resolution
converts a sequence Sampling Frequency
filters out unwanted
converts the sample-and- converts a sample of binary codes to a
hold output to binary code impulse to a level reconstructed frequencies before
guard-band sampling
oversampling undersampling analog signal perfect takes place
sampling
formation
digital voltmeter function generators frequency counters all of the above
successive approximation
flash ADC sigma-delta ADC dual-slope ADC
ADC a large number of
output lines is a large number of
It requires the input voltage comparators is
to be applied to the inputs a long conversion time is required to required to represent
required simultaneously
simultaneously decode the input a resonable sized
binary number
voltage
The Conversion takes
20s 10s 1s
place continuously

decoder priority encoder multiplexer demultiplexer

displacement per second distance per second samples per minute samples per second
more complex circuitry less complex circuitry longer conversion shorter conversion
time time
successive
Single -slope analog to dual slope analog to digital ramp analog approximation
digital converter digital converter to digital converter analog to digital
converter
Device to connect
Device to collect data from Block of data to keep Indispensable part
through all over the
other computer data separately of computer world
single bit of information two bits of information four bits of eight bits of
information information
bit word nibble double word

Memory Location Memory Address Memory Bank Memory Rank

Memory Location Memory Address Memory Bank Memory Rank

Memory Location Memory Address Memory Bank Unit of Transfer

Access Time Memory Cycle Time Transfer Rate Unit of Transfer

Access Time Memory Cycle Time Transfer Rate Unit of Transfer

Memory Addressing Direct Addressing Indirect Addressing Control Unit

Read Out Memory Read Once Memory Read Only Memory Read One Memory
They lose memory when They do not lose memory They lose memory They do not lose
power is removed when power is removed when power is memory when power
supplied is supplied
EPROM EEPROM Masked ROM PROM
Compact Disk-Read Only Compressed Disk- Compressed Disk-
Floppy disk Random Access
Memory Read Only Memory
Memory
Main Memory Secondary Memory Static Memory Volatile Memory
Floppy Disk Hard Disk Magnetic Type RAM
Memory
 Previous Read Only Programmable Read Out Programmable Read Previous Read Out
Memory Memory Only Memory Memory
It is Reversible Process It is Irreverible Process It is Synchronous It is Asynchronous
Process Process
EPROMs can be
EPROMs can be EPROMs can be erased erased by shorting EPROMs can be
programmed only once by UV all inputs to the erased electrically
ground
Easy Programmable Read Erasable Programmable Eradicate Easy Programmable
Only Memory Read Only Memory Programmable Read Read Out Memory
Only Memory
ROM Masked ROM EPROM EEPROM
Computer Cache Memory Digital Cameras & Cell LCD Screens Workstations &
Phones Servers
4 5 6 7
Write Operation Read Operation Refresh Operation Both a & b ONLY
Write Operation Read Operation Refresh Operation All of the above
Capacitor or MOSFET FET or JFET Capacitor or BJT
Low power BJT or MOS
High power consumption Low power consumption consumption High power
consumption
Large storage capacity Large storage capacity Less storage Less storage capacity
capacity
It can’t hold the data till a It doesn’t holds the It is highly densed It is not flexible
long period charge till a long period
EPROM & DRAM EPROM & SRAM EEPROM & DRAM EEPROM & SRAM
Flash Memory type Ferroelectric RAM Magneto Resistive SRAM
(FeRAM) RAM (MRAM)
Ferroelectric RAM Magneto Resistive
Flash Memory type (FeRAM) RAM (MRAM) SRAM

PAL PPL PLA APL

Applications Specific Programmable Logic

Integrated Circuit (ASIC) Fixed Function ICs Devices (PLDs) None of the above

Applications Specific Programmable Logic

Fixed Function ICs None of the above
Integrated Circuit (ASIC) Devices (PLDs)
Applications Specific Programmable Logic
Fixed Function ICs None of the above
Integrated Circuit (ASIC) Devices (PLDs)
Applications Specific Programmable Logic
Fixed Function ICs None of the above
Integrated Circuit (ASIC) Devices (PLDs)
Programmable Large Device Programmable Long Device
Programmable Logic Programmable
Device Lengthy Device
Externally Programmed RAM PROM EPROM
ROM
PROM EPROM CDROM PLA
To protect from high To increase the memory To implement the As a switching
voltage storage programmes devices
MPGA PLA PAL CPLD
CPLD PLA PAL ROM
Programmable Loaded Array Programmable Array Logic
Programmable Logic Array
Programmed Array Logic
 Programmable AND Programmable AND
Fixed AND Array Fixed AND Array Array
Fixed OR Array Programmable OR Array Array
Programmable OR
Fixed OR Array Array AND
Programmable Array Programmable Logic Programmable Programmable
Loaded Array Array Logic Logic
One-Time Programmable UV Erasable Version Flash Erasable Version Programmable
None of the above
AND
Fixed AND Array Fixed AND Array Programmable AND Array
Array
Fixed OR Array Programmable OR Array Fixed OR Array Programmable OR
Array
Its outputs are only Its outputs are only It cannot be
Its logic capacity is lost active HIGH active LOW reprogrammed
Sum Term Output ONLY SOP Term Output Product Term Output ONLYPOS Term Output
Configuration Logic Block (CLB) Interconnections I/O Block all of the above
Full Programmable Gate Full Programmable First Programmable Field Programmable
Array Genuine Array Gate Array Gate Array
EPROM FPGA Both a & b ROM
FPGA is slower than PLD FPGA has high power FPGA incorporates None of the above
dissipation logic blocks
Matrix Displays CRTs Numeric Displays Multiplexed Display
7 8 9 10
Capacitor Diodes Inductor LED

Segments a, b, c, d, e are ON
Segments a, b, c, d, e, f are ON
Segments a, b, c are
Segments
ON a, c, d, e, f, g are ON

Segment b is OFF Segment c is OFF Segment d is OFF Segment g is OFF

Dot-Matrix Display Mutliplexed Display Liquid Crystal DisplayTwisted Nematic Display

fewer wires are needed for reduced cost reduced power consumption None of the above
connection
Liquid Crystal Display Logical Crystal Display Logical Crystalline Display
Liquid Crystalline Display
3 to 15V 10 to 15V 15 to 24V 10 to 32V
The ac voltage applied The dc voltage applied
between segment and a between segment and Theaamount of power Forconsumed
adjusting the intensity of the LCD
common element common element
Direct Address LCD Passive Matrix Display Active Matrix DisplayTwisted Nematic Display
High Contrast High Resolution High Viewing Angle High Cost
Low Cost Fast Response Time High Viewing Angle Both a & b ONLY
 Key
It can store single bit of Data
Encoder Circuit

present input values

both past output and present input

edge-triggered
a latch works on the principal of
bistable multivibrator
Q output goes HIGH
No change
SET RESET

when the output follows the input

No change will occur in the output

switch debouncer
It has a RACE condition

Q output follows the Input D when the

enable is high

No change
Interval time
Simple Circuit Design
MOD-16 Counter
the actual number of states in its
sequence
A BCD counter
4-bit Binary Counter
1000
8
32
4 flip-flops

48 ns
 IC 74163

(1111)2

1000
MOD-10
Up-Down Counter
PISO
divide by 2
eight clock pulses
one clock pulse
80 μs
in the propagation delay time of ONE
flip-flop
IC 74194
8 Flip-flops
4 Flip-flops
digital-to-analog converter
nonmonotic and offset error
all of the above

error in the slope of the output

staircase waveform

50μA
the highest binary weighted input

It only uses two different resistor

values

Holding

stabilize the input analog signal during

the conversion process

Tp hold a voltage constant so an ADC

has time to produce an output

sigma-delta ADC
 Sampling Frequency
converts a sequence of binary codes to
a reconstructed analog signal
undersampling
all of the above
dual-slope ADC

a large number of comparators is

required to represent a resonable
sized binary number

The Conversion takes place

continuously

priority encoder
samples per second
shorter conversion time

successive approximation analog to

digital converter

Indispensable part of computer

single bit of information
word

Memory Bank

Memory Rank

Unit of Transfer

Access Time

Memory Cycle Time

Indirect Addressing
Read Only Memory
They do not lose memory when power
is removed
Masked ROM
Compact Disk-Read Only Memory
Secondary Memory
Magnetic Type Memory
 Programmable Read Only Memory
It is Irreverible Process

EPROMs can be erased by UV

Erasable Programmable Read Only

Memory
EEPROM
Workstations & Servers
6
Both a & b ONLY
All of the above
Capacitor or MOSFET
Low power consumption
Large storage capacity
It doesn’t holds the charge till a long
period
EEPROM & SRAM
Flash Memory type

Ferroelectric RAM (FeRAM)

PLA

Fixed Function ICs

Applications Specific Integrated Circuit

(ASIC)
Applications Specific Integrated Circuit
(ASIC)

Fixed Function ICs

Programmable Logic Device

Externally Programmed ROM
EPROM
To implement the programmes
MPGA
ROM
Programmable Logic Array
 Programmable AND Array
Programmable OR Array
Programmable Array Logic
None of the above
Programmable AND Array
Fixed OR Array

It cannot be reprogrammed
SOP Term Output
all of the above
Field Programmable Gate Array
Both a & b
FPGA incorporates logic blocks
CRTs
7
LED

Segments a, b, c, d, e, f are ON

Segment b is OFF

Dot-Matrix Display
None of the above
Liquid Crystal Display
3 to 15V
The ac voltage applied between
segment and a common element
Direct Address LCD
High Cost
Both a & b ONLY