Questions Choice 1

Why latches are called a memory devices? It has capability to store 8 bit of Data

Which of the following is NOT an application of Combinational Circuit? Counter Circuits

In a combinational circuit, the output at any time depends only on the _______ at that
past output values
time.

In a sequential circuit, the output at any time depends only on the input values at that time. past output values

What does the triangle on the clock input of a any Flip Flop mean? Level Enabled

a latch works on the principal of bistable

Why Latch has Two Stable States?
multivibrator
When a active high is applied to the Set line of an SR latch, then Q' output goes HIGH
When both inputs of SR latches are low, the latch is in ___________ condition. Set
What is the Full form of SR latch? SET RESET

When is the Flip-Flop said to be transparent? When the Q output is opposite the input

If both inputs of an SR Flip Flop are low,what will happen when the clock goes high? An invalid state will exist

Which one of the following is the application of an SR flip-flop? transistion pulse generator
One disadvantage of the SR flip-flop is It has no enable input
The Output toggles if one of the input is
Which of the Following is not correct for the D Flip Flop?
held high
What is the Output condition of JK Flip Flop when inputs J= 0 & K= 0? Set
Which of the following is not generally associate with Flipflops? Hold Time
Which of following is an ADVANTAGE of an Asynchronous Counter Circuit? High Propogation Delay
Which of the following is the alternative name for 4-bit Binary Counter? MOD-10 Counter

The modulus of a counter is the number of flip-flops

A decade counter with a count of zero (0000) through nine (1001) is known as an ASCII counter
Which of the following is NOT the alternate name for BCD Counter? 4-bit Binary Counter
Which of the following is a valid state in an 8421 BCD counter? 1010
A 3-bit binary counter has a maximum modulus of 3
A 5-bit binary counter has a maximum modulus of 5
A modulus-12 counter must have 12 flip-flops
A 4-bit ripple counter consists of flip-flops that each have a propagation delay from clock to
Q output of 12 ns. For the counter to recycle from 1111 to 0000, it takes a total 12 ns
propogation delay of _______________.
Which of the following IC is the synchronous, presettable, 4-bit binary counter? IC 7490

A 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWN
Counter mode is ___________. (0001)2

Three cascaded modulus-10 counters have an overall modulus of 30

Which of the following MOD Counter is widely used in Digital Clock? MOD-5

Which type of the Counter or Shift Register is used in Automatic Parking Control Circuit? Up-Down Counter

Which of the following type of shift register is similar to Multiplexing Technique? SISO

The output frequency of single flip-flop will be ________ of input frequency of flip-flop. divide by 2

To enter a byte of data serially into an 8-bit shift register, there must be one clock pulse
To parallel load a byte of data into a shift register with a synchronous load, there must be one clock pulse

With a 100 kHz clock frequency, eight bits can be serially entered into a shift register in 80 μs

With a 1 MHz clock frequency, eight bits can be parallel entered into a shift register 1 μs
Identify The IC number for Bidirectional Universal Shift Register IC 7495
A modulus-8 ring counter requires 8 Flip-flops
A modulus-8 Johnson counter requires 8 Flip-flops
A DAC is a digital-to-analog computer
A type of Error associated with digital to analog converters (DACs) is: nonmonotonic error
In troubleshooting a DAC, we check its performance characteristics, such
nonmonotonicity
as______________

What is gain error in a DAC missing codes

A Binary weighted digital to analog converter has an input resistor of 100kΩ. What will be 50μA
current through the resistor, if the resistor is connected to a 5V Source?

In a binary weighted DAC, the lowest-value resistor corresponds to the highest binary weighted input

As Compared to binary weighted digital to analog DAC converter , the major advantage of It only uses two different resistor values
the R/2R ladder digital to analog (DAC) is

Which term applies to the maintaining of a given signal level until the next sampling Holding

Sample and hold the output of the binary

In analog to digital converter (ADCs) sample - and - hold circuits are designed to
counter during the conversion process

What is the Purpose of Sample and Hold Circuit? To keep temporary memory

The most common ADC seen in telecommunications based on audio signals is flash ADC
Identify from the following performance parameter of ADC in which suits the definition of
Aliasing
no. of samples per second.
converts the sample-and-hold output to
The quantization process
binary code
Aliasing results in oversampling
The dual slope analog to digital conver finds extensive use in _____ digital voltmeter
A digital voltmeter uses a flash ADC

It requires the input voltage to be applied

What is the Primary disadvantage of the Flash analog to digital converter (ADC)?
to the inputs simultaneously

What is the Conversion time of flash converter? 20s

In a flash Analog to Digital convertor,the output of each comparator is connected to an
decoder
input of a ______________
The throughput of a flash ADC is measured in displacement per second
The main advantage of the successive - approximation A/D converter over the counter -
more complec circuitry
ramp A/D converter is its:

The ADC0808 is an example of a _____________ Single -slope analog to digital converter

Memory is a/an ___________ Device to collect data from other computer

A flip flop stores __________ single bit of information

A register is able to hold __________ of information bit
Which of the following parameter of memory defines the section of memory in a single
Memory Location
memory array?
Which of the following parameter of memory defines the group of chips that make up a
Memory Location
memory module that stores data in units such as words or bytes?
Which of the following parameter of memory defines the maximum number of bits that can
Memory Location
be read or written into the memory at a time?

Which of the following parameter of memory defines the time taken by RAM to complete Access Time
read/write operation from the instant that an address is sent to the memory?

Which of the following parameter of memory defines the sum of access time & additional
Access Time
time required before a second access can commence in case of RAM ONLY?

Data stored in an electronic memory cell can be accessed at random and on demand using
Memory Addressing
__________
A ROM is defined as __________ Read Out Memory

Why are ROMs called non-volatile memory? They lose memory when power is removed

Which type of ROM has to be custom built by the factory? EPROM

CD-ROM refers to __________ Floppy disk

Which of the following memories are magnetic memory type? Main Memory
Which of the following memory is an example of sequential access memory? Floppy Disk
The full form of PROM is __________ Previous Read Only Memory
Which of following processes matches for Fusing process in PROM? It is Reversible Process

Which of the following best describes EPROMs? EPROMs can be programmed only once

The full form of EPROM is __________ Easy Programmable Read Only Memory

Which type ROM can be used to erase the contents by an electrical signal? ROM
Which of the following is NOT an application of SRAM? Computer Cache Memory
How many no. of transistors are used in fabricating a SRAM Chip? 4
Which of the following operations are performed by SRAM? Write Operation
Which of the following operations are performed by DRAM? Write Operation
Which of the following devices used in fabricating a Dynamic RAM ICs? Capacitor or MOSFET
High power consumption
Which of the following features best defines about Dynamic RAM?
Large storage capacity

What is the disadvantage of MOS capacitor in DRAM? It can’t hold the data till a long period

With which of the following two memory devices, NVRAM Chip is formed? EPROM & DRAM
Which of following is the most widely used type of NVRAM? Flash Memory type
Which of the following type of NVRAM stores the information in the form of voltage in a
Flash Memory type
capacitor?

When both the AND and OR are programmable, such PLDs are known as __________ PAL

Applications Specific Integrated Circuit

Which of the following approach in digital circuit design work with fixed functions?
(ASIC)

Applications Specific Integrated Circuit

Which of the following design approach in digital circuits offers HIGHEST RELIABILITY?
(ASIC)

Which of the following design approach in digital circuits will NOT provide Design Applications Specific Integrated Circuit
Flexibility? (ASIC)

Applications Specific Integrated Circuit

Which of the following design approach in digital circuits will have Design Security Issues?
(ASIC)
The full form of PLD is __________ Programmable Large Device
The evolution of PLD began with __________ Externally Programmed ROM
For reprogrammability, PLDs use __________ PROM
Why antifuses are implemented in a PLD? To protect from high voltage
Which of the following is the type of Factory Programmable Logic Devices? MPGA
Which of the following is NOT the type of Field Programmable Logic Devices? CPLD
The full form of PLA is _____________. Programmable Loaded Array
Fixed AND Array
Which of the following combination best defines Programmable Logic Array (PLA)?
Fixed OR Array
PAL refers to ____________ Programmable Array Loaded
Which of the following design versions are NOT available in PAL devices? One-Time Programmable
Which of the following combination best defines Programmable Array Logic (PAL)? Fixed AND Array
Fixed OR Array
If a PAL has been programmed once ____________ Its logic capacity is lost
Which of the following output is generated from PAL circuit? Sum Term Output ONLY
Which of the following is/are the basic element/s of FPGA? Configuration Logic Block (CLB)
FPGA stands for __________ Full Programmable Gate Array
Which of the following is a reprogrammable gate array? EPROM
How FPGA differs from PLD? FPGA is slower than PLD
Which o fthe following display devices are NOT the type of Digital Displays Matrix Displays
In 7 segment display, how many LEDs are used? 7
In seven segment display, which of the following component is used to construct seven
Capacitor
segments?
In a Common Anode Seven Segment Display, which of the segment LEDs are ON for
Segments a, b, c, d, e are ON
displaying decimal digit '0'?
In a Common Anode Seven Segment Display, which of the segment LED will be OFF for
Segment b is OFF
displaying decimal digit '6'?
Which of the following type of Alphanumeric Display conatins LED aligned in the form of
Dot-Matrix Display
Matrix?

Which of the following factor is NOT an ADVNATGE of Multiplexed Displays? fewer wires are needed for connection

The full form of LCD is ____________ Liquid Crystal Display

Select the operating voltage range for LCDs. 3 to 15V
The ac voltage applied between segment
What is backplane in LCD?
and a common element
Which of the following type of LCD is used in Watches & Calculators? Direct Address LCD
Which of following DO NOT describe Active Matrix LCD? High Contrast
Which of following advantages is related to Active Matrix LCD? Low Cost
 Choice 2 Choice 3 Choice 4 Key
It can single bit of Data It has internal memory of 4 bit None of the above 2

Latch Circuits Encoder Circuit Shift Register Circuits 3

intermediate values present input values clock pulses 3

intermediate values both past output and present input present input values 3

edge-triggered Both None 2

a latch works on the principal of a latch works on the principal of astable

a latch works on the principal of oscillator 1
monostable multivibrator multivibrator
None Q output goes LOW Q output goes LOW 4
No change Reset Invalid 2
SET READY SET RESTART START RESET 1

when the output follows the input when you can see through the IC packaging None 2

No change will occur in the output The output will toggle The output will reset 2

astable oscillator racer switch debouncer 4

It has a RACE condition It has no clock Input It has only a single input 2
Q output follows the Input D when the The output compliment follows the input when
Only one of the input can be high at a time 2
enable is high enabled
Reset Toggle No change 4
Propogation Delay Time Interval time setup time 3
Produces Decoding Error Prone to Glitches Simple Circuit Design 4
MOD-6 Counter MOD-16 Counter MOD-4 Counter 3

the actual number of states in its sequence the number of times it recycles in a second the number of logic gates used 2
 a binary counter A BCD counter an octal counter 3
Decade Counter Divide by 10 Counter Modulus of 10 Counter 1
1011 1111 1000 4
6 8 16 3
8 16 32 4
3 flip-flops 4 flip-flops synchronous clocking 3

24 ns 36 ns 48 ns 4

IC 7493 IC 74160 IC 74163 4

(1111)2 (1101)2 (1110)2 2

100 1000 10000 3

MOD-9 MOD-10 MOD-30 3

Bidirectional Shift Register Universal Shift Register Ring Counter 1

SIPO PISO PIPO 3

divide by 4 divide by 8 divide by 16 1

two clock pulses four clock pulses eight clock pulses 4

one clock pulse for each 1 in the data eight clock pulses one clock pulse for each 0 in the data 1

8 μs 80 ms 100 ms 1

in the propagation delay time of EIGHT in the propagation delay time of ONE flip-
8 μs 4
flip-flops flop
IC 74164 IC 74194 IC 74195 3
4 Flip-flops 12 Flip-flops 5 Flip-flops 1
4 Flip-flops 12 Flip-flops 5 Flip-flops 2
 digital analysis calculator data accumulation converter digital-to-analog converter 4
incorrect output codes offset error nonmonotic and offset error 4

differential nonlinearity low and high gain all of the above 4

error in the slope of the output staircase more or less input voltage is required for
None 2
waveform the first step than what is specified

5mA 500μA 50mA 1

the lowest binary weighted input the first input the last input 1
The Virtual Ground is elimated and the circuit
it has a fewer part of the same number of Its Operation is much easier to analyse is therefore easier to understand and 1
inputs
troubleshoot

Aliasing shannon frequency sampling stair-stepping 1

stabilize the comparator threshold voltage stabilize the input analog signal during the sample and hold the D/A converter staircase
3
during the comparison process conversion process waveform during the conversion process

Tp hold a voltage constant so an ADC has To hold a voltage constant so a DAC has To hold data after multiplexer has selected an 2
time to produce an output time to produce an output output
successive approximation ADC sigma-delta ADC dual slope ADC 3

Quantization Error Resolution Sampling Frequency 4

converts a sequence of binary codes to a filters out unwanted frequencies before
converts a sample impulse to a level 3
reconstructed analog signal sampling takes place
undersampling guard-band formation perfect sampling 2
function generators frequency counters all of the above 4
successive approximation ADC sigma-delta ADC dual-slope ADC 4

a large number of output lines is required a large number of comparators is required to

a long conversion time is required 4
to simultaneously decode the input voltage represent a resonable sized binary number

10s 1s The Conversion takes place continuously 4

 priority encoder multiplexer demultiplexer 2

distance per second samples per minute samples per second 4

less complex circuitry longer conversion time shorter conversion time 4

successive approximation analog to digital

dual slope analog to digital converter digital ramp analog to digital converter 4
converter

Block of data to keep data separately Indispensable part of computer Device to connect through all over the world 3

two bits of information four bits of information eight bits of information 1

word nibble double word 2

Memory Address Memory Bank Memory Rank 3

Memory Address Memory Bank Memory Rank 4

Memory Address Memory Bank Unit of Transfer 4

Memory Cycle Time Transfer Rate Unit of Transfer 1

Memory Cycle Time Transfer Rate Unit of Transfer 2

Direct Addressing Indirect Addressing Control Unit 3

Read Once Memory Read Only Memory Read One Memory 3

They do not lose memory when power is They lose memory when power is supplied They do not lose memory when power is 2
removed supplied
EEPROM Masked ROM PROM 3

Compact Disk-Read Only Memory Compressed Disk-Read Only Memory Compressed Disk-Random Access Memory 2

Secondary Memory Static Memory Volatile Memory 2

Hard Disk Magnetic Type Memory RAM 3
 Programmable Read Out Memory Programmable Read Only Memory Previous Read Out Memory 3
It is Irreverible Process It is Synchronous Process It is Asynchronous Process 2
EPROMs can be erased by shorting all
EPROMs can be erased by UV EPROMs can be erased electrically 2
inputs to the ground
Eradicate Programmable Read Only
Erasable Programmable Read Only Memory Easy Programmable Read Out Memory 2
Memory
Masked ROM EPROM EEPROM 4
Digital Cameras & Cell Phones LCD Screens Workstations & Servers 4
5 6 7 3
Read Operation Refresh Operation Both a & b ONLY 4
Read Operation Refresh Operation All of the above 4
FET or JFET Capacitor or BJT BJT or MOS 1
Low power consumption Low power consumption High power consumption
2
Large storage capacity Less storage capacity Less storage capacity

It doesn’t holds the charge till a long period It is highly densed It is not flexible 2

EPROM & SRAM EEPROM & DRAM EEPROM & SRAM 4

Ferroelectric RAM (FeRAM) Magneto Resistive RAM (MRAM) SRAM 1

Ferroelectric RAM (FeRAM) Magneto Resistive RAM (MRAM) SRAM 2

PPL PLA APL 3

Fixed Function ICs Programmable Logic Devices (PLDs) None of the above 2

Fixed Function ICs Programmable Logic Devices (PLDs) None of the above 1

Fixed Function ICs Programmable Logic Devices (PLDs) None of the above 1

Fixed Function ICs Programmable Logic Devices (PLDs) None of the above 2

Programmable Long Device Programmable Logic Device Programmable Lengthy Device 3

 RAM PROM EPROM 1
EPROM CDROM PLA 2
To increase the memory storage To implement the programmes As a switching devices 3
PLA PAL CPLD 1
PLA PAL ROM 4
Programmable Array Logic Programmable Logic Array Programmed Array Logic 3
Fixed AND Array Programmable AND Array Programmable AND Array
4
Programmable OR Array Fixed OR Array Programmable OR Array
Programmable Logic Array Programmable Array Logic Programmable AND Logic 3

UV Erasable Version Flash Erasable Version None of the above 4

Fixed AND Array Programmable AND Array Programmable AND Array 3
Programmable OR Array Fixed OR Array Programmable OR Array
Its outputs are only active HIGH Its outputs are only active LOW It cannot be reprogrammed 4
SOP Term Output Product Term Output ONLY POS Term Output 2
Interconnections I/O Block all of the above 4
Full Programmable Genuine Array First Programmable Gate Array Field Programmable Gate Array 4
FPGA Both a & b ROM 3
FPGA has high power dissipation FPGA incorporates logic blocks None of the above 3
CRTs Numeric Displays Multiplexed Display 2
8 9 10 1

Diodes Inductor LED 4

Segments a, b, c, d, e, f are ON Segments a, b, c are ON Segments a, c, d, e, f, g are ON 2

Segment c is OFF Segment d is OFF Segment g is OFF 1

Mutliplexed Display Liquid Crystal Display Twisted Nematic Display 1

reduced cost reduced power consumption None of the above 4

Logical Crystal Display Logical Crystalline Display Liquid Crystalline Display 1

 10 to 15V 15 to 24V 10 to 32V 1
The dc voltage applied between segment
The amount of power consumed For adjusting the intensity of the LCD 1
and a common element
Passive Matrix Display Active Matrix Display Twisted Nematic Display 1
High Resolution High Viewing Angle High Cost 4
Fast Response Time High Viewing Angle Both a & b ONLY 4