2015 5th Nirma University International Conference on Engineering (NUiCONE)
Design of SRAM Array Using 8T Cell for Low
Power Sensor Network
Colin David Karat
VLSI Design and Embedded System,
SIT, Valachil-574143
Mangaluru, India
Abstract—The application of sensor networks varies from
medical field to the military application. The raw data onto the
sensor node is of large quantity and it is necessary to store these
data bits. In this paper, design of optimized Static Random
Access Memory (SRAM) array for the sensor application is
implemented. SRAM cell is designed using 8T. The Half Select
Condition Free Cross Point 8T SRAM is modified, using
transmission gates as access transistors. By simulation, it is
observed that the write-ability is enhanced and reduction in the
power dissipation. Apart from the memory cell, the SRAM array
has been constructed using the optimized peripheral circuits.
Simulations show that reading and writing of data takes place
correctly.
Keywords—SRAM array , Sensor Network, Static Noise Margin.
I. INTRODUCTION
The common man’s lifestyle is revolutionized by the
development of wireless sensor network. The application of
sensor network ranges from military surveillance to farming
fields. In the field of medical electronics, wireless sensors are
used for the medical diagnosis like heart beats monitoring,
blood sugar values etc. Health monitoring analysis requires
feedback. The limited energy source and heat dissipation limit
the required sensor nodes to be highly energy efficient.
Even with most energy-efficient sensor network the power
consumption is in order of tens of mill watts. The continuous
transmission of sensed raw data would lead to data congestion
in the sensor network [1]. Hence, signals are processed to
reduce the amount of data transmission. This requires large
memory area to store the data bits. The computation intensive
wireless sensor node with increased memory size significantly
to reduce the requirement of data transmission.
The SRAM array is used as the representative memory for
Large Scale Integration (LSI), because of its fast operation and
low power consumption in standby mode. Around 40% of the
logic LSI is occupied by the SRAM array nowadays, so that
the nature of the logic LSI such as the power, supply voltage,
978-1-4799-9991-0/15/$31.00 ©2015 IEEE
Soorya Krishna K
Electronics and Communication,
SIT, Valachil-574143
Mangaluru, India
and the chip size is limited by the characteristic of the SRAM
array [2]. The SRAM cache consists of an array of bi- stable
memory bit cells along with peripheral circuits. Efficient
SRAM arrays design will be useful in reducing power
consumption. The trade- off of SRAM array area for achieving
low power consumption is a viable option for reducing the
overall form factor of wireless sensor network [1]. In energy
constrained application such as sensor nodes and medical
implants, energy efficiency and reliability will be the main
issues. The size of the wireless sensor node is limited by
energy carrying capacity (battery size) hence increased energy
efficiency of SRAM array would require smaller size battery
[1].
In the SRAM array design, the memory cell is an important
component which decides the performance of the array. Basic
SRAM cells are constructed using 6T and improved using
various techniques called as bit cell optimization [2]. Based on
the type of applications, 6T SRAM cells are moved to 7T, 8T,
10T etc. In [1] and [3], 8T SRAM architecture is used to
overcome from 6T SRAM trade off. Using 8T SRAM cells,
power consumption is reduced and write-ability is improved.
Different types of 8T SRAM architectures such as
Differential Data Aware Power Supplied (D2AP) [4], Half
Select Condition Free Cross Point 8T (CR8T) [5] etc, are
developed. The other structures available are Read Decoupled
8T and 10T Cell [1]. In this, read operation has been
decoupled to avoid half select problem by providing separate
read/ write ports.
The implemented design is a further modification of CR8T
structure which gives us better Write Margin (WM) and
reduces power dissipation. The proposed CR8T is
implemented using two Transmission Gates (TG) in place of
NMOS access transistors.
Section 2 describes the design of SRAM array of bit cells and
its peripheral circuits such as Sense Amplifier, Decoder, and
Write Driver. Section 3 gives simulation results. Section 4
gives simulation of 4x4 SRAM array and Conclusion is given
in Section 5.
 II. DESIGN OF SRAM ARRAY

A. Design of Modified CR8T SRAM Cell

Half Select Free Cross Point (CR8T) SRAM cell comprises

access transistor (M3, M4, M5, M6), driver transistors (M1
and M2) and load transistor (M7 and M8). The access
transistor is controlled by the Word Line (WL) and Word
Line (WLB) [5]. On signal activation, the internal storage
nodes are exposed to bit lines. In the, modified CR8T, two
access transistors of CR8T are replaced by Transmission
Gates (TG) as shown in Fig. 1. In case of CR8T, data will pass
from the bit line to cell only when access transistor is on. The
data onto NMOS and PMOS of TG is complementary, only
then data passes from BL to the cell node Q. Due to the TG
lower impedance, the Write Ability (WA) of the cell has been
enhanced. Hence, the degradation of WM in CR8T is
overcome. SRAM cells are selected only if both WL and WLB
are complementary and hence internal storage node gets
exposure to the bit lines.
Transistor Width to Length (W/L) values in the Modified
CR8T cell is designed based on the equation 1 and 2 [6].
Fig. 1: Modified CR8T SRAM
(W/L)3/(W/L)1 = 2[(VDD-1.5Vtn)/(VDD-2Vtn)2] (1)
The layout of Modified CR8T SRAM shown in Fig. 2.The
(W/L)5/(W/L)3 = µn/µp[(VDD-1.5Vtp)/(VDD+2Vtp) ] 2
(2) bit lines are constructed using metal-1indicated by BL and
BLBAR, word lines are constructed using metal-2 indicated as
WORD and WORDBAR.
Where (W/L)3/(W/L)1 is the Aspect Ratio (AR) of access
transistor to the driver transistor and (W/L)7/(W/L)3 is the AR of
load transistor to access transistor. Vtn is the threshold voltage of
NMOS in equation 1 and Vtp threshold voltage of PMOS in equation
2. For the stable working, the cell is designed for kp = kn and
µn=2µp. For finding the stable region of operation, the butterfly
diagram of modified cell is plotted. The Table I shows the
W/L of modified CR8T SRAM.

TABLE I
W/L Values of the Modified CR8T Transistor

Transistor W/L Ratio(µm)

Load (M7, M8) 10/0.18

Driver (M1,M2) 5/0.18

Transmission Gates 8/0.18 Fig. 2: Layout of Modified CR8T

NMOS (M3, M4)

B. Sense Amplifier
Transmission Gates 8/0.18
PMOS (M5, M6) There are different types of sense amplifier available [7],
[12]. Because of the constraints faced in case of current mirror
and voltage latch type sense amplifier, Current Mode Voltage
Sense Amplifier (CMVSA) has been preferred for 8T SRAM
it is chosen based on the high speed of operation and low In the layout, Metal -5 is used for common VDD and Metal-4
power dissipation [7]. for the ground.

Fig. 4: Schematic of 2 to 4 Domino CMOS Wallace Tree

Decoder

Fig. 3: Layout of Current Mode Voltage Sense Amplifier

The layout of CMVSA is shown in Fig. 3. The two PMOS at
the top is pre-charged by SE_1 and SE_2 at the beginning of
the cycle and then the NMOS at the bottom is turned ON by
Sense Enable (SE).

C. Domino CMOS Wallace Tree Decoder

Implementations of different decoders are described in [8]

and [9]. The number of transistors used in different decoder
structure is given in Table II. Based on the Table II, it is found
that Domino CMOS Wallace Tree Decoder is better at higher
frequencies with less power dissipation.

TABLE II
Number of Transistors Required
Type of Decoder 2:4 Decoder 3:8 Decoder

Basic Gates 28 70
Fig. 5: Layout of 2 to 4 Domino CMOS Wallace Tree Decoder
Wallace Tree 23 51
D. Write Driver
Domino CMOS 25 55
Different types of write driver circuits are analyzed namely
transmission gate type, stacked NMOS type and two input
AND gate [12]. A simple write driver is used here and its
layout is shown in Fig. 6 [10]. Its function is to quickly
The 2 to 4 Domino CMOS Wallace tree decoder schematic discharge one of the bit lines from pre-charge level to below
and layout are shown in Fig. 4 and Fig. 5. The PMOS in the the write-margin of the cell. Only one write driver is necessary
inverter part of the decoder is twice the aspect ratio of NMOS. for each column of SRAM array. Even though greater
discharge of highly capacitive bit-line is required in write
operation still it takes place faster than read operation.
Normally the write driver is enabled by Write Enable (WE)
signal and drives the bit line using full swing discharge from
pre-charge level to the ground. Only when the WE is high
input data will pass to the cell. The difference between write
drive for bit line bar and the bit line is a single inverter before
the input data.

Fig. 8: Write Operation of proposed CR8T SRAM Layout

The comparison of the schematic and layout response is
shown in Fig. 9. It appears that there exists a significant
difference between the schematic and layout responses. This is
because of the parasitic effect in the
layout.

Fig. 6: Layout of Write Driver Circuit for BL

III. SIMULATION RESULT

A. Read Write Operation of Modified CR8T

In read-write operation of modified CR8T, there is an

Fig. 9: Comparison of Modified CR8T Layout versus
enhancement in the write-ability of the cell as shown in Fig.
Schematic
7. The write operation of modified CR8T layout is shown in
Fig. 8.
B. Butterfly Diagram of Proposed CR8T

The equal butterfly response of modified CR8T SRAM Cell

is shown in Fig. 10. It is observed that low noise margin and
high noise margin are equal. This is the required condition for
the stable circuit [11].

Fig. 7: Modified CR8T SRAM Read Write Operation Fig. 10: Butterfly Diagram of Modified CR8T Structure
C. Rail to Rail Smulation of CMVSA Layout
The rail to rail simulation of the layout of CMVSA is shown
in Fig. 11. The bit lines are exited with pulsed input. The
V(se) is enabled after 1.5µs and the data is read at the Vout.
Fig. 11: Simulation Result of CMVSA Sense Amplifier
D. Simulation of Domino CMOS Wallace Tree Decoder
Layout
The Layout response of Domino CMOS Wallace tree decoder
is shown in Fig. 12.
Fig. 12: Response of 2 to 4 Domino CMOS Wallace Tree
Decoder
The comparison of schematic and layout simulation is shown
in Fig. 13.
Fig. 13: Comparison of Domino CMOS Wallace Tree Decoder
Layout versus Schematic
E. Layout Simulation of Write Driver Connected to Bit Line
The data is passed on to the BL only during the WE period,
after this cycle it does not write data into the cell. The
waveforms are as shown Fig. 14.
Fig. 14: Output of Write Driver Layout for Bit Line
Comparison of layout and schematic output of write driver is
shown in Fig. 15.
Fig. 15: Comparison of Write Driver Layout versus Schematic
IV. RESULT OF 4X4 PROPOSED CR8T STRUCTURE
A. Layout of Proposed CR8T Structure
The layout of 4x4 SRAM array is shown in Fig. 16. The
4x4 layout consist SRAM cells which are connected to one
another by word line by Metal-2. The bit lines are drawn using
Metal-1. The pre-charging of the bit lines is made through
pseudo PMOS. The row and column decoder are constructed
and connected to the word line and bit lines of the cell.
Column decoder was connected to the pass transistor, to select
the appropriate column to which the data is to be written. The
sense amplifier is carefully designed to obtain the fall swing
during the read operation. The write driver is connected to the
bit line and bit line bar through which the pre-charge is
discharged and data is written into the selected cell.

Fig. 16: Layout of 4x4 8T SRAM Array with Peripheral
Circuits
Fig. 17 shows the read write operation of 4x4 modified
CR8T array. Data “1” is written to first cell of first row of the
array all the other cells in column 1 is “0”. The data is read
when sense enable signal is applied and output is taken at V
(out).
Fig. 17: Read/Write Operation in SRAM Array
V. CONCLUSION
CR8T structure is modified by replacing NMOS access
transistor by TG. From the simulation results, it is observed
that the write-ability of the cell is improved. Optimized
peripheral circuits such as Sense Amplifier, 2 to 4 Domino
CMOS Wallace Tree Decoder, and pseudo PMOS pre-charge
circuits are designed. Schematic as well as layout of each
circuit is constructed and working is verified. Using these
peripheral circuits along with SRAM cell, 4x4 array is created
and tested for read and write operations.
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