Circuit placement is the process of determining the location of each gate
(or block in some cases) in the netlist. The traditional objectives include wire- length, timing, and congestion. Recently, thermal hotspot, power consumption, and power supply noise issues drew much attention because the location of gates has a non-negligible impact on these reliability concerns. In order to han- dle large-scale circuits, placement is usually done in two steps: global place- ment and detailed placement as in the case with routing. Global placement is mainly concerned with “rough” location of the gates, e.g., which region of the chip a gate is located. Some gates may be overlapping with each other in a global placement solution. These overlaps are then removed during the detailed placement. This chapter presents sample problems related to the following works: Mincut placement [Breuer, 1977] and terminal propagation [Dunlop and Kernighan, 1985] Gordian placement [Kleinhans et al., 1991] TimberWolf algorithm [Sun and Sechen, 1995] The first work is based on utilizing partitioning to perform placement. The second work is based on quadratic placement. The third work is based on Sim- ulated Annealing [Kirkpatrick et al., 1983]. The first two are global placers, while the third does both. These works are targeting wirelength reduction.