Microcomputer Block Diagram

CPU

A dd re ss Bu s Da ta Bus Co n tro l Bu s

In t e rf a ce Circ uit r y RAM ROM Perip h er a l D e vice s

F1-1

TM-1

CPU Functional Units

CPU

In st r uc t io n Re g ist e r ( IR)

Pro gr am Co u nt er ( PC)

Inst r u ct io n De co d e an d C on t r o l U nit

Re g ist e r 0 Re g ist e r 1

A r it h m et ic an d Lo g ic Un it ( A LU ) Reg ist er n - 1

F1-2

TM-2

Opcode Fetch

CPU
A d dr e ss Bu s

N Pr o g ram Co u n t e r D a t a Bu s

Op c od e Inst ru ct io n Re g ist e r Co nt ro l Bus Clo ck Re ad

RA M
N+2 N+1

Op co d e

N N-1

F1-3

TM-3

Memory Maps

1 Byte
F FFF 7 6 5 4 3 2 1 0 6 5 ,5 3 5 FF FF

4 K ROM
F0 0 0 EFFF

4 4 K Em pt y

H exa d ec im al A d dr esse s

De cim a l A dd re sse s

. . .
0004 0003 0002 0001 0000

4000 3 FFF

4 3 2 1
0 0000

1 6 K RA M

F1-6/7

TM-4

16-Bit Addresses

Bit 1 5 = m os t -sig n if ican t b it

B it 0 = lea st -sig n if ica nt bit

15

14

13

12

11

10

(a )

9
1 0 0 1 1

C
1 0 0 1 1

F
1 1 0

3
0 1 1

(b )

F1-8

TM-5

The Development Cycle

S pecify software

Design software

E dit

Translat e

P reliminary t est ing

C oncept

Int egrate and verify

Product

S pecify hardware

D esign hardware

Build prot otype

P reliminary t est ing

1-11

TM-6

Steps in the Development Cycle

List ing f ile ( .L ST)

L ist in g f ile ( .M A P)

Edit o r

Sou rc e f ile (. SRC)

A sse m b le r

Ob je ct f ile (. OBJ)

L in ke r/ lo ca t o r

A b so lut e o b je ct f ile

Sim ula t o r

So f t ware sim u lat io n

(For a b solu t e f iles) Em u lat o r Ha rdw are em u lat io n

Le g e nd : Ut ilit y p ro g ram o r d ev elo p m e nt t o o l

OBJHEX c o nv er sio n

He x f ile (. HEX)

Do wn lo ad / t e rm in al e m ula t e

RA M

Use r f ile EPROM Pro g ram m er Ex ec ut io n e nv iro nm e n t EPROM

Fact o ry m ask p ro ce ss

ROM

1-13

TM-7

Motorola S-records
S00900006D796E616D656F S11320003C3C000A327C201661000020534666F4F2 S11320101E3C00E44E4E53636F7474204D61634B59 S10C2020656E7A6965200D0A0061 S113202A1E3C00F81019670000064E4E60F64E7505 S9030000FC
(a)

S1 1 3 2 0 0 0 3 C3 C0 0 0 A 3 2 7 C2 0 1 6 6 1 0 0 0 0 2 0 5 3 4 6 6 6 F4 F2

Che ck sum Da t a By t es Lo ad A d d r ess Byt e Co u n t Re co r d T y pe

(b)

1-14

TM-8

68000 Programmer's Model

31

16

15

8 7

D0 D1 D2 D3 D4 D5 D6 D7
31 16 15 0

D at a Re g is t e rs

A0 A1 A2 A3 A4 A5 A6
31 16 15 0

A dd re ss Reg ist ers

A7 A7
31 24 23 0

U ser St ack Po int e r ( USP) Su p erv iso r St ac k Po in t e r (SSP)

PC Pro g ra m Co un t er
15 8 7 0

123
CCR

SR St a t u s Re g ist e r

F2-1

TM-9

68000 Status Register

U ser By t e ( Co nd it io n Co d e Re gist er )
9 I1 8 I0 4 X 3 N 2 Z 1 V 0 C

Syst e m Byt e
15 T 13 S 10 I2

123
Carry Ove rf lo w Ze ro Ne g at ive Sig n Ex t e nd Int er rup t M ask Sup e rviso r St a t e Trac e Mo d e

F2-4

TM-10

Condition Code Computation

1 1 1

00011001 01110000 10001001

Z = 0 N = 1

C = Sm D m + Rm D m + Sm Rm = 0 0 + 0 0 + 0 0 = 0 V = Sm Dm Rm + Sm D m Rm = 0 0 0 + 1 1 1 = 1 X = C = 0

Rm = 1 Dm = 0 Sm = 0

F2-5

TM-11

68000 Memory Map -- Byte View --

1 By t e ( 8 b it s) F FFFF F

0 000 04 0 000 03 0 000 02 0 000 01 00 000 0

F2-7

TM-12

68000 Memory Map -- Word View --

1 W ord ( 1 6 b it s)

FFF FFE

By t e FFF FFE

By t e FFF FFF

N ot e : Ev e n b y t e s co r re spo n d t o u p pe r b yt es o n t h e ex t e rn al d at a b us. Od d b yt es c o r r esp o n d t o lo w e r b yt es o n t h e e xt er n al d at a b us.

By t e 4 By t e 2 By t e 0 By t e 5 Byt e 3 By te 1

0 000 04 0 000 02 00 000 0

F2-8

TM-13

68000 Memory Map -- Longword View --

1 L o ng w or d ( 3 2 b it s )

W or d a dd re ss: n + 4

B yt e n + 4

et c.

L o ng w o rd s ca n b e at a ny e ve n a dd re ss

n + 8 n + 4 n

B yt e n

B yt e n + 1

B y te n + 2

B y te n + 3

Wo rd ad d ress: n

W o rd ad dr ess: n + 2

F2-9

TM-14

68000 Addressing Modes

Mode Data Register Direct Address Register Direct Absolute Short Absolute Long Register Indirect Postincrement Register Indirect Predecrement Register Indirect Register Indirect with Offset Register Indirect with Index & Offset PC Relative with Offset PC Relative with Index and Offset Immediate Implied Register Assembler Syntax Dn An xxx.W or <xxx xxx.L or >xxx (An) (An)+ -(An) d16(An) d8(An,Xn) d16(PC) d8(PC,Xn) #data CCR, SR, USP, SSP, PC Effective Address Generation EA = Dn EA = An EA = (next word) EA = (next two words) EA = (An) EA = (An), An ` An + N An ` An - N, EA = (An) EA = (An) + d16 EA = (An) + (Xn) + d8 EA = (PC) + d16 EA = (PC) + (Xn) + d8 DATA = next word(s) EA = CCR, SR, USP, SSP, PC

Notes: EA = effective address An = address register Dn = data register Xn = address or data register used as index register CCR = condition code register SR = status register USP = user stack pointer SSP = supervisor stack pointer

PC = program counter ( ) = contents of d8 = 8-bit offset (displacement) d16 = 16-bit offset (displacement) N = 1 for byte, 2 for word, 4 for longword. (If An is the stack pointer and the operand size is byte, N = 2 to keep the stack pointer on a word boundary.) ` = is replaced by

T2-1

TM-15

Data Register Direct

Instruction: MOVE.B D0,D3 Register Contents Before:....D0.....10204FFF ...........D3.....1034F88A After:.....D0.....10204FFF ...........D3.....1034F8FF

On ly b it s 0 -7 af f ec t e d

F2-10

TM-16

Address Register Direct

Instruction:

MOVEA.L A3,A0
Mo ve t o a d dr e ss r e g ist e r

Before:

Register Contents A0.....00200000 A3.....0004F88A A0.....0004F88A A3.....0004F88A

After:

3 2 bit s are m ov e d

F2-11

TM-17

Absolute Short

Instruction:

MOVE.L #$1E,$800

So urc e a dd re ssin g m o d e is im m e d ia t e

Before:

**** MEMORY **** Address Contents 000800 12 000801 34 000802 56 000803 78 000800 000801 000802 000803 00 00 00 1E

De st in at io n a dd re ssin g m o d e is ab so lu t e sho rt

After:

3 2 -b it o p e ran d siz e m o v es d at a t o f o u r c on se cu t iv e b y t e lo ca t io n s

F2-13

TM-18

Absolute Long

Instruction: MOVE.B #$1E,$8F000 **** MEMORY **** Address Contents 08F000 FF 08F000 1E

Before: After:

D est ina t io n ad d ressin g m od e is a b so lut e lo n g

Op era n d siz e is b yt e

F2-14

TM-19

Register Indirect

Instruction:

MOVE.L D0,(A0)

Before:

**** MEMORY **** Address Contents 001000 55 001001 02 001002 3F 001003 00 001000 001001 001002 001003 10 43 83 4F

A0 co nt ain s t h e a d dr ess o f t h e d e st in at ion

Registers A0 00001000 D0 1043834F

A0 do e s no t ch an g e

After:

A0 00001000 D0 1043834F
A lo n g w o r d is w r it t e n t o ad d r e ss $ 0 0 1 0 0 0

F2-17

TM-20

Postincrement Address Register Indirect

Instruction:

MOVE.W (A5)+,D0

Before:

**** MEMORY **** Address Contents 001000 45 001001 67 001002 89 001003 AB 001000 001001 001002 001003 45 67 89 AB

Registers A5 00001000 D0 0000FFFF

A dd re ss re gist e r in cr em e n t e d b y nu m b e r o f b y t e s m ov e d, 2

After:

A5 00001002 D0 00004567

F2-18

TM-21

Predecrement Address Register Indirect

Instruction:

MOVE.W D0,-(A7)

**** MEMORY **** Address Contents Before: 001000 10 001001 12 001002 83 001003 47 After: 001000 001001 001002 001003 01 43 83 47

Registers A7 00001002 D0 00000143

A dd re ss re gist e r d e cre m en t ed b y nu m b e r o f b y t e s m ov e d, 2

A7 00001000 D0 00000143

F2-19

TM-22

Register Indirect With Offset

Instruction: MOVE.W 6(A0),D0 **** MEMORY **** Address Contents Before: 001026 07 001027 BF After: 001026 001027 07 BF

Ef f e ct ive a d dr ess is 6 p lu s va lu e in A 0

Registers A0 00001020 D0 00000000 A0 00001020 D0 000007BF

A d dre ss r e g is t e r do e s no t ch an g e

F2-20

TM-23

Register Indirect With Index and Offset

A d dr ess r e g ist e r Ind e x r eg ist er , 3 2 b it s

Instruction: MOVEA $10(A0,D0.L),A1 **** MEMORY **** Address Contents 00101C EF 00101D 10

Before:

Registers A0 0000100A A1 00000000 D0 00000002 A0 0000100A A1 FFFFEF10 D0 00000002

After:

00101C 00101D

EF 10

W o r d v alu e is sig n-e xt en d ed b e ca use d est ina t io n is a n a dd r e ss r e gist e r

No t e: EA = $ 1 0 + $ 1 0 0 A + $ 2 = $ 1 0 1 C

F2-22

TM-24

PC-Relative With Offset

Instruction:

MOVE.W $1020(PC),D5

**** MEMORY **** Address Contents Before: 001020 AB 001021 CD After: 001020 001021 AB CD

Registers PC 00001000 D5 12345678 PC 00001004 D5 1234ABCD

In st r uc t io n is t w o w o rd s lo ng , s o PC is in cr em e n t e d b y f o ur

F2-23

TM-25

PC-Relative With Index and Offset

Instruction:

MOVE.W $1020(PC,D0.W),D5
On ly lo w - o rd er 1 6 b it s o f D 0 use d a s ind e x

Before:

**** MEMORY **** Address Contents 001026 FE 001027 DC

Registers PC 00001000 D0 ABCD0006 D5 12345678 PC 00001004 D0 ABCD0006 D5 1234FEDC

After:

001026 001027

FE DC

F2-26

TM-26

Immediate

Instruction:

MOVE.L #$1FFFF,D0

Im m e dia t e d at a f ollo w

Before: After:

Register Contents D0 12345678 D0 0001FFFF

Base : $ = he xa d ecim al @ = oc tal % = b in a ry & ( o r n o t h in g ) = d ec im al ' A B' = A SCII ch ara ct er s

F2-28

TM-27

68000 Signals

Vc c (2 ) GND (2 )

A d dr ess Bu s

A1 -A 2 3

68000
D at a Bu s CL K AS R/ W FC0 Pro ce ssor St a t u s FC1 FC2 UDS L DS D TA CK A syn ch ro n o us Bu s Co n t ro l D0 -D1 5

MC 6 8 0 0 Perip h era l Co n t ro l

E V MA VPA

BR BG BGAC K

Bu s A rb it ra t io n Co n t ro l

B ERR Sy st e m Co n t r ol RESET HA L T

IPL0 IPL1 IPL2 In t e rrup t Co n t ro l

F2-33

TM-28

Upper Data Strobe and Lower Data Strobe

Int er n a l Sig n als

Bu s Sig n als

A2 3

A2 3

A1 A0

A1 WORD / BYT E UD S ( ev en b yt e) 1 0 A0 X 0 1 U DS 0 0 1 L DS 0 1 0

WORD / BYT E

LD S ( o dd b yt e )

( a)

(b )

F2-34

TM-29

Decoding with -UDS and -LDS

68 0 00
A 1 -A2 3 D 8 -D 1 5 D 0 -D7 A d d r e ss B us
D a t a B us ( u pp e r b y t e) D a t a B us ( l ow er b y t e )

A d dre ss De co d ing

Up p er RA M CS

Lo wer RAM CS

UD S

L DS

F2-36

TM-30

Generation of -DTACK

A d dre ss Bu s

6 80 0 0
A dd re ss De co d ing RA M Ad d re s s D e co d ing RA M

74 07 +5 V 10 K DT A CK

CS

740 7

CS

Fro m o t h e r RA Ms , ROM s, I/ O De v ic es , et c.

F2-36

TM-31

Function Code Outputs

Function Code FC2 0 0 0 0 1 1 1 1 FC1 0 0 1 1 0 0 1 1 FC0 0 1 0 1 0 1 0 1 Address Space Type (Undefined, reserved) User Data User Program (Undefined, reserved) (Undefined, reserved) Supervisor Data Supervisor Program CPU Space (Interrupt Acknowledge) T2-3

TM-32

Read Cycle Timing

DT AC K m u st b e asse rt ed b ef o r e t h e e n d o f S4 , ot h erw ise w ait st at es ar e in sert ed D at a lat ch e d in t o CPU at be g in nin g o f S7

S0

S1

S2

S3

S4

S5

S6

S7

CLK FC0 -FC2 A1 -A2 3 AS UDS L DS R/ W DT A CK D8 - D1 5 D0 - D7

F2-39

TM-33

Write Cycle Timing

S0

S1

S2

S3

S4

S5

S6

S7

CL K FC0 -FC2 A1 -A2 3 AS UDS L DS R/ W DT A CK D8 - D1 5 D0 - D7 F2-40

TM-34

Data Movement Instructions

Instruction EXG LEA LINK MOVE MOVEA MOVEM MOVEP MOVEQ PEA UNLK

Operation Exchange registers Load effective address Link and allocate stack Move source to destination Move source to address register Move multiple registers Move to peripheral Move short data to destination Push effective address Unlink stack T3-3

TM-35

Integer Arithmetic Instructions

Instruction ADD ADDA ADDI ADDQ ADDX CLR CMP CMPA CMPM DIVS DIVU EXT EXTB MULS MULU NEG NEGX SUB SUBA SUBI SUBQ SUBX Operation Add source to destination Add source to address register Add immediate data to destination Add short data to destination Add with extend bit to destination Clear operand Compare source to destination Compare source to address register Compare memory Signed divide Unsigned divide Sign extend Sign extend byte Signed multiply Unsigned multiply Negate Negate with extend Subtract source from destination Subtract source from address register Subtract immediate from destination Subtract short from destination Subtract with extend bit from destination T3-4

TM-36

CMP Example

Instruction:

CMP.B #'z',D7

A SCII co d e f o r 'z ' is $ 7 A D 7 also co n t a in s ASCII co d e f or ' z'

Register Contents Before: D7 FFFFFF7A SR 001F After: D7 SR FFFFFF7A 0014

D7 d o e s n o t ch an g e

Notes:

01111010 - 01111010 00000000

12 3

Z= 1 N = 0 V = 0 ( sig n b it d oe s n ot ch an g e) C = 0 ( b o rro w no t re q u ir ed ) X = 1 (n o ch an g e)

F3-5

TM-37

DIVS Example

Instruction:

DIVS #-3,D7

Div is or , - 3

Register Contents Before: D7 0000000E SR 001F After: D7 SR 0002FFFC 0018

D ivid en d , 1 4

Qu o t ie n t , -4

Re m ain d er , 2

Notes: 14 / -3 = -4 with a remainder of 2

F3-8

TM-38

Boolean Instructions

Instruction AND ANDI EOR EORI NOT OR ORI Scc TST

Operation AND source to destination AND immediate data to destination Exclusive OR source to destination Exclusive OR immediate data to destination Complement destination OR source to destination OR immediate data to destination Test condition codes and set operand Test operand and set condition codes T3-5

TM-39

EOR Example
Instruction: EOR.L D6,(A4)+ **** MEMORY **** Address Contents Before: 003100 AB 003101 CD 003102 EF 003103 10 After: 003100 003101 003102 003103 ABCDEF10 + 12345678 B9F9B968 1 2 3
Z= N = V = X = 0 1 C = 0 ( alw a ys) n ot af f e ct e d ( assu m e 0 )

Registers A4 00003100 D6 12345678 SR 0000

So ur ce o p e ran d

De st ina t io n o p e ran d

B9 F9 B9 68

A4 00003104 D0 12345678 SR 0008

A 4 in cre m en t ed by four

Notes:

F3-10

TM-40

Shift and Rotate Instructions

Instruction ASL Operation Arithmetic shift left
C X

Bit Movement
Op era n d 0

ASR

Arithmetic shift right

Op er a nd

C X

LSL

Logical shift left

C X

Ope ra nd

LSR

Logical shift right

Op e ran d

C X

ROL

Rotate left
C Op e ran d

ROR

Rotate right

Op er an d

ROXL

Rotate left with extend bit

Op e ran d

ROXR

Rotate right with extend bit

Op era nd

SWAP

Swap words of a longword

1 6 b it s

1 6 b it s

T3-6

TM-41

ASR Example

Instruction:

ASR.B D3,D2

A rit hm e t ic shif t righ t : sig n b it d o es n o t ch an g e !

Before:

Register Contents D3 00000002 D2 00000068 SR 001F D3 D2 SR 00000002 0000001A 0000

Sh if t c o un t in D3

Sh if t d at a in D 2

After:

Notes:

01101000 00110100 00011010 1 2 3 0

C = Z= N = V = X = 0 0 0 0 ( alw ay s)

F3-11

TM-42

Bit Manipulation Instructions

Instruction BCHG BCLR BSET BTST

Operation Change bit Clear bit Set bit Test bit T3-7

TM-43

BTST Example

Instruction:

BTST #7,D5

T e st b it 7 o f D 5

Before:

Register Contents D5 FFFFFF7F SR 0000 D5 SR FFFFFF7F 0004

Bit 7 = 0

After:

Z = 1

F3-12

TM-44

Binary-Coded Decimal Instructions

Instruction ABCD NBCD SBCD Operation Add source to destination Negate destination Subtract source from destination T3-8

TM-45

ABCD Example

Instruction: ABCD -(A3),-(A4) **** MEMORY **** Address Contents 00200E 98 00210E 54

O p e r an d siz e alw a ys b y t e

Before:

Registers A3 0000200F A4 0000210F SR 001F A3 0000200E A4 0000210E SR 0011

X= 1

After:

00200E 00210E
1

98 53

Bot h a d dr ess r e g ist e r s d e cr e m en t ed b y o n e

Notes:

10011000 01010100 1 + 1 1 11101101 + 00000110 11 1 11110011 + 01100000 01010011 1 2 3

---XNZVC 00010001
(X = 1 ) 98 + 54 + 1 = 15 3 ( t h e h u nd r e d s d ig it is st o r e d in C & X)

( ad d 0 6 )

( ad d 6 0 )

Z= 0 C = X = 1 N = V = u nd e f ine d ( a ssum e 0 )

F3-13

TM-46

Program Flow Instructions

Instruction Bcc BRA BSR DBcc JMP JSR NOP RTE+ RTR RTS +privileged instruction

Operation Branch conditionally Branch always Branch to subroutine Test, decrement, and branch Jump to address Jump to subroutine No operation Return and deallocate stack Return and restore condition codes Return from subroutine

T3-9

TM-47

BRA Example

Instruction:

BRA $20A0

Br a n ch d e st in at io n

Before:

**** MEMORY **** Address Contents 002050 60 002051 4E 002050 002051 60 4E

Registers PC 00002050
In st r uc t io n w o r d

After:

PC 000020A0

Notes:

Displacement = X 2052 + X = 20A0 X = 20A0 - 2052 = 4E

Bra n ch o f f s et , 8 b it s

F3-15

TM-48

BSR/RTS Example
BSR $ 4 0 F2
BEFO RE
RE GIS T ERS:

A FT ER
RE GIS T ERS:

PC A7

0 0 5 0 16 0 000 305 0

PC A7

0 0 4 0 F2 0 000 304 C

MEMO RY:

MEMO RY:

00 501 A 0 0 5 0 1 8 F0 DA 00 501 6 6 1 0 0

MA IN PROGRA M BSR $ 4 0 F2

00 50 1A 0 0 5 0 1 8 F0 DA 00 50 16 6 1 00

MA IN PROGRA M BSR $ 4 0 F2

0 0 4 0 F A 4 E7 5

RTS SU BROU TIN E

0 0 4 0 F A 4 E7 5

RTS SU BROU TIN E

0 0 4 0 F2

0 0 4 0 F2

00 3 05 0 1 234 00 3 04 E 5 678 0 0 3 0 4 C 9 A BC

A7 STA CK

00 3 05 0 1 234 00 3 04 E 5 01A 00 3 04 C 0 000

STA CK A7

a dd re ss o f ins t ru ct ion f o llo w in g BSR

RT S
BEFORE
REGIST ERS:

A FT ER
REGIST E RS:

PC A7

0 0 4 0 FA 0 00 0 3 04 C

PC A7

0 05 01A 0 00 0 30 5 0

ret u r n t o in st r u ct io n f o llo w in g BSR

MEMORY:

MEMORY:

00 5 01 A 0 0 5 0 1 8 F0 DA 00 5 01 6 61 00

MA IN PROGRA M BSR $ 4 0 F2

00 5 01 A 0 0 5 0 1 8 F0 DA 00 5 01 6 61 00

MA IN PROGRA M BSR $ 4 0 F2

0 0 4 0 FA 4 E7 5

RT S SU BROU TINE

0 0 4 0 FA 4 E7 5

RT S SU BROU TINE

0 0 4 0 F2

0 0 4 0 F2

003 050 1 2 34 003 04E 5 0 1A 003 04C 0 0 00

ST A CK A7

003 050 1 23 4 003 04E 5 01 A 003 04C 0 00 0

A7 ST A CK

F3-16

TM-49

System Control Instructions

Instruction ANDI++ CHK EORI++ ILLEGAL MOVE++ ORI++ RESET+ STOP+ TAS TRAP TRAPV

Operation AND immediate to status register/condition code register Trap on upper out-of-bounds operand Exclusive OR immediate to status register/condition code register Illegal instruction trap Move to/from status register/condition code register OR immediate to status register/condition code register Assert RESET line Stop processor Test and set operand Trap unconditionally Trap on overflow

+privileged instruction ++privileged instruction if SR specified T3-10

TM-50

TRAP Example

Instruction: TRAP #5 **** MEMORY **** Address Contents 002FFA 12 002FFB 34 002FFC 56 002FFD 78 002FFE 9A 002FFF BC 000094 00 000095 01 000096 80 000097 F0 002FFA 002FFB 002FFC 002FFD 002FFE 002FFF 000094 000095 000096 000097 00 1F 00 00 20 02 00 01 80 F0

Before:

Registers PC 00002000 A7' 00003000 SR 001F

Sy st e m St a ck Po int er

V ec t o r ad d r e ss f o r t ra p 5

V ec t o r f o r t rap 5

Exc ep t ion p ro ce ssing b e gin s at ad d r ess $ 0 1 8 0 F0

After:

PC 000180F0 A7' 00002FFA SR 201F

Sy st e m St a ck Po int er d e cr e m e nt ed by 6 Su p er viso r St a t e b it = 1

SR sa ve d o n syst em st ac k

PC sav ed o n sy st e m st a ck

Notes:

Vector read from address $80 + (5 x 4) = $94

F3-18

TM-51

68000 Instruction Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Operation Word (1st word specifies operation and addressing modes) Immediate Operand (if any, one or two words) Source Effective Address Extension (if any, one or two words) Destination Effective Address Extension (if any, one or two words) F3-19

TM-52

Effective Address Encoding

Addressing Mode Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Address Register Indirect with Index* Absolute Short Absolute Long Program Counter with Displacement Program Counter with Index* Immediate or Status Register * One extension word required Two extension words required For Immediate addressing, one or two extension words required depending on the size of the operation One extension word required; see Table C-4 for the encoding T3-11 Mode Bits 000 001 010 011 100 101 110 111 111 111 111 111 Register Bits register number register number register number register number register number register number register number 000 001 010 011 100

TM-53

68000 Condition Code Encoding

Mnemonic T F HI LS CC(HS) CS(LO) NE EQ VC VS PL MI GE LT GT LE

Condition true false high low or same carry clear carry set not equal equal overflow clear overflow set plus minus greater or equal less than greater than less or equal

Encoding 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Test 1 0 C Z C+Z
C

C
Z

Z
V

V
N

N
N V + N V N V + N V N V Z +N V Z Z + N V + N V

Not available for Bcc instruction Twos complement arithmetic = Boolean AND + = Boolean OR T3-12

TM-54

Opcode Map
Bits 15 through 12 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Operation Bit Manipulation/MOVEP/Immediate Move Byte Move Long Move Word Miscellaneous ADDQ/SUBQ/Scc/DBcc Bcc/BSR MOVEQ OR/DIV/SBCD SUB/SUBX (Unassigned) CMP/EOR AND/MUL/ABCD/EXG ADD/ADDX Shift/Rotate (Unassigned) T3-13

TM-55

Assembler Operation
PROG.OBJ

L eg e nd : Ut ilit y p ro g ram

PRO G.SRC

A68 K Use r f ile PROG.L ST

( a)

C o m m an d

Inp u t f ile

Lis t ing o ut ut f ile

O b je ct co d e o ut p ut f ile

A ssem ble r op t ion s

( b)

A 6 8 K PROG.SRC, PRO G.L ST , PROG.OBJ, X S

F4-1

TM-56

Assembler Files

La b el f ield

Mn e m o nic f ie ld

Op er an d f ie ld

C om m en t f ield (e m p t y )

PROG

LOOP

ORG.....$1000 LEA.....$800,A0 MOVE.B..#50,D0 CLR.W...D7 ADD.W...(A0)+,D7 SUBQ.B..#1,D0 BRA.....* END

Sou r ce f ile

( a)

L ine nu m b e r A d d re ss Co n t e n t s So u rce f ile

1 2 3 4 5 6 7 8
(b )

00001000.................ORG.....$1000 00001000.41F80800.PROG...LEA.....$800,A0 00001004.103C0032........MOVE.B..#50,D0 00001008.4247............CLR.W...D7 0000100A.DE58.....LOOP...ADD.W...(A0)+,D7 0000100C.5300............SUBQ.B..#1,D0 0000100E.60FE............BRA.....* 00001010.................END

L ist in g f ile

F4-2

TM-57

Listing Examples
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 00001000 00001000 00001002 00001004 00001008 00000064 0000100A 0000100E 00001012 00001016 0000101A 0000101E 00001022 00001026 0000102A 0000F000 0000102C 00001030 00001032 00001034 00001036 00001038 6006 60FE 6000FFFE 181B 3A3C0064 3A3C0064 3A3C0064 3A3C0064 3A3C0064 3E3CFFFB 3E3CFFFB 3A390000 F000 3A390000 F000 4E71 4E71 67FA ORG BRA BRA HERE BRA MOVE.B COUNT EQU MOVE.W MOVE.W MOVE.W MOVE.W MOVE.W MOVE.W MOVE.W MOVE PORT BACK EQU MOVE NOP NOP BEQ END $1000 *+8 * HERE (A3)+,D4 100 #COUNT,D5 #100,D5 #$64,D5 #144Q,D5 #%01100100,D5 #-5,D7 #$FFFB,D7 $F000,D5 $F000 PORT,D5 ;"*" location counter ;branch to itself ;branch to itself ;indirect addressing ;equate symbol to value ;symbol as immed. data ;decimal ;hexadecimal ;octal (A68K format) ;binary ;negative number, decimal ;negative number, decimal ;data address ;equate symbol as address ;data address (symbol) ;code address (NOP = ; no operation) BACK

F4-4

TM-58

Assemble-Time Operators
Operator .NOT. .LOW. .HIGH. .LWRD. .HWRD. * / + .MOD. .SHR. .SHL. .AND. .OR. .XOR. .EQ. .NE. .GE. .LE. .GT. .LT. .UGT. .ULT. Function Unary minus Logical NOT Low byte High byte Low word High word Multiplication Division Addition Subtraction Modulo Logical shift right Logical shift left Logical AND Logical OR Logical XOR Equal Not Equal Greater or equal Less or equal Greater than Less than Unsigned greater than Unsigned less than Precedence 1 1 1 1 1 1 3 3 4 4 3 3 3 5 6 6 7 7 7 7 7 7 7 7 Type Unary Unary Unary Unary Unary Unary Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary

Operators apply to A68K. Different assemblers may support different operators. Relational operators return 1s (true) or 0s (false). T4-1

TM-59

Examples of Assemble-Time Operators

1 2 3 4 5 6 7 8 9 10 11

00000064 00002000 00002000 00002004 00002008 0000200C 00002010 00002014 00002018 0000201C 00002020

COUNT 3A3CFFFF 3A3C0009 3A3C0001 3A3C0400 3A3C0040 3A3C0041 3A3CFFFF 3A3C0032

EQU ORG MOVE MOVE MOVE MOVE MOVE MOVE MOVE MOVE END

100 $2000 #-1,D5 #4+50/10,D5 #25.mod.6,D5 #$8000.shr.5,D5 #$45&$F0,D5 #.high.'AB',D5 #5.gt.4,D5 #COUNT/2,D5

F4-5

TM-60

Assembler Directives
Directive ORG EQU END DC DS RSEG EXTERN PUBLIC Operation set program origin equate value to symbol end of source program define data constant define RAM storage begin relocatable segment define external symbol define public symbol [label] [label] ORG symbol EQU END DC DS RSEG Syntax value value label number[,number][...] count name

EXTERN symbol[,symbol][...] PUBLIC symbol[,symbol][...]

T4-2

TM-61

Listing Examples
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Address 00001000 00001000 00000064 00002000 00002000 0000000D 00003000 00003000 00003004 00003006 0000300A 00004001 00004002 00005000 00005000 00000050 00006000 00006000 00006050 00007000 00007000 00007002 00007006 0000700A 0000700C 00000000 00000000 00000004 Contents 1A3C0064 1A3C0064 0005FFFF 05FF 4A4F484E 0D00 000F 6100 *************** ORG START MOVE.B COUNT EQU ORG HERE MOVE.B CR EQU ORG NUM DC MORE DC.B NAME DC.B DC.B ORG VALUE DC ORG DC.W LENGTH EQU ORG BUFFER DS.B TEMP DS.B ORG MOVE.L MOVEA LOOP MOVE.B SUBQ.B BNE RSEG BEGIN MOVE.B END CH4-6.SRC ********************* $1000 #100,D5 100 $2000 #COUNT,D5 $0D define a symbol $3000 set origin 5,-1 word size default 5,-1 byte size constants 'JOHN' ASCII string CR,0 CR is a symbol $4001 15 decimal constant $5000 'a' 80 $6000 LENGTH 1 $7000 #LENGTH,D1 use R1 as counter #BUFFER,A1 A1 points to buff #0,(A1)+ clear location #1,D1 done? LOOP no: clear again EPROM #44,D5

7250 327C6000 12FC0000 5301 66F8 1A3C002C

F4-8

TM-62

Linker Operation

P ROG .H EX F ILE 1 . OB J FIL E 2 .O BJ X LIN K F ILE 3 . OB J

Le g en d :
Ut i lit y pr o g r a m

Us er f ile F ILE 4 . O BJ PRO G. MA P

( a)

Co m m an d CPU In p ut f ile s

O pt i o ns f o llo w

A bso l u t e o u t p u t f i le f o r m at t e d in S- r ec o r d s

L ist in g f ile

XL IN K 6 8 K F IL E1 .OBJ FIL E2 .O BJ FIL E3 .O BJ FIL E4 .OB J / O= PROG.H EX M= PRO G.M A P

( b)

F4-10

TM-63

User Mode vs. Supervisor Mode

Feature Entered by FC2 = Active stack pointer Other stacks using SR access Read: Write: Instructions available User Mode Clearing S-bit in SR 0 USP A0 - A6 Entire SR CCR bits only All except AND #data,SR EOR #data,SR MOVE <ea>,SR MOVE USP,An MOVE An,USP OR #data,SR RESET RTE STOP T6-1 Supervisor Mode Exception processing 1 SSP USP, A0-A6 Entire SR Entire SR All

TM-64

Changing Between User Mode and Supervisor Mode

T ra ns it io n m a y o cc ur o n ly d ur in g ex ce pt io n p r o ce ssing

U ser M o de

Su pe rv isor Mo d e

T ran sit io n m ay o ccu r t h r o u gh f o u r in st r uc t io n s: MOV E t o SR A N DI t o SR EOR t o SR RT E

F6-1

TM-65

Exception Tree

Exc ep t ion

Ext e r n al

Int e r na l

In t er r u p t

In st r uc t io n

Exec ut io n Er r o r

Use r V e ct o r

A ut o V e ct o r

Bu s Er r o r

Re s e t

T RA P T RA PV CH K

T r a ce

D iv id eb y - ze r o

Pr iv ileg e V io la t io n

A - lin e o r F- line Em ula t io n

A d dr ess Er r o r

Ille g al In s t r uc t io n

F6-2

TM-66

Exception Processing Sequence

St art e xc ep t ion

Ma ke in t ern al c op y of SR

S = 1, T = 0

Int err up t ? no

y es

Up d at e in t e rru p t m a sk lev el

Ob t a in v ec t o r n um be r

V ec t o r a dd re ss = ve ct or n u m b er x 4

Pus h PC an d c o pie d SR o n t o st ac k

( V ec t o r ad d re ss) -----> PC

C on t in u e e xe cu t io n

F6-3

TM-67

Stack Frame for Exceptions

(except bus error and address error)

Hig h -Me m o r y
15 0

n+6 n+4 n+2 n Pro g r am Co u nt e r ( lo w ) Pr o g ra m C o un t e r (h ig h ) St at u s Re g ist e r

SP ( old )

SP ( n ew )

Lo w -Mem or y

F6-4

TM-68

Exception Vector Address

A3 1

A 10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

all ze r o s

V7

V6

V5

V4

V3

V2

V1

V0

V e ct o r n u m b er

F6-5

TM-69

Reset and Exception Vector Assignments

Vector Number 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-23 24 25 26 27 28 29 30 31 32-47 48-63 64-255 Hexadecimal Address 000 004 008 00C 010 014 018 01C 020 024 028 02C 030 034 038 03C 040-05C 060 064 068 06C 070 074 078 07C 080-0BC 0C0-0FC 100-3FC Assignment Reset SSP Reset PC Bus Error Address Error Illegal instruction Divide-by-zero CHK instruction TRAPV instruction Privilege violation Trace Line 1010 emulator Line 1111 emulator (reserved) (reserved) Format error (68010) Uninitialized interrupt vector (reserved) Spurious interrupt Level 1 interrupt autovector Level 2 interrupt autovector Level 3 interrupt autovector Level 4 interrupt autovector Level 5 interrupt autovector Level 6 interrupt autovector Level 7 interrupt autovector TRAP instruction vectors (reserved) User interrupt vectors

The reset vector is four words and resides in the supervisor program (SP) space. All other vectors reside in the supervisor data (SD) space. The spurious interrupt vector is taken when there is a bus error during an interrupt acknowledge cycle. Trap #n uses vector number 32 + n. See Table 6-5.

T6-2

TM-70

Exception Grouping and Priority

Group 0 Exception Reset Address Error Bus Error Trace Interrupt Illegal Instruction Privilege Violation TRAP, TRAPV CHK Zero Divide Processing Exception processing begins within two CPU cycles Exception processing begins before the next instruction

Exception processing begins by normal instruction execution

T6-3

TM-71

Traps vs. Subroutines

Features Initiated from Routine executes in Registers saved Registers saved on Routine ends with Privilege state after is Traps user mode or supervisor mode supervisor mode PC and SR system stack RTE user mode or supervisor mode Subroutines user mode or supervisor mode user mode or supervisor mode PC user stack or system stack RTS user mode or supervisor mode T6-4

TM-72

Vector Assignments for TRAP Instructions

Instruction TRAP #0 TRAP #1 TRAP #2 TRAP #3 TRAP #4 TRAP #5 TRAP #6 TRAP #7 TRAP #8 TRAP #9 TRAP #10 TRAP #11 TRAP #12 TRAP #13 TRAP #14 TRAP #15 Vector Number 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Vector Address $000080 $000084 $000088 $00008C $000090 $000094 $000098 $00009C $0000A0 $0000A4 $0000A8 $0000AC $0000B0 $0000B4 $0000B8 $0000BC T6-5

TM-73

Stack Frame for Bus Error and Address Error

Hig h - Me m o ry
15 0

n+1 4 n+1 2 n+1 0 n+ 8 n+ 6 n+ 4 n+ 2 n Prog r a m Co u nt er ( lo w ) Pr o g ram Co u n t e r ( h ig h) St at us Re g ist e r In st ruc t io n Re g is t e r Ac ce s s ad d r es s ( lo w ) A c c ess a dd re ss (h ig h ) A cc es s t yp e

SP (o ld )

SP ( ne w )

Lo w -M em o ry

( a)

15

u n de f in ed

R/ W I/ N FC 2 FC1 FC 0

142 4 3
Fu nc t io n C o de I/ N 0 = in s t r uc t io n 1 = n o t a n in st r u ct io n R/ W 0 = w r it e c yc le 1 = re ad cy cle

( b)

TM-74

F6-6

TM-75

Power-on Reset Timing

...

CL K
+5V

Vcc

0V

> 100 ms RESET

H A LT < 4 c lo c ks B u s Cyc les 1 SS P H SSP L PC H PC L 14 42 44 3 1 44 24 43 In it ializ e SSP In it ializ e P C

1 42 4 44
E xec ut e 1 st in st ru c t io n

L eg e nd :
1 Int er na l st art -u p t im e Bus s t at e u n kn ow n A ll c o nt r o l sig n als in ac t ive . D at a b us in r ea d m o d e Bu s c y cle ( m e m o ry r e ad o r m em o r y w r it e )

F6-7

TM-76

A Switch as an Input Device and an LED as an Output Device

+5 V Re sist o r 22 0 Sw it c h OPEN CL OSED L ED OF F ON

Sw it c h W ir e

LED

( a)

+5 V Re sis t o r 22 0 Sw it c h OPEN CL OSED L ED ? ?

Sw it c h Co m p u t e r

L ED

( b)

F7-1

TM-77

Interface to Switches and LEDs (conceptual)

D at a Bu s Ad d re ss Bus D15 6 800 0 D14 D13 D1 5 D1 4 D1 3

L ED # 7
D D D D D D D D Q Q Q Q Q Q Q Q

+5 V

0 0 C 0 0 0

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 UD S AS R/ W D T A CK Co n t ro l Bu s

D12 D11 D10 D9 D8

0 0 C

A2 3 A2 2 A2 1 A2 0 A1 9 A1 8 A1 7 A1 6 A1 5 A1 4 A1 3 A1 2 A1 1 A1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 U DS AS R/ W

D1 2 D1 1 D1 0 D9 D8

L ED # 0
WRIT E LED S

REA D SWIT C HES

0 0
+5 V

F7-2

TM-78

Timing for MOVE.B $00C000,D0

Op co d e f et ch Hig h- w o rd o f a d dr ess ( $0 000 ) Lo w - w o rd o f ad d re ss ( $ C0 0 0 ) Me m o ry lo ca t io n $ 0 0 C0 0 0

Mem or y r e ad CPU clo ck :

M em o ry r e ad

Me m o r y r ea d

M em or y r e ad

13 2
One clo ck p er io d t im e

t hre e - st a t e b uf f ers e na b led D a t a f r o m sw it ch e s lat ch ed int o r eg ist er D 0 , b it s 0 -7 , a t t h e st ar t of S7

S0

S1

S2

S3

S4

S5

S6

S7

CL K F C0 -FC2 A1 - A 2 3 AS UDS LD S R/ W DT A CK D 8 -D1 5 D 0 -D7

$ 0 0 C0 0 0

sw it c h d at a

F7-3

TM-79

Example of Partial Decoding

0 0 C
( a)

A 23 A 22 A 21 A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 UDS AS R/ W

0 0
REA D SW IT CH ES

A 23 A 22 A 21 A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 UDS AS R/ W

W RIT E L ED S

A d dr e ss: A23 0 0 0 0 A19 0 0 0 0 A15 1 1 0 0 A1 1 X X X X A7 X X X X A3 X X X A0 0

0
(b )

XX X0
F7-5

TM-80

Flowcharts for Program-Conditional I/O

In pu t F lo w c h ar t :

O ut p ut Flo w c h a r t :

E nt er

En t e r

Rea d D e v ic e S t a t u s Flag

Re ad D ev ice S t at us F la g

NO

D e vic e Re ad y ?
YE S

NO

De v ic e Rea d y ?
Y ES

In p ut D at a

Ou t p u t Da t a

Clea r Flag

Cle ar Fla g

Ex it

Exit

( a)

(b )

F7-7

TM-81

Keyboard Interface

D a ta Bu s

D8 Ke yb o ard KBD D A TA D D D D D D D D Q Q Q Q Q Q Q Q D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8

F L AG K EYH IT S Q R

REA D K BD D A T A REA D KBD ST A T U S ( a) Da t a ar e st o re d in lat ch an d f la g is se t

A k ey is pr ess e d

KBD DA T A K EYH IT ( b)

V alid D at a

F7-6

TM-82

Interface Using a Peripheral Interface IC

Da t a B us

CPU

A d dr ess Bu s Co nt ro l Bus

Pe r ip h e r al In t er f a ce IC
A1 A0 R/ W A d d r e ss D ec o din g Re ad St at us e t c. e t c. CS In p u t W rit e C o nt ro l etc . etc . Ou t p u t

Pe ri p h er a l Dev ic e

F7-9

TM-83

Program Execution Without Interrupts or With Interrupts

t im e

M ain P r o g r am

( a)

Int er r up t - le v el exe c u t io n * Base - lev el exe c u t io n

ISR

ISR

ISR

**

**

**

M ain

Ma in

M ain

Ma in

* ** ( b)

Int er r up t Ret ur n f r o m int e r r up t in s t r uc t io n

F7-11

TM-84

Interrupt Priority Conditions on IPL2, -IPL1, and -IPL0

Signal
IP2 IP1 IP 0

Interrupt 0 1 2 3 4 5 6 7

Condition No interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt

Maskable Yes Yes Yes Yes Yes Yes No

Priority Lowest (etc.) (etc.) (etc.) (etc.) (etc.) Highest T7-3

1 1 1 1 0 0 0 0

1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0

TM-85

Autovectors for Automatic IACK Cycles

Interrupt 0 1 2 3 4 5 6 7 Vector Address (Autovector) $000064 $000068 $00006C $000070 $000074 $000078 $00007C T7-4

TM-86

Vector Addresses for User IACK Cycles

Vector Number 0 1 2 etc. 255 Vector Address $000000 $000004 $000008 etc. $0003FC T7-5

TM-87

Interrupt Circuitry

+5 V 1 0K V PA 74 07

680 00
N o n - Mas k ab le In t er r u p t ( NM I) A3 A2 A1 +5 V

7 4 HC 1 3 8 C B A 7 6 5 4 3 2 1 0 IA C K 7 IA C K 6 IA C K 5 IA C K 4 IA C K 3 IA C K 2 IA C K 1

+5 V IN T 7 IN T 6 IN T 5 IN T 4 IN T 3 IN T 2 IN T 1 +5 V

7 4 H C1 4 8 7 6 5 4 3 2 1 0 AS E1 A2 A1 A0 IPL 2 IPL 1 IPL 0 FC 2 FC 1 FC 0 +5 V E1 E2 E3

E1 E2 E3

7 4 H C1 3 8 C B A 7 6 5 4 3 2 1 0 IA ( In t e rr up t Ac k n o w led g e ) S P ( Sup e r v is o r P r og r a m ) S D ( Su p e r v is o r Da t a )

UP ( Us er P ro g ram ) UD ( Us er D at a)

F7-12

TM-88

Bus Connections for DMA Interface

Da t a Bu s

CPU
A dd re ss Bu s C o nt ro l Bu s

Me m o r y

DMA Co n t r o lle r

Dev ic e

F7-13

TM-89

Device-to-Memory Transfer Using DMA

D at a Bu s A dd re ss Bu s Co n t r o l Bus

Me m o r y

DMA Co n t ro l le r

Dev ic e

F7-14

TM-90

68000 Bus Arbitration Control Signals

68 000 CPU

D MA Co nt ro lle r BR BG BR BG BGA CK

BGA CK

F7-15

TM-91

Bus Arbitration

6 8 0 0 0 CPU

DMA Co n t r ol le r
Re qu e st t he Bus 1 . A ssert b us r e q ue st ( BR = 0 )

Gr an t t he Bus 1 . A sse r t b u s g ran t ( BG = 0 ) A ckn o w le dg e Bus M ast er sh ip 1 . A ssert b us g r a nt a ck no w le d ge (B GA CK = 0 ) 2 . Ne g at e b u s req u e st ( BR = 1 ) Ter m ina t e Bus A rb it r a t io n 1 . Ne g at e b u s gr an t ( BG = 1 ) a nd w a it f o r BGA CK t o be n e ga t e d Op er a t e as Bu s Mast e r t im e 1 . Pe r f o r m d at a t r an sf e rs acc o r d in g t o sam e r u les t h e CPU u se s

Rele ase Bu s M ast ersh ip 1 . Ne g at e b u s g ran t ack no w le d g e ( BGA CK = 1 ) Resu m e N o rm a l Pr o ce ssing

F7-16

TM-92

Timing for Bus Arbitration

t im e

BR

BG

BGA CK

1 2 3
CPU cy cles

1 2 3
C PU cy cle s

DM A cy cles

F7-17

TM-93

Block Diagram of the 68KMB

T e rm ina l/ H o st Co m p u t e r 68 000 CPU Sy st e m Cloc k

M isce lla n eo u s In pu t / Ou t p u t De vic es

6 8 6 8 1 DUA RT

Re s e t Cir c uit

Sy st e m Bu ses

Int e r rup t Circ u it

A dd r e ss D ec od e Cir c uit

Mo nit o r EPRO Ms (1 6 K)

U ser EPRO Ms ( 1 6 K)

RAM s ( 1 6 K)

Ext e rn al Int err u p t s

F8-3

TM-94

68000 CPU

14, 49

+5 V
16, 53

V cc G ND

15

68000 CPU
C LK

+5 V
20 19 21

E V MA V PA BR BG B G A CK AS R/ W U DS L DS D T A CK F CO F C1 F C2 IPL 0 IPL 1 IPL 2 B ERR RESET H A LT

13 11 12

6 9

A2 3 A2 2 A2 1 A2 0 A1 9 A1 8 A1 7 A1 6 A1 5 A1 4 A1 3 A1 2 A1 1 A1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1

52 51 50 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

A d d r es s Bu s

Co n t r o l Bu s

7 8 10

28 27 26

25 24 23

22 18 17

7 X 1 0 K

D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5

D at a Bu s

F8-4

TM-95

68KMB Clock Circuit

7 4 HC 1 4
1 2

0 . 0 1 F
3 4 5 6

47 C LK to 680 00

1K

1K

10 pF

3.68 64 MHz

13

12

BA U D CL K

to 686 81

F8-6

TM-96

68KMB Reset Circuit

+5 V

+5 V

1N 9 14

1 0K
9

7 4 HC1 4
8 11 10

7 407
3 4

RESET to 68 000 H A LT

100 RESET

2 2 F

F8-7

TM-97

68KMB Interrupt Circuit

M ON IT OR + 2 2 F

+5V IN T 7 Ext er na l In t e r ru pt s IN T 6 IN T 5 IN T 4 IN T 3 IN T 2 IN T 1

7 x 10K 4 3 2 1 13 12 11

7 4 HC1 4 8 7 6 5 4 3 2 1 0 E1 7 4 H C1 3 8 A2 A1 A0
6 7 9

IPL 2 IPL 1 IPL 0 740 7

13 12

to 68 000

+5 V X1 6

10

E0 GS

15 14

V PA

11

10

A3 A2 A1 +5V 7 4 H C1 3 8 f ro m 680 00
3

3 2 1

C B A

6 7 9 10 11 12 13 14 15

FC 2 FC 1 FC 0 +5 V

2 1

C B A

AS

4 5

E1 E2 E3

7 6 5 4 3 2 1 0

IA SP SD

4 5

E1 E2 E3

7 6 5 4 3 2 1 0

7 9 10 11 12 13 14 15

IA CK7 IA CK6 IA CK5 IA CK4 IA CK3 IA CK 2 IA CK1

to 686 81

UP UD

F8-8

TM-98

68KMB Address Decoding

f ro m 68 000

A20 A19 A18 A17 A16 A15 A14 UD S LDS AS +5 V

1 2 3 4 5 6 7 8 9 11 20 10

I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 Vc c GN D

1 6 L8

O8 O7 O6 O5 O4 O3 O2 O1

19 18 17 16 15 14 13 12 9 8

EPROM 0 U EPROM 0 L EPROM 1 U EPROM 1 L RA M0 U RA M0 L D UA RT

t o EPRO M, RA M , & D UA RT c hip se le ct inp u t s

D T A CK

t o 6 800 0

7 407

F8-9

TM-99

68KMB Memory Map

FFFFFE

Re f le ct ed

7 M w o rd s

200000 1FFFFE

Ex pa ns io n

9 9 2 K w o rd s

010000 00FFFE
D UA RT 8 K w or d s ( I/ O) 1 M w o rd s ( 2 M b y t e s)

8 M w o rd s ( 1 6 M b y t e s)

00C000 00BFFE
RA M0 U RA M 0 L

008000 007FFE
EPROM1 U EPROM1 L

8 K w or d s ( syst e m / u ser )

004000 003FFE
EPROM0 U EPROM0 L

8 K w or d s ( u ser )

000000

8 K w o rd s ( MON 6 8 K)

F8-10

TM-100

Monitor EPROMs

f r om 68 000

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

2 23 21 24 25 3 4 5 6 7 8 9 10

A1 2 A1 1 A1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

2764A EPROM
( m o nit or )

D7 D6 D5 D4 D3 D2 D1 D0

19 18 17 16 15 13 12 11

D15 D14 D13 D12 D11 D10 D9 D8 + 5V

V cc Vpp PGM

28 1 27

OE f ro m A d dr ess D ec od e Cir cu it EPROM0 U

20

22

t o / f ro m 680 00

CS

GN D

14

f ro m 680 00

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

2 23 21 24 25 3 4 5 6 7 8 9 10

A1 2 A1 1 A1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

2764A EPROM
( m o nit or )

D7 D6 D5 D4 D3 D2 D1 D0

19 18 17 16 15 13 12 11

D7 D6 D5 D4 D3 D2 D1 D0

+ 5V V cc Vpp PGM
28 1 27

OE f ro m A dd r e ss De co d e C ir cu it EPROM0 L
20

22

CS

GN D

14

F8-12

TM-101

User EPROMs
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
2 23 21 24 25 3 4 5 6 7 8 9 10

f ro m 6 800 0

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

2764A EPROM
(u se r )

D7 D6 D5 D4 D3 D2 D1 D0

19 18 17 16 15 13 12 11

D1 D1 D1 D1 D1 D1 D9 D8 +5 V

5 4 3 2 1 0

Vc c Vp p PGM

28 1 27

OE f ro m A d d r ess D ec o de Cir cu it EPROM 1 U

20

22

t o/ f ro m 68 000

CS

GND

14

f ro m 680 00

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

2 23 21 24 25 3 4 5 6 7 8 9 10

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

2764A EPROM
( use r )

D7 D6 D5 D4 D3 D2 D1 D0

19 18 17 16 15 13 12 11

D7 D6 D5 D4 D3 D2 D1 D0

+5 V Vc c Vp p PGM
28 1 27

OE f ro m A d dr ess D ec od e Cir cu it EPROM1 L

20

22

CS

GND

14

F8-13

TM-102

System/User RAM

f ro m 6 800 0

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

2 23 21 24 25 3 4 5 6 7 8 9 10

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

6264 RA M

D7 D6 D5 D4 D3 D2 D1 D0

19 18 17 16 15 13 12 11

D1 D1 D1 D1 D1 D1 D9 D8

5 4 3 2 1 0

+5V Vcc
28 26

R/ W f r o m A d dr ess D ec od e Cir cu it RA M0 U

27 20

W CS

OE GND

22

t o / f ro m 68 000

14

f ro m 6 800 0

A1 3 A1 2 A1 1 A1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1

2 23 21 24 25 3 4 5 6 7 8 9 10

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

6264 RA M

D7 D6 D5 D4 D3 D2 D1 D0

19 18 17 16 15 13 12 11

D7 D6 D5 D4 D3 D2 D1 D0 +5V

Vcc

28 26

R/ W f ro m A d dr e ss D ec od e Cir cu it RA M0 L

27 20

W CS

OE GND

22

14

F8-14

TM-103

68681 DUART

J3
D B2 5 S
25 30 11

t o / f ro m 68 000

D7 D6 D5 D4 D3 D2 D1 D0 RESET R/ W D T AC K A4 A3 A2 A1

16 24 17 23 18 22 19 34 8 9

D7 D6 D5 D4 D3 D2 D1 D0 RESET R/ W D T A CK RS4 RS3 RS2 RS1 IRQ IA CK CS

TxD A
31 12

T1 I

T1 O

Rx DA

R1 0

R1 I

14

2 7

T e r m ina l/ H os t Co m p u t e r

68681 DUA RT
11 10

MA X 232
TxD B
10

J8
D B2 5 S
7 3

T2 I

T2 O

6 5 3 1

Rx DB
1

R2 0

R2 I

+5V
16

O p t io n al Ser ia l Por t

+
3

C1 + C1 4

Vcc
2

t o / f ro m In t e r r u pt Cir cu it f r om A d d r e ss D e co d e Cir c uit f r o m Clo ck Cir cu it

IN T 2 IA CK 2 D UA RT

21 37

4 X 1 0 F +

V+
6

C2 +
5

V15

35

C2 -

G ND

32

BA UD CL K

C LK/ X1
33 15

J1
8 7 9 3 17 4 11 5

X2

40

+ 5V
20

V cc G ND

O P7 O P6 O P5 O P4 O P3 O P2 O P1 O P0 IP5 IP4 IP3 IP2 IP1 IP0

26 14 27 13 28 12 29

38 39 2 36 4 7

14 15 16 12 13 6 20 10

Mis c ellan e ou s Inp u t / Ou t pu t D ev ic e s

+5V

F8-15

TM-104

Expansion to 6800 Peripherals

J2
D7 D6 D5 D4 D3 D2 D1 D0 t o / f ro m 680 00 A 16 A3 A2 A1 RESET V PA E R/ W t o / f ro m In t e r ru pt Circu it IN T3 SD +5V
1 2 3 4 5 6 7 8

11

14 15 16

Exp an sion t o 6 8 0 0 Pe rip he r a ls

13 18 17 19

12 9

20

10

2 0 - pin h ea de r

F8-16

TM-105

68681 Interface to LEDs and Switches (I/O Board #1)

686 81 DU ART OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 15 26 14 27 13 28 12 29
8 7 9 3

J1 17 15 13 11 8 6 4 2

7 4 LS2 4 4 3 5 7 9 12 14 16 18

8 220

+5 V

17 4 11 5

20

1, 19 +5V

10

+5 V 38 39 2 IP3 IP2 IP1 7 IP0 6 1 0 k

6 14 15 16 12 13

IP5 IP4

36 4

F9-3

TM-106

Interface to Switches and 7-Segment LED (I/O Board #2)

686 81 DU ART OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 15 26 14 27 13 28 12 29 J1
8 7 9 3 17 4 11 5

7 4 LS2 4 4 17 15 13 11 8 6 4 2 3 5 7 9 12 14 16 18 7 22 0 1 13 10 8 7 2 11 a b c d e f g

+5 V 14, 3

a f g c d b

20 10

1, 19 +5V

MA N 7 2 A 7 -s eg m e nt co m m o n an od e LED +5 V

IP3 IP2 IP1 IP0

2 36 4 7

16 12 13 6

4 1 0 k

F9-4

TM-107

4-Digit 7-Segment Display (I/O Board #3)

+5 V 6 86 8 1 28 12 29 J1 5 13 12 18 V cc O P2 O P1 O P0
4 11 5

DA TA CL OCK ENA BL E MC1 4 4 9 9 a b c d e 4 3 2 1 17 16 15 14

8 47 14 13 8 7 6 1 2 4 a a b b c c d d e e ff g dp 4 ,1 2 e d dp f g a b f

4 MA N 4 7 4 0 A

a b g f

a b g f

a b g

20 10

+5 V

e d

e d

e d

6 0 .0 1 5 F 9

f O SC g GN D D4 7 D3 8 D2 10 h (d p ) D1 11

dp

dp

dp

4,12

4 ,1 2 4 2 N3 9 0 4

4 ,1 2

F9-6

TM-108

MC14499 Timing

t im e

ENA BL E ( OP0 ) CL OCK ( OP1 )

D AT A ( OP2 )

d1

d2

d3

d4

d1 9

d20

F9-7

TM-109

MC14499 Digit and Bit Sequence

t im e Bit N o .
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

1 4 2 4 3 1 42 4 3 1 4 2 4 3 1 4 2 4 3 1 4 2 4 3
De cim a l Poin t s Dig it 1 D ig it 2 D igit 3 Dig it 4

F9-8

TM-110

8-Digit 7-Segment Display (I/O Board #4)

D IGIT MC1 4 4 9 9 DA TA CL OCK EN ABL E

SEG

D IGIT MC1 4 4 9 9

SEG

D A TA C LO CK EN AB LE

h et c.

F9-9

TM-111

68681 Input Expansion Using 74LS165s

Ex t e r n al Inp u t s J1 6 868 1 D UA RT L SB
20

MSB

+ 5V
10

6 H

5 G

4 F

3 E

14 D

13 C

12 B

11 A DA T A 1 0 IN CL K 2 9

6 H

5 G

4 F

3 E

14 D

13 C

12 B

11 A DA T A IN CL K 2 etc . 10

IP0

D AT A O UT G ND 8, 1 5

7 4 L S1 6 5 Vcc 16 + 5V 7 nc L O AD 1

D AT A O UT G ND 8, 1 5

7 4 L S1 6 5 Vc c 16 +5V 7 nc L O AD 1

O P1 O P0

12 29

11 5

F9-10

TM-112

6821 Interface to the 68000 (I/O Boards #5 & #6)

J2
1

26 27 28 D5 29 D4 D7 D6

6 821 PIA CA 2 CA 1 39 40

D7
2

D6
3

D5
4

D4
5

PA 7 PA 6 PA 5 PA 4 PA 3 PA 2

9 8 7 6 5 4 3 2

30 D3 31 D2 32 D1 33 D0

D3
6

D2 D1 D0
7 8

23 CS2 24 CS1
1 2

SD A16
11

PA 1 PA 0

22 +5 V CS0

7 4 HC 0 0
4

PB 7 PB 6 34 RESET 21 R/ W 25 E 38 IRQA 37 IRQB 35 RS1 36 RS0 CB2 CB1 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0

17 16 15 14 13 12 11 10

VPA RESET R/ W E INT 3

18 13 19 17 12 14

6 5

A3 A2 A1
15 16 20 10

nc

19 18

+5V

+5 V

20 1

V cc GN D

F9-11

TM-113

Keypad Interface to the 6821 (I/O Board #5)

68 21 PIA

PA 0
3

PA 1
4

PA 2 PA 3
5

0
6 N

PA 4 4
7 M

PA 5 8
8 L

PA 6 C
9 K

PA 7 Gra yh ill PN 8 8 BA 2

F9-12

TM-114

Output to a MC1408L8 DAC (I/O Board #6, 1 of 4)

68 21
9 5 6 7 8

M C1 4 0 8 L 8 1 k V r ef +
14

+5V 1 50 10 0
15

PA 7
8

D7 D6 D5 D4 V r ef -

PA 6
7

PA 5
6

1 k

PA 4
5 9 10 11 12

PA 3
4

D3 D2 D1
+ 1 2 V -1 2 V 1

PA 2
3

nc

4 .7 k

PA 1
2

PA 0
13 16 2

D0
4

+5 V

V CC COMP

IO

2 3

4 6

VO
8 1

L M3 0 1

1 5 pF

GND V EE
3

3 3 pF

-1 2 V

F9-13

TM-115

Low-Pass Filter and Audio Output (I/O Board #6, 2 of 4)

0 .0 4 4 F VO 2 .4 k
+12V -12V 7 2 4 6 3 8 3

( f ilt er ed ) A ux ilia r y Jack

+ 1 2 V -1 2 V 7 2 4 6

1 .2 k VO

1 .2 k

2 5 F

0 .0 2 2 F

L M3 0 1 ( lo w - pa ss f ilt e r )

+
8 1

5 k

LM 3 0 1 ( vo lt ag e f o llo w e r )

Sp ea k e r

33 pF

3 3 pF

F9-15

TM-116

Interface to ADC0804 Analog-to-Digital Converter (I/O Board #6, 3 of 4)

AD C0 8 0 4 682 1
19 3

V cc WR Vin ( + ) IN TR CS RD Vr ef V in( - )

20

+5V 10 k t r im p o t ( t r an sd uc er)

C B2 C B1

6 Di f f e re nt ial In p ut s 7

18

1 2

nc

PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

17 16 15 14 13 12 11 10

11 12 13 14 15 16 17 18

D7 D6 D5 D4 D3 D2 D1 D0

C LK R

19

1 5 k CL K IN
4

1 5 0 pF D GN D A GN D
10 8

F9-16

TM-117

Timing for ADC0804 Conversions

Clea r INT R

St a r t o f Co n ve rsio n

En d o f Co nv er sion

C le ar IN TR

St ar t Ne xt Co nv er sio n

WR

1 0 0 s
IN T R

F9-17

TM-118

Microphone Input to the ADC0804 (I/O Board #6, 4 of 4)

1 k 1% 100 k 1% VA 1 k +
+ 1 2 V -1 2 V 7

VB 1 0 k

47
4 6

1 0 F

+ 1 2 V -1 2 V 7 2 4 6 3 8 1

47

Mic rop h o ne 200

1 k 1%

2 3

2 2 k +5V 2 2 k

1 0 0 k 1%

LM 3 0 1 ( p r e -am p )

LM 3 0 1 (a m p )

33 pF +5 V 1N914

33 pF

1 .2 k 0 .0 4 4 F 2 .4 k 1 .2 k
+ 1 2 V -1 2 V 7 2 3 4 6 3

L F3 9 8 ( sa m p le an d h o ld )
+12V -1 2 V

A DC0 8 0 4

18 k V C
1 4 8 5

5 . 6 k

20

V cc

+5 V

0 .0 2 2 F

8 1

L M3 0 1 ( lo w -p a ss f ilt e r )

6 7

0 .0 0 1 F

V in (+ )
7

33 pF

V in (- )

CS RD

6 821 CB2 CB1

19 18 3 5

WR IN T R V re f CL K R D7 D6 D5 D4 D3 D2 D1 D0
9 19

nc

PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

17 16 15 14 13 12 11 10

11 12 13 14 15 16 17 18

15 k CL K IN
4

1 50 pF D GND A GND
10 8

TM-119

F9-19

TM-120

Sample-and-Hold Waveforms

1 0 0 s m in im un Sign a l a t V C

Sig n al at V D

V o lt a ge

T im e

F9-20

TM-121

68000-Family Features
48-pin 68008 Data Bus (bits) Address Bus (bits) Data Cache (bytes) Instruction Cache (bytes) On-Chip Memory Management On-Chip FloatingPoint Unit 52-pin 68008 68000 68010 68020 68030 68040

8 20 No No

8 22 No No

16 24 No No

16 24 No No

32 32 256 No No

32 32 256 256 Yes No

32 32 4096 4096 Yes Yes

T10-1

TM-122

Comparison of Five Recent Microprocessors

68040 Company Motorola Introduced Architecture Width (bits) Registers (general/FP) Multiprocessing Support? Device Size (mm) Transistors (millions) Clock (MHz) SPECint 92 SPECfp 92 Peak Power (Watts) Price ($US/1000 units) 1989 CISC 32 16/8 No 10.8 x 11.7 1.2 25 21 15 6 $233

80486 Intel 6/91 CISC 32 8/8 No not available 1.2 50 27.9 13.1 5 $432

PowerPC IBM/Motorola 4/93 RISC 32 32/32 Yes 11 x 11 2.8 80 85 105 9.1 $557

Pentium Intel 3/93 CISC 32 8/8 Yes 17.2 x 17.2 3.1 66 67.4 63.6 16 $898

Alpha 21064 DEC 2/92 RISC 64 32/32 Yes 15.3 x 12.7 1.68 200 130 184 30 $505

Source: IEEE Spectrum, December 1993, p. 21 Integer and floating-point performance benchmarks

T10-10

TM-123