Professional Documents
Culture Documents
Automating with
STEP7 in STL and SCL
Programmable Controllers
SIMATIC S7-300/400
by Hans Berger
Table of Contents
5.2 Set and Reset . . . . . . . . . . 142 6.6.6 Writing into the Load Memory . . 162
5.3 RS Flipflop Function . . . . . . 144 7 Timer Functions . . . . . . . . . 164
5.3.1 Memory Functions with Reset 7.1 Programming a Timer . . . . . . 164
Priority . . . . . . . . . . . . . . 144
5.3.2 Memory Function with Set 7.1 .1 Starting a Timer . . . . . . . . . 164
Priority . . . . . . . . . . . . . . 144 7.1 .2 Specifying the Time . . . . . . . 165
5.3 .3 Memory Function in a Binary 7.1 .3 Resetting a Timer. . . . . . . . . 166
Logic Operation . . . . . . . . . 144 7.1 .4 Enabling a Timer . . . . . . . . . 166
5.4 Edge Evaluation . . . . . . . . . 145 7.1 .5 Checking a Timer. . . . . . . . . 166
7.1 .6 Sequence ofTimer Instructions . 167
5 .4.1 Positive Edge . . . . . . . . . . 146 7 .1 .7 Clock Generator Example . . . . 167
5.4.2 Negative Edge . . . . . . . . . . 146
5.4.3 Testing a Pulse Memory Bit. . . 147 7.2 Pulse Timers . . . . . . . . . . . 168
5.4.4 Edge Evaluation in a Binary 7.3 Extended Pulse Timers . . . . . . 170
Logic Operation . . . . . . . . . 147 7 .4 On-Delay Timers . . . . . . . . . 172
5.4.5 Binary Scaler . . . . . . . . . . 148
7.5 Retentive On-Delay Timers . . . 174
5.5 Example of a Conveyor Belt
Control System . . . . . . . . . 148 7.6 Off-Delay Timers . . . . . . . . . 176
7 .7 IEC Timer Functions . . . . . . . 178
6 Move Functions . . . . . . . . . 152
6 .1 7.7.1 Pulse Generation SFB 3 TP . . . 178
General Remarks on Loading
and Transferring Data . . . . . . 7.7.2 On Delay SFB 4 TON . . . . . . 179
152
7.7.3 Off Delay SFB 5 TOF . . . . . . 179
6.2 Load Functions . . . . . . . . . 154
6.2.1 General Representation of a 8 Counter Functions . . . . . . . 180
Load Function . . . . . . . . . . 154 8.1 Setting and Resetting Counters . . 180
6.2.2 Loading the Contents of 8.2 Counting . . . . . . . . . . . . . 181
Memory Locations . . . . . . . 154
6.2.3 Loading Constants . . . . . . . . 155 8 .3 Checking a Counter . . . . . . . . 182
6.3 Transfer Functions . . . . . . . . 156 8.4 Enabling a Counter . . . . . . . . 182
6.3.1 General Representation of a 8.5 Sequence ofCounter Instructions 183
Transfer Function . . . . . . . . 156 8.6 IEC Counter Functions . . . . . . 184
6.3.2 Transferring to Various Memory
8.6 .1 Up Counter SFB 0 CTU . . . . . 184
Areas . . . . . . . . . . . . . . . . . 156
8.6.2 Down Counter SFB 1 CTD . . . . 184
6.4 Accumulator Functions . . . . . 157 8.6 .3 Up-Down Counter SFB 2 CTUD. 185
6.4.1 Direct Transfers Between 8.7 Parts Counter Example . . . . . . 185
Accumulators . . . . . . . . . . 157
6.5 Exchange Bytes in Accumulator 1 . 158 Digital Functions . . . . . . . . . . . . .189
6.6 System Functions for Data 9 Comparison Functions . . . . . 190
Transfer . . . . . . . . . . . . . 159
9.1 General Representation of a
6.6.1 Copying Memory Area . . . . . 160 Comparison Function . . . . . . . 190
6.6.2 Uninterruptible Copying of
Variables . . . . . . . . . . . . . 160 9.2 Description of the Comparison
6 .6.3 Initializing a memory area. . . . 161 Functions . . . . . . . . . . . . . 191
6.6.4 Copying STRING Variables . . 161 9.3 Comparison Function in a Logic
6.6.5 Reading from Load Memory . . 161 Operation . . . . . . . . . . . . . 192
Table of Contents
32.4.1 Creating the STEP 7 Project. . . 473 34.2 Digital Functions . . . . . . . . . 489
32.4.2 Unconvertible Functions . . . . 474 34.2.1 Comparison Functions . . . . . . 489
32.4.3 Address Changes . . . . . . . . 474 34.2.2 Math Functions . . . . . . . . . . 490
32.4.4 Indirect Addressing . . . . . . . 475
34 .2.3 Arithmetic Functions . . . . . . . 490
32.4.5 Access to "Excessively Long"
Data Blocks . . . . . . . . . . . 477 34 .2.4 Conversion Functions . . . . . . 490
32.4.6 Working with Absolute Addresses 477 34 .2.5 Shift Functions . . . . . . . . . . 490
32.4.7 Parameter Initialization . . . . . 477 34.2.6 Word Logic Operations. . . . . . 490
32.4.8 Special Function Organization 34.3 Program Flow Control . . . . . . 491
Blocks . . . . . . . . . . . . . . 477
32.4.9 Error Handling. . . . . . . . . . 477 34 .3.1 Jump Functions . . . . . . . . . . 491
34.3.2 Master Control Relay. . . . . . . 491
33 Block Libraries . . . . . . . . . 480 34.3.3 Block Functions . . . . . . . . . 491
33.1 Organization Blocks . . . . . . . 480 34.4 Indirect Addressing . . . . . . . . 491
33.2 System Function Blocks . . . . . 481 35 SCL Statement and Function
33.3 IEC Function Blocks . . . . . . 484 Overview . . . . . . . . . . . . . 492
33 .4 S5-S7 Converting Blocks . . . . 485 35 .1 Operators . . . . . . . . . . . . . 492
33 .5 TI-S7 Converting Blocks . . . . 486 35 .2 Control Statements . . . . . . . . 492
33.6 PID Control Blocks . . . . . . . 487 35 .3 Block Calls . . . . . . . . . . . . 492
33.7 Communication Blocks . . . . . 487
35 .4 SCL Standard Functions . . . . . 493
33.8 Miscellaneous Blocks . . . . . . 487
35.4.1 Timer Functions . . . . . . . . . 493
34 STL Operation Overview . . . 488 35 .4.2 Counter Functions . . . . . . . . 493
34.1 Basic Functions . . . . . . . . . 488 35.4.3 Conversion Functions . . . . . . 493
35 .4.4 Math Functions . . . . . . . . . . 494
34.1.1 Binary Logic Operations . . . . 488
35 .4.5 Shift and Rotate . . . . . . . . . . 494
34.1.2 Memory Functions . . . . . . . 489
34.1 .3 Transfer Functions . . . . . . . . 489 Index . . . . . . . . . . . . . . . . . . 495
34.1 .4 Timer Functions . . . . . . . . . 489
34.1 .5 Counter Functions . . . . . . . . 489 Abbreviations . . . . . . . . . . . . . . 503