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Ad 7400
Ad 7400
AD7400
VIN+
T/H
VIN– Σ-∆ ADC
UPDATE WATCHDOG
REF
CONTROL LOGIC
UPDATE WATCHDOG
GND1 GND2
Figure 1.
TABLE OF CONTENTS
Features .............................................................................................. 1 Typical Performance Characteristics ..............................................9
Applications ....................................................................................... 1 Terminology .................................................................................... 12
General Description ......................................................................... 1 Theory of Operation ...................................................................... 13
Functional Block Diagram .............................................................. 1 Circuit Information .................................................................... 13
Revision History ............................................................................... 2 Analog Input ............................................................................... 13
Specifications..................................................................................... 3 Differential Inputs ...................................................................... 14
Timing Specifications .................................................................. 4 Digital Filter ................................................................................ 15
Insulation and Safety-Related Specifications ............................ 5 Applications Information .............................................................. 17
Regulatory Information ............................................................... 5 Grounding and Layout .............................................................. 17
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Evaluating the AD7400 Performance ...................................... 17
Characteristics .............................................................................. 6 Insulation Lifetime ..................................................................... 17
Absolute Maximum Ratings ............................................................ 7 Outline Dimensions ....................................................................... 18
ESD Caution .................................................................................. 7 Ordering Guide .......................................................................... 18
Pin Configuration and Function Descriptions ............................. 8
REVISION HISTORY
5/2018—Rev. G to Rev. H 4/2011—Rev. C to Rev. D
Changes to Minimum External Air Gap (Clearance) Parameter, Changes to Dynamic Input Current Parameter, Table 1 ..............3
Minimum External Tracking (Creepage) Parameter, Tracking
Resistance (Comparative Tracking Index) Parameter, and 1/2011—Rev. B to Rev. C
Isolation Group Parameter, Table 3, and 5000 V rms Isolation Changes to Features Section ............................................................1
Voltage Parameter, Table 4 .............................................................. 5 Changes to Input-to-Output Momentary Withstand Voltage
Added Note 1 and Note 2, Table 3; Renumbered Sequentially .. 5 Parameter, Table 3, UL Column, Table 4, and Note 1, Table 4...........5
Changes to Ordering Guide .................................................................... 18
6/2013—Rev. F to Rev. G
Changes to Figure 12 and Figure 13............................................. 10 9/2007—Rev. A to Rev. B
Updated VDE Certification Throughout ......................................1
3/2012—Rev. E to Rev. F Changes to Table 6.............................................................................7
Changed IDD1 Parameter from 12 mA to 13 mA, Table 1 ............ 3
12/2006—Rev. 0 to Rev. A
7/2011—Rev. D to Rev. E Changes to Features ..........................................................................1
Changes to Minimum External Air Gap (Clearance) Parameter, Changes to Table 6.............................................................................7
Table 3 and Minimum External Tracking (Creepage) Parameter, Changes to Analog Input Section................................................. 13
Table 3 ................................................................................................ 5 Changes to Figure 26...................................................................... 15
Changes to Figure 5; Pin 1 Description, Table 8; and Pin 7
Description, Table 8.......................................................................... 8 1/2006—Revision 0: Initial Version
Rev. H | Page 2 of 20
Data Sheet AD7400
SPECIFICATIONS
VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, and VIN− = 0 V (single-ended); TA = TMIN to TMAX,
fMCLK = 10 MHz, tested with Sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted.1
Table 1.
Parameter Y Version1, 2 Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 16 Bits min Filter output truncated to 16 bits
Integral Nonlinearity3 ±15 LSB max −40°C to +85°C; ±2 LSB typical
±25 LSB max >85°C to 105°C
Differential Nonlinearity3 ±0.9 LSB max Guaranteed no missing codes to 16 bits
Offset Error3 ±0.5 mV max
±50 µV typ TA = 25°C
Offset Drift vs. Temperature 3.5 µV/°C max −40°C to +105°C
1 µV/°C typ
Offset Drift vs. VDD1 120 µV/V typ
Gain Error3 ±1 mV max
Gain Error Drift vs. Temperature 23 µV/°C typ −40°C to +105°C
Gain Error Drift vs. VDD1 110 µV/V typ
ANALOG INPUT
Input Voltage Range ±200 mV min/mV max For specified performance; full range ±320 mV
Dynamic Input Current ±8 µA max VIN+ = 400 mV, VIN− = 0 V
±0.5 µA typ VIN+ = VIN− = 0 V
Input Capacitance 10 pF typ
DYNAMIC SPECIFICATIONS VIN+ = 35 Hz, 400 mV p-p sine
Signal-to-(Noise + Distortion) Ratio (SINAD)3 70 dB min −40°C to +85°C
65 dB min >85°C to 105°C
79 dB typ
Signal-to-Noise Ratio (SNR) 71 dB min −40°C to +105°C
Total Harmonic Distortion (THD)3 −88 dB typ
Peak Harmonic or Spurious Noise (SFDR)3 −88 dB typ
Effective Number of Bits (ENOB)3 11.5 Bits
Isolation Transient Immunity3 25 kV/µs min
30 kV/µs typ
LOGIC OUTPUTS
Output High Voltage, VOH VDD2 − 0.1 V min IO = −200 µA
Output Low Voltage, VOL 0.4 V max IO = +200 µA
POWER REQUIREMENTS
VDD1 4.5/5.25 V min/V max
VDD2 3/5.5 V min/V max
IDD14 13 mA max VDD1 = 5.25 V
IDD25 6 mA max VDD2 = 5.5 V
4 mA max VDD2 = 3.3 V
1
Temperature range is −40°C to +85°C.
2
All voltages are relative to their respective ground.
3
See the Terminology section.
4
See Figure 14.
5
See Figure 15.
Rev. H | Page 3 of 20
AD7400 Data Sheet
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted.1
Table 2.
Parameter Limit at TMIN, TMAX Unit Description
fMCLKOUT2 10 MHz typ Master clock output frequency
9/11 MHz min/MHz max Master clock output frequency
t13 40 ns max Data access time after MCLK rising edge
t2 3 10 ns min Data hold time after MCLK rising edge
t3 0.4 × tMCLKOUT ns min Master clock low time
t4 0.4 × tMCLKOUT ns min Master clock high time
1
Sample tested during initial release to ensure compliance.
2
Mark space ratio for clock output is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
200µA IOL
TO OUTPUT +1.6V
PIN
CL
25pF
04718-002
200µA IOH
t4
MCLKOUT
t1 t2 t3
04718-003
MDAT
Rev. H | Page 4 of 20
Data Sheet AD7400
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 3.
Parameter Symbol Value Unit Conditions
Input-to-Output Momentary Withstand Voltage VISO 5000 min V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 7.81, 2 min mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 7.81, 2 min mm Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 mm Insulation distance through insulation
min
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Isolation Group II Material group (DIN VDE 0110, 1/89, Table 1)
1
In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m.
2
Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
REGULATORY INFORMATION
Table 4.
UL1 CSA VDE2
Recognized Under 1577 Approved under CSA Component Certified according to DIN V VDE V 0884-10
Component Recognition Acceptance Notice 5A (VDE V 0884-10):2006-122
Program1
5000 V rms Isolation Voltage Basic insulation per CSA 60950-1-07 and Reinforced insulation per DIN V VDE V 0884-10
IEC 60950-1, 780 V rms maximum (VDE V 0884-10):2006-12, 891V peak
working voltage
Reinforced insulation per CSA
60950-1-03 and IEC 60950-1, 390 V
rms maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1
In accordance with UL 1577, each AD7400 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).
2
In accordance with DIN V VDE V 0884-10, each AD7400 is proof tested by applying an insulation test voltage ≥ 1671 V peak for 1 second (partial discharge detection
limit = 5 pC).
Rev. H | Page 5 of 20
AD7400 Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 5.
Description Symbol Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms I–IV
For Rated Mains Voltage ≤ 450 V rms I–II
For Rated Mains Voltage ≤ 600 V rms I–II
CLIMATIC CLASSIFICATION 40/105/21
POLLUTION DEGREE (DIN VDE 0110, Table 1) 2
MAXIMUM WORKING INSULATION VOLTAGE VIORM 891 V peak
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC VPR 1671 V peak
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A VPR
After Environmental Test Subgroup 1 1426 V peak
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/3 1069 V peak
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) VTR 6000 V peak
SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, ALSO SEE Figure 4)
Case Temperature TS 150 °C
Side 1 Current IS1 265 mA
Side 2 Current IS2 335 mA
INSULATION RESISTANCE AT TS, VIO = 500 V RS >109 Ω
350
300
SAFETY-LIMITING CURRENT (mA)
250
SIDE #2
200
150
SIDE #1
100
50
0
04718-026
Rev. H | Page 6 of 20
Data Sheet AD7400
Rev. H | Page 7 of 20
AD7400 Data Sheet
VDD1 1 16 GND2
VIN+ 2 AD7400 15 NC
VIN– 3 TOP VIEW 14 VDD2
(Not to Scale)
NC 4 13 MCLKOUT
NC 5 12 NC
NC 6 11 MDAT
VDD1 /NC 7 10 NC
04718-004
GND1 8 9 GND2
NC = NO CONNECT
Rev. H | Page 8 of 20
Data Sheet AD7400
100 –90
200mV p-p SINEWAVE ON VDD1 VDD1 = VDD2 = 5V
90 NO DECOUPLING
–80
VDD1 = VDD2 = 4.5V TO 5.25V
80
–70
70
–60
60
PSRR (dB)
SINAD (dB)
–50
50
–40
40
–30
30
–20
20
04718-005
–10
04718-008
10
0 0
0 100 200 300 400 500 600 700 800 900 1000 0.195 0.215 0.235 0.255 0.275 0.295 0.315
SUPPLY RIPPLE FREQUENCY (kHz) ± INPUT AMPLITUDE (V)
Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 9. SINAD vs. VIN
(1 MHz Filter Used)
–90 0.5
VIN+ = –200mV TO +200mV
0.4 VIN– = 0V
–80
–70 0.3
VDD1 = VDD2 = 4.5V
DNL ERROR (LSB)
–60 0.2
SINAD (dB)
–50 0.1
–40 0
VDD1 = VDD2 = 5.25V
VDD1 = VDD2 = 5V –0.1
–30
–20 –0.2
–0.3
04718-009
–10
04718-006
0 –0.4
0 500 1000 1500 2000 2500 3000 3500 4000 0 10000 20000 30000 40000 50000 60000
INPUT FREQUENCY (Hz) CODE
Figure 7. SINAD vs. Analog Input Frequency for Various Supply Voltages Figure 10. Typical DNL, ±200 mV Range
(Using Sinc3 Filter, 256 Decimation Rate)
0 0.8
8192 POINT FFT VIN+ = –200mV TO +200mV
–20 fIN = 35Hz VIN– = 0V
SINAD = 79.6991dB 0.6
–40 THD = –92.6722dB
DECIMATION BY 256
0.4
–60
INL ERROR (LSB)
–80 0.2
(dB)
–100 0
–120
–0.2
–140
–0.4
04718-010
–160
04718-007
–180 –0.6
0 2 4 6 8 10 12 14 16 18 20 0 10000 20000 30000 40000 50000 60000
FREQUENCY (kHz) CODE
Figure 8. Typical FFT, ±200 mV Range Figure 11. Typical INL, ±200 mV Range
(Using Sinc3 Filter, 256 Decimation Rate) (Using Sinc3 Filter, 256 Decimation Rate)
Rev. H | Page 9 of 20
AD7400 Data Sheet
0.0036
100 IDD2 @ +25°C VDD1 = VDD2 = 5V
0.0034
0 VDD1 = VDD2 = 4.5V
IDD2 @ –40°C
IDD2 (A)
OFFSET (µV)
0.0033
–50 VDD1 = VDD2 = 5V
0.0032
–100
0.0031
VDD1 = VDD2 = 5.25V
04718-014
–150
0.0030
–0.34
–0.30
–0.26
–0.22
–0.18
–0.14
–0.10
–0.06
–0.02
0.02
0.06
0.10
0.14
0.18
0.22
0.26
0.30
0.34
–200
04718-011
–45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105
TEMPERATURE (°C) VIN DC INPUT VOLTAGE (V)
Figure 12. Offset Drift vs. Temperature for Various Supply Voltages Figure 15. IDD2 vs. VIN at Various Temperatures
9
0.3 VDD1 = VDD2 = 4.5V TO 5.25V
6
0.2
3
0.1
IIN (µA)
VDD1 = VDD2 = 5V 0
GAIN (%)
–3
VDD1 = VDD2 = 4.5V
–0.1
–6
04718-015
–0.2
–9 0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
–0.35
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
04718-012
–0.3
–45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105
TEMPERATURE (°C) VIN+ DC INPUT (V)
Figure 13. Gain Error Drift vs. Temperature for Various Supply Voltages Figure 16. IIN vs. VIN+ DC Input
0.0099
0
VDD1 = VDD2 = 5V
0.0098
–10
0.0097
TA = +85°C –20
0.0096 TA = +25°C
–30
0.0095
–40
IDD1 (A)
CMRR (dB)
0.0094
TA = –40°C –50
0.0093
–60
0.0092
–70
0.0091
–80
04718-013
0.0090
04718-016
–90
0.0089
–0.34
–0.30
–0.26
–0.22
–0.18
–0.14
–0.10
–0.06
–0.02
0.02
0.06
0.10
0.14
0.18
0.22
0.26
0.30
0.34
–100
0.1 1 10 100 1000 10000
Figure 14. IDD1 vs. VIN at Various Temperatures Figure 17. CMRR vs. Common-Mode Ripple Frequency
Rev. H | Page 10 of 20
Data Sheet AD7400
1.0
BANDWIDTH = 100kHz 11.0
10.8
0.8
10.6
10.4
0.6 VDD1 = VDD2 = 4.5V
NOISE (mV)
MCLKOUT (MHz)
10.2
10.0
0.4
9.8
04718-017
VDD1 = VDD2 = 5V
04718-024
9.2
0
0
0.05
0.10
0.15
0.20
0.25
0.30
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
9.0
5
–5
15
25
35
45
55
65
75
85
95
–45
–35
–25
–15
105
VIN DC INPUT (V) TEMPERATURE (°C)
Figure 18. RMS Noise Voltage vs. VIN DC Input Figure 19. MCLKOUT vs. Temperature for Various Supplies
Rev. H | Page 11 of 20
AD7400 Data Sheet
TERMINOLOGY
Differential Nonlinearity Total Harmonic Distortion (THD)
Differential nonlinearity is the difference between the measured THD is the ratio of the rms sum of harmonics to the
and the ideal 1 LSB change between any two adjacent codes in fundamental. For the AD7400, it is defined as
the ADC.
V2 2 + V32 + V4 2 + V5 2 + V6 2
Integral Nonlinearity THD(dB) = 20 log
V1
Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function. where:
The endpoints of the transfer function are specified negative V1 is the rms amplitude of the fundamental.
full scale, −200 mV (VIN+ − VIN−), Code 12,288 for the 16-bit V2, V3, V4, V5, and V6 are the rms amplitudes of the second
level, and specified positive full scale, +200 mV (VIN+ − VIN−), through the sixth harmonics.
Code 53,248 for the 16-bit level. Peak Harmonic or Spurious Noise
Offset Error Peak harmonic or spurious noise is defined as the ratio of the
Offset error is the deviation of the midscale code (Code 32,768 rms value of the next largest component in the ADC output
for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V). spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
Gain Error
determined by the largest harmonic in the spectrum, but for
Gain error includes both positive full-scale gain error and
ADCs where the harmonics are buried in the noise floor, it is a
negative full-scale gain error. Positive full-scale gain error is the
noise peak.
deviation of the specified positive full-scale code (53,248 for the
16-bit level) from the ideal VIN+ − VIN− (+200 mV) after the Common-Mode Rejection Ratio (CMRR)
offset error is adjusted out. Negative full-scale gain error is the CMRR is defined as the ratio of the power in the ADC output at
deviation of the specified negative full-scale code (12,288 for ±200 mV frequency, f, to the power of a 200 mV p-p sine wave
the 16-bit level) from the ideal VIN+ − VIN− (−200 mV) after the applied to the common-mode voltage of VIN+ and VIN− of
offset error is adjusted out. Gain error includes reference error. frequency fS, expressed as
Signal-to-(Noise + Distortion) Ratio (SINAD) CMRR (dB) = 10log(Pf/PfS)
This ratio is the measured ratio of signal-to-(noise + distortion) where:
at the output of the ADC. The signal is the rms amplitude of the Pf is the power at frequency f in the ADC output.
fundamental. Noise is the sum of all nonfundamental signals up PfS is the power at frequency fS in the ADC output.
to half the sampling frequency (fS/2), excluding dc. The ratio is
Power Supply Rejection Ratio (PSRR)
dependent on the number of quantization levels in the digitization
Variations in power supply affect the full-scale transition but
process; the more levels, the smaller the quantization noise. The
not converter linearity. PSRR is the maximum change in the
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
specified full-scale (±200 mV) transition point due to a change
converter with a sine wave input is given by
in power supply voltage from the nominal value (see Figure 6).
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Isolation Transient Immunity
Therefore, for a 12-bit converter, this is 74 dB. The isolation transient immunity specifies the rate of rise/fall of
Effective Number of Bits (ENOB) a transient pulse applied across the isolation boundary beyond
The ENOB is defined by which clock or data is corrupted. (It was tested using a transient
pulse frequency of 100 kHz.)
ENOB = (SINAD − 1.76)/6.02
Rev. H | Page 12 of 20
Data Sheet AD7400
THEORY OF OPERATION
CIRCUIT INFORMATION A differential input of 320 mV results in a stream of, ideally, all
The AD7400 isolated Σ-Δ modulator converts an analog input 1s. This is the absolute full-scale range of the AD7400, while
signal into a high speed (10 MHz typical), single-bit data 200 mV is the specified full-scale range, as shown in Table 9.
stream; the time average of the modulator’s single-bit data is Table 9. Analog Input Range
directly proportional to the input signal. Figure 22 shows a Analog Input Voltage Input
typical application circuit where the AD7400 is used to provide
Full-Scale Range +640 mV
isolation between the analog input, a current sensing resistor,
Positive Full Scale +320 mV
and the digital output, which is then processed by a digital filter
Positive Specified Input Range +200 mV
to provide an N-bit word.
Zero 0 mV
ANALOG INPUT Negative Specified Input Range −200 mV
The differential analog input of the AD7400 is implemented Negative Full Scale −320 mV
with a switched capacitor circuit. This circuit implements a To reconstruct the original information, this output needs to be
second-order modulator stage that digitizes the input signal digitally filtered and decimated. A Sinc3 filter is recommended
into a 1-bit output stream. The sample clock (MCLKOUT) because this is one order higher than that of the AD7400
provides the clock signal for the conversion process as well as modulator. If a 256 decimation rate is used, the resulting
the output data-framing clock. This clock source is internal on 16-bit word rate is 39 kHz, assuming a 10 MHz internal clock
the AD7400. The analog input signal is continuously sampled frequency. Figure 21 shows the transfer function of the AD7400
by the modulator and compared to an internal voltage reference. relative to the 16-bit output.
A digital stream that accurately represents the analog input over
time appears at the output of the converter (see Figure 20).
65535
MODULATOR OUTPUT
+FS ANALOG INPUT
53248
SPECIFIED RANGE
ADC CODE
ANALOG INPUT
04718-020
0
differential input of −200 mV produces a stream of 1s and 0s
–320mV –200mV +200mV +320mV
that are high 18.75% of the time.
ANALOG INPUT
ISOLATED NONISOLATED
5V 5V/3V
SINC3 FILTER
Σ-Δ CS
VIN+ MOD/ MDAT MDAT
+ ENCODER DECODER
INPUT SCLK
CURRENT MCLKOUT MCLK
VIN–
RSHUNT SDAT
DECODER ENCODER
Rev. H | Page 13 of 20
AD7400 Data Sheet
DIFFERENTIAL INPUTS When a capacitive load is switched onto the output of an op
amp, the amplitude momentarily drops. The op amp tries to
The analog input to the modulator is a switched capacitor correct the situation and, in the process, hits its slew rate limit.
design. The analog signal is converted into charge by highly This nonlinear response, which can cause excessive ringing, can
linear sampling capacitors. A simplified equivalent circuit lead to distortion. To remedy the situation, a low-pass RC filter
diagram of the analog input is shown in Figure 23. A signal can be connected between the amplifier and the input to the
source driving the analog input must be able to provide the AD7400. The external capacitor at each input aids in supplying
charge onto the sampling capacitors every half MCLKOUT cycle the current spikes created during the sampling process, and the
and settle to the required accuracy within the next half cycle. resistor isolates the op amp from the transient nature of the load.
φA The recommended circuit configuration for driving the differential
VIN+
1kΩ
φB inputs to achieve best performance is shown in Figure 24. A
2pF
capacitor between the two input pins sources or sinks charge
φA 2pF to allow most of the charge that is needed by one input to be
1kΩ effectively supplied by the other input. The series resistor again
VIN– φB
isolates any op amp from the current spikes created during the
sampling process. Recommended values for the resistors and
04718-027
φA φB φA φB
MCLKOUT capacitor are 22 Ω and 47 pF, respectively.
Figure 23. Analog Input Equivalent Circuit R
VIN+
Because the AD7400 samples the differential voltage across its C AD7400
analog inputs, low noise performance is attained with an input
04718-028
R
VIN–
circuit that provides low common-mode noise at each input.
The amplifiers used to drive the analog inputs play a critical role in Figure 24. Differential Input RC Network
attaining the high performance available from the AD7400.
Rev. H | Page 14 of 20
Data Sheet AD7400
DIGITAL FILTER
MCLKOUT
A Sinc3 filter is recommended for use with the AD7400. This
ACC1+ ACC2+
filter can be implemented on an FPGA or a DSP. The following IP_DATA1
ACC3
Z Z Z
04718-021
Verilog code provides an example of a Sinc3 filter implementation + + +
on a Xilinx® Spartan-II 2.5 V FPGA. This code can possibly be
Figure 25. Accumulator
compiled for another FPGA, such as an Altera® device. Note
that the data is read on the negative clock edge in this case, Z = one sample delay
although it can be read on the positive edge if preferred. Figure 28 MCLKOUT = modulators conversion bit rate
*/
shows the effect of using different decimation rates with various
filter types. always @ (negedge mclk1 or posedge reset)
if (reset)
/*`Data is read on negative clk edge*/ begin
module DEC256SINC24B(mdata1, mclk1, reset, /*initialize acc registers on reset*/
DATA); acc1 <= 0;
input mclk1; /*used to clk filter*/ acc2 <= 0;
input reset; /*used to reset filter*/ acc3 <= 0;
input mdata1; /*ip data to be end
filtered*/ else
begin
output [15:0] DATA; /*filtered op*/
/*perform accumulation process*/
integer location; acc1 <= acc1 + ip_data1;
integer info_file; acc2 <= acc2 + acc1;
reg [23:0] ip_data1; acc3 <= acc3 + acc2;
end
reg [23:0] acc1;
/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)
reg [23:0] acc2; */
reg [23:0] acc3; always @ (posedge mclk1 or posedge reset)
reg [23:0] acc3_d1; if (reset)
word_count <= 0;
reg [23:0] acc3_d2;
else
reg [23:0] diff1; word_count <= word_count + 1;
reg [23:0] diff2; always @ (word_count)
reg [23:0] diff3; word_clk <= word_count[7];
reg [23:0] diff1_d; /*DIFFERENTIATOR (including decimation stage)
reg [23:0] diff2_d; Perform the differentiation stage (FIR) at a
lower speed.
reg [15:0] DATA;
DIFF1 DIFF2 DIFF3
+ + +
reg [7:0] word_count; ACC3
– – –
reg word_clk; Z–1 Z–1 Z–1
reg init;
04718-022
/*Perform the Sinc ACTION*/ WORD_CLK
Rev. H | Page 15 of 20
AD7400 Data Sheet
always @ (posedge word_clk or posedge reset) DATA[9] <= diff3[17];
if(reset) DATA[8] <= diff3[16];
begin DATA[7] <= diff3[15];
acc3_d2 <= 0; DATA[6] <= diff3[14];
diff1_d <= 0; DATA[5] <= diff3[13];
diff2_d <= 0; DATA[4] <= diff3[12];
diff1 <= 0; DATA[3] <= diff3[11];
diff2 <= 0; DATA[2] <= diff3[10];
diff3 <= 0; DATA[1] <= diff3[9];
end DATA[0] <= diff3[8];
end
else endmodule
begin
90
diff1 <= acc3 - acc3_d2; SINC3
diff2 <= diff1 - diff1_d; 80
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3; 70
SINC2
diff1_d <= diff1; 60
diff2_d <= diff2;
SNR (dB)
end 50
DIFF3 DATA
04718-025
10
Figure 27. Clocking Sinc Output into an Output Register
0
1 10 100 1k
WORD_CLK = output word rate
DECIMATION RATE
*/
Figure 28. SNR vs. Decimation Rate for Different Filter Types
always @ (posedge word_clk)
begin
DATA[15] <= diff3[23];
DATA[14] <= diff3[22];
DATA[13] <= diff3[21];
DATA[12] <= diff3[20];
DATA[11] <= diff3[19];
DATA[10] <= diff3[18];
Rev. H | Page 16 of 20
Data Sheet AD7400
APPLICATIONS INFORMATION
GROUNDING AND LAYOUT These tests subjected populations of devices to continuous
cross-isolation voltages. To accelerate the occurrence of failures,
Supply decoupling with a value of 100 nF is strongly recom- the selected test voltages were values exceeding those of normal
mended on both VDD1 and VDD2. Decoupling on one or both use. The time-to-failure values of these units were recorded and
VDD1 pins does not significantly affect performance. In used to calculate acceleration factors. These factors were then
applications involving high common-mode transients, care used to calculate the time to failure under normal operating
should be taken to ensure that board coupling across the conditions. The values shown in Table 7 are the lesser of the
isolation barrier is minimized. Furthermore, the board layout following two values:
should be designed so that any coupling that occurs equally
affects all pins on a given component side. Failure to ensure this • The value that ensures at least a 50-year lifetime of
may cause voltage differentials between pins to exceed the continuous use
absolute maximum ratings of the device, thereby leading to • The maximum CSA/VDE approved working voltage
latch-up or permanent damage. Any decoupling used should be
It should also be noted that the lifetime of the AD7400 varies
placed as close to the supply pins as possible.
according to the waveform type imposed across the isolation
Series resistance in the analog inputs should be minimized to barrier. The iCoupler insulation structure is stressed differently
avoid any distortion effects, especially at high temperatures. If depending on whether the waveform is bipolar ac, unipolar ac,
possible, equalize the source impedance on each analog input to or dc. Figure 29, Figure 30, and Figure 31 illustrate the different
minimize offset. Beware of mismatch and thermocouple effects isolation voltage waveforms.
on the analog input PCB tracks to reduce offset drift.
RATED PEAK VOLTAGE
EVALUATING THE AD7400 PERFORMANCE
A simple standalone AD7400 evaluation board is available with
04718-029
0V
04718-030
INSULATION LIFETIME 0V
All insulation structures, subjected to sufficient time and/or Figure 30. Unipolar AC Waveform
voltage, are vulnerable to breakdown. In addition to the testing
performed by the regulatory agencies, Analog Devices has RATED PEAK VOLTAGE
04718-031
lifetime of the insulation structure within the AD7400.
0V
Rev. H | Page 17 of 20
AD7400 Data Sheet
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16 9
7.60 (0.2992)
7.40 (0.2913)
1 10.65 (0.4193)
8
10.00 (0.3937)
03-27-2007-B
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7400YRWZ −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD7400YRWZ-REEL −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD7400YRWZ-REEL7 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
EVAL-AD7400EDZ Evaluation Board
EVAL-CED1Z Development Board
1
Z = RoHS Compliant Part.
Rev. H | Page 18 of 20
Data Sheet AD7400
NOTES
Rev. H | Page 19 of 20
AD7400 Data Sheet
NOTES
Rev. H | Page 20 of 20