intel. PRELIMINARY 80C186XL/80C188XL 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS = Low Power, Fully Static Versions of 90¢180/80¢ 188, 1 Operation Modes: Enhanced Mode DRAM Retresn Control Unit —Power-Save Mode —Direct interface to 800187 (80C186XL Only) —Compatible Mode —NMOS 80186/80188 Pin-for-Pin Replacement for Non-Numerice Applications im Integrated Feature Set —Statie, Modular CPU —Clock Generator —2 Independent DMA Channels — Programmable Interrupt Controller 3 Programmable 16-Bit Timers. — Dynamic RAM Refresh Control Unit —Programmable Memory and Peripheral Chip Select Logie — Programmable Walt State Generator —Local Bus Controller —Power-Save Mode — System-Level Testing Support (High Impedance Test Mode) = Completely Object Code Compatible with Existing 6086/8088 Software and Has 10 Additional instructions over, 8086/8088 1 Speed Versions Available 25 MHz (806 186XL25/80C188xL25) — 20 MHz (60C186XL20/80C188XL20) = 12 MHz (60C186XL12/80C188XL 12) m Direct Addressing Capability to ‘1 MByte Memory and 64 Kbyte I/O m Available in 68-Pin: —Plastic Leaded Chip Carrier (PLCC) —Ceramic Pin Grid Array (PGA) —Ceramic Leadless Chip Carrier (JEDEC A Package) 1m Available in 80-Pi = Quad Flat Pack (EIAS) Shrink Quad Fiat Pack (SGFP) & Avaliable In Extended Temperature Range (— 40°C to +85°C) ‘The intel e061 86XL ts @ Modular Core re-implomentation of the 8016 microprocessor. offer higher speed and lower power consumption than the standard 80C186 but maintains 100% clock-for-olock functonel some Patiilty. Packaging and pinout ar algo ential, 134 Novem 1984 (Onder urban roti?80C186XL/60C188XL 16-Bit High-Integration Embedded Processors CONTENTS PAGE INTRODUCTION . iar ‘80C186XL CORE ARCHITECTURE ...... 137 80C186XL Glock Generator ... 197 Bus Intorface Unit 1.38 90C186XL PERIPHERAL ‘ARCHITECTURE 4.98 Chip-Select/Ready Generation Logic .... 1-98 DMA Unit... Timer/Counter Unit ...... Interrupt Control Unit... Enhanced Mode Operation (Quoue-Status Mode : DRAM Refresh Control Unit Power-Save Gontrol .. Intertace for 800187 Math Coprocessor (B0C186XL Only) 1 ONCE Test Mode .. PACKAGE INFORMATION ............. 1-41 Pin Descriptions . seseeees batt 80C186XL/80C188XL. Frou Diagrams 240 ELECTRICAL SPECIFICATIONS 155 Absolute Maximum Ratings . 2 185: DC SPECIFICATIONS 185 Power Supply Currant 166 CONTENTS PAGE AC SPECIFICATIONS .. 1.87 Major Cycle Timings (Read Cycle) ....... 157 Major Cycle Timings (Write Cycte) 150 Maer Cyla Timings tern ‘Acknowledge Cycle) Software Halt Cyclo Timings look Timings Ready, Peripheral and Queve Statue Timings --... Reset and Hold/tLDA Timings ‘AC TIMING WAVEFORMS. AC CHARACTERISTICS EXPLANATION OF THE AC ‘SYMBOLS. 17 DERATING CURVES 80C186XL/80C180XL EXPRESS 60 196x1 /20C 188XL EXECUTION 174 TIMINGS, 174 INSTRUCTION SET SUMMARY ........1-78 REVISION HISTORY 181 ERRATA 181 PRODUCT IDENTIFICATION tot 4.98900 186XL/800100XL a1 i [em F TT tT TT mg 23 ap 8 nore: Ph names in parontheses apples to 80Ct88xL 4-96 Figure 1. 80C186XL/80C186XL Block Diagram PRELIMINARY I80C 186XL/60C188XL. IAL Emcor ‘Sia eae ae Sous apa dB sara Figure 2, Oscilator Configurations (eee text) 1 I pins that lffor between the 80C186XL and the 0C186XL are given In parenthosos. ‘Tha following Functional Descrition describes tho base architecture of the B0CTBEXL. Tho BOCT8EXL fea very high Intogalion 16xt microprocessor. It ‘orbinas 19°20 of the most common microproces- ‘s0r_ system components onto ons. chip. The BOCIBEXL ls object code compatible with tho 2088/8088 micro cs and adds 10 now in- Suction types fo tho 6086/8068 instruction set. ‘Tho 80C186XL has two major modes of operation, Compatible and Fnhannad In Compatsia Mada the SOCTA6XL Is completely compatible with NMOS £80186, with the exceplion of 8087 suppor. The En- bhanced mode Ads three now features tothe system esis These are Power Save contol, Dynamic RAM rofresh, and an asynchronous Numerics Co- processor interface (B0C186XL ony). 80C186XL CORE ARCHITECTURE. 80C186XL Clock Generator ‘The 80C186XL provides an on-chip clock gonorator {or both intemal ant external clack generation. The ‘lock generator features a crystal oscilator, a dvide- by-two counter, synchronous. and asynchronous ready inputs, and reset cicuty l PRELININARY the time base for tne 80C188XL. ‘The output ofthe oscillator isnot directly available outside the BOCTEEXL. The recommendad Confira is shown in Figur 2. When ued {hirgovertone mode, tho tank crcult is recom fod for elablo poration. aRemately, the oseilator ‘may bo driven from an external soutoe as shown in Figure 2a “The crystal or clock frequency crower rast be twice the required processor operating frequency due to the internal dhvide by two counter. This counter is sed o drive al internal phase clocks and the oxter- hal CLKOUT signal, CLKOUT fe. 50% duly cyclo processor clock and can be used to dive other sy fem components. All AC Timings are referenced to eukour Intel recommonds te following values for crystal se- lection parameters. “Temperature Range: ‘Application Spocific ESR (Equivalent Series Resistance): 60 max (Sinn Capacitance of Cysta): 7.0 pf max (Load Capacitance}: 20pF £2 pF Drive Level 2mW max 13780C188x1 a0C18exL Bus Interface Unit The 80C1B6XL provides a local bus controller to ‘generate the local bus contol signals, In alton employs a HOLD/HLDA protocal for refuting the local bus fo other bus'mastors. It also proviges, ‘cuiputs that can be used to enable extemal butlors and to direct tho flow of data on and off the local bus, ‘The bus controler is responsible for generating 20 bits of address, read and writ stranae, bus cycle Status information and data (for wite operations} n- formation. It is also responsiole for reading data ‘rom the local bus during a read operation. Syncheo: ous and asynchronoue ready input pine are provi (to extend a bus cycle beyond the minimum four states (clock). ‘The 000100XL bus controler also generates two Control signals (DEN and DT/R) when intertacing to ‘exiomal transceiver chips. This capably allows te Addition of transcoivers for simole buffering of tha uttploxed eddress/data bus, During RESET the local bus controler wal perform the following aeton: ‘Drive DEN, RD and WA HIGH for one clock ey- la, then float them. * Drive 56-53 tn the inactive stato (all HIGH) and then fost, ‘Drive LOCK HIGH and then float. * Flogt ADO—15 (ADN=A), A18=10 (AO At0), BA (RFSH, OT/R. * Drive ALE LOW ‘Drive HLDA Low. BOOSH, USS. Tes, MeStvPEnEo, WOST/ ERROR and TEST/BUSY pins have internal pullup evieos which aro active while RES is appiod, Se ‘essve loacing or grounding cortain of these pins Causes the 60C186XL to enter an alternative mods of operation: ‘+ FD/EEMD low results in Queue Status Mode, ‘+ UGS and LCS low rosuits in ONCE Modk ‘+ TEST/BUSY iow (and high itor) resute in En, hhaneed Mode, 80C186XL PERIPHERAL ARCHITECTURE All the 80C186XL integrated peripherals are con- ‘woted Uy 10-bit registers contained within an ini. ‘al 256-Dyte coniral block. The control block may be ‘mapped into either memory or 1/0 space. Internal logic wil recognize control block addesses and re 4-98 ‘pond to bu cycles. An offset map of ine 2ot-byto Control register block is shown in Figure 3. Chip-Select/Ready Generation Logic ‘The 80C18EXL contains logic which provides Programmable chip-select goneration far both mom. ‘ries and. peripherals. In addlion, can bo Programmes to provide READY (or WAIT state) gen ‘ration. It can also provide latched address bits At fansi AP. Tha chip-eolet Inoo aro active fr ell nen ory and 1/0 cycles in thet programmed. areas, whether they be generated by the CPU or by the integrated DMA unt. ‘Tho 60CIBSXL provides 6 memory chip select out- puts for 9 address. areas; upper mamory, iowar ‘memory, and midrange memory. One each is pri {0 Tor Upper memory and Towar memory, while four ‘re provided for midrange memory. oan UA Deseo Chama 1 UA Dessior Coaoalo On ste cont Retes Tine Cort Rogie " Tne 1 Cont Rat se Tine 0Conl Roget . Naemetcitctereton | ‘Figure 3. Internal Register Map ‘Tho 80C186XL provides a chip eoloct, called UCS, forthe top of mamory. Tha top af memory ie woualy used as the systom momory Bocause after coset the, ®0C186XL begins executing et memory location FFFFOH. PRELIMINARY |‘The 80C186X1 provides a chip select for ow momo. {y eallod LCS. The bottom of memory contains the interrupt vector table, starting at location 00000H. ‘The a0C18aXL provides four MICS lines which aro ‘active within a user-locatable memory block. This block can be located within the BOC1BEXL 1 Mbyte momory address space exclusive of the areas do- {hed by UCS arnt ECS. Bol Uw busy audios aed ‘ze ofthis memory block are programmable. ‘The e0C186XL can generate chip selects for up to ‘seven peripheral devices. These chip selects are ac- tive for seven contiguous blocks of 128 bytes above fa programmable baso address. The base address ‘ay be located in ether memory or /0) space ‘Tho B0CtB6XL can gonorato a READY signal intr- peripheral or memory is programmable to provide ‘0-3 walt states for all aooessos to tho area for which the chip solect is active. In adion, the BOGTEEXL may be programmad to etnor ignore ex ‘temal READY for each chip-seect range individually fF to factor external READY with the integrated ready generator. ‘Upon RESET, the Chip-Select/Ready Logi wil por- ‘orm the folowing actions: * All chip-solect outputs wil be crven HIGH, ‘= Upon leaving RESET, the UCS line will be pro {grammed to provide chip solects to a 1K block With tho aosompanying HEADY eoritol bs eat at (17 to insert 3 walt states in conjunction with @ ternal READY (i¢., UMCS resets to FFFEH). ‘+ No other chip select or READY control renistors hhavo any predefined values after RESET. Thoy will nt become active untl the CPU accesses bar DMA Unit ‘The 800186xL_ DMA contvller proves two Index pendent high-speed DMA channels, Data wansfors ean occur between memory and 1/0 spaces (0.., Memory to 1/0) or within the same space (0.9, Momory to Momory or VO to 1/0}, Data can’ bo transferred cither in bytes (8 bite) or in words (16 bits) to or from even oF odd addresses. NOTE: (Only byte transfers are possibie on the B0C188XL. Each DMA channel maintains both a £0-bit source ‘and destination pointer which can bo optionally in- ‘remantod of decremented aftor each data transfor {by one or two depending on byte or word transfers). Each data transfer consumes 2 bus oyeas (a min ] PRELIMINARY eoctssxL/soctesxL imum of 8 clocks), one cycle to fetch data and the ‘other to store data, ‘Timer/Counter Unit ‘The 80C186XL provides thres internal 16-bit pro grammabio timers, Two of these are highly flxiblo {nd aro connocted to four extommal pine (2 per timer. “They can be used to count external evant, timo ex ‘temal events, ganerate nonrepattive wavetors, tc. The third timer is not connected to any external ins, arid fs useful for res-ine coding and Uw dor lay applications. in adalton, the third timer can be used as a prescalr tothe other two, or as a DMA request source. "The B0CTBEXL can receive nterupts from @ number ‘of sources, both intornal and external. Tho BOCTREXL has 5 external and 2 internal intorupt ‘sources (Timer/Couners and OMA). Tho internal ine {erupt controler serves to merge these requests on € peoiy basis, for individual serico by the CPU. Enhanced Mode Operation In Compatible Mode the 80C186XL operates with all the features ofthe NMOS soe, witn the exception ‘9f 8087 suppert (Le. no math copracessing is poss blo in Compatible Mode). Queue-Status information 's etl avallablo for dosian purposes other than 8087 support. [AI the Enhanced Mode features aro completoly ‘eakac! whan In Compatina Mode. Awa to any of the Enhanced Mode registers will have no effect, while a road wil not return any valid dala Power-Save, DRAM relresh, and numerics coproc- ‘ess0r suppor (BOCTBEXL ory) in addition to all the ‘Compatible Mode features. Hf connected to a math coprocessor (B0C196XL ‘niy), this mode will be invoked automatically. With ‘utan NPX, this mode can be entored by tying the RESET output signal from the 80C186KL' to the TEST/BUSY input Queue-Status Mode ‘The quioue-status mado is ontorod by strapping tho RD pin ow. RD le camplod at RESET and if LOW, the 80C186XL will configure the ALE and WR pins to be QS0 and QSi respectively. This mode is ava. able on the B0C188XL in both Compatible and En- hanced Moces, 138 IE eT80C1B6xL/e0C188XL DRAM Refresh Control Unit ‘The Relresh Control Unit (ROU) automaticaly gon- ‘rates DRAM refresh bus cycles. The FCU operates ‘only in Enhanced Mode. Aftr @ oroarammahia nas. ‘vaiod when the BIU executes the roftesh bus cycle, Power-Save Control ‘Tho 80C186XL, when in Enhanced Mode, can enter {8 Power saving state by internally dividing tha pron @stor clock frequency by a programmable factor ‘This divided frequency fe also available. at tho CLKOUT pin, All intemal logic, including the Refresh Control Unit ‘and the timers, have their cocks siowed down by the vision facir. To maintain areal timo count ora fixed ORAM relies rat, Uiese pennerals must be ‘e-programmed when entering and leaving the pow. er-save mod, Intertace for 800187 Math Coprocessor (80C186XL Only) {In Enhanced Mode, three ofthe micrango memory Chip selects are rodtined according to Table 1 for use withthe 800187. The fourth chip select, HOSE 1.40 intel. functions 2s in compatihia mode, and may be pro ‘grammed for activity with ready logic and walt states ‘accordingly. As in Compatible Mode, MICS? wil une. tion for one-fourth a programmed block size, ]PEREQ Processor Exionsion Request WCSi_ |ERROR Nex Error NCEE |HCEE Mid-Range chip Select NGSS_|NFS Numeric Processor Select ONCE Test Mode To facitate testing and inspection of devices when fixed into a targot system, the BOCI8EXL has a fast ‘ode avaiable which allows ell pins to be placed in 2 high-impedance stats. ONCE stands for “ON Cir cult Emulation”. When’ placed ‘in this mode, the 80C186XI. wil put ai pine In the high impodance state untl RESET. ‘The ONCE mode is solocted by tying the UCS and tho ECE LOW during RESET, These pins are sar pled on the low-to-high transiion of tho RES pin. ‘The UGS and the LCS ping have woak internal pul: Lp resistors simiiar to tho RD and TEST/BUSY pins 1 guarantee ONCE Mode i nol entered inadver. tently during normal operation. LCS and UCS must be held low at least one clock aftor RES goes high {0 quarantes entrance info ONCE Mode, PRELIMINARY |PACKAGE INFORMATION ‘This section describes the pin functions, pinout and thormal characteristics for the 80CI86XL in the ‘Quid Pia Pack (GFP), Pasic Leaded Chip Carioe (PLCO), Leadloss Chip Carir (LOC) and the Shrink ‘Quad Flat Pack (SQFP). For complete package ‘spectications and informa, 900 the Intel Packag ing Oulines and Dimensions Guide (Order Number 231969). Pin Descriptions Each pin ological set of pins i described in Tablo ‘9, There are four columns for cash entry in tho Pin Desorption Table, The following sections doscribo ‘each column, in Name In this column is a ranemonic that do- scribes the pin function, Negation of the signal namo (0, RESIN) implies that {he signal Is acave low. Pin Type ‘A.pin may be either power (P), ground (G), mput ony (), output oniy (O) or ‘ut/output (1/0). Please note that some Bin have more than one function. input Type (tor land VO types only) ‘These ara two diferent types of Input ping on the 80C186XL: asynchronous land synchronous. Asynehronoue pins equi that eatup and hold timos be mot only to guarantee cognition, Synehro- ‘nous, input pins roqure thatthe setup fand hold times be met 10 guavantos Column 2: Column at | PRELIMINARY 800186XL/0C188xL, proper aperation. Stated simpy. missing atup oF hold on an esyachronous pin will sult in something minor (Le. tn- ‘or count will be missed) whereas miss- Inga eotup or hold on a eynchronous in rosult in system fara (tho system wil “Tock up")- ‘An ingut pin may aeo bo ego or lvel Column 4: Output States (for © and 1/0 types only) ‘The stato of an output or I/O pin is do- pendent on the operating made of the Sevice. Thoro are four modes of opera- tion that are diferent from normal active ‘mode: Bus Hold, Reso, Ile Mode, Pow ferdown Mode, This column describes the output pin state in each of these modes. “The legend for interpreting the information inthe Pin Descritions is shown in Table 2, please rofer to tho table enty for “The "1/0" signifies that the pins are bidroc- have bath an input and ust function) ‘Tho “'S” indicates that, a8 an input the signal must be synchronized to CLKOUT for proper operation. ‘The "H(@2)" Indicates that these pins wil float while the processor is hr Uw Holl Ackwowlodgo, stato: FQ) indicates that theso pins wil oat while RESIN: ‘slow. {All pins float while the processor is in the ONCE Mode (withthe excopton of X2). +8180C186XL/e0ctAAKt 442 2. Pin Description Nomenclature Description P Power Pin apply + Voo voltage) a ‘Ground (connect to Vés) ' Input only pin ° Output only pin Vo__| inpur/Output pin SE) | Synchronous, edge sensitive ‘S(0__| Synchronous, level sensitive AG) | Aeynehronous, edge sensttve A()__| Asynchronous, level sensitive Hi) | Output driven to Voc during bus oid 40) | Output ivan to vgs auring bus hold H@) | Output oats during bus hold HQ) | Output remains active during bus hold HO0__ | uinut rota currontotato during bus okt ROWH) | Ouiput woakly held at Voc during reset R(t) | Output driven to Voc during reset F0) —| Output dvon to Ves curing reset F@) | Output toats during reset QQ) | Outputremaine active during reset FO0__| Outout retains curont stata ring rosot PRELIMINARY |intel. soc eexist0cre8xt ‘Tabla 2. Pin Dencriptions J wou | Coot Pin Description Ve Sp Pe 7 wipers Ves 8 Syn Grand : nese? 0 THO) | RESET Oupu cats ta ha GPUs grt andan (1). | boused as @ system reset itis active HIGH, synchronized withthe processor clock, and lasts an intogor numberof ‘lock periods corresponding to the length ofthe RES signal Resat gnae inacua > lonkout parade attar BES goa —— xt TAG) ‘Crystal Inputs X1 and x2 provide external connections for a 9 oi TG) | furdemental made or third overtone parallel resonant crystal {or the intemal oscillator. X1 can connect to an extemal RIG) | clock inetoad of a oryetai. In thie cae, minimize the ‘capacitance on X2. The input or osolatorfraquancy is internally divided by two to ganorat the clock signal (CLKOUN, FES A ‘An active RES causes the processor to immediately ‘rminato ts prosontactvly, clear the intonal ogi, and ‘enter a dormant stato. This signal may be asynchronous to ‘the clock. The processor bogie fetching instructione _approximataly 6% clock cycles aftor FES is roturnad HIGH. For proper itaization, Voc must be within specifications andthe clock signal must bo stab for more than 4 clocks. ‘with RES nt LOW. RES ls Internally synchronized. This Is provided with a Schmite-tigger to faciitate power-on. generation ve an RC network. Teevevey| 1 | Ae) “The TEET pin io sampled during and aftr rosot te dotormino ‘whether the processor is to enter Compatible or Enhanced Mode. Enhanced Mods requires TEST to be HIGH on the Fiing edge of HES and LOW four CLKQUT cycles later. Any ‘trer combination wil place tne processor n Compattbie Mode. During power-up, ace FES is required to configure ‘TEST/BUSY as an input, A weak internal pullup ensures a HIGH stato when tho inoutis not externally driven. ‘TEST-—In Compatible Mode ths pin s configured to operate ag TEST. This pinis examined by the WAIT instruction. ithe ‘TEST inputle HIGH when WAIT execution bagin, instruction ‘execution wil suspond. TEST wil be resampled every tive locks unt t goes LOW, at which time execution wil resume Fintrrupts are enabled while the processoris, wating for TEST, interrupts wil bo serviced. BUSY (80C186XL Oniy)—In Enhanced Mode, this pins Configured to operate as BUSY. The BUSY input is used to ‘notify the 80C186XL of Math Coprocessor activity. Floating pont instructions executing Inthe 80c l@6XL sample the BUSY pin to determine when the Math Copracessor is ready toaccept anew command. BUSY is active HIGH. NOTE: Pi nanos in parentheses epoily to tho 80C1804L. | PRELIMINARY 14380C186XL/80C189XL intgl. Table 3. Pin Descriptions (Continued) Pin Pin] Input | Output Name Type | Type | States cece MAINO 1 pao “Timer inputs are used either as lock or contol signal, TMRING | Ae) \dopending upon the programmed timer mode. These Inpuls are ace HIGH (or LOWto-HIGH transitions are Counted) and internally synchronized, Timor Inputs rust be tied HIGH when not being used as clock or rtrigger inputs TMA OUT ° H(Q) | Timer outputs are used ts provide single pulee or IMs. OUT R(1)_| continuous waveform generation, depencing upon the timer mode selected. These outputs are not floated ‘during a bus hold. DRGO | Aw DMA Requestis assoriod HIGH by an extemal dovico DRat \Wwhn its ready for DMA Channel 0 ort to perform a transfer. These signals are lovol-tiggored, synchronized Na Ae) ‘The Non-Maskable interrupt input causes a Typo 2 itorrupt. An NMI wansiton from LOW to HIGH is latched and synchronized intemally, ad initiate tho interupt atthe next instruction boundary. NIM must be ‘assertod fo atleast one CLKOUT period. Tho Non- Maskabie intertupt cannot be avoiged by programming. NTO a) Maskabiointomupt Request can be roquosted by INT1/SELECT A) ae aeceee ins. When configured as inputs, those pine ar ative HIGH: Intorust Romusts are INTRARNTAD) || vO | AE | HO) | Symenntsed nora. Ree eg INTS/INTAT/RO A RZ) | configured to provide active-LOW interrupt. {cknowodgo ciput sana. Alntomupt inputs may bo ‘configured obo ol a0go- or lovesnggred To ‘our recognition, msrp requnsts fue rsain cv unto rtoruptsacknowedgod. Whon Slave Mode is selecog, the tuncton ofthese pin changes {cee ntrupt Gontoersecton ofthis data shan ‘Ai9/88 ° H@) | Addross Bus Outputs and Bus Cycle Status (2-6) ANB /S5 Fi) | indicat tho four most significant address bits during Ty. AIT/S4 ‘These signals aro active HIGH, Atwsss During Ta Ta, Tw and Ty, the $8 pins LOW to indicate (A8-A15) ‘8 CPU-iniatad bus cycle or HIGH to indicate a DMA- intlated or refresh bus cycle, During tho samo T-states, ‘89, 64 and 85 ero always LOW, On Une 60C 18EXL, ‘A15--AB provide valid address information forthe entire bus cyclo. (ORE [1 | SO | He | Alone ianpanmante ee (50-00 Fi@)_ | tullined mamery er/O datos (7a ata (a, ca) Ta, Tw and T4) bus. The bus is active HIGH. For SEC{ Bit, Apis aratogeus to SEE rte ower bof the dates pinay thougn Up HIS LOW seg hon aby obo tanstred onto hoover tn eft busin momo er/0 epee, Pin names in parentheses epply tothe SOC 86x. 4 PRELIMINARY l“Table 3.Pin Descriptions (Continued) ‘806 186XL/80G 188XL, ‘need tobe latched. On the 80C188XL, FFSHis asserted LOW to indieate a ratresh bus oye, In Enhanced Modo, BEE (FESH)willalo bo used signify DRAM Totresh cycles. Aretresh cyci is indicated by both BHE (RESH) and AO boing HIGH, '800186xL. BRE and AO Encoding 20 fan Funetion 0 | Word Tranetor 1 | Byte Transfer on upper hal of data bus (015-08) 1 | 0 | Byte Transfer on lowor half of data bus (07-Da) 1_| 4 | Retrosh ‘ALE/OSO 00) co) ‘Adress Latch Enable/Queve Status 0s provided by the processor {olatch the address, ALE is ace HIGH, with addresses guaranteed vali.on the taling edge, Wavasi 4@) R@) ‘Write Strobe/Quoue Status 1 indicat that the data onthe bua sto be written into a mamory or an /O davies. tis active LOW, When ‘me processor isin Guove Status Modo, ino ALE/GISO and WH/QSt pins provide information about processor/Insiruction queue. Intoraction asi | aso ‘Queue Operation ° No queue oparation| ° Fist opcode byte fetched trom the queue 1 ‘Suosequent byt fetched rom ine queue 1 Empty the queue D/GSND HQ) RO) ‘Read Strobe isan active LOW signal which indicates thatthe ‘processor Is performing a memory or 70 read cya. tis guarantees ‘otto go LOW before the A/D bus is floated. An internal pull-up ‘ensures that FD/CISMD is HIGH during RESET. Following RESET the pinis sempled to determine whathor tho processor isto provide ALE, RD, and WA, or quous status information. To enable Queue ‘Stats Modo, RD must bo connected to GND. ‘ARDY ay) st) ‘Aeyrohonous Ready norms to procesor thatthe aderossod ‘paar space ori} coice wl somplto a data ans: The [ARDY pn accopte ain edo thet asynchronous fo LKOUT trai acive HIGH. The ang edge of ARDY us be Syctrnied tthe proceaor clock Gomang ARDY HiGhi ait hays user thorendy cordon othe CPU. is ino fund, ksh ba bed LOW told conto tothe SROY pi. in names in parentheses apply tothe SOCTEXL | PRELIMINARY a 1-45OC 1R6XI/A0C1BeXL intel. ‘Table 3. Pin Descriptions (Continued) in| input Type ‘Output States Pin Description enoy 1 [aw ‘Synehronaus Ready iorms the proosssor thatthe addressed ‘memary space or /O device wil complote a data ransfer, Tho 'SRDY pin acoopts an active HIGH input synchronized to CLOUT, ‘The use of SADY allows a rolaxed system timing over ARO This is accomplished by alination of the one-half clock cycle required ‘internally synchonize the ARDY input signal. Connecting SROY igh wl alwaye assort the ready conaliton to the CPU. I this line is unused, it should be tod LOW to yield contrel tothe AFIDY pin. HQ) RQ) TORK outputinicatos that other systom bus masters are not io {gain contol ofthe system bus. LOCK is active LOW. The LOCK Signal is raquastad hy the LOCK prefixinetucton and e ativatod ‘atthe beginning ofthe frst data cyco associated wih tho instruction imediatoly folowing ihe LOCK prefix It romans active nti the completion ofthat instruction. No instruction prefetching will cour while LOOK s assole Bus Cycle Status Information Bus Cycle initiated a © | interrupt Acknowledge 1 | Roadi/o © | Wete v0 4 | Hatt © | instruction Fotch 1 | Road Data trom Memory © | Write Data to Memory 1_| Passive (no bus oye) =a nccco/el a se0++00/y 2 may be used as a logical M/iO inicator, andS1 as a DT/AL incicatr. HOLD Tao LDA HO) RO) HOLD indicates that anothor bus master is requosting the local bus. ‘The HOLD input s active HIGH. The processor gonorstes HLDA (HIGH) in response to a HOLD request. Simultanecus vith tho lcouanoe of HLDA, the processcr wil latte kal bus und contol lines. After HOLD is detoctod as being LOW, the processor will lower HLDA. When the processor neads to run another bus cyclo it will again crive the local bus and contol nes. In Enhanced Mode, HLDA wil go low when a DRAM refresh cycle 's pending in the processor and an external bus master has contro! of the bus. itll be up to the external master to rlingush the bus by loworing HOLD 00 thatthe processor may exevule tin rettesh ole. in namoe in peontheses apply to the 690109X1. 1-46 PRELIMINARY |80¢ 186XL/80C 188xL. ble 2. Pin Deoeriptions (Continued) Pin Pin Name | Type Input | Type ‘Output States Pin Description es vo) aD HC) Rw) Upper Memory Op Selects an active LOW output ‘whenever a memory eferanco is made tothe defined Upper portion (1K-258K block) of memory. The ‘sree range activating UES ls software Programmable. (UGS and UGS aro sampled upon the rising edge of RES. Itboth pins are held low, the processor wil ontor ‘ONCE Meda. In ONCE Mode al pine assume a high Impedance stato and remain so untl a subsequent ESET. UCS has a woak intrnal pulup thats active fliring RESET to anaiva that tha processor doos not fentor ONCE Modo inadvertently. es v0 a Ha) Rw Lower Memory Ohip Selects active LOW whenever a ‘memory reference is made to the defined lower partion (1K-25640 of momory. The address range activating is sofware programmable. UGS and TCS are sampled upon the rising edge of RES, Irbotn pins are neta ion, ine processor wit enter ‘ONCE Mode. In ONCE Mode al pins assume a high impedance stato and remain so unt a subsequent ‘only during RESET to oneure that ho processor d ‘ot enter ONGE mode inadvertently. Wes0/penco | v0 Vii AD Hq) ‘Mid-Range Memory Chip Select signals aro active LOW WLM ‘8 PEREQ input (Processor Extension Raquest). When. ‘connected o the Math Coprocessor, this input is used to signa tho 80C186X1 whon to make numeric deta {eanstors to and from the coprocessor. MCS bacomes [NBS (Numevic Processor Select) which may only be sctvatod by communication to tne C187, MEST becomes! in Enhanoad Maa and eset 9 ‘Signal aumorics coprocassor eros. HO) Ra) Peripheral Chip Solet signals 0-4 are active LOW whan a referance is made to the defined peripheral faroa (64 Kbyte /O or | MByte memory space), The Hun) Ra) Peripheral Chip Select 6 or Latched At may be programmed to provide a sith perioral chip selec, or {o provide an infrnaly latched A1 signal. The addres ‘axige acvating PUSS is sonware-programmabia. 1/A1 does not flat during bus HOLD. When programmed to provide latched At, this in wil otain the previously latched value during HOLD. NOTE: Pr names in perontheses apply to the 60C108xL. ] PRELIMINARY 147tocteex. ancient intel. ‘Table 2.Pin Descriptions (Continued) Pin | Pin | input | Output Namo_| Type | Type | States in Deseription Fese/aa | 0 | — | vcn7Hion | Perpneral Chip Soiect 6 or Latched A2 may be programmed R(1) | to provide a seventh poriphoral chip select orto proved an Internally latched A2 signal. Tho address range activating Is software-programmahin PCSR/A2 docs not float ‘ding bus HOLD. When programmed to provide latched A2, {his pin wal rotan the previously latched value during HOLD. a) -_ — neo ae transferred tothe procesor. Whon HIGH the processor ‘laces write data on the data bus. DEN © | = | @ ~ | oma Enapie's provided asa data bus vancolver ouput (1.2) | enable. DEN i active LOW during each merry and 70 ac2908 (including 606187 accous) DEN fe HIGH witenover D/A changes sata. ving RESET, DEN ic stvom HIGH for ‘one coc, ton floated NG. —[— — | Notconnected. To maintain compatbity with future products do not connect to these pins. Note: Pin nares in prenthoses apply othe 60C188XL, el PRELIMINARY |intel. pean octet Ceramic Leadiess Chip Carrier (JEDEC Type A) commana ene RS = N Z EY 4 ed =| = Ey i Z S i Tn SS : nt areas nan rnar a sen ®O8OGGO08 @®@@@OGQGO088 e8 e® ss, «dss . 88 $3 pes @®@ e©® @®@ @ ®@@QGGOOOOOO® @@®OODOOO Soto00c wet me ns FHC sumer ™ Figure 4. 60C186XL/60C188XL Pinout Diagrame } PRELIMINARY 1-49HI@!. Shrink Quad Fiat Pack 82 Bee ORL nore: 300000006 nos the ltl FPO ruber. Figure 4 80G186X1/800188XL Pinout Diagrams (Continucd) fAintel. soc eextseocssex. Pinstic Leaded Chip Cartier Contacts Facing Up Contacts Facing Down, Ns0c 186x120 ] TDOODDDKE (See Note) ‘80-Pin Quad Fiat Pack (EIAs) Contacte Contacts Facing Up san FACING Down (oy i Noe: YOO00000A inlotas the Ine FPO number. Figure 4. 800186XL/80C288XL Pinout Diagrams (Continued) | PRELIMINARY 151‘BOCTBEXL/80C188XL intel. “Table 4..66/PLCC Pin Funct ‘AD Bus Bus Control vo ro} w| | Aleraso [er ves ry 01 15| | BRE@rSR | oa tes 2 abe 3/ | a 8 no8 4] | st 3 weso/penca | 93 04 3] | ae WCSW/ERROR | 37 aoe 8| | Ro/asmo | ee Wiese 3 408 4| | wRrost Wessnmrs | 35 407 2| | any 5 noe — | se | | env ° Faso 2 aoa) | 44 | | DEN 2 Post 2 soir | 12 | | ova 0 FOS? 23 aoriain — | 40 | | toew a Fess = aoa |"? | | How 50 st 20 aoisaiy | 5 | | HUDA 51 essay | at pou | 8 Poseaz | na postat) | aveise Py qwawo | 20 a7/84 7 TwAINY | 2t mores co qwrouro | ze 9/s6 & mwnours | 2 rao io rat 19 nore: Pr nae in puenhoes apy oth 608K. “Table 5. LOC/PGA/PLCG Pin Locations with Pin Names 1] Abeta) 18 | ORG 35 | WOSSNPS | [2] 2 | aor 18 | paar as | WS 89 | 51 3 | aoiacaray | | 20 | TuRINo 37 | WOSi/eRROR | | 54 | 52 4 | abe at | TMRINY 38 | WGSb/PEREG | | 5 | ARoY 8] aoisat | | ee | twnouro | | 30 | DEW 26 | GLkOUT 8 | ADs z| twrourt | | 4 | orm sr | RESET 7| apie | | 24 | Res a1 invammrat | | 88 | x2 8 | ape 2s | BOT 42 nranmras | | 60 | xt 9 | Vos 28 | Veg #2 | Yoo 60 | Vss 10 | abiiarn | | a7 | PST 44 | wivsecect | | 61 | Abevas0 11 | Abo 23 | POSE 45 | nto 2 | RD/oSS 12 | arora) | | 20 | Boss 48 | Nu 3 | Wavost 43 | ave 20 | POSE a7| Testvsusy | | 64 | BE GSA) 14 | AD0 A) a | POSB/at 49 | Lock es | ato/se 4s | apt a2 | POSSrn2 a9 | sauy 6 16 | A035) as | (cs 50 | How er 17 | abo au | es 51 | HLDA 3 Note: Pin namos in parentheses apply to the 90C1B8XL. 152 PRELIMINARY |800 186xL/80C188XL. ‘Table 6. QFP Pin Funotione with Location ‘AD Bus Bus Control Processor Control vo ‘ADO e4 | | auevaso 10 | | RES 65 | | OCs 6 At ee | | BHe@ren | 7] | rcocr 40 | | 10s 40 Abe 68 2a] | xt 16 ADS 7o| | st a2] | xe 17 | | MOSo/PEREQ | 99 ADA | | SB 21 | | cuxour 19| | MOST/ERROR | 40 ‘ADS 76 | | RO/OSMD @| | Testeusy | 29 | | Mese 41 ADS 78 | | WRrast | | 0 | | MCSaNPS | 42 aD? e0 | | ARDY 20 | | into a ‘ADB (A8) 65 | | saoy 27 | | wwrisetect | 92 | | Peso 54 ‘AD9 (A9) 67 | | DEN 38 | | INT2ANTAG | 25 | | POST 62 aptoato) | 69] | OT/R a7 | LINTaANTAT | 96 | | POSE 51 apis) | 74] | TOR 20 rs 50 api2aiz) | 75 | | HOLD 26 49 api3(ais) | 77] | HLA 25 | | PowerandGround_| | BoSé/A1 48 anit) — | 79 Veo! sa | | POBR/A> “7 ADI5 (AIS) 1 Veo. 3 Ai6/S3 3 Mo Connection Voo 72| | TRINO 69 AI7/S4 4| [Ne 2| | oo 73 | | TRIN’ 58 16/85 5] | Nc 41 | | Ves 12| | trouro | 57 19/88 6] [nc 14 | Ves 13| | twRour1 | 56 NG. 48] [Ves 53 No. By Rao or No. “8 brat 60 NG. “ Ne 62 No. 6 Nore: in names in parentheses appy tothe B0C86XL. “Table 7. QFP Pin Locations with Pin Names 1 | ADIS(At5) ar] a1 | MCSE 61 | ORGO 2| No. ee | St 42 | MOES/APS ee | No. 9 | Ate/so 2s | 50 43 | No. ea | NC. 4 | Atz/s4 24 | Ne. 44 | NG. 64 | ADO 8 | ate/ss 25 | HULDA, as | TS 5 | Ana (any 6 | Ato/s6 26 | HOLD 46 | CCS. 66 | ADI 7 | BHE/RFSA) 27 | sRDY 47 | POSB/AZ 67 | ADO (AB) 8 | WRrast 28 | COCR 43 | POSB/At 8 | aD2 9 | RO/GSMO 29 | TesT/eusy 49 | Post 69 | ADIO(A10) 10 | ALE/QS0 30 | NMI 50 | POSS 70 | De 11 | NO. 31 | INTO st | POSE 71 | ADIT (At) we | Vor se | inrs/eeceet | | se | POST 72 | Yoo 18 | Voo 38 | Voo. 53 | Voo 73 | Voo 14] NG 34 | Voo 54 | POSS 74 | ADE 15 | NO. 35 | INTO/INTAS ss | FES 75 | Ata (ata) 16 | x1 36 | INTa/INTAT 56 | TMROUT1 76 | ADS a7 | xe 37 | OR 87 | TMROUTO 77 | ADI9(At3) 18 | RESET 38 | DEN 68 | TRING 78 | ADE 19 | CuKouT 39 | Mcso/penca | | 59 | TMRINO 79 | ADIA(At4) 20 | ARDY 40 | MCSI/ERROR | | 60 | DROY 80 | AD7 Pin names in parntheses apply tothe 80Ct8x1. } PRELIMINARY 1880c 186xL/60c188xL intel 7 “Table 6. 909 Pin Functions with Loorton ‘AD Bus ‘Bue Control Processor Control v0 ry +] | @eas. | ze] | RES 73] [OS 2 ADI 3 (BHE (RFSH) 26 RESET 34 ws 63 02 e| | wo] | x 3 03 2| | 81 | pe 23 | | mesovpcrea | s7 hos x | & a| | Gtxour | 36] | woswennon | 5 05 t«| | Roos | 23 | | Testreusy | ze | | ose 50 ‘ADS 16 ‘WRvas1 ca NMI 47 MCSS/NPS 60 aor 18 | | anov a7 | | nto ° ‘ADB (A8) 2 ‘SRDY “4 INTI/SELECT | 49 POSO mn ‘ADS (AQ) 5 ‘DEN 56 INT2/INTAG 52. POST 69 api | 7| | ore sa] Lintantat__| sa | | poss fa gona | 8| | Cook 6 Pos or poraia | 12 | | HOLD 43] Cpoweeome] | POSS 6 AD13 (A13) 16 HLDA 42 ae POSS/A1 85 pow | a7 | Yoo wo] | poseaz | be aos) | 19 Veo i" AN6/S3 a No Connection Veo 20 TMR INO 7 Ma7/84 z| [We a] | ve so||iwan: — | t6 aie/ss z| | Nc 25 | | vos s1| |twrouro | 75 A086 24 | | no. 35 | | Veo ei} |mmaours | 74 NG 55 | | vos = NG. 72] | Ves 31 | | orao 79 Ves a1 | Loaar 78 Yes 70 vss 0 Nore: Pin pamos in parentheses apy to tho B0C188XL. ‘Table 9. SOFP Pin Locations with Pin Names 1] Abo at | ates 41 | Vos 61 | Vog. 2 | Ane (aa) 22 | arise 43 | HLDA eo | Uee 3 | api 23 | ate/ss 43 | HOLD 63 | ICs 4) Nc 24 | atgvse 44 | SRDY 4 | POSB/A2 5 | AD8(AS) 2s | Ne. 45 | COOK 65 | POSB/A1 6 | D2 26 | SHE (RFSH) 4g | TEST/eusy 66 | POSS 7 | ADI0 (A10) 27 | WR/Gs1 47 | 67 | FOSS 8 | ADs. 28 | RO/GSMO 48 | into 68 | POSE 2 | aoiiann, 29 | ALeraso av | invvsetect | | 69 | Post 10 | Veo. 20 | Vss 50 | Veo. 70 | Vsg. 11 | Voo. at | Ves 51 | Voo 71 | BOSD v2 | ana a2 |x 2 | iNTa/IRTTAD ze | No 13 | abtzaig) 3a | x2 9 | INTa/NTAT 73 | RES 14 | ADs: 34 | RESET 54 | DT/A 74 | TMR OUT 15 | ADIS (A13) 38 | NC. 65 | NS. 78 | TMROUTO 16 | ADE 36 | CLKoUT 6 | DEN 76 | TMAING 47 | aia (ara) 37 | ARDY s7 | MCSo/penea | | 77 | TMRINO 48 | aD7 38 | 52 sa | HCST/ERROR | | 72 | ona 19 | ADIs ais) ov | ST 9 | WCSZ 70 | DRGO 20 | Veo 40| 8 60 | WCS3/NPS 80 | Vas Nore: Pin names in parentheses apply to the B0CTB8XL. nd PRELIMINARYELECTRICAL SPECIFICATIONS. Absolute Maximum Ratings* ‘Ambient Temperature under Bias ....0°Cto + 70°C ‘Storage Temperature 65°C to +160 Voltag on Ary Pin with Respect to Ground . -10Vt0 +7.0v Package Power Dissipation aw. Not to-excood the maximum sliowablo dle tempora- ‘800 186XL/80C188XL, NOTICE: The data choot containe preliminary infor ‘ation on pow products in production. The speci tions are subject to change without roves. Very with your local Intel Sales office that you have tho latost fata shoot before fnalzing a design “WARNING: Stossing the device beyond tha “Absokite Maximum Ratings" may cause pamanent damage. These are stress ratings ony. Coaration bayand tha isnot recommended and ax tended exposure beyond the “Operating Condos” ‘may atfot doco rely. {ure basod on thermal resistance ofthe package. NOTICE: The specifations are subject to change witout notice. f DC SPECIFICATIONS 14 = o°Ct0 +70°0, Voc ~ 5V 10% [symbol] Parameter Min ‘Max [Units] Test Conditions Vn | input Low Votiage =05 |02Vec-03] V (Except Xt) Vir | Olek input Low -05 08 v Vottage Ot) Viv | imputtgh Votage _[02Voo + 08] Voo+ 0s | V (All excoot Xt and FES) Ver | Input High Voliugo ES)| 90 | Vooros | V Vie | look Input High 38 | Votes | V Voltage Ot Vou | Output Low Voltage 04s | V ior = 25mA 0, 1,2) {ou = 20™mA (other) You — | Output High Voltage 24 Voo | _V [lon = —24mae 24V@ Voo= 05 | Voo | V |low= —200 nA @ Voc -0589) cc | Power Supply Gurren 100 | mA |e 25 MH oC Voo = 55¥e) 3 | ma [ezomHz.oc Yoo = 35v0 25 | mA [e12MHa.00 Yoo = 88v wo | wa [epcoe Yoo = 85 i | Input Leakage Curent 10 | pA [wonnt, O45V s Vin 5 Voo Tio | Output Leekage Curent 10 | HA | @05Mnz, O.45V © Vour < Veo!) Vouo _| tock Output Low 045 | V [lao = 40ma | PRELIMINARY 155ooo txt eoe ox intel. DC SPECIFICATIONS (Continued) Ta ~ 0°010 +7070, Vor — SV 410% Symbol Parameter Min ‘Max | Unite | TestConaitions Vowo | Glock Output High Veo — 05 Vv | tesig = =500 nA Ow. Input Capacitance to | pF | eta Co. Output or /0 Capacitance 2 | pF | e1mac@ NoTes: 4. Pins bing tated cing HOLD or by invoking the ONCE Mode. 2. Charactorizaioncondions ae a) Froquency = 1 MHz b) Unmoasured pins at GND; ) Vy a + SQV of O48V. This arametor ent tested 5" Gren is measred wih he dove In RESET wth X1 and X2 van and all cer non-poner pis open. 4. RD/GSUD, UCS, LCS, NCSO/PeREO, MCSi/ERROR and TEST/BUSY pins have intel pulup doves. Losdng some ‘of tooo pins above l= ~200 A can caso th proceso to go ino arate modes of operation. Seo the seaton an Power Supply Current veo Current is tnesrty proportional to clock trequency and is moasurod withthe devi in RESET with X1 « land X2 even end all other nan-powar pins open. | Maximum currant ie given by ioc = § mA % freq. won) |e (tHe) Flaw ‘com tt log i the uisscent leakage curent when the clock is stato. l,i typically less then 100 pA. x | ck raganey (ate) Figure 5. lec ve Frequency Lead PRELIMINARY |intel. eacsosx. 000100. AG SPECIFICATIONS MAJOR CYCLE TIMINGS (READ CYCLE) Ty = OC to +70°C, Voo = SV 410%, ‘Values Jsymbol} Parameter socisexizs | eocteextz0 | eocrsextt2 [uni Frezox [Data in Hots (70) 3 3 3 8 looc196X1. GENERAL TING RESPONSES (Listed More Than Once) Frousy [Status Aotve Delay 3 [=] 3 [a] 3 [rcusn [Status Inactive Delay 3 [»| 3s [al 3 Fresav_[Aderooe Vad Daley 2 [|e |=] Frouax [Address Hott ° ° o Froxpy_[Data Vaid Delay 3 [| 3 als zi vox [Status Hold Te 10 10 10 ne FToaun [ALE Active Delay 2 2 2 [ns Fru. [ALE wiath Tan =| frac] [rac] [ne Fron [ALE inactive Delay 2 2 2 [ne : Fava [Address Vaid toAE Low [Focon to] [Font] [Foon a8] | oe Loading HTuax [Address How tiomALE [Toa —8| [Ton 10} [Towa 13) | ns] Equal inactive Losing HTavon [Address Vaid GockHigh| 0 e ° ts Frcuxz Address Float Dolay Toax |20| Tox [20] Tox |25| rs [reucev|CripSelectAcive Dewy | 3 | 20| 3 | 25| 3 _| 33 | ns FFoxosx|chip-SeletHoldtrom [Torx t0) [Toon 10) [Toronto [ns | Equal \Command inactive Loadiog Hronosx|chip-Selectinscwooey | 3 _[a| 3 _|z0| 3 | 0| re Hoxou. [DEN inactive to T/A Low | 0 ° ° ne | Equal Loaang Frevery [Contot Active Delay 3 |v 3 [zl 3 [sw Frovocx [BEN inactive Delay @ [7] 2 [22] 2 _|a7| ne Fronory|Contot Active Delay2 3 [zo|s |z|_3_[s7[ns FTouv [TOOK Vatariwatdeay | 3 |t7[ 3 |22| 3 _[s7| re | PRELIMINARY +37806 180XL/80C 188XL AC SPECIFICATIONS (continues) MAJOR CYCLE TIMINGS (READ CYCLE) (Continued) Ty = OC to 170%, Vox — BV 10% ‘All timings are measured at 1.5V and 60 pF loading on CLKOUT unioss otherwise noted, ‘ll output test condone are with G, = 50 pF: For AC tests, input Vj. = O.45V and Vin = 2.4V except at Xt where Vin = Voo ~ 0.6¥. intel. Values Test symbol) Parameter | socieexi2s | eocteexi20 | socieextt2 _|Unt| Taran man_[wox| wn [wex] mn [wax [socteext THaING RESPONSES (Read Cycie) Frame | Atraas Fat ° 3 ° 7 {FD Active Frew |RBActvo doy | 8 [aol 3 lal 3 | a7| ve Trurw [FOPuss wan [zc —16] [zi — 20] [eta ~ 25] _| ne rou [FOinecivedeey| 3 [aol 3 [a| 3 |a7| ne Fram [AD inecive — [Tocn— 14] [Ton] [tom] [om] Peal toALEHigh Loading Tray [AD inactvoio [Taa- #8] [Taa-18| |Taa-18| [oe] equal cae thn Leading 188 PRELIMINARY lintel 7 80C186XL/80C188XL AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (WRITE CYCLE) Ta = O'C to +70°C, Voo = BV 10% ‘Al timings are moasured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. ‘All outputtostconsitons are with G, = 50 pF. For AC Insts, Input Vj. = O.45V and Vy = 2.4V except at X1 whore Vin = Veo ~ 0.5¥. Values Isymbo! Parameter ‘ocisext2s | socrsext20 | e0ceextt2 [Unto "tion Min [Max] Min [Max) Min [Max| [a0 186XL GENERAL TIMING RESPONSES (Listed More Than Once) Frousy [Sts Active Deiny sla] 3 || 9 [os[ns [rouse [Status inactive Delay a jal 3 [2] 3 | 35|ns fToxav [Address Vala Dolev 3 _|e| 3 lal 3 [selns FToxax [Address Hold ° ° ° 6 FTcupy [Data Vaid Delay 2 jal e |a| 9 [s/n FTcxox_ [Status Hold Time 10 10 10 ne Fron [ALE Active Delay 20 20 | ne FTusus [ALE With Taa-t| [tant] [Tau 16| | ne [Tow [ALE inactive Delay 2 2 25 | ns TTavu [Address Valisto ALE Low |Toucn—10/ [Toon 10] |Tacw- 15] | ns | Equal Loacing Frusax AddressHoistromALE |Towa 10; [Towa 10] [Town 18| | ns) Equal nactve Loading [raven [Adéross Vaid to tock High | 0 ° ° ne FFowoox [Data Hoid Timo 2 3 3 ns [Tovery [Control Active Delay + a jo! 8 [| 3 [a7|ns [Toverx [Control inactive Delay a (v7) a [esl 3 [arlas Frevesy [Chip Select Active Delay 2 [| 2 |as| a [moe Frexosx|OripSelectHola rem — |Tacn—70| [Ton 10| |Taon—t0| | as | Equal |command inactive Loading [Toncsx|ChipSolectinactve dey | 3 _|17| 8 |@| 8 | s| ns FToxo, [DEN inactive DT/FiLow | 0 ° ° es | Equal Loading frouy [COGR Vatiaiwata Delay eae [er] vee oe 2 |e 9 EE | oa [o0c'196xl. TIMING RESPONSES (write Cycie) FTimawes [WA Pulse Wietn toa] (toa [eta — 25] [ns Fw |WRinactive to ALEHIGh |Toucn— 14 [Toc 14/ [Toon t4] | as | Equal _ Loading FTwnaox [Osta Hovd attr WF Ta -10) |tac~15| |taa-20) fas] equal Loading [Twioex| WF inactive to DEN inaotvel Teucn—10| [Tan] [Toronto] [ne] Equal Leading l PRELIMINARY 1-59socteextseocreext intel. AG SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (INTERRUPT ACKNOWLEDGE CYCLE) Ta = 90 lw +70°C, Yoo = SV #10% All inings are measured at 1.5V and 80 pF loading on CLKOUT unfess othorwiso noted. ‘All output test conditions are with G, = 0 pF. For AG tests, input Vi, = OSV and Vin = 2.4V excent at x1 whore Vin = Veo — 0.5V. Yee Jrmooi| Parameter | soorenaas | socteextan | ancreomti@ jum, 7 | win [Mex] wast wo ocx GENERAL Tm REQUIREMENTS (Usted Hor Tan Once). Few, [ow Sen oy . = = fo Fax [owe ne A) fl 3 3 a joc tex. GENERAL THING RESPONSES (Usted More Than Grom) hess stausAcwe Day 3 [a] 3 [so [S| Fes [Ss rato Dol 3 [a| 3 Tas 9 [a6 | feu naa veer aa sar 3 Tae Fave [pats vais Gat] 0 ol oT [re hee [wanes n ° of Fes [at Vaid Doay 3m] 3 [a] 3 [se Frese [Stats Hols Tie 70 o io] ne Tex [A Atv Doar » 2 Bre Hon. Weer Taal amet [ram ef Fst [As rte = B 7 fans [PdsoesvabsioALELow [foam Tol [Taaw= 0} ffacw =v) [ne] Ema Load Fax [ratesoraaoAE —TRoxe= iol fron} froma =} fw} ews etn tora Hea diss ty ——| “Tou 30 | foo [a0 | Soop Hevre|Cont Ave Ooty? [3 [| 9 [as] 9 Tarts Heverx|Conotinacteoaey | 3 [w7[ a Jas] aor be Hex JON neave woT/RTaw | 0 0 re} Ea Ee Hexerl Corie Ace Baar? | —a is ae Fes BER race Dalay 3 |e} sda a7 | |(Non-Write Cycles) Few [POOR Vetirwatsbeay | 3 [| epee pe 1-69 PRELIMINARY l