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PLL 100

This document provides information about PLL 100, including: 1. A block diagram and description of the main components: phase detector, low-pass filter, and voltage-controlled oscillator (VCO). 2. Expressions to determine the center frequency, lock range, and capture range of the PLL circuit. 3. An overview of how the PLL operates by comparing the VCO signal to the input/reference signal and providing feedback to modify the VCO frequency.

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Nguyen Thanh Binh
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85 views5 pages

PLL 100

This document provides information about PLL 100, including: 1. A block diagram and description of the main components: phase detector, low-pass filter, and voltage-controlled oscillator (VCO). 2. Expressions to determine the center frequency, lock range, and capture range of the PLL circuit. 3. An overview of how the PLL operates by comparing the VCO signal to the input/reference signal and providing feedback to modify the VCO frequency.

Uploaded by

Nguyen Thanh Binh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Name: Nguyen Thanh Binh

ID: 21161230

Group: 2

PLL 100 – PLL 02


PLL 100
1. Block Diagram

2. Function for each block


+ Phase detector: compares the input frequency Fin with the feedback frequency Fout.
+ The output voltage of a phase detector is a DC voltage.
+ Low-pass filter: remove high-frequency noise and produces a DC level, help in establing the dynamic
characteristics of the PLL circuit.
+ Voltage-Controlled Oscillator (VCO) frequency compares with inputs and adjusts until it is equal to the
input frequencies.
3. Expression of PLL
+ The center frequency of PLL is determined by the free-runing frequency of the VCO:
1,2
Fout = Hz
4∗R 1∗C 1
+ The lock range fL and capture range fc of the PLL:
8 Fout
FL = ± Hz
V
+ Where Fout = Free-running frequency of VCO(Hz)
V = (+V) - (-V) (Volts)
( )
1/ 2
Fr
Fc = ± 3 (C2 is farads)
2 π∗3,6∗10 ∗C 2
4. The operation of the PLL:
The underlying mechanism of a PLL operates based on the phase difference between two signals. It
detects this difference, and provides a feedback mechanism to modify the voltage-controlled oscillator
frequency. The PLL compares the voltage-controlled oscillator signal with the input/reference signal.
5. Results of Experiments:
6. Summary of the Datasheet of PLL 100
- Datasheet of NE/SE 565:+ Pin diagram:

Diagram of the 565 PLL. The device is available


as a 14-pin DIP package and as 10-pin metal can
package. The important electrical characteristics
of the 565 PLL are:

Operating frequency range: 0.001 Hz to 500 kHz

Operating voltage range: ±6 to 12 V

Input level required for tracking: 10 mV rms


minimum to 3 V peak-to-peak maximum

Input impedance: 10 kn typically

Output sink current: 1 mA, typically

Output source current: 10 mA, typically

Drift in VCO center frequency (four) with


temperature: 300 ppm/°C, typically

Drift in VCO center frequency with supply


voltage: 1.5%/V maximum Triangle wave
amplitude: typically 2.4 V pp at ±6 V (see block
diagram, pin 9)Square wave amplitude: typically
5.4 V pp at ±6 V (see block diagram, pin 4)
Bandwidth adjustment range: <+1 to> ±60%
7. Function of all the main components of PLL 100

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