Iphone 12 Pro Max Schematic (Phonelumi - Com)

8 7 6 5 4 3 2 1
D D
69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 112 115 118 120 123 126 129 132 134 136 138 140 142 144 146 158 159
C7545_I
C7548_I
C7547_I
150
67 119 122 125 128 131
TP7507_S 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 135 137 139 141 143 145
68 117 121 124 127 130 133 160
XW11131
XW11130
XW11132
XW11102
151
C11134
C11131
C11133
C11130
C11102
C11132
R11103
149
C10813
R10813
PP221_R PP211_R 66
C7546_I
65 152 161
PP12802
C380_W C302_W
64 C361_W R363_W C362_W C301_W R301_W
R319_R
C334_R
C389_W
FL302_R
C304_R
C305_W
153
C388_W
TP12621 TP12610 63 162
C317_R
FL10141 FL10143
R309_R
C314_R
62
JUAT1 J10800 J11100
PP12810
C10443
C6593
C306_W
C324_R
154
61 R316_R
BPF_U_W 163
R365_W
TP12652
60
U6500 C315_R U_5G_U_W 155
XW11100
164
C309_W
R306_R
R6520
C311_R
59
C10441
FLBPF8_R 156
QPLX8_E
XW11101
C333_R
C387_W
157
58
C304_W
C4004_E
J10100
PP212_R
L6520 165
FL10800
C10810
C10800
C10801
C10816
C10812
C10802
PP219_W FD0813
C10817
R10811
C10811
C10815
C10814
R10810
XW11122
XW11153
XW11123
XW11120
C11101
C11153
C11123
C11122
C11121
C11120
C11100
57 C301_R C323_R R318_R
C6520
C10104
TP7507_I
R
TP12650 PP214_R
3_
FL10142 C308_W 166
21
XW12000 C12000
PP
C12001 56
FL301_R
XW310_W C321_W C382_W R311_W
C11025 XW11012 XW11013
PP208_R PP203_R
C6505 U_ROSE_R C303_R C332_R FD0803 167
R4004_E
C11024
C10106 C6506
XW11000
C10442 TP12651 C323_W C322_W C381_W C379_W
C11023 55 168
XW11010
FL11014
C11039
C11031
R11024
C11001
C10722
C10723
C10720
C10721
R200_R
C11034
DZ11014
DZ11012
DZ11013
DZ11010
C1700
R308_R
C313_R
R317_R
TP12655 54
C10903
C10904
C10905
C10902
C10900
C10901
C10103
PP206_R PP209_R
C10105 SB0801
R4003_E
R11023
R4401 C7550_I 169
C7514_I
C7512_I
C7515_I
C207_R
PP12800
R4411 R4414
U1700
PP209_W
36 38 40 42 44 46 48 50 52
C6591 C6507 C312_R C322_R

170
R210_R
FL10140 C7510_I
R307_R
53
35
C4408 C4404
_S
R4001_E
C4001_E
C4003_E
C4002_E
PP7511_S
171
12
FD0800 C7551_I
R4004_E
L4002_E
75
FD0810
PP
39 41 43 45 47 49 51
C7567_I FL300_R C7507_I
C7568_I
PP218_W C10440
TP7508_I 37 172
R4900
C206_R
C7513_I
C5350
C5330
C5393
C5390
C5380
C5370
C5360
C5340
C4409 C4401
R5400
C302_R
R325_R
34 173
R7508_I
C7566_I
J11000 J10700 J10900
C4005_E
C5310
R1620
R315_R
C11041
C300_R
33 C7503_I R7509_I 174
C7543_I
C7542_I
C7541_I
C5400
PP7542_S PP7541_S
C7565_I XW11004
FLHPF6_R
L7500_I
32 C4406 C4403 C7519_I 175
C10503
C11040
C305_R
8
XW12657
C5395
65
C6256 U11040
L7501_I
XW12658
C5300
C11004
12
PP7580_I C10502
C5320
TP
C7539_I
TP12657 TP12620 TP12611 31 R305_R
176
R10142
R10143
R10141
PP200_R C204_R C203_R C202_R
C5302
C11021 FL10501 C205_R C201_R C200_R
C5392 C4407 C4402
C6250
R10140 R2963 PP7581_I C11033 C10545 30 C7506_I 177
R5511 R5521 C310_R R11040
C2945
C2926
PP12894 C7524_I C7540_I
7
C6255
89
PP12898 PP128A4
C10912
C10914
R10914
C10913
C10910
C10501
C10911
12
C4433
PP12870
C4434
29 178
C10704
PP
C2915
C2912
FL10700
C10542
C10701
C10700
C10715
C10714
C10712
C10710
R10710
C10702
C10711
PP7540_I
R5520
C6252
C6253
C5303 R5510 PP12832
C8106
C2963
C5305
C7526_I
C2924 C10716 L6250 C7530_I
FL11015
R11030
C10703
C4464
C4461
C4429
C4465
C4470
C10550
R2901 C2958 C2910 28
C4436 C4410 179
C4423
C2936 C2938 R11039 C11022 R11021 R11020 C11020 DZ11015 C11032 C11003 C11038 C11037 C11002 C11030 C10541
R8100
U5300 C5311
R4463
R4485
XW6200 C7521_I
C6260
R10550 27 180
C2951
SH0802 C10540
C8107 C8122
FL10200
C5391 PP12893
C7525_I
C8109
C2959
C4411
C10551 26 181
XW4410
R10540
C8108
C5304
C5301
Q4400
C7500_I
C5950 L5300
PP7543_S
C7522_I
C7001
C5397
C10552 25 C6270 182
C4424
XW8100
C7000 C10506
XW5300
C7011
C7012
C10500
C8121
C6251
C6254
C7534_I 183
C10537 24 R6250
C2950
C2921 C10200 C10203
U6250
R13801
C8102
NFC_F
FL10500
U8100
XW6250
U5950
C8125
PP12809
23 C7509_I 184
R6251
XW6251
C10536
C7022 C10219 C4422 R2424
XR7510_I
C7096
22 C7536_I 185
C5922
C10544
R5506
R5505
R5541
R5540
R5402
R5403
R5401
R5530
R5531
XW4413
C8120
C10211
C7098
PP128A3
C10204
186
C6272
C5650
C5660
XW4450
21
C2916
C7535_I
C2935
C5951 C10521 C10554
C6271 C8124
C4427 R4651 C4654 PP12899
U2420
C6249
C4655
C10212
C2420
C5693
C5690
C5680
C5670
FL10201 20 187
C7532_I
L7000
XW12655
C10543
L7001
FL7500_I
C10520 C8123
J10500
R4450
C5640 U4400 188
C8100
U7000 C10202 19 C7528_I
R5710
C2954
C10534
C8103
C7092
C7091
C4421
PP12860
J10200 18 R2423 189
R2422
C5923
C5920
C10217 C10209
R4461
C7508_I
C5630 R5851
U4600
26
C10523 C10535
C5695
PP12859
28
C4466
190
C4652
U5920 R2421
1
C2931
C7527_I C7538_I C7537_I
C10231
PP
C7502_I
C8130 C8140
R2425
B6
R10200 C10210
28
C2925
C7511_I
C8101
C8104
R5850
C7517_I
1
PP128B7 PP12824
PP
C10522 16 17 191
R2420
C5692 C4426
C5610
C4639
C4653
C10218 C7904 C7902
C7093
C7094
C10531
PP12896 192
C7920
C2943
PP12892
R4451
C2956
C5921 R2472
4
8B
R2426
PP128B3
C7005 C7010 C10207

C10232 L7502_I
12
C10215 15
C5930
PP
C5605
193
C5700
C7505_I
C10525 C10530 PP128B8
C7903 R2475
R4413
R4412
R2904
C2923 C5902
C10216 C10208
U5600 194
C5903
C5611
C4631
C10524 13 14 C7905
PP128A2
C2470 R2473
C2957
R7810
XW4411
195
C10230
C10206 C5691
C2942 R7569_I
XW7000
C9491 C10532 C4428
C5600
PP12804
C7020 C5604 PP12805
C2920
C7801
R2476
C7021
196
C7090
C4441
C4440
C4467
C4462
C7097 R7316 L6400 C4438 C4437
C7910
C5697
R7315
XW7317
C2905
12
U5900 U2470
C6401
C4435
C5901
C10533
FL2923
C2900 C7095 U5930

C10504
R7801 C4463 197
L4650
PP12823
PP12867
R7321 11
C10505
C2902 198
C2903
PP12825
R7800
C10511
R10230
C2922 U9400 C9490 U7320 10 C4468
96
PP12895
28
C4651
C4432
1
199
L5600 Y1000
C2907
PP
C5900
C7800
R4400
R5861 R2474
R5930
U2900 U7330 U7310 U7340 C5931
XW5601
9 C6402
PP128B2 R5720 R7301
C2940 200
R7304
R7303
C10512 C7911 R2461 R2460
C5601
C2908
C6400
R5860 R2470
U7800
C5602
R7821
C7820
8 C6403
C1970
C9400 C7303 C7304 C6428
XW12656
201
C2904
C10513 R2471 R2450 R1410 R1013
C7930
C2946 7
C6429
C6422
PP12854 PP12849 R1010 R1121 R1131 R1101 R1130 R1100 202
C2919
R1970
PP12850
R2451 C1940
C2944
U6400
6 C6423
XW12654
C5603 203
C6430 PP12855 PP12852
R1011 R2310 R2311 R0700
C7821
FD0814
5
C2948
PP12817
C1901
C1948
C2090
C2080
C2088
C1922
C1946
C2901
C2927
XW1940
C6420
R10670
204
1
FL10660
85
PP12853
12
C1921
R0721
R0722
R0720
R0723
R1403
R1402
R1001
R1260
R1240
R1400
R0701
R2340
R2341
C1903
C1021
C1020
R1021
C2098
R0802
R0807
C2096
FL1950
4
PP
TP12656 TP12654 TP7508_S
XW10641
XW10640
C1904 C2091 C2073 C2083
XW10620
C10600
C10601
C10620
C10650
C10640
C10671
C10670
PP12848
TP12688 C10661 205
PP12866 TP12653 PP12803 TP12687 605
XW7902
C2917
C10660 FD0804
U7300 C6421
C2010
C2955 PP12815 604
206
PP12811
C12100 3
C2941
XW12100 603
C6431
CP1 CN1 CM1 CL1 CK1 CJ1 CH1 CF1 CD1 CB1 CY1 BV1 BT1 BP1 BM1 BK1 BJ1 BG1 BE1 BC1 BA1 AW1 AU1 AR1 AN1 AL1 AJ1 AG1 AF1 AD1 AB1 Y1 V1 T1 P1 M1 K1 H1 G1 F1 F1 D1 C1 B1 A1 207
2 C6410 C6412
C2911
C7302
C6411
C7931
C2947
C2960
602 PP12836 208
R2900 CP2 CM2 CL2 CK2 CJ2 CH2 CF2 CD2 CB2 CY2 BV2 BT2 BP2 BM2 BK2 BJ2 BG2 BE2 BC2 BA2 AW2 AU2 AR2 AN2 AL2 AJ2 AG2 AF2 AD2 AB2 Y2 V2 T2 P2 M2 K2 H2 G2 F2 F2 D2 C2 A2
1
209
C2011
C7928
PP12834 CP3 CN3 CM3 CL3 CK3 CJ3 CH3 CF3 CD3 CB3 CY3 BV3 BT3 BP3 BM3 BK3 BJ3 BG3 BE3 BC3 BA3 AW3 AU3 AR3 AN3 AL3 AJ3 AG3 AF3 AD3 AB3 Y3 V3 T3 P3 M3 K3 H3 G3 F3 E3 D3 C3 B3 A3
PP12876
601
C2929 C7915 C7926 C7927
FL2925
J10600
210
C7901 C7932
CP4 CN4 CM4 CL4 CK4 CJ4 CH4 CF4 CD4 CB4 CY4 BV4 BT4 BP4 BM4 BK4 BJ4 BG4 BE4 BC4 BA4 AW4 AU4 AR4 AN4 AL4 AJ4 AG4 AF4 AD4 AB4 Y4 V4 T4 P4 M4 K4 H4 G4 F4 E4 D4 C4 B4 A4
C7301
C7300
PP12872
C7925
C
211
C
J_INT_BOT
PP128B9 PP12835
600
PP12871
SB0802 JUAT2 R0712

CP5 CN5 CM5 CL5 CK5 F5 E5 D5 C5 B5 A5
C2085
C2913
C2949
212
R0713
213
599
PP12808 CP7 CM7 CL7 CK7 F7 E7
597 598
CN7 D7 C7 B7 A7
591
C2952 589 587 585 583 581 579 577 575 573 571 569 567 565 563 561 559 557 555 553 551 549
XW1000
CG8 CE8 BU8 BR8 BN8 BL8 BH8 BF8 BD8 BB8 AY8 AV8 AT8 AP8 AM8 AK8 AH8 AE8 AC8 AA8 W8 L8 J8
547 215
XW10651
XW10650
214
C10693
C10690
C10610
R10610
C10692
C10695
C10651
C10630
C10681
C10682
C10691
PP12889
C1907
PP12806
FL10651
C2939
CG10 CE10 BU10 BR10 BN10 BL10 BH10 BF10 BD10 BB10 AY10 AV10 AT10 AP10 AM10 AK10 AH10 AE10 AC10 AA10 W10 L10
FD0811 217
PP12837
596 595 594 593 592 590 588 586 584 582 580 578 576 574 572 570 568 566 564 562 560 558 556 554 552 550 548
C2937
PP128B5 CP11 CN11 CM11 CL11 CK11 F11 E11 D11 C11 B11 A11
PP128A0
545 216
546 CG12 CE12 CC12 CA12 BW12 BU12 BR12 BN12 BL12 BH12 BF12 BD12 BB12 AY12 AV12 AT12 AP12 AM12 AK12 AH12 AE12 AC12 AA12 W12 U12 R12 N12 L12 J12
C10694 C10611 XW10652 XW10630 FL10680 CP13 CN13 CM13 CL13 CK13 F13 E13 D13 C13 B13 A13
C1102
R0803
C2953
CG14 CE14 CC14 CA14 BW14 BU14 BR14 BN14 BL14 BH14 BF14 BD14 BB14 AY14 AV14 AT14 AP14 AM14 AK14 AH14 AE14 AC14 AA14 W14 U14 R14 N14 L14 J14 218
FD0801 PP12883
C1103
C2934
544
219
PP12884 CG16 CE16 CC16 CA16 BW16 BU16 BR16 BN16 BL16 BH16 BF16 BD16 BB16 AY16 AV16 AT16 AP16 AM16 AK16 AH16 AE16 AC16 AA16 W16 U16 R16 N16 L16
XW3380
543
C2700
R0804
220
C2701
CP19 CN19 CM19 CL19 CK19 CG18 CE18 CC18 CA18 BW18 BU18 BR18 BN18 BL18 BH18 BF18 BD18 BB18 AY18 AV18 AT18 AP18 AM18 AK18 AH18 AE18 AC18 AA18 W18 U18 R18 N18 L18 J18 F19 E19 D19 C19 B19 A19
542
221
541 CP21 CN21 CM21 CL21 CK21 CG20 CE20 CC20 CA20 BW20 BU20 BR20 BN20 BL20 BH20 BF20 BD20 BB20 AY20 AV20 AT20 AP20 AM20 AK20 AH20 AE20 AC20 AA20 W20 U20 R20 N20 L20 J20 F21 E21 D21 C21 B21 A21
C2711
2
8C
PP128C0
R0800
222
C1995 C1920
C2001 C1936
12
R1960
C1964
PP
C9022
C1862 C1872 C1891 C1893 C1873 C2032 C2030 C4200
3
C2710
8C
PP128A1 PP128C1
540 CP22 CN22 CM22 CL22 CK22 CG23 CE23 CC23 CA23 BW23 BU23 BR23 BN23 BL23 BH23 BF23 BD23 BB23 AY23 AV23 AT23 AP23 AM23 AK23 AH23 AE23 AC23 AA23 W23 U23 R23 N23 L23 J23 F22 E22 D22 C22 B22 A22
12
223
PP
C9000 C9021 C9010 C1955 539 C24 B24

C1112
C1935
C1910
CP24 CN24 CM24 CL24 CK24 F24 E24 D24 A24

CG25 CE25 CC25 CA25 BW25 BU25 BR25 BN25 BL25 BH25 BF25 BD25 BB25 AY25 AV25 AT25 AP25 AM25 AK25 AH25 AE25 AC25 AA25 W25 U25 R25 N25 L25 J25 224
C1832
C1200
C1833
C1830 538 C1113

C1963
225
C1874 C1895 C1892 C2025 C2024 C2033
CG27 CE27 CC27 CA27 BW27 BU27 BR27 BN27 BL27 BH27 BF27 BD27 BB27 AY27 AV27 AT27 AP27 AM27 AK27 AH27 AE27 AC27 AA27 W27 U27 R27 N27 L27 J27
C4201 537 CP28 CN28 CM28 CL28 CK28 F28 E28 D28 C28 B28 A28
R1660 226
C1950
C2020
C2052 C1831
R1200
CG29 CE29 CC29 CA29 BW29 BU29 BR29 BN29 BL29 BH29 BF29 AV29 AT29 AP29 AM29 AK29 AH29 AE29 AC29 AA29 W29 U29 R29 N29 L29 J29
536
C1122
XW3350
CP30 CN30 CM30 CL30 CK30 F30 E30 D30 C30 B30 A30 227
1
PP12887
88
PP12882
C1947
12
XW4200
PP
C1900 C2050
C1863 C1808 C1894 C2026 PP12821 535
R2022
C1861 U1000 C1123 228
R1961
XW3310
XW1902
C1860 C1809
C1210
534
U9000 R2021
0
229
88
PP12879
R0808
R2391
C4210
12
PP
U4200
C4290
533
C1926
CG35 CE35 CC35 CA35 BW35 BU35 BR35 BN35 BL35 BH35 BF35 AV35 AT35 AP35 AM35 AK35 AH35 AE35 AC35 R35 N35 L35 J35
R9022 230
C1938
C4202
XW3410
XW1930
C1866
R1140
C1140
C1864
C1834
C3311
C3402 532
R1210
R9021
C1806 231
CG37 CE37 CC37 CA37 BW37 BU37 BR37 BN37 BL37 BH37 BF37 BD37 BB37 AY37 AV37 AT37 AP37 AM37 AK37 AH37 AE37 AC37 R37 N37 L37 J37
R2390
C1923 531
R9020 C1804 CG39 CE39 CC39 CA39 BW39 BU39 BR39 BN39 BL39 BH39 BF39 BD39 BB39 AY39 AV39 AT39 AP39 AM39 AK39 AH39 AE39 AC39 R39 N39 L39 J39 232
XW3300
C9040
R1603
R1610
C1928
C1803
C1802
530
C1927
C1810 C3301 233
C1918
C2000 CP42 CN42 CM42 CL42 CK42 CG41 CE41 CC41 BR41 BN41 BL41 AT41 AP41 AM41 AK41 AH41 AE41 AC41 R41 N41 L41 J41 F42 E42 D42 C42 B42 A42
C9134
C1941 C1805 529
234
C9001 C9020 C9030 C4203
XW3370
R9000 PP12838
C1807
CP43 CN43 CM43 CL43 CK43 CG44 CE44 CC44 BR44 BN44 BL44 AT44 AP44 AM44 AK44 AH44 AE44 AC44 AA44 W44 U44 R44 N44 L44 J44 F43 E43 D43 C43 B43 A43
528
R1606
R1607
PP12868
235
C1917
C1916
R3300
L4200
CG46 CE46 CC46 BR46 BN46 BL46 AT46 AP46 AM46 AK46 AH46 AE46 AC46 AA46 W46 U46 R46 N46 L46 J46
527
C9133
C9130
C9132
C1812
236
C1811
XW3301
C4204
526 CG48 CE48 CC48 BR48 BN48 BL48 AT48 AP48 AM48 AK48 AH48 AE48 AC48 AA48 W48 U48 R48 N48 L48 J48
R1608
R1622
237
C1801
C1932
525
238
C9115
CG50 CE50 CC50 CA50 BW50 BU50 BR50 BN50 BL50 AT50 AP50 AM50 AK50 AH50 AE50 AC50 AA50 W50 U50 R50 N50 L50 J50
C2087 C1906 C1999 C1996 524 CP51 CN51 CM51 CL51 CK51 F51 E51 D51 C51 B51 A51
C2086
239
C1924
R1621
C9103
CG52 CE52 CC52 CA52 BW52 BU52 BR52 BN52 BL52 AT52 AP52 AM52 AK52 AH52 AE52 AC52 AA52 W52 U52 R52 N52 L52 J52
C1945
C1931
C9104
523 CP53 CN53 CM53 CL53 CK53 F53 E53 D53 C53 B53 A53
240
XW1901
C8302 C8301
R9115
C8308
C8307
L9110
C1905
CG54 CE54 CC54 BR54 BN54 BL54 BH54 BF54 BD54 BB54 AY54 AV54 AT54 AP54 AM54 AK54 AH54 AE54 AC54 R54 N54 L54 J54
L9120
C8022
C8020
C8021
C8001
C8004
522 CP55 CN55 CM55 CL55 CK55 F55 E55 D55 C55 B55 A55
241
R0801
C9120
C9125
R9131
R9101
CG56 CE56 CC56 BR56 BN56 BL56 BH56 BF56 BD56 BB56 AY56 AV56 AT56 AP56 AM56 AK56 AH56 AE56 AC56 R56 N56 L56 J56
521
C9193
R1300
PP9101
242
C9100 XW3400
R0809
520
C9111
CP58 CN58 CM58 CL58 CK58 F58 E58 D58 C58 B58 A58 243
C8330
R2440
R2441
519
244
R1250
C8023 C8024
PP12818
C8006 C8009 C8025 528
XW3320
245
PP12807 C8003
R1650
R1002
517
246
XW8000
R0806
PP7515_S
U8300
6
PP9100
88
PP12888 PP12885 PP12856 516

C9192
R8310
12
C1909
247
PP
C8040
U9100 R0810
C8340
CP62 CM62 CL62 CK62 CJ62 CH62 CF62 CD62 CB62 CY62 BV62 BT62 BP62 BM62 BK62 BJ62 BG62 BE62 BC62 BA62 AW62 AU62 AR62 AN62 AL62 AJ62 AG62 AF62 AD62 AB62 Y62 V62 T62 P62 M62 K62 H62 G62 G62 F62 D62 C62 A62 PP12863
515
248
XW0711
C9195
R0805
PP7516_S 514 CP63 CN63 CM63 CL63 CK63 CJ63 CH63 CF63 CD63 CB63 CY63 BV63 BT63 BP63 BM63 BK63 BJ63 BG63 BE63 BC63 BA63 AW63 AU63 AR63 AN63 AL63 AJ63 AG63 AF63 AD63 AB63 Y63 V63 T63 P63 M63 K63 H63 G63 G63 F63 D63 C63 B63 A63 C2099
249
R8311
513
U8000 C2097 C1942 PP12873
R1012 C1908 R8301 R8300 R1015 R1014 R4910 C1902 R1601 R2431 R2430
250
C2081 C2092 C1937 C1997 C1998 C2082 C2093
XW8300
PP128A7
512
251
C8303
C9110
L9130 L9100 C8324 C8306 511

C8309
C8030
C8325 252
C9112
510
C1933
253
C3525 C3570 C3302 C3540 C3411 C3412 C3371 C3312
C3300
C3404
C3370
C3310
C9101
C9194
R9121
R9120
C9106
C3545
C3546
C9117
C8323
509
C8300
254
C8304
C8322
C8321
C8320
R9116 PP12822
PP128A5
508
255
C3410
R8050
C8007
C8008
C9116
C3535
507
C9105 C9102 C8002 C8000 256
C3406
R9122 506
PP128A9 257
XW12601
505 PP12874
258
SH0801 L3301 L3300 L3302 L3410 L3370 L3311
XW12600
C3408
C3580
PP12875 PP12847
504
XW3340
L3411 259
XW3430
SH0800 503 PP12820 PP12816

260
502
L3310 PP12819
C3555
TP12615 261
R9102
C4001 C4012 501
C4041
C4003
C4004
C4025
C4040
C4062 262
C4092
R9100 C3380 C9564 C3640 C3462

C3504 C3490 C3491 C3492
PP12890
500
C3603 R3603 263
C3382
C3407
C3405
XW12674
PP12891
499 497
C3493
PP128A8
C9131
264
C3481 C3459 C3457 C3463 C3458 C3460 C3470 C3456
C9122 C9123 L3380
SB0804 265
C3320
L3321
C3483
C3321
495
C4042 C3381 266
L4001
C3464
C4045 496 267
C3671
C1707_E
C3530
XW1701_E
493 268
C9121 XW12672
C3350
PP12812
C3461
C4090
494 269
L3350 L3320
C1711_E
C3455
C1706_E C1703_E 491 270
C3422
L1702_E TP12630
492 C3351 271
U4000
C3465
XW4900
L1701_E
R1712_E
XW4910
489 272
C3469
C3354
C4060
TP12631 490 273
C3454
C3342
C4091
274
C1710_E
487
C3423
C3452
C1715_E
L3420
R1713_E
C3341
U_QET1_E C4061 L3340
XW3646
488 275
U3300
C3466
276
C1708_E
C3343
C3471
PP12858
C4043
485
C3421 277
L4000
C1705_E
PP12828
XW3650
486
C3420 C3390 278
C3451
C3340 C3401
C3450
XW3647
279
484
B B
C9124
R3670
R4100
C3403
R3671
280
L3400
C3392
C4007 C4024 DZ10004 483
C1709_E
XW4920
L3390
XW1702_E
C3468
C3670
XW4100
C3472
281
C4005
C4010
C3566
C4011
C1704_E
XW4101
C4008 C4023 C10004 482

L1703_E C4006 C4022 481
PP12827
282
C10002
C3520
J10000
C3467
C1701_E
C3673
283
C3431
C10001 480
C3506 C4044
XW3600 284
L3401
C3432
479
XW3420
C3391
XW3360
C9551 285
C3480
L3330
C3453
XW3390 478
R4920 286
PP7508_S
PP7533_S
477
XW3580
C3482 C3508 C3651 C3652 R3661 PP12843 287

R3600
C3505
C9552
DZ10003
C3521
C3507
C3522
476
C3509
XW10000
XW10001
PP12844 288
C3430
C10003 C3330
PP12833 474 L9550 C3364 289
C3334
C3333
XW11707 475
L3430
C9550
L3360 C9310 C3515 C3523
C11790
XW3330
XW11790
C3590
XW11701 R12312 C3332 290
473
Y3600 291
XW11724 R12311 472 C3699 292
C3610
C11791 C11711 R12310
C3331
PP12840
C11796
471
4
R11796
86
87
PP12877 PP12865
PP12839
R3620 293
12
12
C7401
C3360
PP
PP
SB0803 C11797 C12313 R12313
C9395
C11701 470 PP12830
C9561
C9562
U9500 C7400 R3610 294
C3363
C3362
PP12829
PP12861
C3361
C11710 C11707 469 PP12813
PP12842 L9300 C3510 295
C9602
U9300
PP12846 PP12862
R11710 C11709 C11700 468
C9391
296
L9301
U9600
PP12841
PP12845
C11706 R11700 467 C9563 297
C12310
PP12857
C9601
R12320
PP128A6
U7400
C9603
466
C9390
PP12831
XW11706 C11724 PP12814
C9600 298
U8400
C9910
R9910
R9911
C9911
R9301
C11702 C12320 465
C8400 PP12801
301
299
C12311
XW11804
C12301 464 C9330 C9301
300
C11705
463
J_SIM_E
C11704
XW11805 R12321 302
303
C12312
U9910 C12321
462
305
461 336 333 330 328 326 324 322 319 316 313 310 307
XW11803 XW11808 C12322 304
C2323
460 338 335 332 321 318 315 312 309 306
340
R12322
C9931 R9950 R9930 XW11802 XW11809 337 334 331 329 327 325 323 320 317 314 311 308 339
459
341
C12300
458
342
R12323
PP208_W U9930 U9920 XW11801 XW11806
457
J11800 C2209_E
343
R2206_E
R2203_E
XW11807
456
R2003_E
XW11800 344
455 R2208_E
XW9940 C9921 XW9920 XW11817 345
C11819 454 C3601_E
DPLX7_E
C11817 346
R2009_E
XW11814 XW11822 C2207_E
C11822 453 R3601_E
347
C11818 C11823
XR2207_E
452
C11882 C3603_E 348
XW11823
451
TP12671 TP12675 349
C2208_E
XW11882
C3605_E
R3602_E
C2001_E
C11820
C2212_E
450
R3603_E R3604_E L3602_E 350
XW11880 C11880
PAUHBL_E
TP12616 TP12613 XW11820
449
C3602_E 351
C2006_E
FL11801 C11883 C11850
448 C2009_E
352
TP12672 TP12670
C3802_E
R3802_E
C11881 C11814 447
C2211_E PA_LB_E 353
XW11850
DPLX9_E
C2007_E
FL11881 C11821 446
TP12641 TP12640 354
C3805_E
R11818 C11815
J_SIM_E 445 C2004_E
355
TP12614 TP12639 C3801_E
C11871 C11816 444 C2202_E 356
C2005_E
C3804_E
R3801_E
C11813 443
R2204_E 357
TP12673 TP12674 R11870
C11870
C3006_E
R3002_E
R3803_E
R3804_E
R2209_E
C11803 442
R2205_E 358
C2002_E
C3803_E
XW11860 441
C2210_E
XW11703
C325_W 359
L3503_E C314_W
440 L3801_E
TP12637 TP12636 TP12612 C11860 360
PP221_W C11275 C324_W
R3503_E
C312_W
439 C3005_E C3009_E 363
C11282
BPF_L_W
FL11200
XW11300
XW11302
FL11230
R11290
R3005_E
PP220_W C311_W
C11286
365
C318_W
C11272
C310_W L3502_E
438
XW11250 361
XW11202
XW11260
C11271
366
XW11213
TP12638 TP12635 TP12617 362

437 R312_W
R313_W
364
C11300
C11302
C11230
C11207
C11213
C11253
C11250
R11210
C11210
C11242
C11241
C11200
C2010_E R2008_E R2002_E R2005_E
L2002_E
C3008_E
436 L3001_E
DPLX1_E
FD0802 R11276 C11283 R11283 R11282 C11264 C11260 C11294
XR2006_E XW364_W L2001_E 373
374
R2007_E
435
C11296 C11291 C11290 R3004_E C313_W
372
434 CPLR_L_E C333_W
R3003_E
C3501_E 375
U_5G_L_W
C383_W
433 C316_W 367
TPLX3_E
R3501_E
C3523_E
376
432 FD0805
C319_W
C3007_E
J11200 C315_W
R3522_E
431 368
L3501_E
377
C3504_E
C3502_E
C3503_E
R3502_E
430
C3001_E C3003_E C3002_E C3004_E C3522_E R373_W C371_W C376_W FD0815
429
369
378
SB0805 428
427
409 405 370
423 421 419 417 415 413 411 403 401 399 397 395 393 391 389 387 385 383 381
R11275 R11281
XW11203
426
XW11211
XW11262
C11243
C11240
C11212
C11270
C11285
C11301
C11263
C11293
C11208
C11206
C11254
C11252
C11211
XR11252
C11273
C11287
C11292
C11297
C11295
407 379 371

425
R11291
C11274
C11280
R11280
424 422 420 418 416 414 412 410 408 406 404 402 400 398 396 394 392 390 388 386 384 382 380
FD0812 XW11301 C11262
A iPhone 12 Pro Max SYNC_DATE=18/10/2021 A

DRAWING TITLE
D54AP CRB MLB LAYOUT

PART NUMBER SIZE
820-01940 D
www.itesla.solutions REVISION
https://paypal.me/Torsioniforums/
A.1.1
NOTICE OF PROPRIETARY PROPERTY: AUTHOR
THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF ITESLA SOLUTIONS.
Filip Pusca
THE POSESSOR AGREES TO THE FOLLOWING: ASSEMBLY
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
A/B
PAGE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 0/1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
159 158 146 144 142 140 138 136 134 132 129 126 123 120 118 115 112 111 109 107 105 103 101 99 97 95 93 91 89 87 85 83 81 79 77 75 73 71 69
150
131 128 125 122 119 67
FD0911 FD0913
145 143 141 139 137 135 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70
160 151 133 130 127 124 121 117 68 FD0905
149
66
161 152 65
R3201_E L3202_E C3202_E C3107_E R3101_E R0966 R0912 R0913 R0914 R0915 R0919 R0918 R0916 R0917 R0920 R0921 R0922 R0923 R0925 64
C2502_E
R3103_E
L3101_E
C5901_E C5902_E
R0926
L3102_E
162 153 63
J_SMYR_E
L3201_E
FD0914
R0962
R0967
L2501_E R2505_E
62
C2501_E
R3104_E
C3110_E
TPLX2_E
R0927
L1_LNA_E
C3701_E
163 154
61
C3201_E
L2500_E R2504_E
R0968
60
155
C2503_E
164
DSM_LB_E
R0928
59
R3701_E
R0958
156
157
R3105_E
58
U_BG1_E
R0969
165
FD0904 C3101_E L3103_E C3108_E C3109_E
C2504_E
R0929
57
C3703_E
R2501_E
166 R3106_E
CPLR_U_E R13800
56 PP214_W
R0970
167
SH0901
XR2502_E
R0930
168 55
54
XR2905_E
R2503_E
C2702_E C2721_E C2722_E
C2701_E
169
R0971
C3105_E
C2902_E C2901_E C2903_E C2904_E 52
R0931
50 48 46 44 42 40 38 36
170
C3106_E C3102_E C3103_E 53 35
U_TAN_E
C3104_E
171
R2904_E
R2701_E
R0904
51 49 47 45 43 41 39
C203_W
R0935
172 37
C482_W
C480_W
C481_W
C479_W
R201_W C204_W
173
R0959
34
R2901_E
R2703_E
C408_W
R0905
FL_ISG_U_W
174 33
R0934
_E
26
PP4627_E
MIMO_U_E
46
PP
175 C407_W 32
C406_W
R0942
R2903_E
R2702_E
R5040
176 31
R0936
C404_W
C405_W
177 PP242_W
DSMUHB_E
30
PP5910_E
R0943
R2902_E
R2704_E
Y7500_S
R0901
PP5901_E
PP235_W
178 29
C466_W
PP5903_E
C201_W R233_W PP5906_E PP233_W
U_2G_U_W
R0932
PP5909_E PP5908_E
179 PP5904_E
C2614_E
28 PP5907_E PP5905_E
PP5902_E
PP234_W
R0906
C2704_E
180 27
R0956 R0965 R0948 R0947
PP251_W
C202_W C231_W R238_W C244_W C230_W R237_W C243_W
R463_W
181 C7529_S C7531_S
R0933
26
182 25 FD0921
C2723_E
PP250_W
XR2705_E
R0944
C461_W
PP4645_E
183 24
R0914 R0945 R0940 R0939 R0938 R0937 R0902 R0946 R0955 R0949 R0951 R0954 R0953 R0950 R0952
184 23 PP4610_E
C2703_E
C2706_E
PP216_W PP7502_S PP4661_E
C491_W
C270_W
PP4691_E
185 C3903_E R3901_E PP4669_E
L3902_E
C7512_S
C463_W
22
R461_W
FL5921_E TP12615
186 C7507_S
C2708_E
C2709_E
R2708_E
R2709_E
21
C462_W
C7550_S
C7510_S
C2612_E
C7514_S
R2607_E
L2602_E
C2608_E
L7500_S
C232_W
187
R2606_E
L2601_E
20
R7508_S
C254_W
C233_W
QPLX4_E
188 C257_W C252_W
C7547_S
C7548_S
C7558_S
C7546_S
R3904_E R3905_E 19
R3903_E
189
C3904_E
FD0902 R7509_S T7500_S 18
C3901_E
C5912_E
C5922_E
C5921_E
C7513_S
C7551_S
R3902_E
PP7580_S
190
C7503_S
C250_W
PP7517_S
L3901_E
PP4724_E
FD0922
L3903_E
FL5911_E
PP236_W
191
C1801_E
R5931_E
C7542_S 17 16
C7519_S
C3902_E
C5911_E PP203_W
192 FL5931_E
L7501_S PP7523_S PP213_W PP207_W
U_WLAN_W C7541_S PP205_W
C7524_S
15
L253_W
PP7581_S
193
R257_W
SH0900 C7539_S
C1802_E
C7540_S C7530_S
194 C7506_S J_FEZ_E PP4735_E
XW5824_E
L1800_E
PP212_W
C7504_S
XW5809_E
XW5812_E
XW5801_E
14 13
DSM_HB_E
PP232_W PP252_W
195 C5807_E C5808_E C5805_E C5826_E C5824_E C5809_E C5819_E R5932_E PP244_W
C7521_S C7525_S
C5828_E R7503_S
R0964
196 PP239_W
W
PP206_W PP4679_E
C5817_E
3_
PP210_W PP211_W
25
R7502_S
ST0900
12
C7500_S C7526_S FD0920
PP
PP215_W PP243_W
197 C5823_E XW5815_E
PP7537_S
R7501_S 11 PP4694_E
PP4670_E
_E
PP201_W
198 PP7538_S
93
C7534_S C7522_S
46
PP
C7509_S
C7536_S
PP204_W
R7500_S 10
C5818_E
C1808_E PP4738_E
PP202_W PP4695_E
199 PP4628_E
NFC_P
9
C7505_S
PP7513_S PP4696_E
C7572_S
200
_E
C5802_E
04
58
XW
U_APTU_E
PP7514_S PP4629_E
8
L255_W
R7572_S
FL7500_S
C7517_S
C5814_E
201
XW5803_E
PP7501_S PP4604_E
202
C5803_E C7573_S
7
PP223_W
U_SMR_E
XW5825_E
PP222_W
C2610_E
C2611_E
C2609_E
C2605_E
C2601_E
C2604_E
C2606_E
C2602_E
R2609_E
R2610_E
R2602_E
R2604_E
R2603_E
R2605_E
R2601_E
C2603_E
XR2608_E
PP4603_E
XW5814_E 6 FD0923
R7571_S
203
C5815_E
_E
C5806_E
PP4605_E
83
46
5
W
PP
PP228_W
9_
22
204 C7571_S
PP
PP4731_E
XW5805_E
205 C1807_E C1806_E C7527_S
C5820_E
C1805_E 605
C730_E
C246_W
R259_W
C905_E
C226_W
C786_E
C714_E
C738_E
C785_E
C717_E
R907_E
R905_E
R906_E
C256_W
PP225_W
206 R0957 C5827_E C7537_S C7538_S C7532_S C7528_S C7508_S 604
PP4745_E
PP4716_E
C721_E C787_E C752_E C728_E C1804_E 603 3

PP7536_S
PP224_W
207 C725_E 2 PP4714_E
XW5807_E
C7502_S
C5816_E
C1803_E
C7535_S
C5801_E
C7511_S
602 PP4712_E
208
C4304_E
XW4303_E
C904_E
C4306_E
PP4718_E
C247_W
C765_E 1
XW4302_E
FL4301_E
C245_W
PP4739_EPP4689_E
PP4717_E
209
R904_E
C1800_E L7502_S
XW5811_E
XW5810_E
XW5806_E
XW5808_E
601 PP4737_E
210
U4300_E C789_E C5830_E C5804_E C5825_E C5822_E C5812_E C5821_E XW5802_E
C5811_E C5810_E C5813_E PP4668_E
PP4686_E
XW5813_E
C
C758_E
C4303_E
C4301_E
C
PP4685_E
_E
PP4719_E
C4305_E
C4302_E
33
211
47
PP4662_E PP4660_E
C735_E J_INT_TOP
PP
C759_E 600
C906_E
212 C776_E
C722_E
PP4651_E
213 PP4639_E
599
C737_E R909_E C706_E
PP4638_E
597
C756_E
549 551 553 555 557 559 561 563 565 567 569 571 573 575 577 579 581 583 585 587 589 591 598
215 C715_E C757_E 547
214 PP4635_E
C712_E
217 C775_E
C241_W EEPROM_E 548 550 552 554 556 558 560 562 564 566 568 570 572 574 576 578 580 582 584 586 588 590 592 593 594 595 596 PP4634_E
C760_E
216 C709_E 545 PP4687_E
C902_E 546
R235_W
PP4730_E
PP4637_E
PP227_W
218
C228_W R908_E
C701_E C903_E
PP4688_E
XW914_E
PP4636_E PP226_W
544
219
SWD_E
R0900
C754_E
XW913_E
220 R202_W
C908_E C745_E 543
PP4692_E
C205_W
PP4672_E
C206_W
C755_E PP4725_E
221 FL_ISG_L_W C901_E

C747_E C766_E
542 PP4671_E
C751_E
C907_E
541 PP4736_E
222 TP7501_E
R910_E R911_E XW912_E R901_E
223 C777_E 540
C720_E TP7503_E
C746_E
224
C788_E
U_BB_E 539
C782_E
538
225
R5610_E
R13900
TP7500_E
C764_E
C761_E
C763_E
C762_E
C432_E
C708_E PP4721_E
226 C732_E 537

XW702_E
C704_E
C750_E
C780_E 536
227
C726_E
XW701_E
C784_E 535
228
C711_E 534
R5611_E
XW405_E
JDEBUG_E
C769_E
229
C778_E 533 PP4684_E

230
PP4723_E
532
C407_E
231
531
C411_E
232 C707_E
233 L401_E L406_E L405_E C713_E 530

PP4600_E
529
C406_E
234 C783_E
528
235 C781_E
527
236 C412_E C705_E PP4743_E
PP4647_E
PP4734_E
526
237
C736_E
C517_E
C402_E
R630_E
525
238
C401_E
C734_E
PP4741_E PP4720_E
524
239
PP4728_E
523
240 R632_E R601_E
C522_E
C748_E
C744_E
C739_E
C740_E
C767_E
C731_E
C774_E
C742_E
C719_E
C770_E
C727_E
C741_E
C772_E
C771_E
C724_E
C723_E
R903_E
R902_E
522
241 R631_E R602_E
521
C518_E
242 C513_E TP12611 TP012600 PP4744_E

520
L407_E C729_E
PP4740_E PP4644_E
R610_E
243 R5602_E R5601_E

C773_E
C743_E
C526_E
XW601_E
C523_E PP4729_E
C608_E
C702_E
519
244
UBBPMU_E R5604_E R5605_E
R5635_E
XW501_E
C733_E 528
245
C516_E
C408_E
E
TP7502_E
8_
PP4609_E
XW401_E
40
R13810
XW
517 TP12612 TP12603

XW402_E
246
C430_E
C768_E
C749_E
C779_E
C716_E
C710_E
C410_E R5030
C435_E
XW406_E
516
C718_E
XW407_E PP4654_E
247
C525_E
C528_E C524_E FD0915

C433_E 515 PP4632_E
248
C515_E
PP4726_E
C502_E
C514_E 514
XW403_E
PP4655_E
_E
249 TP12614 TP12602
52
PP4658_E
46
C512_E PP4611_E
PP
XW404_E
513 PP4722_E
250
C501_E
C509_E
251 L403_E C511_E C503_E

DZ5600_E C602_E C605_E
XW602_E
R607_E
XW605_E
512
TP12660
C405_E
R4100_E
R4101_E
R4140_E
252 C427_E 511 PP4656_E

C601_E
TP12613 TP12601
C403_E
510
253
PP4727_E
509
UBBPMK_E
R5631_E
R603_E
254 TP12681
R678_E
PP4612_E
C429_E
255
C434_E C413_E L404_E L402_E Y601_E
508
C404_E
507
256
XW603_E
506 PP4653_E
257
C604_E
XW604_E
C1903_E C1901_E
258 C409_E C603_E 505
504
259
C1900_E SH0902
C1907_E
C1906_E
503 TP12661
260
502
C1401_E
FL1401_E
R5634_E
C1136_E
261
C1138_E C1226_E
XW502_E
C1902_E C1908_E
XW1114_E
501 PP4698_E
U_SP3T_E
C1137_E
262 XW1182_E
500
C1120_E
C1143_E
C1132_E
C1118_E
C1117_E
C1119_E
C1116_E
C1133_E
R0977
R0978
R0979
R0961
TP12680
C1904_E
263
C1135_E
_E
TP12685
XW
17
11
18
11
_E
497 499
XW
XW1119_E
264
XW1164_E
XW1120_E
C1140_E
C1139_E
C1142_E
U_APTL_E
XW1165_E
265
R0990 PP4608_E
PP4602_E
495
266
R0911
PP4601_E
TP12686
267 L1900_E R0924
C1124_E
XW1154_E 496
C1905_E
XW1237_E
268 C1208_E 493
R0903
XW1239_E
269 C1214_E 494
C1123_E
C1109_E
XW1153_E
270 C1102_E 491

_E
04
XW1189_E
11
XW
XW1103_E XW1186_E
271 C1224_E 492
C1211_E XW5040
PP4681_E
C1603_E
XW1232_E
XW1238_E
XW1601_E
L1602_E
XW1201_E
272
C1607_E C1108_E 489 PP4732_E
PP4706_E
PP4704_E
PP4682_E
C1605_E
C1204_E
XW1102_E
PP4709E
273 490
C1606_E
PP4705_E
PP4707_E
_E
C1122_E
01
XW5030
C1121_E XW1152_E
11
XW
XW1184_E XW1151_E XW1181_E PP4708_E

274
L1601_E 487
C1227_E
C1232_E PP4702_E PP4701_E

C1101_E XW1231_E
PP4641_EPP4640_E
PP4703_E
275 488 PP4700_E
C1107_E
C1610_E
C1221_E
XW1115_E
276 XW1229_E
XW1105_E
PP4711_E
XW1190_E C1106_E C1113_E

277 485 PP4646_E PP4710_E
C1141_E
XW1155_E
XW1230_E
C1231_E C1125_E 486
278
U_QET0_E R1613_E PP4742_E
R1612_E
XW1240_E
B
C1238_E
B
C1216_E
279
C1615_E
XW1287_E
484
280 XW1166_E
C1239_E
XW1291_E
U_SDR_E L1402_E
C1134_E
C1229_E
483
C1611_E
R1402_E PP4643_E
C1608_E
281 XW1163_E C1129_E

XW1235_E
482
XW1233_E
L1406_E
XW1183_E
282 C1230_E 481 PP4642_E
283
XW1207_E
C1217_E
C1105_E
XW1187_E
480
C1609_E
284 C1202_E XW1228_E

C1225_E
479
_E
XW1208_E
85
L1603_E
C1115_E
11
285 C1203_E XW1214_E

XW
XW
478
11
C1604_E
11
XW1216_E
_E
286 C1236_E XW1112_E C1213_E

477
XW1113_E
XW1215_E
XW
16
XW1162_E
287
02
_E
R0907 C1131_E 476

288
C1601_E
C1206_E C1112_E
474
XW1210_E
289
C1234_E XW1218_E C1237_E 475
XW1209_E
290 C1145_E
C1233_E
XW1211_E
XW1161_E
473
291
C1218_E XW1217_E C1207_E
472 PP4690_E
PP4715_E
292
XW1223_E
XW1160_E
C4403_E C4404_E C1128_E

293
R0908 471 PP4713_E
XW1213_E
C1235_E 470
R0909
XW1106_E
294 XW1107_E
L1403_E 469
295 R0910 XW1108_E XW1236_E
U4400_E
XW1110_E
XW1109_E
XW1157_E
XW1158_E
XW1156_E
468
XW1203_E
R1403_E
XW1202_E XW1204_E XW1205_E XW1226_E XW1206_E XW1227_E XW1212_E
296
XW1224_E XW1225_E
C1144_E
C1201_E
C1205_E
C1103_E
C1110_E
C1126_E
C1219_E
C1220_E
C1127_E
C1209_E
C1114_E
C1400_E
C1228_E
C1104_E
C1212_E
C1130_E
C1222_E
C1111_E
C1215_E
C1223_E
C1210_E
R0975
R0963
XW1159_E
297 L1407_E 467
466
298 R5636_E
FL4401_E C4401_E
299 465
301
300
464
463
302
303
462 TP12622
606
305
307 310 313 316 319 322 324 326 328 330 333 336 461
304
306 309 312 315 318 321 332 335 338 460
340
607
339 308 311 314 317 320 323 325 327 329 331 334 337
459
341 TP12622
458
608 342
PP4622_E
457
343
R2804_E R2801_E R2803_E R2802_E R2102_E R0973 R0972 XR2107_E C2109_E C2103_E C2105_E C2107_E R2101_E R2106_E R2105_E
C418_W
456
C417_W
609 344
C415_W
C485_W
C486_W
C484_W
C416_W
PP4623_E
455
C2804_E
R0974
345
454
610 346
453
C414_W
C2110_E
C471_W
XR2805_E
347
452
611 348
PP217_W
451
MIMO_L_E
C483_W
349
C2803_E
R473_W
R2110_E
450
612 350
U_2G_L_W
449
351
C489_W
C2801_E
C476_W
448
C2120_E
613 352
447
353
R466_W
C2802_E
C492_W
446
C2111_E
614 354
445
355
C2304_E
C490_W
C2313_E C2302_E C2305_E C2314_E 444

615 356
PA_HB_E
R2108_E
C3301_E 443 TP12610

C2311_E
357
442
616 358
C2115_E
441
359
C2306_E
360
L5_LNA_E 440
R2307_E
363 439
365
438
361
R2303_E
366 362 C3302_E L3302_E PA_LMB_E 437

C2309_E
364
R3301_E
436
R2302_E
373
374 L3301_E 435
R2306_E
372
375 434
FD0910
R2301_E
367 433
C2308_E
376
432
C2310_E
368 FD0900 431
_E
R2111_E C2113_E R2109_E C2112_E
C2122_E
C2108_E
C2102_E
C2104_E
C2106_E
C2114_E
_E
377 R0976 PP4620_E
21
PP4624_E
C2101_E
25
R2308_E C2312_E C2301_E C2303_E C2315_E
46
XR2304_E
46
R2305_E
C2307_E
430
PP
PP
429
369
378
FD0912
428
427
370 405 409
381 383 385 387 389 391 393 395 397 399 401 403 411 413 415 417 419 421 423
426
371 379 407 FD0901
425
380 382 384 386 388 390 392 394 396 398 400 402 404 406 408 410 412 414 416 418 420 422 424
A iPhone 12 Pro Max SYNC_DATE=18/10/2021 A

DRAWING TITLE
D54BB CRB MLB LAYOUT

PART NUMBER SIZE
820-01971 D
www.itesla.solutions REVISION
https://paypal.me/Torsioniforums/
A.1.1
NOTICE OF PROPRIETARY PROPERTY: AUTHOR

PROPRIETARY PROPERTY OF ITESLA SOLUTIONS.
Filip Pusca
THE POSESSOR AGREES TO THE FOLLOWING: ASSEMBLY
A/B
PAGE
IV ALL RIGHTS RESERVED 1/1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CK
D54 MLB TOP

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
10 0024125573 ENGINEERING RELEASED 2020-07-01
CRB
LAST_MODIFICATION=Wed Jul 1 16:52:56 2020 LAST_MODIFICATION=Wed Jul 1 16:52:56 2020 LAST_MODIFICATION=Wed Jul 1 16:52:56 2020
PAGE CSA CONTENTS SYNC DATE PAGE CSA CONTENTS SYNC DATE PAGE CSA CONTENTS SYNC DATE
D
1 1 TABLE OF CONTENTS 49 58 CAMERA: PMU 2: Aliases 0.143.0 05/14/2019 97 134 INTERPOSER: Aliases (3/4) D
2 2 SYSTEM: BOM Tables 50 59 CAMERA: Discrete LDOs + Misc 0.143.0 05/14/2019 98 135 INTERPOSER: Aliases (4/4)
3 3 CONSTRAINTS: 90-Ohm temp 07/01/2019 51 62 CAMERA: Actuator Supply (Alex) 99 138 HIERARCHIES D53_mlb_ice_0.19.002/01/2019
4 4 CONSTRAINTS: Power temp 07/01/2019 52 64 CAMERA: Will 100 1 FRONT PAGE
5 5 CONSTRAINTS: Misc. temp 07/01/2019 53 65 CAMERA: Strobe Driver 101 2 MODULE
6 6 CONSTRAINTS: 50-Ohm 07/01/2019 54 70 PEARL: VCSEL Driver 102 3 FILTERS MATCHING
7 7 SYSTEM: Bootstrapping 55 71 PEARL: Aliases 103 1 FRONT PAGE
8 8 SYSTEM: Mechanical 56 73 SENSORS: Accel / Gyro 104 17 QET_DISCRETE_1 08/01/2019
9 10 SOC: NAND + USB & Misc 57 74 SENSORS: Jarvis (Top) 105 20 LB PAD 08/01/2019
10 11 SOC: PCIE 58 78 AUDIO: Codec: Analog (1/2) 106 22 UHB LAT PAD 08/01/2019
11 12 SOC: ISP 59 79 AUDIO: Codec: Power & I/O (2/2) 107 30 COUPLER LOWER 08/01/2019
12 13 SOC: Display 60 80 AUDIO: Bot Speaker Amp 108 35 LOWER ANTENNA FEEDS_ANT3 08/01/2019
13 14 SOC: Serial 61 81 AUDIO: Top Speaker Amp 109 36 LOWER ANTENNA FEEDS_ANT7 08/01/2019
14 15 SOC: GPIO 62 82 AUDIO: Aliases 0.143.0 05/14/2019 110 38 LOWER ANTENNA FEEDS_ANT9 08/01/2019
15 16 SOC: AOP & SMC & NUB 63 83 HAPTIC: Haptic Amp 111 40 UPPER ANTENNA FEEDS_ANT8 10/02/2019
16 17 SOC: Ocelot 64 84 HAPTIC: Sakonnet 112 1 NFC: TABLE OF CONTENTS
17 18 SOC: Power (CPU/GPU & SRAM & SOC) 65 90 TOP MODULE: Touch Processor 113 74 NFC_F
18 19 SOC: Power (Fixed & 1V2) 66 91 TOP MODULE: Display Power 114 75 NFC_P_CP
C 19 20 SOC: Power (DDR & AOP/AVE/ISP/USB) 67 93 LIGHTNING: Lightning Controller 115 1 TABLE OF CONTENTS 05/08/2018 C
20 21 SOC: Power (GND) 68 94 LIGHTNING: USB-PD 116 4 5G rFEM (UAT) D52_WIFI_MASTER_0.17.0
21 23 SOC: Aliases: I2C AP/ISP 69 95 LIGHTNING: Accessory Buck 117 5 5G rFEM (LAT) D52_WIFI_MASTER_0.17.0
22 24 SOC: Aliases: I2C AOP/SMC 70 96 LIGHTNING: eUSB
23 25 SOC: Aliases: GPIOs 71 97 LIGHTNING: Aliases
24 26 SOC: Aliases: Misc 72 99 LVL SHIFT: Misc Nets
25 27 SOC: Aliases: FF-Specific 73 100 B2B: Battery 0.99.0 06/20/2019
26 29 NAND 74 101 B2B: Cyclone 0.99.0 06/20/2019
27
28
31
33
NAND: Aliases
SYS PWR: PMU: Bucks (1/5)
75
76
102
105
B2B: Camera Wide
B2B: Camera Superflex
0.99.0
0.99.0
04/03/2019
04/03/2019
EEEE Codes TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

29 34 SYS PWR: PMU: Bucks (2/5) 77 106 B2B: Jasper 0.99.0 04/03/2019 TABLE_5_ITEM
825-7691 1 EEEE FOR 639-08572 MPYK CRITICAL EEEE:08572

30 35 SYS PWR: PMU: LDOs (3/5) 78 107 B2B: FCAM 0.99.0 04/03/2019 TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10112 NY8W CRITICAL EEEE:10112

31 36 SYS PWR: PMU: GPIO (4/5) 79 108 B2B: Juliet 0.99.0 04/03/2019 TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10113 NY9G CRITICAL EEEE:10113

32 37 SYS PWR: PMU: Misc (5/5) 80 109 B2B: Romeo 0.99.0 04/03/2019 TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10115 NY9Y CRITICAL EEEE:10115

33 38 SYS PWR: PMU: Aliases: GPIO 81 110 B2B: Sensor TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10116 NYC9 CRITICAL EEEE:10116

34 39 SYS PWR: PMU: Aliases: Misc. 82 111 B2B: Strobe 0.99.0 04/03/2019 TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10117 NYCN CRITICAL EEEE:10117

35 40 SYS PWR: Charger 83 112 B2B: Dock
36 41 SYS PWR: Charger/Boost: Aliases D52_AP_MASTER_0.175.0 84 113 B2B: Dock (Cont)
B 37 42 SYS PWR: Boost 85 117 B2B: Display/Touch Combo (1/2) 0.99.0 04/03/2019
B
38 44 SYS PWR: Wireless Charger 86 118 B2B: Display/Touch Combo (2/2) 0.99.0 04/03/2019
39 45 SYS PWR: Wireless Charger: Level Shifters 87 120 B2B: UAT1 D53_mlb_ice_0.19.0
02/01/2019
40 46 SYS PWR: Wireless Charger: Boost 88 121 B2B: UAT2
41 47 SYS PWR: Wireless Charger: Aliases 89 122 B2B: LAT
42 49 SYS PWR: NTCs (Top) 90 123 B2B: SIM
43 50 SYS PWR: NTCs (Bottom) 09/03/2019 91 126 TESTING: Test Points D52_AP_MASTER_0.199.0
44 53 CAMERA: PMU 1: Power (1/2) 92 128 TESTING: Probe Points D52_AP_MASTER_0.199.0
45 54 CAMERA: PMU 1: I/O (2/2) 93 130 INTERPOSER: Symbol (1/2)
46 55 CAMERA: PMU 1: Aliases 0.143.0 05/14/2019 94 131 INTERPOSER: Symbol (2/2)
47 56 CAMERA: PMU 2: Power (1/2) 95 132 INTERPOSER: Aliases (1/4)
48 57 CAMERA: PMU 2: I/O (2/2) 96 133 INTERPOSER: Aliases (2/4)
Sub-designs
Hierarchies
HARD/ FORCE
SOURCE PROJECT SUB-DESIGN NAME VERSION SYNC_DATE/TIME
APNs
SOFT SUBDESIGN
D52 HIER_ARROW 0.49.0 S 2020_06_30_13:39:10 N Packaging Options

A TABLE_5_HEAD
D54 HIER_RADIO_MAV_TOP 3.25.0 S 2020_06_30_13:38:18 N PACK_OPTIONS TO INCLUDE IN NETLIST TABLE OF CONTENTS A
DRAWING TITLE
051-05170 1 SCH,MLB,TOP,D54 SCH CRITICAL ?

TABLE_5_ITEM
D54 HIER_NFC_TOP 0.19.0 S 2020_06_30_13:40:07 N D54
SCH,MLB,TOP,D54
D54 HIER_WIFI_TOP 0.15.0 S 2020_06_30_13:37:33 N DRAWING NUMBER SIZE
051-05170 D
TABLE_5_ITEM
Apple Inc.
820-01940 1 PCB,MLB,TOP,D54 PCB CRITICAL ?
Pages REVISION
10.0.0
HARD/
SOURCE PROJECT SUB-DESIGN NAME SUB-DESIGN PAGES VERSION SOFT SYNC_DATE/TIME NOTICE OF PROPRIETARY PROPERTY: BRANCH
D52 AP_MASTER 2,7,10-21,23-26,29,31,33-40,42,44-47,49,53-54,56-57,62,64-65,70-71,73-74,78-81,83-84,90-91,93-97,99 3.91.0 S 2020_07_01_16:41:16

PROPRIETARY PROPERTY OF APPLE INC.
crb-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1 OF 138
SHEET
IV ALL RIGHTS RESERVED 1 OF 117
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Multi-Vendor Criticals Capacitor Alternates Level Shifter Alternates

Capacitors 0.1uF, 01005 TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_CRITICAL_HEAD
In descending order of value, then package size Capacitors (cont'd) PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT PART NUMBER CRITICAL PART# COMMENT
PART NUMBER
TABLE_CRITICAL_HEAD TABLE_CRITICAL_HEAD TABLE_CRITICAL_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENT CRITICAL PART# COMMENT

TABLE_ALT_ITEM
132S0316 01005,0.1uF, 6.3V 311S00231 311S00232 ? ALL IC,74AVC2T45,XCVR,2 BIT,2 SPLY,X2SON8 311S00232 IC,74AVC2T45,XCVR,2 BIT,2 SPLY,X2SON8
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
132S00185 132S0316 ? ALL CAP,CER,X5R,0.1UF,20%,6.3V,01005
TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
138S0979 131S00303 311S00230 311S00212 ? ALL 311S00212

CAP,CER,X5R,10UF,20%,10V,0402,H=0.65MM
TABLE_CRITICAL_ITEM
CAP,CER,NPO/COG,100PF,5%,16V,01005
TABLE_CRITICAL_ITEM
0.22uF, 01005
RefDes field intentionally left blank to allow selective single-sourcing
IC,74AVC1T45,XCVR,1 BIT,2 SPLY,X2SON6
TABLE_ALT_ITEM
IC,74AVC1T45,XCVR,1 BIT,2 SPLY,X2SON6
TABLE_CRITICAL_ITEM
138S0652 CAP,CER,X5R,4.7UF,20%,6.3V,H=0.65MM,0402 131S00323 CAP,CER,NPO/COG,56PF,5%,25V,01005 TABLE_ALT_HEAD TABLE_CRITICAL_HEAD

311S00261 311S00233 ? ALL IC,LSF0101,XCVR,2 BIT CFG,2 SPLY,X2SON6 311S00233 IC,LSF0101,XCVR,2 BIT CFG,2 SPLY,X2SON6
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
138S00070 CAP,X5R,4.7UF,20%,25V,0402 131S0643 CAP,CER,NP0/C0G,56PF,5%,25V,01005 PART NUMBER

TABLE_CRITICAL_ITEM
311S00235 IC,NVT0202,XCVR,2 BIT, 2 SPLY,BIDI,DFN8
D
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM
132S00014 01005,0.22uF, 6.3V
D
132S0663 CAP,CER,X5R,1UF,10%,25V,0402 131S0216 CAP,CER,NP0/C0G,47PF,5%,16V,01005 132S00233 132S00014 ? 01005,0.22uF,6.3V,Taiyo
138S0683 CAP,CER,X5R,1UF,10%,25V,0402
TABLE_CRITICAL_ITEM
131S0804 CAP,CER,27PF,5%,C0G,25V,0201
TABLE_CRITICAL_ITEM
132S00304 132S00014 ? 01005,0.22uF,6.3V,Kyocera

TABLE_ALT_ITEM
Power Inductor Alternates

0.47uF, 01005
138S0692 CAP,CER,X5R,1UF,20%,6.3V,0201 131S0223 CAP,CER,NP0/C0G,27PF,5%,16V,01005 TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
PART NUMBER
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
138S00014 CAP,CER,1UF,20%,16V,X5R,0201,H=0.39MM 131S0215 CAP,CER,NP0/C0G,22PF,5%,16V,01005 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
TABLE_CRITICAL_ITEM
PART NUMBER
TABLE_ALT_ITEM
152S00876 Cyntec,IND
152S00721 152S00876 ? ALL Taiyo,IND,MLD,1UH,3.6A,60MO,2016

132S0304 CAP,CER,X5R,0.22UF,20%,6.3V,0201 131S0225 CAP,CER,NP0/C0G,15PF,5%,16V,01005 TABLE_ALT_ITEM
138S00128 01005,0.47uF,6.3V,Kyocera TABLE_CRITICAL_ITEM
138S00133 138S00128 ? ALL 01005,0.47uF,6.3V,Murata

TABLE_ALT_ITEM
152S00897 Taiyo,IND
152S00930 152S00897 ? ALL Cyntec,IND,CPLD,0.1UH,6.1A,27MO,2016

132S00008 CAP,CER,0.1UF,10%,50V,X7R,0402 131S0220 CAP,CER,NP0/C0G,12PF,5%,16V,01005 TABLE_ALT_ITEM
138S00133 01005,0.47uF,6.3V,Murata TABLE_CRITICAL_ITEM
138S00269 138S00128 ? ALL 01005,0.47uF,6.3V,Taiyo

TABLE_ALT_ITEM
152S00826 152S00821 ? ALL Taiyo,IND,MLD,1UH,2.2A,60MO,2012

132S0288 CAP,CER,X5R,0.1UF,10%,16V,0201 131S00353 CAP,CER,NPO/COG,10PF,5%,16V,01005 TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
138S00269 138S00133 ? ALL 01005,0.47uF,6.3V,Taiyo

TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
152S00831 152S00818 ? ALL Taiyo,IND,MLD,0.22UH,5.3A,40MO,1608

132S0288 CAP,CER,X5R,0.1UF,10%,16V,0201 TABLE_CRITICAL_ITEM
Ferrites 1uF, 0201 152S00984 Cyntec.IND

TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
152S00991 152S00984 ? ALL Taiyo,IND,MLD,0.47UH,3.5A,34MO,1614

132S0534 CAP,CER,X5R,0.1UF,10%,25V,0201 TABLE_CRITICAL_ITEM
TABLE_CRITICAL_HEAD TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENT PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT 152S00992 152S00985 ? ALL Taiyo,IND,MLD,0.47UH,4.0A,45MO,2012
132S0664 CAP,CER,0.047UF,10%,25V,X5R,0201 PART NUMBER
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
155S0576 FERR BD,10 OHM,50%,750MA,0.07 DCR,01005 TABLE_ALT_ITEM
138S0706 CAP,X5R,1UF,20%,10V,0201 152S00989 152S00982 ? ALL Taiyo,IND,MULT,0.47UH,2.8A,70MO,1608

132S00025 CAP,CER,X5R,0.047UF,20%,6.3V,01005 TABLE_CRITICAL_ITEM
138S0739 138S0706 ? ALL CAP,CER,X5R,1UF,20%,10V,0201,SAMSUNG
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
155S00168 FLTR,NOISE,65 OHMZ,3.4OHM,0.7-2GHZ,0605 TABLE_ALT_ITEM
152S00872 152S00918 ? ALL TDK,IND,MLD,0.47UH,5.6A,36MO,H=0.8,2016

132S00093 CAP,X5R,0.022UF,20%,6.3V,01005 138S0945 138S0706 ? ALL CAP,CER,X5R,1UF,20%,10V,0201,KYOCERA
TABLE_ALT_ITEM
152S00847 152S00918 ALL Boost/Yeti (2117/0.8mm)

2.2uF, 0201 ?
TABLE_CRITICAL_ITEM
CYNTEC,IND,MLD,0.47UH,5.6A,26MO,H=0.8,2016
132S0245 CAP,CER,X5R,0.01UF,10%,6.3V,01005
RefDes field intentionally left blank to allow selective single-sourcing TABLE_ALT_ITEM
Resistors 152S01282 152S01255 ? ALL

TABLE_CRITICAL_ITEM
TAIYO,IND,MLD,0.47UH,5A,30MO,H=0.65,2117
132S0396 CAP,CER,X5R,1000PF,10%,10V,01005 TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM TABLE_CRITICAL_HEAD
PART NUMBER Boost/Yeti (2117/0.65mm)

132S0296 CAP,CER,X5R,1000PF,10%,6.3V,01005 CRITICAL PART# COMMENT
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
138S0831 CAP,CER,X5R,2.2UF,20%,6.3V,0201
138S00049 138S0831 ?
Misc. Alternates
CAP,CER,X5R,2.2UF,20%,6.3V,0201
132S0318 CAP,CER,X5R,820PF,10%,10V,01005 118S00068 RES,MF,1.3 MOHM,1%,200PPM,1/20W,0201
132S0275 CAP,CER,X5R,470PF,10%,10V,01005
TABLE_CRITICAL_ITEM
117S0055 RES,MF,1/20W,2M OHM,5,0201,SMD

TABLE_CRITICAL_ITEM
3uF @ 1V, 0201

TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM TABLE_ALT_HEAD
131S0883 CAP,CER,NP0/C0G,220PF,2%,50V,0201
Misc. PART NUMBER PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_CRITICAL_HEAD
PART NUMBER CRITICAL PART# COMMENT
C C
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM TABLE_ALT_ITEM
138S00139 0201,3uF@1V
131S00170 CAP,CER,C0G,220PF,5%,25V,01005 TABLE_CRITICAL_HEAD
138S00138 138S00139 ? ALL 0201,3uF@1V,KYOCERA

TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENT
TABLE_ALT_ITEM
155S00437 155S00402 ? ALL FERR BD,33OHM,25%,1.5A,55MOHM DCR,0201 155S00402 FERR BD,33OHM,25%,1.5A,55MOHM DCR,0201
131S00053 CAP,CER,C0G,220PF,5%,10V,01005 TABLE_CRITICAL_ITEM
138S00164 138S00139 ? ALL 0201,3uF@1V,TAIYO

TABLE_CRITICAL_ITEM
377S0106 SUPPR,TRANS,VARISTOR,12V,33PF,01005 TABLE_ALT_ITEM
155S00194 155S00400 ? ALL FERR BD,150OHM,25%,200MA,0.7OHM DCR,01005 155S00400 FERR BD,150OHM,25%,200MA,0.7OHM DCR,01005
132S0249 CAP,CER,X7R,220PF,10%,10V,01005 TABLE_CRITICAL_ITEM
138S00280 138S00139 ? ALL 0201,3uF@1V,SAMSUNG

107S0257 THERMISTOR,NTC,10K OHM,1%,B=3435,01005 155S00414 155S0876 ? ALL FERR BD,10OHM,50%,1.1A,0.05OHM DCR,01005 155S0876 FERR BD,10OHM,50%,1.1A,0.05OHM DCR,01005
4uF, 0201
TABLE_CRITICAL_ITEM
131S0307 CAP,CER,NP0/C0G,100PF,5%,16V,01005 TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
RefDes field intentionally left blank to allow selective single-sourcing 155S00131 155S0755 ? ALL FERR BD,240OHM,25%,200MA,1.0OHM DCR,01005 155S0755 FERR BD,240 OHM,25%,200MA,1.0 DCR,01005
2020 MLCCs
TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT 155S00583 155S00140 ? ALL FERR BD,33OHM,25%,400MA,0.20DCR,01005 155S00140 FERR BD,33OHM,25%,400MA,0.20DCR,01005
PART NUMBER
TABLE_CRITICAL_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
138S00071 0201,X5R,4UF,0201,0.55MM,MURATA 377S00070 377S00001 ALL 377S00001

16uF, 0402, 4V ? TVS,BIDIR,5.8V,6PF,01005
TABLE_ALT_ITEM
TVS,BIDIR,5.8V,6PF,01005
138S00116 138S00071 ? CAP,X5R,4UF,0201,0.55MM,TAIYO
TABLE_ALT_HEAD TABLE_ALT_ITEM
377S00140 377S00001 ? ALL TVS,BIDIR,5V,6PF,01005 377S00129 SUPRESS,TRANS,6.8V,100PF,01005

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 138S00117 138S00071 ? CAP,X5R,4UF,0201,0.55MM,KYOCERA
PART NUMBER Primary: Murata TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
377S0168 377S00129 ALL 107S0244

138S00316 138S00313 ? ALL CAP,X5R,16UF,20%,4V,M,0402
TABLE_ALT_ITEM
Taiyo
4.7uF, 0402 ? SUPPRESS,TRANS,6.8V,100PF,AMOTECH,01005
TABLE_ALT_ITEM
THERMISTOR,NTC,100K OHM,1%,B=4250,01005
107S0245 107S0244 ? ALL THERMISTOR,NTC,100K OHM,1%,B=4250,01005

TABLE_ALT_ITEM
138S00314 138S00313 ? ALL CAP,X5R,16UF,20%,4V,M,0402 Kyocera PART NUMBER
ZRB Cap ALTs

TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM TABLE_ALT_ITEM
138S0719 0402,4.7uF,10V
138S00315 138S00313 ? ALL CAP,X5R,16UF,20%,4V,M,0402 Samsung 138S1103 138S0719 ? ALL CAP,CER,X5R,4.7UF,20%,10V,0402
11uF, 0402, 4V 15uF, 0402

All RefDes in ( ) are single-sourced from Murata TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART NUMBER
PART NUMBER Primary: Murata PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
TABLE_CRITICAL_ITEM
PART NUMBER
TABLE_ALT_ITEM
138S00175 CAP,X5R,4.7UF,20%,25V,0402
138S00240 138S00187 ? ALL CAP,X5R,4.7UF,20%,25V,0402

138S00318 138S00317 ? ALL CAP,X5R,11UF,20%,4V,M,0402-3T Kyocera TABLE_ALT_ITEM
138S00003 0402,15uF,6.3V
138S00048 138S00003 ? 0402,15uF,6.3V, Kyocera
0-ohm, 0201, 4.5A

TABLE_ALT_ITEM
138S00319 138S00317 ? ALL CAP,X5R,11UF,20%,4V,M,0402-3T Samsung (C1805,C3321,C1872,C3371,C3382)
138S00320 138S00317 ? ALL CAP,X5R,11UF,20%,4V,M,0402-3T

TABLE_ALT_ITEM
Taiyo
18uF, 0402
TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
2.7uF, 0201, 6.3V PART NUMBER
TABLE_CRITICAL_ITEM
PART NUMBER
TABLE_CRITICAL_ITEM
B B
TABLE_ALT_HEAD TABLE_ALT_ITEM
138S00146 CAP,CER,X5R,18UF,20%,6.3V,MUR,0402 TABLE_ALT_ITEM
117S00012 RES,MF,0 OHM,1/10W,4.5A,0201

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 138S00221 138S00146 ? ALL CAP,CER,X5R,18UF,20%,6.3V,MUR,0402 117S00040 117S00012 ? ALL RES,MF,0 OHM,1/10W,4.5A,0201
PART NUMBER Primary: Murata
20uF, 0402
Low-noise, 0201, 2.2uF
TABLE_ALT_ITEM
138S00326 138S00325 BOARD_ID:D52&BOARD_ID:D54 ALL CAP,X5R,2.7UF,20%,6.3V,M,0201 Kyocera (61184814) All parts are single-sourced except for approved parts (listed below)
TABLE_ALT_ITEM TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
138S00327 138S00325 ? ALL CAP,X5R,2.7UF,20%,6.3V,M,0201 Samsung PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT RefDes field intentionally left blank to allow selective single-sourcing
PART NUMBER
2.7uF, 0201, 4V
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
138S0884 CAP,CER,X5R,20UF,20%,6.3V,0402,H=0.7MM TABLE_ALT_HEAD
138S00339 138S0884 ? Taiyo PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: C3302,C3312,C3333,C3350,C3364,C1893,C3412,C3423,C3525,C3535,C3403,C1807,C1866,C1874,C2030
PART NUMBER Primary: Murata TABLE_ALT_ITEM
TABLE_ALT_ITEM
Kyocera ALT removed due to 63646020 138S00185 138S00246 ? CAP,X5R,2.2UF,20%,25V,0402
138S00324 138S00321 ? ALL CAP,X5R,2.7UF,20%,4V,M,0201 Taiyo
138S00322 138S00321 ? ALL CAP,X5R,2.7UF,20%,4V,M,0201

TABLE_ALT_ITEM
TABLE_ALT_ITEM
Kyocera
22uF, 0402
All RefDes in ( ) do not include Kyocera ALT
22uF, 0704
138S00323 138S00321 ? ALL CAP,X5R,2.7UF,20%,4V,M,0201 Samsung PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
PART NUMBER PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
PART NUMBER
TABLE_CRITICAL_ITEM
138S00279 CAP,X5R,26UF,20%,4V,SEMCO,0402
MAV20 PDN Single-source
138S00144 138S00279 ? ALL CAP,X5R,26UF,20%,4V,MURATA,0402

TABLE_ALT_ITEM
138S00296 CAP,X5R,22UF,20%,16V,MUR,H=0.8MM,0704
TABLE_ALT_ITEM
138S00347 138S00296 ? ALL CAP,X5R,22UF,20%,16V,TAI,H=0.8MM,0704
138S00143 138S00279 ? (C409_E,C431_E) CAP,X5R,22UF,20%,4V,KYOCERA,0402
0.22uF, 01005
All RefDes in ( ) are single-sourced from Murata 10uF @ 1V, 4-Term
TABLE_ALT_HEAD TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
PART NUMBER PART NUMBER
TABLE_CRITICAL_ITEM
138S00149 0402-3T,10.5uF@1V
132S00233 132S00014 ? [SEE BELOW] 01005,0.22uF,6.3V,Taiyo 138S00148 138S00149 ? ALL 0402-3T,10.5uF@1V, Kyocera
132S00304 132S00014 ? [SEE BELOW] 01005,0.22uF,6.3V,Kyocera 138S00150 138S00149 ? ALL 0402-3T,10.5uF@1V, SEMCO
TABLE_ALT_ITEM
(C705_E-C720_E,C723_E-C725_E,C727_E,C730_E,C731_E,C734_E,C736_E-C742_E,C744_E,C749_E-C751_E,C754_E-C760_E,C766_E,C767_E,C770_E-C772_E,C774_E-C776_E,C778_E-C786_E)
2.2uF, 0201
All RefDes in ( ) are single-sourced from Murata
(C705_E-C720_E,C723_E-C725_E,C727_E,C730_E,C731_E,C734_E,C736_E-C742_E,C744_E,C749_E-C751_E,C754_E-C760_E,C766_E,C767_E,C770_E-C772_E,C774_E-C776_E,C778_E-C786_E) 138S00151 138S00149 ? ALL 0402-3T,10.5uF@1V, TY
22uF, 0402 3T (WiFi)

A
TABLE_ALT_HEAD
A
PART NUMBER
PART NUMBER
TABLE_ALT_ITEM
PAGE TITLE
138S00049 138S0831 ? [SEE BELOW]
TABLE_CRITICAL_ITEM
SYSTEM: BOM Tables

CAP,CER,X5R,2.2UF,20%,6.3V,0201
TABLE_ALT_ITEM
138S0986 CAP,CER,3-TERM,7.5UF,20%,4V,0402
(C701_E,C702_E,C704_E,C721_E,C722_E,C726_E,C728_E,C729_E,C732_E,C733_E,C735_E,C743_E,C745_E,C746_E,C747_E,C748_E,C752_E,C768_E,C769_E,C773_E,C777_E,C789_E) 138S00024 138S0986 ? ALL CAP,CER,3-TERM,7.5UF,20%,4V,0402
4uF, 0201 DRAWING NUMBER
051-05170
SIZE
D
All RefDes in ( ) are single-sourced from Murata
PART NUMBER ALTERNATE FOR

PART NUMBER
BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
Display Choke Alternates Apple Inc. REVISION
10.0.0
TABLE_ALT_ITEM
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT NOTICE OF PROPRIETARY PROPERTY: BRANCH
138S00116 138S00071 ? [SEE BELOW] CAP,X5R,4UF,0201,0.55MM,TAIYO
TABLE_ALT_ITEM
PART NUMBER
TABLE_ALT_ITEM
155S00524 FLTR,NOISE,35 OHMZ,3 OHM,7GHZ,50MA,0403

TABLE_CRITICAL_ITEM

crb-1
138S00117 138S00071 ? [SEE BELOW] CAP,X5R,4UF,0201,0.55MM,KYOCERA 155S00415 155S00524 ? ALL FLTR,NOISE,35 OHMZ,3 OHM,7GHZ,50MA,0403 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
(C511_E-C518_E,C522_E,C524_E-C526_E,C702_E,C764_E,C768_E-C769_E,C777_E,C787_E,C788_E,C1135_E-C1142_E,C1226_E,C1227_E,C5801_E-C5803_E,C5823_E,C5827_E,C5828_E)
(C511_E-C518_E,C522_E,C524_E-C526_E,C702_E,C764_E,C768_E-C769_E,C777_E,C787_E,C788_E,C1135_E-C1142_E,C1226_E,C1227_E,C5801_E-C5803_E,C5823_E,C5827_E,C5828_E)
2 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
90-ohm Diff Pair Constraints

Electrical Spacing CSet Definitions
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR DIELECTRIC BASED SPACING RULES
OVERRIDE
DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
DP:DP_90_LPDP*_WIDE* RULE DEFINITION LIST OF VALUES
LPDP E_LPDP_WIDE E DIFF_PAIR Y
E_LPDP_SWIDE E DIFF_PAIR DP:DP_90_LPDP*_SWIDE* Y A_DIELECTRIC_(N)X
EXAMPLE: 1,3-5,7L,8L-10L
Calculates dielectric distance from stackup, 1.5,2,2.5,3,4

E_LPDP_TELE E DIFF_PAIR DP:DP_90_LPDP*_TELE* Y
shortest distance is used unless 'L'is defined
EXAMPLE: 2,1DL,3D-5D,7V,8VL-10VL
PLEASE USE HYBRID TABLE

A_DIELECTRIC_(N)XD XV,XVL,X
E_LPDP_FCAM E DIFF_PAIR DP:DP_90_LPDP*_FCAM* Y Calculates dielectric distance from Hybrid Table and
stackup, shortest distance is used unless 'L' defined
?
D
E_LPDP_JASPER E DIFF_PAIR DP:DP_90_LPDP*_JASPER* Y A_DIELECTRIC_(N)XIN_(N)XOUT
EXAMPLE: 2_4,3L_5L
D
Calculates dielectric distance from stackup, ?
MIPI E_MIPI_DISPLAY E DIFF_PAIR_MIPI-D DP:DP_90_MIPI*DISPLAY* N
shortest distance is used unless 'L' is defined
E_MIPI_IRCAM E DIFF_PAIR_MIPI-C DP:DP_90_MIPI*_IRCAM*
Pin Delay Check

N
PCIE E_PCIE_NAND E DIFF_PAIR DP:DP_90_PCIE*_NAND* Y
E_PCIE_WLAN E DIFF_PAIR DP:DP_90_PCIE*_WLAN* Y
E_PCIE_BB E DIFF_PAIR DP:DP_90_PCIE*_BB* Y PIN DELAY MAPPING FILE
USB E_KRAKEN_DP E DIFF_PAIR DP:DP_90_KRAKEN* Y REFERENCE DESIGNATOR PIN DELAY CSV FILE NAME
E_MIKEYBUS_DP E DIFF_PAIR DP:DP_90_MIKEYBUS* Y U1000 SicilyPinDelay.csv

E_USB_DP E DIFF_PAIR DP:DP_90_USB* Y J10800 D54_JulietPinDelay.csv
E_EUSB_DP E DIFF_PAIR DP:DP_90_EUSB* Y *Location: /physical/rule/pindelays
Physical
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE
DOMAIN
LPDP 90_LPDP_WIDE P A_90_OHM_DIFF DP:DP_90_LPDP*_WIDE* Y

90_LPDP_SWIDE P A_90_OHM_DIFF DP:DP_90_LPDP*_SWIDE* Y
90_LPDP_TELE P A_90_OHM_DIFF DP:DP_90_LPDP*_TELE* Y
90_LPDP_FCAM P A_90_OHM_DIFF DP:DP_90_LPDP*_FCAM* Y
90_LPDP_JASPER P A_90_OHM_DIFF DP:DP_90_LPDP*_JASPER* Y
MIPI-D 90_MIPI_DISPLAY P A_90_OHM_DIFF DP:DP_90_MIPI*DISPLAY* Y
MIPI-C 90_MIPI_IRCAM P A_90_OHM_DIFF DP:DP_90_MIPI*_IRCAM* Y
PCIE (Gen4) 90_PCIE_NAND P A_90_OHM_DIFF DP:DP_90_PCIE*_NAND* Y
90_PCIE_BB P A_90_OHM_DIFF DP:DP_90_PCIE*_BB* Y
PCIE (Gen2) 90_PCIE_WLAN P A_90_OHM_DIFF DP:DP_90_PCIE*_WLAN* Y
USB 90_KRAKEN_DP P A_90_OHM_DIFF DP:DP_90_KRAKEN* Y
90_USB_DP P A_90_OHM_DIFF DP:DP_90_USB* Y
90_EUSB_DP P A_90_OHM_DIFF DP:DP_90_EUSB* Y
C MIKEYBUS 90_MIKEYBUS_DP P A_90_OHM_DIFF DP:DP_90_MIKEYBUS* Y

C
Spacing
OVERRIDE
DOMAIN
LPDP 90_LPDP_WIDE S A_DIELECTRIC_3X = Y

90_LPDP_SWIDE S A_DIELECTRIC_3X = Y
90_LPDP_TELE S A_DIELECTRIC_3X = Y
90_LPDP_FCAM S A_DIELECTRIC_3X = Y
90_LPDP_JASPER S A_DIELECTRIC_3X = Y
MIPI-D 90_MIPI_DISPLAY S A_DIELECTRIC_3X = Y
MIPI-C 90_MIPI_IRCAM S A_DIELECTRIC_2X = Y
PCIE (Gen4) 90_PCIE_NAND S A_DIELECTRIC_3X = Y
90_PCIE_BB S A_DIELECTRIC_3X = Y
PCIE (Gen2) 90_PCIE_WLAN S A_DIELECTRIC_3X = Y
USB 90_KRAKEN_DP S A_DIELECTRIC_3X = Y
90_USB_DP S A_DIELECTRIC_3X = Y
90_EUSB_DP S A_DIELECTRIC_3X = Y
MIKEYBUS 90_MIKEYBUS_DP S A_DIELECTRIC_2X = Y
Class-Class Spacing
CLASS TO CLASS SPACING
CLASS NAME CLASS NAME CONSTRAINT SET
LPDP <-> LPDP 90_LPDP_WIDE 90_LPDP_WIDE A_DIELECTRIC_2X
90_LPDP_WIDE 90_LPDP_SWIDE A_DIELECTRIC_2X
90_LPDP_WIDE 90_LPDP_TELE A_DIELECTRIC_2X
B 90_LPDP_WIDE
90_LPDP_WIDE
90_LPDP_FCAM
90_LPDP_JASPER
A_DIELECTRIC_2X
A_DIELECTRIC_2X B
90_LPDP_SWIDE 90_LPDP_SWIDE A_DIELECTRIC_2X
90_LPDP_SWIDE 90_LPDP_TELE A_DIELECTRIC_2X
90_LPDP_SWIDE 90_LPDP_FCAM A_DIELECTRIC_2X
90_LPDP_SWIDE 90_LPDP_JASPER A_DIELECTRIC_2X
90_LPDP_TELE 90_LPDP_TELE A_DIELECTRIC_2X
90_LPDP_TELE 90_LPDP_FCAM A_DIELECTRIC_2X
90_LPDP_TELE 90_LPDP_JASPER A_DIELECTRIC_2X
90_LPDP_FCAM 90_LPDP_FCAM A_DIELECTRIC_2X
90_LPDP_FCAM 90_LPDP_JASPER A_DIELECTRIC_2X
90_LPDP_JASPER 90_LPDP_JASPER A_DIELECTRIC_2X
MIPI-D 90_MIPI_DISPLAY 90_MIPI_DISPLAY A_DIELECTRIC_2X
PCIE (Gen2) 90_PCIE_WLAN 90_PCIE_WLAN A_DIELECTRIC_2X
USB 90_KRAKEN_DP 90_KRAKEN_DP A_DIELECTRIC_2X
90_KRAKEN_DP 90_USB_DP A_DIELECTRIC_2X
90_KRAKEN_DP 90_EUSB_DP A_DIELECTRIC_2X
90_USB_DP 90_USB_DP A_DIELECTRIC_2X
90_USB_DP 90_EUSB_DP A_DIELECTRIC_2X
90_EUSB_DP 90_EUSB_DP A_DIELECTRIC_2X
A SYNC_MASTER=temp SYNC_DATE=07/01/2019 A
PAGE TITLE
CONSTRAINTS: 90-Ohm
DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

crb-1
3 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power Constraints
Physical Physical (continued)
OVERRIDE
OVERRIDE
DOMAIN DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
LX/CX Nodes PWR_SHAPE_LX P PWR_SHAPE LX*,!LX_CHARGER_BOOT*,!LX_DPMIC* Y Arc PWR_50UM P PWR_50UM PP1V2_ARCAMP_VD_FILT_INTERNAL Y

PWR_SHAPE_LX_DPMIC P PWR_SHAPE LX_DPMIC* Y PWR_50UM P PWR_50UM PP1V8_ARCAMP_VA_VL_INTERNAL Y
PWR_SHAPE_LX P PWR_SHAPE CX* Y PWR_SHAPE P PWR_SHAPE PP_ARCAMP_VBOOST Y
System-Wide PWR_SHAPE P PWR_SHAPE PP_VDD_MAIN Y PWR_SHAPE P PWR_SHAPE ARCAMP_TO_SOLENOID_OUT* Y
PWR_SHAPE P PWR_SHAPE PP_VDD_BOOST* Y PWR_80UM P PWR_80UM AGND_ARCAMP Y
PWR_50UM P PWR_50UM PP3V0_S2 Y Touch PWR_100UM P PWR_100UM PP1V2_TOUCH_S2* Y
D
PWR_SHAPE P PWR_SHAPE PP1V8_IO Y PWR_80UM P PWR_80UM PP3V1_TOUCH_S2* Y
D PWR_SHAPE P PWR_SHAPE PP1V8_S2
PP1V8_S4
Y PWR_200UM P PWR_200UM PP1V8_TOUCH_S2*
PP7V3_DISPLAY_AVDDH*
Y
PWR_SHAPE P PWR_SHAPE Y Display PMIC PWR_SHAPE P PWR_SHAPE Y
PWR_200UM P PWR_200UM PP1V2_IO Y PWR_SHAPE P PWR_SHAPE PP4V6_DISPLAY_VDDEL* Y
PWR_200UM P PWR_200UM PP1V2_S2 Y PWR_SHAPE P PWR_SHAPE PNVAR_DISPLAY_VSSEL* Y
PWR_200UM P PWR_200UM PP1V2_S4 Y Kraken PWR_SHAPE P PWR_SHAPE PP_ACC_VAR Y
SoC:CPU/GPU PWR_SHAPE P PWR_SHAPE PP_CPU_PCORE Y PWR_80UM P PWR_80UM PP_VAR_USB_RVP Y
PWR_SHAPE P PWR_SHAPE PP_CPU_ECORE PWR_200UM P PWR_200UM PP_KRAKEN_ACC1* Y
Y
PWR_SHAPE P PWR_SHAPE PP_GPU Y PWR_SHAPE P PWR_SHAPE PP_KRAKEN_ACC2* Y
SoC:SRAM/SOC PWR_SHAPE P PWR_SHAPE PP_CPU_SRAM Y PWR_80UM P PWR_80UM ANALOG_VDD_MAIN_OV_R Y
PWR_SHAPE P PWR_SHAPE PP_SRAM_S1 Y Parrot PWR_80UM P PWR_80UM PP3V3_USB_S2 Y
PWR_SHAPE P PWR_SHAPE PP_SOC_S1 Y AF/OIS (Shared) PWR_SHAPE P PWR_SHAPE PPVAR_RCAM_PVDD Y
SoC:Fixed PWR_SHAPE P PWR_SHAPE PP0V78_SOC_FIXED_S1 Y Wide RCAM PWR_100UM P PWR_100UM PPVAR_WIDE_PVDD_CONN Y
PWR_80UM P PWR_80UM PP0V78_VDD_FIXED_XTAL Y PWR_100UM P PWR_100UM PP3V2_WIDE_AVDD1 Y
PWR_80UM P PWR_80UM PP0V78_SOC_FIXED_PCIE_REFBUF PWR_200UM P PWR_200UM PPVAR_WIDE_AVDD2 Y
Y
SoC:VDD12 PWR_80UM P PWR_80UM PP1V2_S1 Y PWR_100UM P PWR_100UM PP1V6_WIDE_DVDD* Y
PWR_80UM P PWR_80UM PP1V2_S1_XTAL Y SWide RCAM PWR_100UM P PWR_100UM PP2V85_SWIDE_AVDD1 Y
PWR_200UM P PWR_200UM PP1V2_SOC PWR_200UM P PWR_200UM PPVAR_SWIDE_AVDD2 Y
Y
PWR_80UM P PWR_80UM PP1V2_SOC_FILT Y PWR_100UM P PWR_100UM PP1V2_SWIDE_DVDD Y
PWR_80UM P PWR_80UM PP1V2_VDD12_FMON Camera VDDIO PWR_80UM P PWR_80UM PP1V8_*VDDIO* Y
Y
PWR_80UM P PWR_80UM PP1V2_VDD12_ULPPLL_S2 Y Tele RCAM PWR_100UM P PWR_100UM PPVAR_TELE_PVDD_CONN Y
PWR_80UM P PWR_80UM PP1V2_IO_GRP* PWR_100UM P PWR_100UM PP0V8_TELE_DVDD1 Y
Y
SoC:DDR PWR_SHAPE P PWR_SHAPE PP_DCS_S1 Y PWR_100UM P PWR_100UM PP0V975_TELE_DVDD2 Y
PWR_200UM P PWR_200UM PP0V6_VDDQL_S1 Y PWR_100UM P PWR_100UM PP2V85_TELE_AVDD1 Y
PWR_SHAPE P PWR_SHAPE PP1V06_S2 Y PWR_200UM P PWR_200UM PP1V35_TELE_AVDD2 Y
SoC:Misc. PWR_SHAPE P PWR_SHAPE PP0V7_VDD_LOW_S2 FCAM PWR_200UM P PWR_200UM PP1V1_FCAM_DVDD Y
Y
PWR_80UM P PWR_80UM PP0V7_VDD_LOW_*LPPLL Y PWR_200UM P PWR_200UM PP2V85_FCAM_AVDD* Y
C PWR_SHAPE
PWR_SHAPE
P
P
PWR_SHAPE
PWR_SHAPE
PP_AVE_S1
PP_DISP_S1
Y
Y
Juliet IRCAM PWR_80UM
PWR_80UM
P
P
PWR_80UM
PWR_80UM
PP2V85_IRCAM_AVDD
PP1V2_IRCAM_DVDD
Y
Y
C
PWR_200UM P PWR_200UM PP0V6_VDDIO06_GRP1_* Y Jasper PWR_80UM P PWR_80UM PP3V0_JASPER_RX_AVDD* Y
NAND PWR_100UM P PWR_100UM PP_NAND_VDDIO1_R Y PWR_80UM P PWR_80UM PP3V3_JASPER_TX_AVDD* Y
PWR_300UM P PWR_300UM PP_NAND_VDDIO1_F Y PWR_SHAPE P PWR_SHAPE PP1V1_JASPER_DVDD* Y
PWR_SHAPE P PWR_SHAPE PP0V83_NAND Y B2B PWR_DEFAULT P PWR_DEFAULT PP1V8_ALS_S2 Y
PWR_100UM P PWR_100UM PP0V83_NAND_PLL Y PWR_80UM P PWR_80UM PP1V8_COMPASS_S2_CONN Y
PWR_SHAPE P PWR_SHAPE PP2V625_NAND Y
PMU PWR_SHAPE P PWR_SHAPE PP1V5_VLDOINT Y Kobol PWR_80UM P PWR_80UM PP_VDDIO_IMU Y
PWR_SHAPE P PWR_SHAPE PP0V9_S1 Y Penrose PWR_80UM P PWR_80UM PP3V0_PENROSE_SVDD* Y
Yangtze PWR_SHAPE P PWR_SHAPE PP_VBUS1_E75 Y Dock PWR_80UM P PWR_80UM PP1V8_DOCK_S2_CONN Y
PWR_SHAPE P PWR_SHAPE PP_VBUS2_DOTARA Y PWR_200UM P PWR_200UM PPVAR_EIGER_S2* Y
PWR_SHAPE P PWR_SHAPE PP_CHARGER_PMID Y Display PWR_80UM P PWR_80UM PP1V2_DISPLAY_S2_CONN Y
PWR_SHAPE P PWR_SHAPE PP_BATT_VCC_YANGTZE Y PWR_80UM P PWR_80UM PP1V8_DISPLAY_DVDD_CONN Y
PWR_100UM_LX P PWR_100UM LX_CHARGER_BOOT* Y PWR_SHAPE P PWR_SHAPE PP1VX_DISPLAY_S2* Y
PWR_SHAPE P PWR_SHAPE PP6V0_CHARGER_LDO_INTERNAL Y PWR_80UM P PWR_80UM PP3V0_DISPLAY_S2* Y
PWR_80UM P PWR_80UM PP1V8_ALWAYS Y NFC/Ironman NFC PWR_80UM P PWR_80UM PP1V2_NFC_S2 Y
Dotara PWR_SHAPE P PWR_SHAPE PAC_DOTARA_COIL1 Y PWR_SHAPE P PWR_SHAPE PP_NFC_*_VDDBOOST Y
PWR_SHAPE P PWR_SHAPE PAC_DOTARA_AC2 Y PWR_100UM P PWR_100UM PP_NFC_*_VDDC Y
PWR_SHAPE P PWR_SHAPE DOTARA_TX_BANK_2 Y PWR_100UM P PWR_100UM PP_NFC_*_MIX Y
PWR_SHAPE P PWR_SHAPE PAC_DOTARA_COIL2 Y PWR_100UM P PWR_100UM PP_NFC_*_VDDNV Y
PWR_100UM P PWR_100UM DOTARA_COMM* Y PWR_100UM P PWR_100UM PP_NFC_*_TVDD Y
PWR_200UM P PWR_200UM DOTARA_CLAMP* Y PWR_100UM P PWR_100UM PP_NFC_*_VDDPLL Y
PWR_200UM P PWR_200UM DOTARA_BOOT* Y PWR_100UM P PWR_100UM PP_NFC_*_VHV Y
PWR_SHAPE P PWR_SHAPE PP_DOTARA_VMID Y PWR_100UM P PWR_100UM PP_NFC_*_MIX,PP_NFC_*_VCASCHI,PP_NFC_*_VCASLO Y
PWR_SHAPE P PWR_SHAPE PP_DOTARA_VRECT Y PWR_100UM P PWR_100UM PP_NFC_*_VREF Y
B B
PWR_200UM P PWR_200UM PP1V8_DOTARA_LDO Y PWR_100UM P PWR_100UM PP_NFC_*_AVDD Y
PWR_100UM P PWR_100UM PP5V0_VDD_DOTARA Y PWR_SHAPE P PWR_SHAPE PP_NFC_*_VUP Y
PWR_100UM P PWR_100UM PP5V0_DOTARA_VMID Y PWR_SHAPE P PWR_SHAPE NFC_P_ANT_POS, NFC_P_ANT_NEG Y
PWR_80UM P PWR_80UM PP1V2_DOTARA_S2 Y PWR_SHAPE P PWR_SHAPE NFC_F_ANT_POS, NFC_F_ANT_NEG Y
Camera PMUs PWR_SHAPE P PWR_SHAPE PP1V3_CAM_PMU*_BUCK0 Y Arrow PWR_SHAPE P PWR_SHAPE PP1V0_S4 Y
PWR_SHAPE P PWR_SHAPE PP_VDD_MAX_CAM_PMU* Y PWR_SHAPE P PWR_SHAPE PP1V0_R1_ANA_S4 Y
PWR_SHAPE P PWR_SHAPE PP_VDD_RTC_CAM_PMU* Y QETs/APTs PWR_SHAPE P PWR_SHAPE PP_APT_L_PA Y
PWR_SHAPE P PWR_SHAPE PP1V8_CAM_PMU1_IO_SW Y Radio PWR_100UM P PWR_100UM PP_VDD_RF_1V2 Y
PWR_100UM P PWR_100UM PP_VIO_RFFE*_1V8*,PP_RFFE*1V8* Y
PWR_SHAPE P PWR_SHAPE PP1V2_INT_CAM_PMU* Y PWR_80UM P PWR_80UM PP_1V8_LDO6 Y
Will/Jasper PWR_100UM P PWR_100UM PP3V0_WILL_VDD Y PWR_80UM P PWR_80UM PP_UIM1_LDO11 Y
PWR_100UM P PWR_100UM PP1V8_CAM_PMU2_IO_SW Y PWR_80UM P PWR_80UM PP_UIM2_LDO13 Y
PWR_100UM_HV P PWR_100UM PN_JASPER_VDDHV* Y PWR_100UM P PWR_100UM PP_QET1_VDD_AMP* Y
PWR_100UM P PWR_100UM PP_JASPER_VDDLAS* Y PWR_100UM P PWR_100UM PP_QET1_VAUX_S Y
Strobe PWR_SHAPE P PWR_SHAPE PP_STROBE_DRIVER_COOL_LED Y PWR_100UM P PWR_100UM PP_QET1_PA_VBAT_LDO Y
PWR_SHAPE P PWR_SHAPE PP_STROBE_DRIVER_WARM_LED Y PWR_100UM P PWR_100UM PP_QET1_AMP_OUT Y
PWR_SHAPE P PWR_SHAPE PP_STROBE_BOOST_OUT Y PWR_SHAPE P PWR_SHAPE PP_QET1_PA Y
Rigel/Pearl PWR_SHAPE P PWR_SHAPE PP_VANA Y PWR_100UM P PWR_100UM SUBUS_UAT_A* Y
PWR_SHAPE P PWR_SHAPE PP_RIGEL_VINCORE Y PWR_100UM P PWR_100UM SUBUS_UAT_B* Y
PWR_SHAPE P PWR_SHAPE PP_RIGEL_BUCK_BOOST_A Y PWR_100UM P PWR_100UM SUBUS_LAT_B* Y
PWR_SHAPE P PWR_SHAPE PP_RIGEL_BUCK_BOOST_B Y PWR_100UM P PWR_100UM SUBUS_LAT_C* Y
PWR_SHAPE P PWR_SHAPE PP_ROMEO_CATHODE Y
PWR_SHAPE P PWR_SHAPE PP_ROMEO_DENSE_ANODE Y
PWR_SHAPE P PWR_SHAPE PP_ROMEO_SPARSE_ANODE Y
PP_ROMEO_A_ANODE DOMAIN NET RULE ASSIGNMENT
PWR_SHAPE P PWR_SHAPE Y
PP_ROMEO_B_ANODE
(E,P,S)
CONSTRAINT SET COMMA SEPARATED NET NAMES (WILDCARD SUPPORT EX: DDR* )
PWR_SHAPE P PWR_SHAPE Y
A
P PWR_100UM ANALOG_NAND_ZQ*
A
PWR_SHAPE P PWR_SHAPE PP_BANE_ANODE Y
PWR_100UM P PWR_100UM PP3V3_MAMABEAR_VDD Y SYNC_MASTER=temp SYNC_DATE=07/01/2019
PAGE TITLE
Audio PWR_50UM P PWR_50UM PP1V8_AUDIO_VA_S2 Y
Codec PWR_200UM P PWR_200UM AGND_CODEC Y CONSTRAINTS: Power
BotSpk PWR_50UM P PWR_50UM PP_VA_BOT_SPK_INTERNAL Y DRAWING NUMBER SIZE
PP_SPKRAMP_BOT_VBOOST 051-05170 D
PWR_SHAPE
PWR_SHAPE
P
P
PWR_SHAPE
PWR_SHAPE SPKRAMP_BOT_TO_COIL_OUT_*
Y
Y
Apple Inc. REVISION
PWR_80UM P PWR_80UM AGND_BOT_SPK Y 10.0.0

TopSpk PWR_50UM P PWR_50UM PP_VA_TOP_SPK_INTERNAL Y NOTICE OF PROPRIETARY PROPERTY: BRANCH
PWR_SHAPE P PWR_SHAPE PP_SPKRAMP_TOP_VBOOST Y THE INFORMATION CONTAINED HEREIN IS THE

crb-1
PWR_SHAPE P PWR_SHAPE SPKRAMP_TOP_TO_COIL_OUT_* Y THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PWR_80UM P PWR_80UM AGND_TOP_SPK Y

4 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power Spacing Clocks

Spacing Physical
DOMAIN
OVERRIDE
DOMAIN
OVERRIDE
CLK P DEFAULT CLK_* Y
GND S MSAP_YIELD GND Y
= CLK P DEFAULT SPMI*CLK* Y
PWR_DEFAULT S DEFAULT Y
= CLK P DEFAULT I2S*MCLK* Y
PWR_50UM S DEFAULT Y
= CLK P DEFAULT SPI*SCLK* Y
PWR_80UM S DEFAULT Y
PWR_100UM S DEFAULT = Y Spacing
D PWR_200UM S DEFAULT =
=
Y
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR D
PWR_300UM S DEFAULT Y DOMAIN
OVERRIDE
= CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
PWR_SHAPE S DEFAULT Y
= CLK S A_DIELECTRIC_1.5X = Y
PWR_100UM_HV S HV_SPACING Y
PWR_SHAPE_LX
PWR_100UM_LX
S
S
NA_DIELECTRIC_2X_LX
NA_DIELECTRIC_2X_LX =
= Y
Y Sensitive Analog
PWR_SHAPE_LX_DPMIC S NA_DIELECTRIC_2X_LX = Y Physical
Class-Class Spacing CLASS NAME

DOMAIN
E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:)
OVERRIDE
Y/N
CLASS TO CLASS SPACING ANALOG_SAKONNET P DEFAULT ANALOG*SAKONNET_TO_HALL* Y

CLASS NAME CLASS NAME CONSTRAINT SET ANALOG P DEFAULT ANALOG*DOTARA* Y
PWR_100UM GND 100UM-249UM_SPACING ANALOG P DEFAULT ANALOG*DOMBRA* Y
PWR_100UM PWR_100UM 100UM-249UM_SPACING ANALOG P DEFAULT ANALOG*SENSE,ANALOG*SENSE_SE,ANALOG*SENSE_FILT Y
PWR_100UM PWR_200UM 100UM-249UM_SPACING ANALOG P DEFAULT ANALOG*ZQ* Y
PWR_100UM PWR_300UM 100UM-249UM_SPACING ANALOG P DEFAULT ANALOG*REXT* Y
PWR_100UM PWR_SHAPE 100UM-249UM_SPACING ANALOG P DEFAULT ANALOG*CAL* Y
PWR_200UM GND 100UM-249UM_SPACING ANALOG P DEFAULT ANALOG_*REF* Y
PWR_200UM PWR_200UM 100UM-249UM_SPACING ANALOG P DEFAULT ANALOG_FB* Y
PWR_200UM PWR_300UM 100UM-249UM_SPACING ANALOG P DEFAULT ANALOG*PDTS* Y
PWR_200UM PWR_SHAPE 100UM-249UM_SPACING ANALOG P DEFAULT ANALOG_KRAKEN_BYPASS Y
PWR_300UM GND 250UM+_SPACING GRP_GPIO P DEFAULT ANALOG_KRAKEN_BI_CCG2B_CC Y
PWR_300UM PWR_300UM 250UM+_SPACING ANALOG P DEFAULT ANALOG_RIGEL_LSCP Y
PWR_SHAPE GND 250UM+_SPACING ANALOG_AMP_FILT P PWR_80UM ANALOG_*_SPK_FILT,ANALOG_ARC_FILT Y
PWR_SHAPE PWR_SHAPE 250UM+_SPACING ANALOG P DEFAULT VSS_PMU_XTAL Y
PWR_100UM_HV GND DEFAULT ANALOG P DEFAULT AMUX* Y
ANALOG_NTC P DEFAULT NTC_STROBE_MODULE* Y
C Diff Pair Constraints ANALOG_NTC

ANALOG_NTC
P
P
DEFAULT
DEFAULT
NTC_PEARL_VCSEL_TO_RIGEL
NTC_STOCKHOLM
Y
Y
C
ANALOG P DEFAULT COIL_TO_SPKRAMP_*_VSENSE_*, SOLENOID_TO_ARCAMP_VSENSE_* Y
Electrical PWR_MIC P PWR_DEFAULT PP_CODEC_TO_MIC*_BIAS*,RET_CODEC_FROM_MIC* Y
OVERRIDE
Spacing
DOMAIN
E_DP_GENERIC E GENERIC_DP DP:DP_CODEC_AOUT* Y

E_DP_GENERIC E GENERIC_DP DP:DP_MIC* Y DOMAIN

OVERRIDE
E_DP_GENERIC E GENERIC_DP DP:DP_PENROSE* Y S
ANALOG A_DIELECTRIC_1.5X = Y
E_DP_GENERIC E GENERIC_DP DP:DP_NTC_* Y
ANALOG_AMP_FILT S A_DIELECTRIC_1.5X = Y
E_DP_GENERIC E GENERIC_DP DP:DP_*MTR* Y
ANALOG_NTC S A_DIELECTRIC_1.5X = Y
E_DP_GENERIC E GENERIC_DP DP:DP_ANALOG*SENSE* Y
ANALOG_SAKONNET S A_DIELECTRIC_1.5X = Y
E_DP_GENERIC E GENERIC_DP DP:DP_ANALOG_VIN_SAKONNET_FROM_HALL* Y
PWR_MIC S DEFAULT = Y
E_DP_GENERIC E GENERIC_DP DP:DP_PMU_VDD_MAIN_SENSE* Y
E_DP_NC E GENERIC_DP DP:DP_NC* Y
E_DP_GENERIC E GENERIC_DP
Grouping Constraints
DP:DP_SHIELD_ETDAC_QET1 Y
Physical Physical Used to clean up CM

OVERRIDE
OVERRIDE
DOMAIN DOMAIN
DP_PWR P PWR_DP DP:DP_CODEC_AOUT* Y GRP_GPIO P DEFAULT GPIO*, IO_* Y

DP_MIC P GENERIC_DP DP:DP_*MIC* Y GRP_NC P DEFAULT NC_* Y
DP_PENROSE P GENERIC_DP DP:DP_PENROSE* Y GRP_I2C P DEFAULT I2C* Y
DP_NTC P GENERIC_DP DP:DP_NTC_* Y GRP_I2S P DEFAULT I2S*LRCLK*, I2S*BCLK*, I2S*DOUT*, I2S*DIN* Y
DP_GENERIC P GENERIC_DP DP:DP_*MTR* Y GRP_SPI P DEFAULT SPI*MOSI*, SPI*MISO*, SPI*CS* Y
B DP_GENERIC
DP_GENERIC
P
P
GENERIC_DP
GENERIC_DP
DP:DP_ANALOG*GPU_SENSE*
DP:DP_ANALOG*SOC_SENSE*
Y
Y
GRP_UART
GRP_SWD
P
P
DEFAULT
DEFAULT
UART*
SWD*
Y
Y
B
DP_PCPU_SENSE P GENERIC_DP DP:DP_ANALOG*PCPU_SENSE* Y GRP_SPMI_DATA P DEFAULT SPMI*DATA* Y
DP_SAKONNET P GENERIC_DP DP:DP_ANALOG_VIN_SAKONNET_FROM_HALL* Y GRP_PCIE_SIDE P DEFAULT PCIE*CLKREQ*, PCIE*PERST* Y
DP_GENERIC P GENERIC_DP DP:DP_PMU_VDD_MAIN_SENSE* Y GRP_LPDP_AUX P DEFAULT LPDP*AUX* Y
DP_NC P GENERIC_DP DP:DP_NC* Y GRP_RFFE_WLAN P DEFAULT RFFE_WLAN_* Y
DP_ETDAC_QET1 P GENERIC_DP DP:DP_SHIELD_ETDAC_QET1 Y GRP_RFFE_BB P DEFAULT SHIELD_RFFE* Y
GRP_CODEC_FILT P PWR_200UM CODEC_*FILTP,CODEC_*FILTN Y
Spacing Spacing
OVERRIDE
OVERRIDE
DOMAIN DOMAIN
DP_PWR S DEFAULT = Y GRP_GPIO S DEFAULT = Y

DP_MIC S A_DIELECTRIC_1.5X = Y GRP_NC S DEFAULT = Y
DP_PENROSE S A_DIELECTRIC_1.5X = Y GRP_I2C S DEFAULT = Y
DP_NTC S A_DIELECTRIC_1.5X = Y GRP_I2S S DEFAULT = Y
DP_SAKONNET S A_DIELECTRIC_1.5X = Y GRP_SPI S DEFAULT = Y
DP_PCPU_SENSE S A_DIELECTRIC_1.5X = Y GRP_UART S DEFAULT = Y
DP_GENERIC S DEFAULT = Y GRP_SWD S DEFAULT = Y
DP_NC S DEFAULT = Y GRP_SPMI_DATA S DEFAULT = Y
DP_ETDAC_QET1 S A_DIELECTRIC_1.5X = Y GRP_PCIE_SIDE S DEFAULT = Y
GRP_LPDP_AUX S DEFAULT = Y
Class-Class Spacing GRP_RFFE_WLAN S DEFAULT = Y
CLASS TO CLASS SPACING GRP_RFFE_BB S DEFAULT = Y
CLASS NAME CLASS NAME CONSTRAINT SET GRP_CODEC_FILT S DEFAULT = Y
DP_MIC DP_MIC DEFAULT
Class-Class Spacing
A DP_MIC
DP_MIC
GND
PWR_MIC
DEFAULT
DEFAULT CLASS TO CLASS SPACING SYNC_MASTER=temp SYNC_DATE=07/01/2019 A
PAGE TITLE
DP_MIC DP_SAKONNET DEFAULT CLASS NAME CLASS NAME CONSTRAINT SET
DP_MIC ANALOG_SAKONNET DEFAULT PWR_SHAPE_LX GND DEFAULT CONSTRAINTS: Misc.
DRAWING NUMBER SIZE
DP_SAKONNET DP_SAKONNET DEFAULT PWR_SHAPE_LX PWR_SHAPE_LX DEFAULT
051-05170 D
DP_SAKONNET
DP_SAKONNET
ANALOG_SAKONNET
GND
DEFAULT
DEFAULT
PWR_SHAPE_LX
PWR_SHAPE_LX
ANALOG
ANALOG_AMP_FILT
A_DIELECTRIC_3X
A_DIELECTRIC_3X
Apple Inc. REVISION
CLK GND DEFAULT PWR_SHAPE_LX ANALOG_NTC A_DIELECTRIC_3X 10.0.0

ANALOG GND DEFAULT PWR_SHAPE_LX ANALOG_SAKONNET A_DIELECTRIC_3X NOTICE OF PROPRIETARY PROPERTY: BRANCH
ANALOG_NTC GND DEFAULT PWR_SHAPE_LX CLK A_DIELECTRIC_3X THE INFORMATION CONTAINED HEREIN IS THE
crb-1
ANALOG_SAKONNET GND DEFAULT PWR_100UM_LX GND DEFAULT
ANALOG_AMP_FILT GND DEFAULT PWR_SHAPE_LX_DPMIC GND A_DIELECTRIC_3X
5 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
50 Thin 50 Wide 50 Wide, External Thin 50 Wide, L8 Thin 50 Wide, L6 Thin

HYBRID IMPEDANCE RULE HYBRID IMPEDANCE RULE HYBRID IMPEDANCE RULE HYBRID IMPEDANCE RULE HYBRID IMPEDANCE RULE
TRACE REFERENCE REQUIRED TRACE WIDTH TRACE REFERENCE REQUIRED TRACE WIDTH TRACE REFERENCE REQUIRED TRACE WIDTH TRACE REFERENCE REQUIRED TRACE WIDTH TRACE REFERENCE REQUIRED TRACE WIDTH
LAYER LAYER(s) IMPEDANCE (OPTIONAL) LAYER LAYER(s) IMPEDANCE (OPTIONAL) LAYER LAYER(s) IMPEDANCE (OPTIONAL) LAYER LAYER(s) IMPEDANCE (OPTIONAL) LAYER LAYER(s) IMPEDANCE (OPTIONAL)
RF SPACING VALUES= ? RF SPACING VALUES= ? RF SPACING VALUES= ? RF SPACING VALUES= ? RF SPACING VALUES= ?
RULE NAME= 50_THIN ZONE NAME= PRIMARY RULE NAME= 50_WIDE ZONE NAME= PRIMARY RULE NAME= 50_WIDE_SURFACE_THIN ZONE NAME= PRIMARY RULE NAME= 50_WIDE_L8_THIN ZONE NAME= PRIMARY RULE NAME= 50_WIDE_L6_THIN ZONE NAME= PRIMARY
ISL2 TOP,ISL3 50 0.029 ISL6 ISL4,ISL8 50 0.098 ISL6 ISL4,ISL8 50 0.098 ISL6 ISL4,ISL8 50 0.098 ISL6 ISL7,ISL5 50 0.038
ISL6 ISL7,ISL5 50 0.038 ISL7 ISL9,ISL5 50 0.092 ISL7 ISL9,ISL5 50 0.092 ISL7 ISL9,ISL5 50 0.092 ISL7 ISL9,ISL5 50 0.092
D
ISL8 ISL9,ISL7 50 0.029 ISL8 BOTTOM,ISL6 50 0.085 ISL8 BOTTOM,ISL6 50 0.085 ISL8 ISL9,ISL7 50 0.029 ISL8 BOTTOM,ISL6 50 0.085
D BOTTOM ISL9 50 0.057 BOTTOM ISL8 50 0.167 BOTTOM ISL9 50 0.057 BOTTOM ISL8 50 0.167 BOTTOM ISL8 50 0.167
50-ohm (Wide) Constraints 50-ohm Thin Overrides

Physical DOMAIN NET RULE ASSIGNMENT
OVERRIDE
(E,P,S)
DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N P A_50_THIN_SE 50_TRX_LB_PAD_ANT1_M
Cellular 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_ANT4* Y P A_50_THIN_SE 50_TRX_ANT3_L5
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_ANT7* Y P A_50_THIN_SE 50_TRX_DPLX_LB_LMB_MB_HB_ANT1
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_ANT9* Y P A_50_THIN_SE 50_TRX_ANT7_UHB_N79_M
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_LB_PAD_* Y P A_50_THIN_SE 50_TRX_ANT7_UHB_N79_L
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_IN_LMB_PAD_2G_LB_OUT_M Y P A_50_THIN_SE 50_TRX_ANT7_UHB_N79_NOTCH
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_LB_PORTB_RX1 Y P A_50_THIN_SE 50_TRX_ANT8_UHB_N79_L
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_LB_PORTB_RX1_M Y P A_50_THIN_SE 50_TRX_ANT8_UHB_N79_NOTCH
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_LB_PORTB_TX_M Y P A_50_THIN_SE 50_TRX_ANT9_UHB_N79_L
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_L5_LNA_IN,50_TRX_ANT3_L5 Y P A_50_THIN_SE 50_TRX_ANT9_UHB_N79_NOTCH
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_PAUHBL_UHB_ANT1_TO_ANT7_M Y P A_50_THIN_SE 50_TRX_CPLR_L_CPL2_ANT_LMB_MB_HB_M
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_PAUHBL_N79_ANT2_TO_ANT9* Y
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_UHB_PAD_PORTB_TX_M Y
DOMAIN NET RULE ASSIGNMENT
50_TRX_WIDE_L8_THIN P A_50_WIDE_L8_THIN_SE 50_TRX_UHB_PAD_N79_PORTB_TX_M Y (E,P,S)
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_UHB_PAD_PORTB_TX Y
S NA_DIELECTRIC_4XV_50_THIN_SE 50_TRX_LB_PAD_ANT1_M
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_CPLR_L_CPL2_IN_LB_LMB_MB_HB Y
S NA_DIELECTRIC_4XV_50_THIN_SE 50_TRX_ANT3_L5
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_HB_PAD_ANT1_M Y
S NA_DIELECTRIC_4XV_50_THIN_SE 50_TRX_DPLX_LB_LMB_MB_HB_ANT1
Arrow 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_R1_AOA1 Y
C C
S NA_DIELECTRIC_4XV_50_THIN_SE 50_TRX_ANT7_UHB_N79_M
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_R1_AOA2 Y
S NA_DIELECTRIC_4XV_50_THIN_SE 50_TRX_ANT7_UHB_N79_L
50_TRX_WIDE P A_50_WIDE_SE 50_R1_ANT* Y
S NA_DIELECTRIC_4XV_50_THIN_SE 50_TRX_ANT7_UHB_N79_NOTCH
50_TRX_WIDE P A_50_WIDE_SE 50_UWB_ANT* Y
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_ANT6_WLAN_A_LAA Y
WiFi 50_TRX_WIDE P A_50_WIDE_SE 50_R1_WLAN_A_LAA_M Y
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_ANT5_WLAN_A_LAA Y
50_TRX_WIDE P A_50_WIDE_SE 50_WLAN_A_LAA_DPLXR Y
S NA_DIELECTRIC_4XV_50_THIN_SE 50_TRX_CPLR_L_CPL2_ANT_LMB_MB_HB_M
50_TRX_WIDE P A_50_WIDE_SE 50_WLAN_A_LAA_BPF_M Y
50_TRX_WIDE P A_50_WIDE_SE 50_WLAN_A_LAA_BPF Y
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_PAUHBU_N79_ANT2_TO_ANT8* Y
Spacing
50-ohm (Hybrid) Constraints
Physical
DOMAIN
OVERRIDE
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N DOMAIN
OVERRIDE
50_TRX_WIDE S NA_DIELECTRIC_4XV_50_WIDE_SE = Y
50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_PAUHBL_UHB_ANT1_TO_ANT7 Y
50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_WLAN_A_C1_TXRX_FEM_M Y
Class-Class Spacing 50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_WLAN_G_BT_ANT3_NPLXR Y
CLASS TO CLASS SPACING 50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_PAUHBL_UHB_ANT2_TO_ANT9_M Y
CLASS NAME CLASS NAME CONSTRAINT SET 50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_CPLR_L_CPL2_ANT_LB_LMB_MB_HB Y
50_TRX_WIDE GND NA_DIELECTRIC_2X_50_WIDE_SE 50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_WLAN_G_BT_ANT3_NPLXR_M Y
50_TRX_WIDE_SURFACE_THIN GND NA_DIELECTRIC_2X_50_WIDE_SURFACE_THIN_SE 50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_R1_ANT2_CH9 Y
50_TRX_WIDE_L8_THIN GND NA_DIELECTRIC_2X_50_WIDE_L8_THIN_SE 50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_ANT8_UHB_N79_M Y
50_TRX_WIDE_L6_THIN GND NA_DIELECTRIC_2X_50_WIDE_L6_THIN_SE 50_TRX_WIDE_L8_THIN P A_50_WIDE_L8_THIN_SE 50_TRX_CPLR_L_CPL3_ANT_LMB_MB_HB Y
50_TRX_WIDE_L8_THIN P A_50_WIDE_L8_THIN_SE 50_TRX_LB_PORTB_TX_ANT2 Y
B 50_TRX_WIDE_L8_THIN P A_50_WIDE_L8_THIN_SE 50_TRX_PAUHBL_UHB_ANT2_TO_ANT9 Y B
50_TRX_WIDE_L8_THIN P A_50_WIDE_L8_THIN_SE 50_WLAN_A_LAT_TXRX_FEM
50-ohm (Thin) Constraints
Y
50_TRX_WIDE_L8_THIN P A_50_WIDE_L8_THIN_SE 50_TRX_ANT1_LB_LMB_MB_HB Y
50_TRX_WIDE_L8_THIN P A_50_WIDE_L8_THIN_SE 50_TRX_ANT8_R1_UHB_N79 Y
Physical 50_TRX_WIDE_L8_THIN P A_50_WIDE_L8_THIN_SE 50_WLAN_A_LAA_DPLXR_M Y
OVERRIDE
50_TRX_WIDE_L8_THIN P A_50_WIDE_L8_THIN_SE 50_TRX_R1_ANT2_CH5 Y
DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N 50_TRX_WIDE_L6_THIN P A_50_WIDE_L6_THIN_SE 50_LAA_RX_XCVR_DRX10 Y
Wildcards 50_RX_THIN P A_50_THIN_SE 50_RX_* Y 50_TRX_WIDE_L6_THIN P A_50_WIDE_L6_THIN_SE 50_TRX_PAUHBU_UHB_ANT2_TO_ANT8_M Y
50_RX_THIN P A_50_THIN_SE 50_LAA_RX_XCVR_PRX12 Y
Direct Net 50_TX0_TX1_THIN P A_50_THIN_SE 50_TX_IN_XCVR_TX0_LB Y Spacing
50_TX0_THIN P A_50_THIN_SE 50_TX_IN_TX0_LB_PAD_TX_LB_IN Y
50_TX0_TX1_THIN P A_50_THIN_SE 50_TX_IN_XCVR_TX1_LB_JB Y DOMAIN

OVERRIDE
50_TX1_THIN P A_50_THIN_SE 50_TX_IN_XCVR_TX1_LB_JB_M Y NA_DIELECTRIC_4XV_50_WIDE_SURFACE_THIN_SE
50_TRX_WIDE_SURFACE_THIN S = Y
50_TX2_THIN P A_50_THIN_SE 50_TX_IN_TX2_UHB_PAD_TX_UHB_IN_1 Y NA_DIELECTRIC_4XV_50_WIDE_L8_THIN_SE
50_TRX_WIDE_L8_THIN S = Y
50_TX2_THIN P A_50_THIN_SE 50_TX_IN_TX2_UHB_PAD_TX_N79_IN Y NA_DIELECTRIC_4XV_50_WIDE_L6_THIN_SE
50_TRX_WIDE_L6_THIN S = Y
50_RX_THIN P A_50_THIN_SE 50_L5_LNA_NOTCH1 Y
50_TRX_THIN P A_50_THIN_SE 50_UHB_L_CPLR_OUT Y
50_TRX_THIN P A_50_THIN_SE 50_WLAN_A_C0_TXRX_FEM_M Y (Thin) Class-Class Spacing
50_TRX_THIN P A_50_THIN_SE 50_WLAN_A_UAT_TXRX_FEM Y
CLASS TO CLASS SPACING
50_TRX_THIN P A_50_THIN_SE 50_TRX_ANT2_LB_LMB_MB_HB_L1 Y
CLASS NAME CLASS NAME CONSTRAINT SET
50_TRX_THIN P A_50_THIN_SE 50_TRX_R1_AOA3 Y
Same Class 50_TX0_THIN 50_TX0_THIN NA_DIELECTRIC_2X_50_THIN_SE
50_TRX_THIN P A_50_THIN_SE 50_TRX_UHB_PAD_N79_PORTB_TX Y
50_TX0_TX1_THIN 50_TX0_TX1_THIN DEFAULT
50_TRX_THIN P A_50_THIN_SE 50_WLAN_A_LAA_ANT5_B2B_M Y
50_TX1_THIN 50_TX1_THIN NA_DIELECTRIC_2X_50_THIN_SE
Spacing 50_TX2_THIN 50_TX2_THIN NA_DIELECTRIC_2X_50_THIN_SE
50_RX_THIN 50_RX_THIN NA_DIELECTRIC_2X_50_THIN_SE
A
GND 50_TX0_THIN GND NA_DIELECTRIC_2X_50_THIN_SE

A
OVERRIDE
DOMAIN
SYNC_DATE=07/01/2019
50_TX0_TX1_THIN GND NA_DIELECTRIC_2X_50_THIN_SE
50_TX_IN_THIN S NA_DIELECTRIC_4XV_50_THIN_SE = Y PAGE TITLE
50_TX1_THIN GND NA_DIELECTRIC_2X_50_THIN_SE
50_TX0_THIN S NA_DIELECTRIC_4XV_50_THIN_SE = Y
50_TX2_THIN GND NA_DIELECTRIC_2X_50_THIN_SE CONSTRAINTS: 50-Ohm
50_TX0_TX1_THIN S NA_DIELECTRIC_4XV_50_THIN_SE = Y DRAWING NUMBER SIZE
50_RX_THIN GND NA_DIELECTRIC_2X_50_THIN_SE
50_TX1_THIN S NA_DIELECTRIC_4XV_50_THIN_SE = Y 051-05170 D
50_TX2_THIN S NA_DIELECTRIC_4XV_50_THIN_SE = Y
TX <-> TX
50_TRX_THIN
50_TX0_THIN
GND
50_TX0_TX1_THIN
NA_DIELECTRIC_2X_50_THIN_SE
NA_DIELECTRIC_4XV_50_THIN_SE
Apple Inc. REVISION
50_RX_THIN S NA_DIELECTRIC_4XV_50_THIN_SE = Y
50_TX0_THIN 50_TX1_THIN NA_DIELECTRIC_4XV_50_THIN_SE 10.0.0
50_TRX_THIN S NA_DIELECTRIC_4XV_50_THIN_SE = Y NOTICE OF PROPRIETARY PROPERTY: BRANCH
50_TX0_THIN 50_TX2_THIN NA_DIELECTRIC_4XV_50_THIN_SE
50_TX1_THIN 50_TX0_TX1_THIN NA_DIELECTRIC_4XV_50_THIN_SE THE INFORMATION CONTAINED HEREIN IS THE
crb-1
50_TX1_THIN 50_TX2_THIN NA_DIELECTRIC_4XV_50_THIN_SE
50_TX2_THIN 50_TX0_TX1_THIN NA_DIELECTRIC_4XV_50_THIN_SE
6 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOOTSTRAPPING
BOARD REV + BOARD ID + BOOT CONFIG
D D
R0723
GPIO_BOARD_REV3 1
1.00K 2 OMIT_TABLE PP1V2_IO
19 OUT 17 30
5%
1/32W
MF
01005
ROOM=SOC
Board Rev [3:0]
R0722 * Float = 0 | PU = 1
GPIO_BOARD_REV2 1
1.00K 2 OMIT_TABLE
19 OUT Note: iBoot uses the inverse of BOARD_REV[3:0], so that it counts up (Pre-Proto = 0x0, PVT = 0xF)
5% TABLE_5_HEAD
1/32W BOARD_REV[3:0] [3] [2] [1] [0] PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
MF
01005 TABLE_5_ITEM
ROOM=SOC Pre-Proto 4'b1111 1 1 1 1 117S0156 4 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0722,R0721,R0720 BOARD_REV:PROTO0 PROTO0

R0721 Proto 1 4'b1110 1 1 1 0 117S0156 3 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0722,R0721 BOARD_REV:PROTO1
TABLE_5_ITEM
PROTO1
GPIO_BOARD_REV1 1
1.00K 2 OMIT_TABLE
19 OUT
TABLE_5_ITEM
5%
Proto 1.5 4'b1101 1 1 0 1 117S0156 3 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0722,R0720 BOARD_REV:PROTO1.5 PROTO1.5
1/32W TABLE_5_ITEM
MF Proto 2 4'b1100 1 1 0 0 117S0156 2 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0722 BOARD_REV:PROTO2 PROTO2

C
01005
ROOM=SOC
Proto 2.5 4'b1011 1 0 1 1 117S0156 3 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0721,R0720 BOARD_REV:PROTO2.5
TABLE_5_ITEM
PROTO2.5 C
R0720 TABLE_5_ITEM
GPIO_BOARD_REV0 1
1.00K 2 OMIT_TABLE Pre-EVT 4'b1010 1 0 1 0 117S0156 2 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0721 BOARD_REV:PRE-EVT PRE-EVT
19 OUT TABLE_5_ITEM
5%
1/32W
EVT 4'b1001 1 0 0 1 117S0156 2 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0720 BOARD_REV:EVT EVT
MF TABLE_5_ITEM
01005
ROOM=SOC Carrier 4'b1000 1 0 0 0 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0723 BOARD_REV:CRB CRB
TABLE_5_ITEM
(Allocate more as necessary in descending order) 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0720 BOARD_REV:DVT DVT
DVT 4'b0001 0 0 0 1 (PVT NOSTUFF ALL)
PVT 4'b0000 0 0 0 0
5 OUT
NC_GPIO_BOARD_ID4 NC_GPIO_BOARD_ID4
MAKE_BASE=TRUE
NO_TEST=1
XW0711 Board ID [4:0]

SHORT-20L-0.05MM-SM * Float = 0 | PU = 1
5 OUT GPIO_BOARD_ID3 GPIO_BOARD_ID3 2 1 TABLE_5_HEAD
MAKE_BASE=TRUE BOARD_ID[4:0] [4] Unused [3] 1=MAV20 [2] [1] [0] 0=MLB, 1=DEV PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
OMIT
ROOM=SOC TABLE_5_ITEM
MLB D52G 5'b01010 0 1 0 1 0 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0712 BOARD_ID:D52 D52 = 01

TABLE_5_ITEM
DEV D52G 5'b01011 0 1 0 1 1 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0713 BOARD_ID:D53G D53G = 10

R0713 TABLE_5_ITEM
GPIO_BOARD_ID2 GPIO_BOARD_ID2 1
1.00K 2 OMIT_TABLE 117S0156 2 RES,MF,1K OHM,5%,1/32W,01005 R0713,R0712 BOARD_ID:D53P D53P = 11
97 5 OUT MLB D53G 5'b01100 0 1 1 0 0
MAKE_BASE=TRUE
D54 = 00
B
5%
B
(D54 both NOSTUFF)
1/32W DEV D53G 5'b01101 0 1 1 0 1
MF
01005
ROOM=SOC
MLB D53P 5'b01110 0 1 1 1 0
R0712
1.00K 2 OMIT_TABLE DEV D53P 5'b01111 0 1 1 1 1
97 5 OUT
MAKE_BASE=TRUE
5%
1/32W MLB D54P 5'b01000 0 1 0 0 0
MF
01005
ROOM=SOC DEV D54P 5'b01001 0 1 0 0 1
5 OUT
MAKE_BASE=TRUE
Boot Config [2:0]

* Float = 0 | PU = 1
USAGE SPEED TEST [2] [1] [0]
SPI1 NOR -- 12MHz -- 0 0 0

22 20
96 OUT
SPI0_AP_FROM_S5E_MISO_BOOT_CONFIG2 No Connect
SPI1 NOR -- 12MHz Test 0 0 1
SPI0 NAND POR 12MHz -- 0 1 0 <-- POR

SPI0 NAND Proto 12MHz Test 0 1 1 <-- Proto Builds
R0701
SPI0_AP_TO_S5E_MOSI_BOOT_CONFIG1 1
4.7K 2
SPI1 NOR -- 24MHz -- 1 0 0
22 20 OUT
1% SPI1 NOR -- 24MHz Test 1 0 1
A A
1/32W
MF
01005 SPI1 NOR -- 6MHz -- 1 1 0 SYNC_MASTER= SYNC_DATE=
ROOM=NAND PAGE TITLE
R0700
SPI1 NOR -- 6MHz Test 1 1 1
SYSTEM: Bootstrapping
SPI0_AP_TO_S5E_SCLK_BOOT_CONFIG0 1
4.7K 2
NOSTUFF DRAWING NUMBER SIZE
<--- Remove at EVT
22 20 OUT
051-05170 D
1%
1/32W Apple Inc. REVISION
MF
01005
ROOM=NAND
10.0.0

crb-1
7 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Conventions:
1. Nets which are not connected on FFs but probed out on dev board should start with "NC_DEV_"
2. Nets that contain "_1V8" are 1.8V logic, all other nets are implied 1.2V logic
3. Components with PACK_IGNORE=TRUE will not be included in the netlist
D D
SHIELDS
CRITICAL
1
SH0800
SM
806-23495
SHLD-TTS-MLB-SOUTH-D54
1
SB0801
STDOFF-2.56OD1.4ID-0.855H-SM
860-01491
ROOM=MECHANICAL
CRITICAL
SB0802 1
1
STDOFF-2.56OD1.4ID-0.855H-SM SH0801
860-01491 SM
ROOM=MECHANICAL
806-26434
SHLD-TTS-MLB-MID-TALL-D54
C 1
CRITICAL
C
SH0802
SM
806-23493
SHLD-TTS-MLB-NORTH-D54
FD0800 FD0810
FID
0P5SQ-CROSS-NSP
1
FID
0P5SQ-SMP3SQ-NSP
1
SOC UF NAND UF
CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED
998-04808 998-00557
ROOM=ASSEMBLY ROOM=ASSEMBLY R0800 R0805
FD0801 FD0811 1
0.00 2 1
0.00 2
FID FID 0% 0%
0P5SQ-CROSS-NSP 0P5SQ-SMP3SQ-NSP 1/32W 1/32W
1 1 MF MF
01005 01005
ROOM=DFM ROOM=DFM
998-04808 998-00557 CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED
R0801 R0806
ROOM=ASSEMBLY ROOM=ASSEMBLY
FD0802 FD0812 0.00 0.00

FID FID 1 2 1 2
0P5SQ-CROSS-NSP 0P5SQ-SMP3SQ-NSP 0% 0%
1 1 1/32W 1/32W
MF MF
01005 01005
998-04808 998-00557 ROOM=DFM ROOM=DFM
B B
ROOM=ASSEMBLY ROOM=ASSEMBLY CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED
FD0803 FD0813 R0802 R0809 R0807

FID FID 1
0.00 2 1
0.00 2 1
0.00 2
1
SB0803 0P5SQ-CROSS-NSP
1
0P5SQ-SMP3SQ-NSP
1 0% 0% 0%
STDOFF-2.56OD1.4ID-0.855H-SM 1/32W 1/32W 1/32W
860-01491 MF MF MF
ROOM=MECHANICAL 998-04808 998-00557 01005 01005 01005
ROOM=ASSEMBLY ROOM=ASSEMBLY ROOM=DFM ROOM=DFM ROOM=DFM
FD0804 FD0814
CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED
FID FID R0803 R0810 R0808

0P5SQ-CROSS-NSP 0P5SQ-SMP3SQ-NSP 1
0.00 2 1
0.00 2 1
0.00 2
1
SB0804 1 1
0% 0% 0%
STDOFF-2.56OD1.4ID-0.855H-SM 1/32W 1/32W 1/32W
860-01491 998-04808 998-00557 MF MF MF
ROOM=MECHANICAL ROOM=ASSEMBLY ROOM=ASSEMBLY 01005 01005 01005
ROOM=DFM ROOM=DFM ROOM=DFM
FD0805 FD0815 CKPLUS_WAIVE=TERMSHORTED
FID
0P5SQ-CROSS-NSP
FID
0P5SQ-SMP3SQ-NSP
R0804
1 1 1
0.00 2
SB0805
0%
998-04808 998-00557 1/32W
1 ROOM=ASSEMBLY ROOM=ASSEMBLY MF
STDOFF-2.56OD1.4ID-0.855H-SM 01005
860-01491 ROOM=DFM
ROOM=MECHANICAL
Interposer Spacers
RefDes called out below
A PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD
A
PAGE TITLE
SYSTEM: Mechanical
TABLE_5_ITEM
870-03604 20 SPACER,INTERPOSER,SMALL,X891 CRITICAL ?

SP0801,SP0802,SP0803,SP0804,SP0805,SP0806,SP0807,SP0808,SP0809,SP0810,SP0811,SP0812,SP0813,SP0814,SP0815,SP0816,SP0817,SP0818,SP0819,SP0820
DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0

crb-1
8 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC 24M XTAL Alternates

4GB DRAM
TABLE_ALT_HEAD

PART NUMBER
TABLE_5_HEAD

TABLE_ALT_ITEM
TABLE_5_ITEM
197S0612 197S00118 ? Y1000 XTAL, 24M, 1612
998-22473 1 Sicily,B1,4GB,M U1000 CRITICAL BOARD_ID:D52&BOARD_ID:D53G

TABLE_ALT_ITEM
197S00120 197S00118 ? Y1000 XTAL, 24M, 1612

TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
998-22472 998-22473 BOARD_ID:D52&BOARD_ID:D53G U1000 Sicily,B1,4GB,H
D 998-22471 998-22473 BOARD_ID:D52&BOARD_ID:D53G U1000 Sicily,B1,4GB,S

TABLE_ALT_ITEM
D
6GB DRAM
TABLE_5_HEAD

TABLE_5_ITEM
998-22474 1 Sicily,B1,6GB,M U1000 CRITICAL BOARD_ID:D53P&BOARD_ID:D54
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
998-22475 998-22474 BOARD_ID:D53P&BOARD_ID:D54 U1000 Sicily,B1,6GB,H

TABLE_ALT_ITEM
998-22476 998-22474 U1000 Sicily,B1,6GB,S
SOC: Misc
BOARD_ID:D53P&BOARD_ID:D54
998-22473
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 1 OF 21
OMIT_TABLE
3 IN
GPIO_BOARD_ID0 CN11 BOARD_ID0 THROTTLE_TRIGGER0 BJ61 NC_DEV_SOC_THROTTLE_TRIGGER0 20
97 3 IN
GPIO_BOARD_ID1 CM15 BOARD_ID1 THROTTLE_TRIGGER1 BJ60 IO_AP_FROM_PMU_SW_SHDN_L IN 20
GPIO_BOARD_ID2 CP9 BOARD ID
BG62 THROTTLE_TRIGGER[0:4]:
97 3 IN BOARD_ID2 THROTTLE_TRIGGER2 IO_AP_FROM_PMU_PRE_UVLO_L IN 20
GPIO_BOARD_ID3 CJ62 BG61 These need an internal pull-up enabled on SoC
3 IN BOARD_ID3 THROTTLE_TRIGGER3 NC_DEV_SOC_THROTTLE_TRIGGER3 20
3 IN
NC_GPIO_BOARD_ID4 CP11 BOARD_ID4 THROTTLE_TRIGGER4 BE62 NC_DEV_SOC_THROTTLE_TRIGGER4 20
REQUEST_DFUx: Legacy button detection BK61

PP1V2_IO REQUEST_DFU1 THROTTLERS
C
20
BE61 IO_SOC_TO_PMU_SOCHOT_RESET_L
C MLB: Hard tie to PP1V2_IO
DEV: Wire to PMU BUTTONO
20 PP1V2_IO BJ62 REQUEST_DFU2
SOCHOT1
CP15 SWD_AP_TO_MANY_SWCLK
OUT 20 96
IO_SOC_FROM_PMU_KRAKEN_FORCE_DFU AN60 DFU SWD_TCK_OUT1 OUT 22 99 101

94 20 IN FORCE_DFU
96 IO_SOC_DFU_STATUS BK62 DFU_STATUS SWD_TMS2 CN15 SWD_AP_BI_NAND_SWDIO 22 96
OUT BI
SWD_TMS3 CP13 SWD_AP_BI_BB_SWDIO Clocked by SWD_TCK_OUT1
NC_DEV_AP_TMR32_PWM0 AG3 FPWM0
BI 99
20
SWD_TMS4 CK62 SWD_AP_BI_R1_SWDIO
PP (dev board only) 20 NC_DEV_AP_TMR32_PWM1 AG2 FPWM1
BI 101
FPWM MISC
NC_DEV_AP_TMR32_PWM2 AJ3 FPWM2 TST_CLKOUT BE60 CLK_AP_TO_PMU_TST_CLKOUT
20 OUT 20 96
PP0V6_VDDQL_S1
ANALOGMUX_OUT CN3 AMUX_SOC_TO_PMU_AMUX_OUT 30
96 IO_PAD_MTR_ANALOG_TEST_P CB60 PAD_MTR_ANALOG_TEST_P

OUT 20
OUT
96 OUT
IO_PAD_MTR_ANALOG_TEST_N CB61 PAD_MTR_ANALOG_TEST_N CFSB CL7
F5
IO_PMU_TO_SOC_KRAKEN_ACTIVE_READY IN 30
1
R1010 1
R1011 1
R1012 1
R1013 1
R1014 1
R1015
CFSB_XTAL IO_AON_TO_AP_XTAL_CFSB IN 20 240 240 240 240 240 240
1% 1% 1% 1% 1% 1%
AG60 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W
MTR HOLD_RESET GND 20 MF MF MF MF MF MF
AF62 01005 2 01005 01005 01005 01005 01005
CD60 TESTMODE GND 2ROOM=SOC ROOM=SOC 2ROOM=SOC 2ROOM=SOC 2ROOM=SOC 2ROOM=SOC
20 NC_DEV_PAD_MTR_VREF_P PAD_MTR_VREF_P
20
PP (dev board only) CD61 CJ3

20 NC_DEV_PAD_MTR_VREF_N PAD_MTR_VREF_N DDR0_RREF ANALOG_DDR0_RREF
DDR0_ZQ BM2 ANALOG_DDR0_ZQ
DDR1_RREF BV60 ANALOG_DDR1_RREF
DDR2_RREF K3 ANALOG_DDR2_RREF
DDR DDR3_RREF Y61 ANALOG_DDR3_RREF
DDR3_ZQ AB62 ANALOG_DDR3_ZQ
LP4_IN_RESET* V60 IO_PMU_TO_SYSTEM_RESET_L 20
IN
XI0 E9 CLK_AP_XTAL_24M_IN
XTAL XO0 D9 CLK_AP_XTAL_24M_OUT 197S00118
CRITICAL
ROOM=SOC_XTAL
Y1000
R1021 1.60X1.20MM-SM
B 1
499 2 CLK_AP_XTAL_24M_OUT_R
24MHZ-30PPM-9.5PF-60OHM
1 3
B
1% NC GND
1/32W
1 C1020 C1021 1
4
2
MF
01005
ROOM=SOC_XTAL
12PF 12PF
5% 5%
2 16V
NP0-C0G
16V
NP0-C0G 2
01005-1
ROOM=SOC_XTAL
01005-1
ROOM=SOC_XTAL
SOC_XTAL_GND
SOC: NAND + USB 2

XW1000
SHORT-20L-0.05MM-SM
OMIT
NO_XNET_CONNECTION
998-22473
U1000
ROOM=SOC_XTAL
ROOM=SOC
SICILY-4GB-1YNM-M
CSP
SYM 2 OF 21
R1001 OMIT_TABLE
CLK_AP_TO_NAND_24M 2
33.2 1 CLK_AP_TO_NAND_24M_R AR2 A28 90_EUSB_PARROT_BI_AP_P
22 OUT NAND_SYS_CLK USB_EDP BI 73 96
1% USB_EDM B28 90_EUSB_PARROT_BI_AP_N

1/32W 96 22 OUT
IO_AP_TO_NAND_RESET_L AJ62 SSD_RESET* NAND - IOS USB
BI 73 96
MF
01005 96 22 OUT
IO_AP_TO_NAND_FW_STRAP AL60 SSD_BFH USB_RESREF D28 ANALOG_SOC_USB_RESREF
ROOM=SOC
EUSB_VBUS_DETECT AG61 PP1V2_IO IN 20

1
R1002
200
1%
1/32W
MF
01005
SYNCING: D52, D53, D54
2ROOM=SOC
A A
PAGE TITLE
SOC: NAND + USB & Misc

DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0

crb-1
10 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: PCIe 30 6 PP1V2_IO
D 998-22473 1
R1100 D
ROOM=SOC U1000 5%
47.0K
SICILY-4GB-1YNM-M 1/32W
CSP MF
01005
2 ROOM=SOC
SYM 3 OF 21
OMIT_TABLE
20 NC_DEV_PCIE_GP0_AP_CLKREQ_L CB3 GP_PCIE_CLKREQ0* ST_PCIE_CLKREQ0* CB2 PCIE_ST0_AP_BI_NAND_CLKREQ_L 22
BI
NC_DEV_PCIE_GP0_AP_RX_P B15 B11 90_PCIE_ST0_AP_FROM_NAND_C_RX_P
PCIE GEN4 - ST LINK 0

20 GP_PCIE_RX0_P ST_PCIE_RX0_P IN 21
NC_DEV_PCIE_GP0_AP_RX_N A15 A11 90_PCIE_ST0_AP_FROM_NAND_C_RX_N RX CAPS LIVE OFF-PAGE
20 GP_PCIE_RX0_N ST_PCIE_RX0_N IN 21
LINK0
GND_VOID
C1102
ROOM=SOC
1 2 0.22UF
20
NC_DEV_PCIE_GP0_AP_TX_P C17 GP_PCIE_TX0_P ST_PCIE_TX0_P C13 90_PCIE_ST0_AP_TO_NAND_C_TX_P CER-X5R 10% 6.3V 01005
90_PCIE_ST0_AP_TO_NAND_TX_P 22
OUT
GND_VOID
NC_DEV_PCIE_GP0_AP_TX_N D17 GP_PCIE_TX0_N ST_PCIE_TX0_N D13 90_PCIE_ST0_AP_TO_NAND_C_TX_N 90_PCIE_ST0_AP_TO_NAND_TX_N
C1103
20 ROOM=SOC OUT 22
1 2 0.22UF
CER-X5R 10% 6.3V 01005
C CF2 CD3
C
20 NC_DEV_PCIE_GP0_AP_RESET_L GP_PCIE_PERST0* ST_PCIE_PERST0* PCIE_ST0_AP_TO_NAND_PERST_L OUT 22
30 6 PP1V2_IO
1
R1130
1
R1101
47.0K
47.0K 5%
5% 1/32W
1/32W MF
MF 01005
2 ROOM=SOC
01005
2 ROOM=SOC
98 BI
PCIE_GP1_AP_BI_WLAN_CLKREQ_L CB4 GP_PCIE_CLKREQ1* GP_PCIE_CLKREQ2* CD2 PCIE_GP2_AP_BI_BB_CLKREQ_L BI 99
BB CLKREQ PULL-UP LIVES IN RADIO HIERARCHY
21 IN
90_PCIE_GP1_AP_FROM_WLAN_C_RX_P B19 GP_PCIE_RX1_P GP_PCIE_RX2_P B22 90_PCIE_GP2_AP_FROM_BB_RX_P 21
IN
RX CAPS LIVE OFF-PAGE
PCIE GEN4 - LINK 2

90_PCIE_GP1_AP_FROM_WLAN_C_RX_N A19 GP_PCIE_RX1_N GP_PCIE_RX2_N A22 90_PCIE_GP2_AP_FROM_BB_RX_N RX CAPS LIVE OFF-PAGE
PCIE GEN2 - LINK 1
21 IN IN 21
LINK1
LINK2
GND_VOID GND_VOID
C1112 C1122
ROOM=SOC ROOM=SOC
1 2 0.1UF 1 2 0.22UF
X5R-CERM 20% 6.3V 01005 C21 C24 CER-X5R 10% 6.3V 01005
98 OUT
90_PCIE_GP1_AP_TO_WLAN_TX_P 90_PCIE_GP1_AP_TO_WLAN_C_TX_P GP_PCIE_TX1_P GP_PCIE_TX2_P 90_PCIE_GP2_AP_TO_BB_C_TX_P 90_PCIE_GP2_AP_TO_BB_TX_P OUT 99
GND_VOID GND_VOID
90_PCIE_GP1_AP_TO_WLAN_TX_N 90_PCIE_GP1_AP_TO_WLAN_C_TX_N D21 GP_PCIE_TX1_N GP_PCIE_TX2_N D24 90_PCIE_GP2_AP_TO_BB_C_TX_N 90_PCIE_GP2_AP_TO_BB_TX_N
C1113 C1123
98 OUT ROOM=SOC ROOM=SOC OUT 99
1 2 0.1UF 1 2 0.22UF
X5R-CERM 20% 6.3V 01005 CER-X5R 10% 6.3V 01005
B B
98 OUT
PCIE_GP1_AP_TO_WLAN_PERST_L CF4 GP_PCIE_PERST1* GP_PCIE_PERST2* CF3 PCIE_GP2_AP_TO_BB_PERST_L OUT 99
R1131 1 R1121 1
100K 100K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
ANALOG_PCIE_RCAL_POS E19 PCIE_RCAL_P GP_PCIE_REF_CLK0_P A7 NC_DEV_PCIE_GP0_AP_REFCLK_P 20
NO_XNET_CONNECTION=1 GP_PCIE_REF_CLK0_N B7 NC_DEV_PCIE_GP0_AP_REFCLK_N 20

1
R1140 GP_PCIE_REF_CLK1_P B5 90_PCIE_GP1_AP_TO_WLAN_REFCLK_P OUT 98
200 A5 90_PCIE_GP1_AP_TO_WLAN_REFCLK_N
1% GP_PCIE_REF_CLK1_N OUT 98
1/32W
MF B4
01005
2 ROOM=SOC GP_PCIE_REF_CLK2_P 90_PCIE_GP2_AP_TO_BB_REFCLK_P OUT 99
GP_PCIE_REF_CLK2_N A4 90_PCIE_GP2_AP_TO_BB_REFCLK_N
ANALOG_PCIE_RCAL_NEG F19 PCIE_RCAL_N
OUT 99
ST_PCIE_REF_CLK0_P B6 90_PCIE_ST0_AP_TO_NAND_REFCLK_P 22 96
OUT
1 C1140 ST_PCIE_REF_CLK0_N A6 90_PCIE_ST0_AP_TO_NAND_REFCLK_N OUT 22 96
10PF
5%
16V
2 NP0/C0G
01005
SYNCING: D52, D53, D54, DEV

ROOM=SOC
A A
PAGE TITLE
SOC: PCIE
DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0

crb-1
11 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
DO NOT SWIZZLE LPDP LANES UNLESS ROUTING NECESSITATES IT

LPDP Swizzle Options:
-P/N can be switched
-Non-sequential lanes can be grouped
(e.g. FCAM 0 -> SOC 5, FCAM 1 -> SOC 2)
SOC: ISP
998-22473
-AUX pin (one per device) doesn't have to match lane numbers
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 4 OF 21
OMIT_TABLE
21 90_LPDP_ISP_FROM_WIDE_RX_D0_N CP19 LPDPRX_RX_D0_P MIPI0C_DPCLK CP60 90_MIPI_ISP_FROM_IRCAM_CLK_P 82
IN IN
21 90_LPDP_ISP_FROM_WIDE_RX_D0_P CN19 LPDPRX_RX_D0_N MIPI0C_DNCLK CN60 90_MIPI_ISP_FROM_IRCAM_CLK_N 82
IN IN
21 90_LPDP_ISP_FROM_WIDE_RX_D1_N CN21 LPDPRX_RX_D1_P MIPI0C_DPDATA0 CN58 90_MIPI_ISP_FROM_IRCAM_D0_P 82

IN BI
MIPI-C
21 90_LPDP_ISP_FROM_WIDE_RX_D1_P CM21 LPDPRX_RX_D1_N MIPI0C_DNDATA0 CP58 90_MIPI_ISP_FROM_IRCAM_D0_N 82
IN BI
21 90_LPDP_ISP_FROM_WIDE_RX_D2_N CP22 LPDPRX_RX_D2_P MIPI0C_DPDATA1 CN59 90_MIPI_ISP_FROM_IRCAM_D1_P 82

IN IN
21 90_LPDP_ISP_FROM_WIDE_RX_D2_P CN22 LPDPRX_RX_D2_N MIPI0C_DNDATA1 CP59 90_MIPI_ISP_FROM_IRCAM_D1_N 82
IN IN
21 90_LPDP_ISP_FROM_FCAM_RX_D0_N CP26 LPDPRX_RX_D3_P MIPI0C_REXT CL55 ANALOG_MIPI_ISP_REXT

IN
90_LPDP_ISP_FROM_FCAM_RX_D0_P CN26 LPDPRX_RX_D3_N 1
R1250
21 IN
ISP_I2C0_SCL CL58 NC_I2C0_ISP_SCL
90_LPDP_ISP_FROM_FCAM_RX_D1_N CN28 LPDPRX_RX_D4_P
17
200
21 IN
ISP_I2C0_SDA CL57 NC_I2C0_ISP_SDA 1%
C
90_LPDP_ISP_FROM_FCAM_RX_D1_P CM28 17
C 21 IN
90_LPDP_ISP_FROM_TELE_RX_D0_P CP30
LPDPRX_RX_D4_N
ISP_I2C1_SCL CM6 NC_I2C1_ISP_SCL 17
PP (dev board only)
1/32W
MF
2 01005
LPDPRX_RX_D5_P CM4
Note: LPDP RX and AUX lanes need a series 0.1uF cap
21 IN
CN30 ISP_I2C1_SDA NC_I2C1_ISP_SDA ROOM=SOC
90_LPDP_ISP_FROM_TELE_RX_D0_N LPDPRX_RX_D5_N
17
I2C
21 IN
21 90_LPDP_ISP_FROM_TELE_RX_D1_P CN32 LPDPRX_RX_D6_P

IN
21 90_LPDP_ISP_FROM_TELE_RX_D1_N CM32 LPDPRX_RX_D6_N
IN
90_LPDP_ISP_FROM_TELE_RX_D2_P CP34 LPDPRX_RX_D7_P
LPDP-RX
21 IN
21 90_LPDP_ISP_FROM_TELE_RX_D2_N CN34 LPDPRX_RX_D7_N
IN
21 90_LPDP_ISP_FROM_SWIDE_RX_D2_N CN36 LPDPRX_RX_D8_P ISP_GPIO_0 CK59 GPIO_ISP_TO_CAM_PMU1_CAM_PMU2_RESET_L 43 46

IN OUT
21 90_LPDP_ISP_FROM_SWIDE_RX_D2_P CM36 LPDPRX_RX_D8_N ISP_GPIO_1 CM7 NC_ISP_GPIO_1 20
IN
ISP_GPIO_2 CL59 NC_ISP_GPIO_2
90_LPDP_ISP_FROM_SWIDE_RX_D0_P CN40 LPDPRX_RX_D9_P
20
21 IN
ISP_GPIO_3 CN5 GPIO_ISP_RCAM_TO_STROBE_KRAKEN_WLAN_FLASH_TRIG
90_LPDP_ISP_FROM_SWIDE_RX_D0_N CM40 OUT 70 75 98
GPIO
21 IN LPDPRX_RX_D9_N
External flash trigger:
21 90_LPDP_ISP_FROM_SWIDE_RX_D1_N CP42 LPDPRX_RX_D10_P Kraken sends signal to Lightning accessory
IN
21 90_LPDP_ISP_FROM_SWIDE_RX_D1_P CN42 LPDPRX_RX_D10_N
IN
90_LPDP_ISP_FROM_JASPER_RX_D0_P CN43 LPDPRX_RX_D11_P

R1240
21 IN
21 90_LPDP_ISP_FROM_JASPER_RX_D0_N CM43 LPDPRX_RX_D11_N
IN
AL2 CLK_ISP_TO_CAM_PMU1_24M_R 1
33.2 2 CLK_ISP_TO_CAM_PMU1_24M
CM24 SENSOR0_CLK 43
ANALOG_LPDP_ISP_RX0_RCAL_POS LPDPRX0_RCAL_P
OUT
1%
CN24 LPDPRX0_RCAL_N 1/32W
1
R1200 CN38
MF
01005
200 LPDPRX1_RCAL_P ROOM=SOC
1% CP38
1/32W LPDPRX1_RCAL_N
MF
01005
2 ROOM=SOC
R1260
ANALOG_LPDP_ISP_RX0_RCAL_NEG AN4
33.2 CLK_ISP_TO_CAM_PMU2_24M
SENSOR1_CLK CLK_ISP_TO_CAM_PMU2_24M_R 1 2 OUT 46
B 1 C1200 21 BI
NC_LPDP_ISP_AUX_RX_D0P CL22 LPDPRX_AUX_D0_P 1%
B
SENSOR CLK
1/32W
NC_LPDP_ISP_AUX_RX_D1P CK24 LPDPRX_AUX_D1_P MF
10PF 21 BI
01005
5% 21 LPDP_ISP_BI_SWIDE_AUX_RX_D2P CL26 LPDPRX_AUX_D2_P ROOM=SOC
BI
2 16V CK28
NP0/C0G
01005 21 BI
NC_LPDP_ISP_AUX_RX_D3P LPDPRX_AUX_D3_P
PACK_OPTION=D53,D54,DEV
ROOM=SOC 21 NC_LPDP_ISP_AUX_RX_D4P CL30 LPDPRX_AUX_D4_P BOMOPTION=PRO
BI
21 NC_LPDP_ISP_AUX_RX_D5P CK32 LPDPRX_AUX_D5_P
BI
21 NC_LPDP_ISP_AUX_RX_D6P CL34 LPDPRX_AUX_D6_P SENSOR2_CLK AN3 NC_SENSOR2_CLK_AP 20
ANALOG_LPDP_ISP_RX1_RCAL_POS BI
CK36
21 BI
1
R1210 21 BI
NC_LPDP_ISP_AUX_RX_D8P CL38
CK40
LPDPRX_AUX_D8_P
200 21 BI
1% CL42
1/32W 21 BI
MF CK43
01005
2 ROOM=SOC 21 BI
ANALOG_LPDP_ISP_RX1_RCAL_NEG AR3
SENSOR3_CLK NC_SENSOR3_CLK_AP 20
1 C1210
10PF
5%
2 16V
NP0/C0G
01005
ROOM=SOC

A A
PAGE TITLE
SOC: ISP
DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0

crb-1
12 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
SOC: DISPLAY / ISP

998-22473
ROOM=SOC U1000
SICILY-4GB-1YNM-M
C C
CSP
SYM 5 OF 21
OMIT_TABLE
SPMI Address Map
21 90_MIPI_AP_TO_DISPLAY_CLK_P CN51 MIPID_DPCLK ISP_SPMI0_SCLK BJ4 SPMI_ISP_TO_CAM_PMU1_CLK 43 BUS DEVICE ADDR LOCATION
OUT OUT
ISP_SPMI
21 90_MIPI_AP_TO_DISPLAY_CLK_N CP51 MIPID_DNCLK ISP_SPMI0_SDATA BJ2 SPMI_ISP_BI_CAM_PMU1_DATA 43 97
OUT BI
BK2 SPMI0 ISP Adams1 0x09 Top MLB
CN55 ISP_SPMI1_SCLK SPMI_ISP_TO_CAM_PMU2_CLK
90_MIPI_AP_TO_DISPLAY_D0_P MIPID_DPDATA0 BJ3
OUT 46
21 OUT
CP55 ISP_SPMI1_SDATA SPMI_ISP_BI_CAM_PMU2_DATA SPMI1 ISP Adams2 0x09 Top MLB
21 OUT
90_MIPI_AP_TO_DISPLAY_D0_N MIPID_DNDATA0
BI 46 97
NOTE: SPMI1 ISP is for D53P/D54 only

DWI_CLK CM3 NC_SOC_DWI_CLK
90_MIPI_AP_TO_DISPLAY_D1_P CP53 MIPID_DPDATA1 1.8V
20
DWI
21 OUT
DWI_DO CK5 NC_SOC_DWI_DATA
21 90_MIPI_AP_TO_DISPLAY_D1_N CN53 MIPID_DNDATA1
20
OUT
MIPI-D
21 90_MIPI_AP_TO_DISPLAY_D2_P CP47 MIPID_DPDATA2 DISP_TOUCH_BSYNC0 CM11 NC_TOUCH_BSYNC0_DISP 21
OUT
21 90_MIPI_AP_TO_DISPLAY_D2_N CN47 MIPID_DNDATA2 DISP_TOUCH_BSYNC1 CN6 NC_TOUCH_BSYNC1_DISP 20
OUT
DISP_TOUCH_EB CM9 NC_SOC_DISP_TOUCH_EB
21 90_MIPI_AP_TO_DISPLAY_D3_P CN49 MIPID_DPDATA3
20
OUT
90_MIPI_AP_TO_DISPLAY_D3_N CP49 MIPID_DNDATA3
21 OUT
DISP_TE F34 IO_AOP_FROM_DISPLAY_TE 87 90 DISPLAY_TE also provides WDG functionality
IN
ANALOG_MIPI_AP_REXT CL53 MIPID_REXT
DISP_MIPI_PWR_DWN D47 IO_AOP_TO_DISPLAY_MIPI_PWR_DWN 87 90
OUT
GPIOS
DISP_HPD CK61 NC_EDP_HPD_DISP
R1300 1 20
NC_DEV_LPDP_AP_TX0P A40 LPDP_TX0P

200 20
DISP_I2C_SCL CL13 NC_SOC_DISP_I2C_SCL
1% NC_DEV_LPDP_AP_TX0N B40 LPDP_TX0N
20
1/32W
20
DISP_I2C_SDA CL60 NC_SOC_DISP_I2C_SDA 20
MF A42
NC_DEV_LPDP_AP_TX1P
LPDP-TX
01005 2 LPDP_TX1P CL62
20
B42 DISP_POL NC_SOC_DISP_POL
ROOM=SOC
20 NC_DEV_LPDP_AP_TX1N LPDP_TX1N
20
20 NC_DEV_LPDP_AP_TX2P A43 LPDP_TX2P

20 NC_DEV_LPDP_AP_TX2N B43 LPDP_TX2N
DISP_AGPIO D45 NC_SOC_DISP_AGPIO
20 NC_DEV_LPDP_AP_TX3P A45 LPDP_TX3P
20
B B
Dev breaks out to baseboard LPDP header B45 BG3
20 NC_DEV_LPDP_AP_TX3N LPDP_TX3N DISP_EXT_HPD NC_SOC_DISP_EXT_HPD 20
DP_WAKEUP CK17 NC_DEV_SOC_DP_WAKEUP PP (dev board only)

20 NC_DEV_LPDP_AP_AUXP A47 LPDP_AUX_P
21
20 NC_DEV_LPDP_AP_AUXN B47 LPDP_AUX_N
LPDP_RCAL_P/N are for LPDP TX, NC if unused 20 NC_DEV_LPDP_AP_RCALP A49 LPDP_RCAL_P

20 NC_DEV_LPDP_AP_RCALN B49 LPDP_RCAL_N
20 NC_LPDP_EXT_AP_TX0_P A53 LPDP_EXT_TX0P

20 NC_LPDP_EXT_AP_TX0_N B53 LPDP_EXT_TX0N


External LPDP not used A58
20 NC_LPDP_EXT_AP_TX3_P LPDP_EXT_TX3P
20 NC_LPDP_EXT_AP_AUX_P A59 LPDP_EXT_AUX_P

20 NC_LPDP_EXT_AP_AUX_N B59 LPDP_EXT_AUX_N
20 NC_LPDP_EXT_AP_RCAL_P A60 LPDP_EXT_RCAL_P

20 NC_LPDP_EXT_AP_RCAL_N B60 LPDP_EXT_RCAL_N

A A
PAGE TITLE
SOC: Display
DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0

crb-1
13 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: AP Serial
998-22473
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
D
SYM 7 OF 21
D 96 20 UART0_AP_FROM_KRAKEN_DEBUG_RXD CH62 UART0_RXD

OMIT_TABLE
I2C0_SCL AG62 NC_I2C0_AP_SCL 21
IN
96 20 UART0_AP_TO_KRAKEN_DEBUG_TXD CP5 UART0_TXD I2C0_SDA AJ61 NC_I2C0_AP_SDA 21
OUT
20 NC_UART1_AP_CTS_L BP2 UART1_CTS* I2C1_SCL AG4 NC_I2C1_AP_SCL 21
20 NC_UART1_AP_RTS_L BM3 UART1_RTS* I2C1_SDA AF2 NC_I2C1_AP_SDA 21
I2C
NC_UART1_AP_RXD BK4 UART1_RXD
20
I2C2_SCL AF3 I2C2_AP_SCL
NC_UART1_AP_TXD BK3 UART1_TXD
OUT 17
20
I2C2_SDA AD2 I2C2_AP_SDA 17
BI
NC_UART2_AP_CTS_L BT4 UART2_CTS*
20
I2C3_SCL CL5 I2C3_AP_SCL_1V8
NC_UART2_AP_RTS_L BT2 UART2_RTS*
OUT 17
20
I2C3_SDA CL49 I2C3_AP_SDA_1V8 NOTE:
20 NC_UART2_AP_RXD BP4 UART2_RXD 1.8V BI 17
NC_UART2_AP_TXD BP3 CL4 I2C_DISPLAY_SCL_1V8 I2S DIN/DOUT are SOC-centric,

20 UART2_TXD I2C4_SCL OUT 17
Alt AP UART7 CL47 I2C_DISPLAY_SDA_1V8 SOC DIN routes to load DOUT and vice-versa
I2C4_SDA
UART
20 NC_UART3_AP_CTS_L CJ61 UART3_CTS*
BI 17
21 NC_UART3_AP_RTS_L CM13 UART3_RTS* I2S0_DIN P2 I2S0_AP_FROM_CODEC_ASP3_DIN 61 96

IN
20 NC_UART3_AP_RXD CP6 UART3_RXD I2S0_DOUT T4 I2S0_AP_TO_CODEC_ASP3_DOUT 61 96 AP I2S0
OUT
NC_UART3_AP_TXD CL15 UART3_TXD I2S0_BCLK P4 I2S0_AP_FROM_CODEC_ASP3_BCLK Used for MikeyBus
R1410
21 IN 61 96
I2S0_LRCK M2 I2S0_AP_FROM_CODEC_ASP3_LRCLK 61 96 (MCLK to Top Spk)

IN
P3 I2S0_AP_TO_SPKRAMP_TOP_MCLK_R 1
33.2 2 I2S0_AP_TO_SPKRAMP_TOP_MCLK
I2S0_MCK OUT 63
1%
96 20 UART4_AP_FROM_KRAKEN_ACC_RXD AL61 UART4_RXD I2S1_DIN AB4 I2S1_AP_FROM_CODEC_ASP4_DIN 61 96 1/32W
IN IN
MF
96 20 UART4_AP_TO_KRAKEN_ACC_TXD AL62 UART4_TXD I2S1_DOUT AD3 I2S1_AP_TO_CODEC_ASP4_DOUT 61 96 01005 AP I2S1
OUT OUT ROOM=SOC
I2S1_BCLK Y3 I2S1_AP_FROM_CODEC_ASP4_BCLK Used for Mics
NC_UART6_AP_RXD_1V8 CK6 UART6_RXD
IN 61 96
20
1.8V I2S1_LRCK Y2 I2S1_AP_FROM_CODEC_ASP4_LRCLK
I2S
Use UART6_TXD as 1.8V GPIO GPIO_AP_TO_TOUCH_RESET_L_1V8 CL2 UART6_TXD
IN 61 96
88 68 OUT
I2S1_MCK AB3 NC_I2S1_AP_MCLK 20
I2S2_DIN V2 I2S2_AP_FROM_BB_DIN 99
IN
I2S2_DOUT Y4 I2S2_AP_TO_BB_DOUT
C
OUT 99
C SPI0: NAND
R1400
20 IN
SPI0_AP_FROM_S5E_MISO_BOOT_CONFIG2
SPI0_AP_TO_S5E_MOSI_BOOT_CONFIG1
AL3
AJ2
SPI0_MISO I2S2_BCLK T2
T3
I2S2_AP_FROM_BB_BCLK
I2S2_AP_FROM_BB_LRCLK
IN 99
20 OUT SPI0_MOSI I2S2_LRCK IN 99
SPI0_AP_TO_S5E_SCLK_BOOT_CONFIG0 1
0.00 2 SPI0_AP_TO_NAND_SCLK_R AL4 V3 NC_I2S2_AP_MCLK
20 OUT SPI0_SCLK I2S2_MCK 20
SPI
0%
1/32W NC_SPI1_MISO_1V8 CK47 SPI1_MISO AP_SPMI2_SCLK AB2 NC_DEV_AP_SPMI2_SCLK
R1401
21 IN 21
SPI1: Cumulus MF
NC_SPI1_MOSI_1V8 CK49 AF4 NC_DEV_AP_SPMI2_SDATA
01005 21 OUT SPI1_MOSI AP_SPMI2_SDATA 21
D53 only NC_SPI1_SCLK_1V8_R 1
0.00 2
ROOM=SOC
NC_SPI1_SCLK_1V8_R CL6 1.8V
21 OUT SPI1_SCLK
0% 21 NC_SPI1_CS_L_1V8 CL51 SPI1_SSIN
OUT
1/32W
MF
01005 SPI2_AP_FROM_TOUCH_MISO BE2 SPI2_MISO
R1402
21 IN
SPI2: Ada ROOM=SOC
PACK_IGNORE=TRUE
SPI2_AP_TO_TOUCH_MOSI BC2
PACK_OPTION=D53,DEV 21 OUT SPI2_MOSI
D52/D54 only SPI2_AP_TO_TOUCH_SCLK 1
0.00 2 SPI2_SCLK_AP_R BC3
21 OUT SPI2_SCLK
0% 21 SPI2_AP_TO_TOUCH_CS_L BA3 SPI2_SSIN
OUT
1/32W
MF
SPI3_AP_FROM_CODEC_MISO BG2
XW1402
SHORT-01005-SP
01005
ROOM=SOC
20
20
IN
SPI3_AP_TO_CODEC_MOSI BE4
SPI3_MISO
SPI3_MOSI
OUT
PACK_OPTION=D54,DEV
1 2 SPI3_SCLK_AP_R BE3 SPI3_SCLK
ROOM=SOC 20 SPI3_AP_TO_CODEC_CS_L BC4 SPI3_SSIN
OUT
998-23033
PACK_IGNORE=TRUE
PACK_OPTION=D52
R1403
SPI3_AP_TO_CODEC_SCLK 1
0.00 2
SPI3: Brighton 20 OUT 998-22473
0%
1/32W
Place series terminations close to SoC Pins ROOM=SOC U1000
MF SICILY-4GB-1YNM-M
XW1403
SHORT-01005-SP
01005
ROOM=SOC
CSP
SYM 8 OF 21
PACK_OPTION=D52,D54,DEV
1 2 OMIT_TABLE
ROOM=SOC 30 GPIO_PMU_TO_SOC_DOUBLE_CLICK_DET_L AW3 SGPIO0 SSPI0_MISO AW2 NC_SSPI0_MISO_AP 20
IN
998-23033 AW4 SSPI
AU4
PACK_IGNORE=TRUE PP (dev board only) 20 NC_SOC_S_GPIO1 SGPIO1 SSPI0_MOSI NC_SSPI0_MOSI_AP 20
B B
PACK_OPTION=D53
SSPI0_SCLK AU3 NC_SSPI0_SCLK_AP
17 I2C0_S_SCL AU1 SI2C0_SCL
20
OUT
17 I2C0_S_SDA AU2 SI2C0_SDA
BI

A A
PAGE TITLE
SOC: Serial
DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0

crb-1
14 OF 138
SHEET
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
D D
SOC: AP GPIO
998-22473
ROOM=SOC U1000
C SICILY-4GB-1YNM-M
CSP
C
SYM 6 OF 21
OMIT_TABLE
19 GPIO_BOARD_REV3 BT3 GPIO0 GPIO GPIO16 BC61 GPIO_AP_FROM_BT_AUDIO_SYNC 19
19 GPIO_BOARD_REV2 BV2 GPIO1 GPIO17 BC60 GPIO_AP_TO_AMUX_PMU_SYNC 19
19 GPIO_BOARD_REV1 BY2 GPIO2 GPIO18 AW62 NC_DEV_AP_GPIO18 19
19 GPIO_BOARD_REV0 BV3 GPIO3 GPIO19 AW61 NC_DEV_AP_GPIO19 19
19 GPIO_AP_CANARY1 BY3 GPIO4 GPIO20 AW60 NC_DEV_AP_GPIO20 19
19 GPIO_AP_CANARY2 BY4 GPIO5 GPIO21 AU62 NC_DEV_AP_GPIO21 19
19 GPIO_AP_BI_CCG2B_SWDIO CK58 GPIO6 GPIO22 AU61 NC_DEV_AP_GPIO22 19
19 GPIO_AP_TO_CCG2B_SWCLK CL11 GPIO7 GPIO23 AU60 NC_DEV_AP_GPIO23 19
19 GPIO_AP_FROM_DISPLAY_PANEL_ID CM5 GPIO8 GPIO24 AR62 NC_DEV_AP_GPIO24 19
19 GPIO_AP_FROM_WLAN_TIME_SYNC CK15 GPIO9 GPIO25 AR61 GPIO_AP_TO_BB_TIME_MARK 19
19 GPIO_AP_TO_BB_PEAK_PWR_IND CN9 GPIO10 GPIO26 AN61 NC_DEV_AP_GPIO26 19
19 GPIO_AP_TO_BB_COREDUMP CP7 GPIO11

19 GPIO_AP_FROM_BB_RESET_DETECT_L CK19 GPIO12
19 GPIO_AP_FROM_CODEC_INT_L CL17 GPIO13
19 NC_AP_GPIO14 CJ60 GPIO14
19 GPIO_AP_TO_SPKRAMP_TOP_RESET_L BC62 GPIO15
B B

A A
PAGE TITLE
SOC: GPIO
DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0

crb-1
15 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: AOP
998-22473
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 9 OF 21
OMIT_TABLE
18 I2C0_AOP_SCL F61 AOP_I2CM0_SCL AOP_FUNC0 E62 GPIO_SCM_AOP_FROM_IMU_DATARDY 19
OUT
18 I2C0_AOP_SDA F62 AOP_I2CM0_SDA AOP_FUNC1 F60 GPIO_SCM_AOP_TO_IMU_SPI_CS_L 19
BI
NOTE: E43 GPIO_AOP_FROM_PEARL_B2B_DETECT
I2C
F45 AOP_FUNC2
I2C1_AOP_SCL AOP_I2CM1_SCL
19
E60 NC_DEV_AOP_FUNC3
D
18 OUT
I2S DIN/DOUT are SOC-centric, AOP_FUNC3
D I2C1_AOP_SDA D42 19
AOP_I2CM1_SDA K61
SOC DIN routes to load DOUT and vice-versa
18 BI
AOP_FUNC4 GPIO_SCM_AOP_FROM_R1_INT 19
SPI0_AOP_FROM_IMU_R1_MISO H60 AOP_SPI0_MISO AOP_FUNC5 D60 GPIO_AOP_TO_R1_COREDUMP_TRIGGER

R1601
101 57 IN 19
101 57 SPI0_AOP_TO_IMU_R1_MOSI H62 AOP_SPI0_MOSI AOP_FUNC6 D62 GPIO_AOP_TO_R1_TIME_SYNC_L 19

OUT
SPI0_AOP_TO_IMU_R1_SCLK 1
33.2 2 SPI0_AOP_TO_IMU_R1_SCLK_R G62 A36 GPIO_AOP_TO_CODEC_RESET_L
101 97 57 OUT AOP_SPI0_SCLK AOP_FUNC7 19
E42 GPIO_AOP_TO_BB_FORCE_PWM
SPI
1% SPI1_SCLK/SSIN: Use as AOP GPIO D55 AOP_FUNC8
1/32W I2C2_AOP_SCL AOP_SPI1_MISO AOP I2C2 SCL E59
19
MF
29 18 IN
D57 AOP_FUNC9 GPIO_AOP_FROM_IRCAM_B2B_DETECT
01005 I2C2_AOP_SDA AOP_SPI1_MOSI AOP I2C2 SDA F57
19
18 OUT
D58 AOP_FUNC10 GPIO_SCM_AOP_TO_R1_SPI_CS_L
ROOM=SOC
GPIO_AOP_TO_WLAN_CONTEXT_B AOP_SPI1_SCLK
19
R1603 F42 NC_AOP_FUNC11

20 OUT
E34 AOP_FUNC11
GPIO_AOP_TO_WLAN_CONTEXT_A 19
GPIO
AOP_SPI1_SSIN D40
1
33.2 2
20 OUT
AOP_FUNC12 GPIO_AOP_TO_ALS_COEX 19
AOP I2S0 61 OUT
I2S0_AOP_TO_CODEC_MCLK1
I2S0_AOP_FROM_CODEC_ASP1_DIN D59 F58 GPIO_AOP_TO_NFC_IRONMAN_EN
96 61 IN AOP_I2S0_DIN AOP_FUNC13 19
Penrose, LDCM, 1% MF
Borealis R1606 1/32W
01005
96 61 OUT
I2S0_AOP_TO_CODEC_ASP1_DOUT E49
D36
AOP_I2S0_DOUT AOP_FUNC14 F53
E58
NC_GPIO_AOP_FROM_TOUCH_CTS 19
2
0.00 1
ROOM=SOC 96 61 IN
I2S0_AOP_FROM_CODEC_ASP1_BCLK AOP_I2S0_BCLK AOP_FUNC15 GPIO_SCM_AOP_BI_PROX_INT_L 19
(MCLK to Codec) 66 65 63 62 61 IN
I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN
I2S0_AOP_FROM_CODEC_ASP1_LRCLK E36 E40 GPIO_SCM_AOP_FROM_ALS_INT_L
AOP_I2S0_LRCK AOP_FUNC16
I2S
96 61 IN 19
0%
1/32W I2S0_AOP_TO_CODEC_MCLK1_R F36 AOP_I2S0_MCK AOP_FUNC17 F51 GPIO_SCM_AOP_FROM_EIGER_INT_L 19
MF
01005
R1607 I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN_R C36 AOP_I2S1_DIN
AOP_FUNC18 E57
F40
GPIO_SCM_AOP_FROM_COMPASS_INT 19
AOP I2S1
ROOM=SOC
0.00 B36 AOP_FUNC19 GPIO_SCM_AOP_FROM_JARVIS_INT
I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT 2 1 I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT_R_SOC AOP_I2S1_DOUT D38
19
Out to BotSpk,
65 63 62 61 OUT
E53 AOP_FUNC20 GPIO_AOP_FROM_TOUCH_INT_L
0% MF I2S1_AOP_AMPS_FROM_CODEC_ASP2_BCLK AOP_I2S1_BCLK
19
R1608 E55 NC_AOP_FUNC21

66 65 63 62 61 IN
TopSpk, Arc, 1/32W
I2S1_AOP_AMPS_FROM_CODEC_ASP2_LRCLK E51 AOP_FUNC21 19
01005 AOP_I2S1_LRCK E38
in from Sak. 0.00 66 65 63 62 61 IN
E47 AOP_FUNC22 NC_DEV_AOP_FUNC22
65 62 OUT
I2S1_AOP_TO_SPKRAMP_BOT_ARCAMP_MCLK 2 1
ROOM=SOC
I2S1_AOP_TO_SPKRAMP_BOT_ARCAMP_MCLK_R AOP_I2S1_MCK
19
(MCLK to Arc 0%
and BotSpk) 1/32W 99 UART1_AOP_FROM_BB_RXD K62 AOP_SPMI1_SDATA SUPPORTS UART
BI
MF
01005 99 UART1_AOP_TO_BB_TXD G61 AOP_SPMI1_SCLK ALT FUNC1
OUT
R1622
ROOM=SOC
100 98 SPMI0_EVENTS_AOP_BI_WLAN_NFC_DATA D43 AOP_SPMI0_SDATA SUPPORTS UART

IN
33.2
UART
100 98 SPMI0_EVENTS_AOP_TO_WLAN_NFC_CLK 1 2 SPMI0_EVENTS_AOP_TO_WLAN_NFC_CLK_R F47 AOP_SPMI0_SCLK ALT FUNC1
OUT
1%
1/32W UART2_AOP_FROM_TOUCH_RXD G60 AOP_UART2_RXD
C
88 68 IN
C
MF
SPMI Address Map 01005
ROOM=SOC
96 88 68 OUT
UART2_AOP_TO_TOUCH_TXD E45 AOP_UART2_TXD
SOC: SMC
BUS DEVICE ADDR LOCATION
Touch UART R1621 1 1
R1620
SPMI0 AOP WLAN 0x0E Bottom MLB D52/D54: WIRED TO ADA 1.00M 1.00M
5% 5%
D52/D53: Top MLB D53: WIRED TO TOUCH B2B 1/32W 1/32W
SPMI0 AOP Ceres (P) 0x0C D54: Bottom MLB MF MF 998-22473
SPMI0 AOP Ceres (F) 0x0B

D53/D54: Top MLB
D52: Bottom MLB
01005 2 2 01005 ROOM=SOC U1000
SICILY-4GB-1YNM-M
NOTE: Ceres (F) default address is 0x0C, programmed to 0x0B on SMT line CSP
SYM 10 OF 21
BUS DEVICE ADDR LOCATION OMIT_TABLE
18 I2C0_SMC_SCL G4 SMC_I2CM0_SCL I2C
OUT
SPMI0 NUB Cota 0x0F Top MLB F26
18 BI
I2C0_SMC_SDA SMC_I2CM0_SDA
SPMI0 NUB DotaraLV 0x0E Top MLB G2
97 18 OUT
I2C1_SMC_SCL SMC_I2CM1_SCL
97 18 I2C1_SMC_SDA H2 SMC_I2CM1_SDA
BI
18 I2C2_SMC_SCL G3 SMC_I2CM2_SCL
OUT
18 I2C2_SMC_SDA F2 SMC_I2CM2_SDA
BI
SOC: NUB
998-22473
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 11 OF 21
R1610 OMIT_TABLE
B 35 27 OUT
SPMI0_NUB_TO_PMU_DOTARA_CLK 2
33.2 1 SPMI0_NUB_TO_PMU_DOTARA_CLK_R D32 NUB_SPMI0_SCLK SPMI B
1% 35 27 SPMI0_NUB_BI_PMU_DOTARA_DATA D4 NUB_SPMI0_SDATA
BI
1/32W
MF
01005 96 68 20 SWD_NUB_TO_PMU_TOUCH_SWCLK F6 NUB_SWD_TCK_OUT0
OUT
ROOM=SOC
96 30 SWD_NUB_BI_PMU_SWDIO F13 NUB_SWD_TMS0 SWD
BI
Touch SWDIO: Wired to Touch B2B (D52/D54) 68 SWD_NUB_BI_TOUCH_SWDIO F11 NUB_SWD_TMS1
BI
Touch SWDIO: No connect (D53) F30
96 70 IN
IO_NUB_FROM_KRAKEN_DOCK_CONNECT NUB_DOCK_CONNECT DOCK
96 70 IO_NUB_FROM_KRAKEN_INT E30 NUB_DOCK_ATTENTION
IN
96 71 GPIO_NUB_FROM_CCG2B_INT_L D2 NUB_GPIO_0
IN
Gecko IRQ needs SOC weak internal PU 96 72 GPIO_NUB_FROM_GECKO_IRQ_L E4 NUB_GPIO_1
IN
Parrot INT needs external or SOC pull-up 73 GPIO_NUB_FROM_PARROT_INT_L E3 NUB_GPIO_2
96 IN
96 72 GPIO_NUB_TO_GECKO_RESET_L F28 NUB_GPIO_3 GPIO
OUT
Can use Dotara GPIO for BBPMU Clock EN 99 GPIO_NUB_TO_BBPMU_CLK_EN_DOTARA E2 NUB_GPIO_4
OUT
20 NC_NUB_GPIO5 F3 NUB_GPIO_5
21 NC_NUB_GPIO6 E28 NUB_GPIO_6
96 70 SWD_DOCK_TO_AP_SWCLK E5 JTAG_TCK
IN
96 70 SWD_DOCK_BI_AP_SWDIO C34 JTAG_TMS
BI
20 GND D6 JTAG_SEL
JTAG
20 NC_DEV_JTAG_TDI B34 JTAG_TDI
20 NC_DEV_JTAG_TDO E6 JTAG_TDO
20 NC_DEV_JTAG_TRST_L D5 JTAG_TRST*
20 90_EUSB_DBG_PARROT_BI_AP_N B30 DBG_USB_EDM

BI
90_EUSB_DBG_PARROT_BI_AP_P A30 DBG_USB_EDP
20 BI
ANALOG_DBG_USB_RESREF D30 DBG_USB_RESREF DEBUG USB
A 1
R1650 20 PP1V2_S2 E32 DBG_PROBE_VALID A
200 MLB: DBG_PROBE_VALID=1 PAGE TITLE
XW1660
SHORT-01005-SP
1%
1/32W
MF
DEV: Jumper for DBG_PROBE_VALID to 0 or 1 SOC: AOP & SMC & NUB
IO_PMU_TO_SYSTEM_RESET_L D51 COLD_RESET*
1 2 2 01005 20 IN DRAWING NUMBER SIZE
ROOM=SOC
IO_PMU_TO_SYSTEM_RESET_L D53 CFSB_AON 051-05170 D
Apple Inc.
20 IN
ROOM=SOC
998-23033
PACK_IGNORE=TRUE 29 27 CLK_PMU_TO_AOP_32K D49 RT_CLK32768 MISC REVISION
IN
PACK_OPTION=D52 IO_SOC_TO_PMU_WDOG_RESET
96 27 OUT
D34 WDOG 10.0.0
R1660 96 20 OUT
IO_AON_TO_AP_XTAL_CFSB A34 AON_SLEEP1_RESET* NOTICE OF PROPRIETARY PROPERTY: BRANCH
68 CLK_NUB_TO_TOUCH_24M 2
0.00 1 CLK_NUB_TO_TOUCH_24M_R F15 NUB_CLK_OUT0
crb-1
OUT
0%
1/32W
MF
ROOM=SOC
20 GND CP4 KIS_DFU_SELECT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
16 OF 138
01005 KIS_DFU_SELECT: SHEET
PACK_OPTION=D54,DEV POR = 0 (GND): USB0 for DFU (legacy)
Debug = 1 (1V2): USB1 for DFU (Kanzi-in-System) IV ALL RIGHTS RESERVED 15 OF 117
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
OCELOT
C PP1V8_IO 30
C
1 C1700
2.2UF
20%
2 6.3V
X5R-CERM
0201
A1
ROOM=SOC_AUX
VCC
U1700
STOCT
WLCSP-1
17 IN
I2C0_S_SCL A2 SCL VIO C2 PP1V2_IO 30
335S00487
I2C0_S_SDA B1 SDA NC A3 VIO=1: 1.2V I2C
17 BI
CRITICAL NC
NC C1 VIO=0: 1.8V I2C
ROOM=SOC_AUX NC
VSS
B2
B3
C3
B B

A A
PAGE TITLE
SOC: Ocelot
DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0

crb-1
17 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: CPU/GPU
998-22473
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 12 OF 21
OMIT_TABLE
2020-MLCC
30 PP_CPU_PCORE AP56 VDD_PCPU CPU/GPU VDD_GPU AA27 PP_GPU 30
138S00317
AP48 AA31
1 C1802 1 C1803 1 C1801 1 C1807 1 C1805 ROOM=SOC_FILT ROOM=SOC_FILT VDD_PCPU VDD_GPU 1 C1831 1 C1832 1 C1833 1 C1834
2.2UF 2.2UF 20UF 20UF 15UF C1804 C1806 AP52
AT41
VDD_PCPU VDD_GPU AA44
AA48
2.2UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 11UF 14UF VDD_PCPU VDD_GPU 20% 20% 20% 20%
D
2 6.3V
X5R-CERM
0201
6.3V
2 X5R-CERM
0201
2 6.3V
CERM-X5R
0402-0.1MM
2 6.3V
CERM-X5R
0402-0.1MM
2 6.3V
X5R
0402-0.1MM-1
20%
4V
X5R
20%
4V
X5R
AT50 VDD_PCPU VDD_GPU AA52 2 6.3V
X5R-CERM
0201
2 6.3V
CERM-X5R
0402-0.1MM
6.3V
2 CERM-X5R
0402-0.1MM
2 6.3V
CERM-X5R
0402-0.1MM PP_SOC_S1 30 D
AT54 AC25
VDD_PCPU VDD_GPU
C1860 C1861 C1830 C1862
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT 0402 0402-D2X-1 ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
PACK_IGNORE=TRUE PACK_IGNORE=TRUE 1 1 1 1
1 3 1 3 AV39 VDD_PCPU VDD_GPU AC33
PACK_OPTION=D52,D53,DEV PACK_OPTION=D52,D53,DEV 2.2UF 2.2UF 2.2UF 20UF
AY54 VDD_PCPU VDD_GPU AC41 20% 20% 20% 20%
2 4 2 4 BF39 AC50 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
CERM-X5R
VDD_PCPU VDD_GPU 0201 0201 0201 0402-0.1MM
BH54 VDD_PCPU VDD_GPU AE27 ROOM=SOC_FILT ROOM=SOC_FILT
ROOM=SOC_FILT ROOM=SOC_FILT
PACK_OPTION=D54
BL39 VDD_PCPU VDD_GPU AE35
BL48 VDD_PCPU VDD_GPU AE44
138S00313
BL52 AE48
BN37
VDD_PCPU
VDD_PCPU
VDD_GPU
VDD_GPU AE52
1 C1863 1 C1863 1 C1864 1 C1866
20UF 16UF 20UF 20UF
BN41 VDD_PCPU VDD_GPU N31 20% 20% 20% 20%
C1805 C1807 BN46 VDD_PCPU VDD_GPU N35 2 6.3V
CERM-X5R 2 4V
X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
14UF 14UF BN50 N39
0402-0.1MM 0402-0.1MM-1 0402-0.1MM 0402-0.1MM
20% 20% VDD_PCPU VDD_GPU ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
4V 4V PACK_IGNORE=TRUE
X5R X5R BN54 VDD_PCPU VDD_GPU N44 PACK_OPTION=D54 PACK_OPTION=D52,D53,DEV
0402-D2X-1 0402-D2X-1 2020-MLCC
BR44 R25
PACK_OPTION=D54
1
2 4
3 1
2 4
3
PACK_OPTION=D54
BR52
BU37
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_GPU
VDD_GPU
VDD_GPU
R33
R41 998-22473
SOC: SOC
BU50 VDD_PCPU VDD_GPU R50 ROOM=SOC U1000
BW39 VDD_PCPU VDD_GPU U27 SICILY-4GB-1YNM-M
BW52 VDD_PCPU VDD_GPU U31 CSP
SYM 13 OF 21
CA37 VDD_PCPU VDD_GPU U44
CA50 U48 OMIT_TABLE
VDD_PCPU VDD_GPU AY25 BF56
CC37 U52 VDD_SOC_S1 SOC VDD_SOC_S1
VDD_PCPU VDD_GPU AA14 BL18
CC44 W29 VDD_SOC_S1 VDD_SOC_S1
VDD_PCPU VDD_GPU AA18 BL23
CC52 W46 VDD_SOC_S1 VDD_SOC_S1
VDD_PCPU VDD_GPU AH20 BL31
AE31 VDD_SOC_S1 VDD_SOC_S1
BL37 VDD_GPU AM54 BN20
ANALOG_PCPU_SENSE_P VDD_PCPU_SENSE VDD_SOC_S1 VDD_SOC_S1
C
96 24 OUT
C PP_CPU_ECORE AT29
VDD_GPU_SENSE AH29 ANALOG_GPU_SENSE_P OUT 96 AH37
AH46
VDD_SOC_S1 VDD_SOC_S1 BN29
AE14
30 VDD_ECPU VDD_SOC_S1 VDD_SOC_S1
AT33 AH54 BR18
1 C1895 1 C1894 1 C1893 ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT VDD_ECPU VDD_SOC_S1 VDD_SOC_S1
20UF 2.2UF 20UF C1891 C1892 C1893 AT37
AV31
VDD_ECPU AK10
AK14
VDD_SOC_S1 VDD_SOC_S1 BR23
BR27
20% 20% 20% 14UF 14UF 14UF VDD_ECPU VDD_SOC_S1 VDD_SOC_S1
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM 2 6.3V
CERM-X5R 20% 20% 20%
BB27 AK18 BR31
0402-0.1MM 0201 0402-0.1MM 4V 4V 4V VDD_ECPU VDD_SOC_S1 VDD_SOC_S1
X5R X5R X5R
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT 0402-D2X-1 0402-D2X-1 0402-D2X-1 BD37 VDD_ECPU AK23 VDD_SOC_S1 VDD_SOC_S1 BR35
PACK_IGNORE=TRUE 1 3 1 3 1 3 AK27
PACK_OPTION=D52,D53,DEV BF31 VDD_ECPU VDD_SOC_S1 VDD_SOC_S1 BU25
BF35 VDD_ECPU AA23 VDD_SOC_S1 VDD_SOC_S1 BU33
2 4 2 4 2 4 PACK_OPTION=D54
BH37 AK31 BW35
VDD_ECPU VDD_SOC_S1 VDD_SOC_S1
AK35 VDD_SOC_S1 VDD_SOC_S1 CE44
ANALOG_ECPU_SENSE_SE BL33 VDD_ECPU_SENSE
96 OUT AK39 VDD_SOC_S1 VDD_SOC_S1 CE52
AK44 VDD_SOC_S1 VDD_SOC_S1 AE18
SOC: SRAM
998-22473
AK48
AK52
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
CG18
CG29
AK56 VDD_SOC_S1 VDD_SOC_S1 N14
ROOM=SOC U1000 AM16 VDD_SOC_S1 VDD_SOC_S1 N18
SICILY-4GB-1YNM-M AM25 N23
CSP VDD_SOC_S1 VDD_SOC_S1
SYM 14 OF 21 AM33 VDD_SOC_S1 VDD_SOC_S1 N27
OMIT_TABLE AC16 N37
VDD_SOC_S1 VDD_SOC_S1
2020-MLCC SRAM
30 PP_CPU_SRAM AT46 VDD_CPU_SRAM VDD_SRAM_SOC_S1 AH50 PP_SRAM_S1 30 AM50 VDD_SOC_S1 VDD_SOC_S1 N56
138S00313 138S00317
AV27 AM12 AP10 R16
1 C1812 1 C1812 1 C1811 1 C1808 ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT VDD_CPU_SRAM VDD_SRAM_SOC_S1 VDD_SOC_S1 VDD_SOC_S1
10UF 20UF 16UF 15UF C1809 C1810 C1808 CC48
AV35
VDD_CPU_SRAM VDD_SRAM_SOC_S1 AM20
AM29
AP14
BH25
VDD_SOC_S1 VDD_SOC_S1 U14
AE23
20% 20% 20% 20% 14UF 11UF 14UF VDD_CPU_SRAM VDD_SRAM_SOC_S1 VDD_SOC_S1 VDD_SOC_S1
2 10V
X5R-CERM 2 6.3V
CERM-X5R 2 4V
X5R 2 6.3V
X5R 20% 20% 20%
BB39 AM37 AP23 U18
0402-0.1MM 0402-0.1MM 0402-0.1MM-1 0402-0.1MM-1 4V 4V 4V VDD_CPU_SRAM VDD_SRAM_SOC_S1 VDD_SOC_S1 VDD_SOC_S1
X5R X5R X5R
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT 0402-D2X-1 0402 0402-D2X-1 BD54 VDD_CPU_SRAM VDD_SRAM_SOC_S1 AM46 AP27 VDD_SOC_S1 VDD_SOC_S1 U23
B B
PACK_IGNORE=TRUE 2020-MLCC PACK_IGNORE=TRUE 1 3 1 3 1 3
PACK_OPTION=D52,D53,DEV PACK_OPTION=D54 PACK_OPTION=D52,D53,DEV BH33 VDD_CPU_SRAM VDD_SRAM_SOC_S1 AT16 AP31 VDD_SOC_S1 VDD_SOC_S1 W12
BL44 VDD_CPU_SRAM VDD_SRAM_SOC_S1 AT25 N46 VDD_SOC_S1 VDD_SOC_S1 W20
2 4 2 4 2 4 PACK_OPTION=D54
BR39 AY12 BL27 AH12
VDD_CPU_SRAM VDD_SRAM_SOC_S1 VDD_SOC_S1 VDD_SOC_S1
BR48 VDD_CPU_SRAM VDD_SRAM_SOC_S1 AY20 AT12 VDD_SOC_S1 VDD_SOC_S1 AP39
CC39 VDD_CPU_SRAM VDD_SRAM_SOC_S1 BD16 CA12 VDD_SOC_S1
VDD_SOC_SENSE AP16 ANALOG_SOC_SENSE_P
VDD_SRAM_SOC_S1 BD25 AT20 VDD_SOC_S1
OUT 96
30 PP_SRAM_S1 R29 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BH12 AV10 VDD_SOC_S1

138S00313
R37 BH20 AV14
1 C1872 1 C1872 1 C1873 1 C1874 1 C1865 AC29
VDD_SRAM_GPU_S1
VDD_SRAM_GPU_S1
VDD_SRAM_SOC_S1
VDD_SRAM_SOC_S1 BN16 AV18
VDD_SOC_S1
VDD_SOC_S1
16UF 15UF 20UF 20UF 2.2UF
20% 20% 20% 20% 20% AC37 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BN25 AV23 VDD_SOC_S1
2 4V
X5R 2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
X5R-CERM AC46 BN33 AY16
0402-0.1MM-1 0402-0.1MM-1 0402-0.1MM 0402-0.1MM 0201 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 VDD_SOC_S1
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT R46 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BN8 BB10 VDD_SOC_S1
PACK_IGNORE=TRUE PACK_IGNORE=TRUE
PACK_OPTION=D54 PACK_OPTION=D52,D53,DEV PACK_OPTION=D52,D53 W25 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BU12 BB14 VDD_SOC_S1
2020-MLCC
W33 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BU20 BB18 VDD_SOC_S1
W50 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BU29 BB23 VDD_SOC_S1
VDD_SRAM_SOC_S1 BU52 AE10 VDD_SOC_S1
VDD_SRAM_SOC_S1 CA16 BD12 VDD_SOC_S1
VDD_SRAM_SOC_S1 CA25 BD20 VDD_SOC_S1
VDD_SRAM_SOC_S1 CA33 BF18 VDD_SOC_S1
VDD_SRAM_SOC_S1 CE29 BF23 VDD_SOC_S1
VDD_SRAM_SOC_S1 CE50
VDD_SRAM_SOC_S1 AC12
VDD_SRAM_SOC_S1 AC20
VDD_SRAM_SOC_S1 AH16
VDD_SRAM_SOC_S1 AH25
VDD_SRAM_SOC_S1 AH33 SYNCING: D52, D53, D54, DEV
A VDD_SRAM_SOC_S1 AH41
AM56
A
VDD_SRAM_SOC_S1 PAGE TITLE
VDD_SRAM_SOC_S1 L25
SOC: Power (CPU/GPU & SRAM & SOC)
VDD_SRAM_SOC_S1 N52
DRAWING NUMBER SIZE
VDD_SRAM_SOC_S1 R20
051-05170 D
VDD_SRAM_SOC_S1 U12
W16
Apple Inc. REVISION
VDD_SRAM_SOC_S1
10.0.0

crb-1
18 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SUBSYSTEM SPECIFIC BOM TABLES
2.2uF 0201 Capacitors (single-source Murata)
SOC: FIXED
TABLE_ALT_HEAD
998-22473
PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS:
ROOM=SOC U1000
TABLE_ALT_ITEM
SICILY-4GB-1YNM-M
138S00049 138S0831 ? (C1970) CAP,CER,X5R,2.2UF,20%,6.3V,0201
CSP OMIT
OMIT_TABLE
SYM 17 OF 21
XW1940
SHORT-20L-0.05MM-SM
30
PP0V78_SOC_FIXED_S1 AP8 VDD_FIXED_S1 VDD_FIXED_PCIE_REFBUF_S1 J12 PP0V78_SOC_FIXED_PCIE_REFBUF 1 2 PP0V78_SOC_FIXED_S1 30
AV56 VOLTAGE=0.8
1 C1901 1 C1907 1 C1908 1 C1909 CA52
VDD_FIXED_S1
VDD_FIXED_S1 FIXED
1 C1940 ROOM=SOC_FILT
2.2UF 220PF 220PF 220PF 0.1UF

D
20%
2 6.3V
X5R-CERM
5%
2 25V
COG
5%
25V
2 COG
5%
2 25V
COG
CE16
CG31
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_PCPU_S1 AP46 20%
2 6.3V
X5R-CERM D
0201
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
30 PP0V78_SOC_FIXED_S1 CG52 VDD_FIXED_MIPID_S1 VDD_FIXED_ECPU_S1 AY39
1 C1906 1 C1905
2.2UF 0.1UF
20% 20% CG56 VDD_FIXED_MIPIC_S1 VDD_FIXED_MTR_S1 CF60
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201 01005 PP0V78_SOC_FIXED_S1 30
C1941 C1942 C1902

1 1 1
CK55 VDD_FIXED_MIPID_PLL_S1 VDD_FIXED_PLL_GPU_S1 AE41
30 PP0V78_SOC_FIXED_S1 0.1UF 0.1UF 0.1UF
20% 20% 20%
2 6.3V 2 6.3V 2 6.3V
1 C1910 X5R-CERM
01005
X5R-CERM
01005
X5R-CERM
01005
0.1UF J20 VDD_FIXED_USB_S1 VDD_FIXED_PLL_DDR0_S1 CE12 ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
20%
2 6.3V VDD_FIXED_PLL_DDR1_S1 BP60
X5R-CERM
01005 VDD_FIXED_PLL_DDR2_S1 AC10
ROOM=SOC_FILT
J52 VDD_FIXED_LPDP_TX_S1 VDD_FIXED_PLL_DDR3_S1 P60
30 GND J56 VDD_FIXED_LPDP_TX_S1
(Not used for MLBs)
CE33 VDD_FIXED_LPDP_RX_S1 VDD_FIXED_PLL_SOC_S1 BH27
PP0V78_SOC_FIXED_S1
30
CE37 VDD_FIXED_LPDP_RX_S1
1 C1916 1 C1918 1 C1917 CE41 VDD_FIXED_LPDP_RX_S1
4UF 0.1UF 0.1UF CE46 VDD_FIXED_LPDP_RX_S1 VDD_FIXED_PLL_ANE_S1 CA35
20% 20% 20%
2 4V 2 6.3V 2 6.3V
X5R
0201
ROOM=SOC_FILT
X5R-CERM
01005
X5R-CERM
01005 R1970
L16 F9 PP0V78_VDD_FIXED_XTAL 1
20.0 2 PP0V78_SOC_FIXED_S1
VDD_FIXED_PCIE_S1 VDD_FIXED_XTAL_S1 30
L20 VOLTAGE=0.8
PP0V78_SOC_FIXED_S1 N16
VDD_FIXED_PCIE_S1
VDD_FIXED_PCIE_S1
1 C1970 5%
1/32W
MF
2.2UF
C
30
C
01005
20%
1 C1922 1 C1921 1 C1920 2 6.3V
X5R-CERM
ROOM=SOC_FILT
4UF 0.1UF 0.1UF 0201

20% 20% 20%
2 6.3V 2 6.3V
ROOM=SOC_FILT
2 4V
X5R X5R-CERM X5R-CERM
0201 01005 01005 [SS] MURATA
ROOM=SOC_FILT
PP1V2_S2
SOC: VDD12
30
30 PP1V2_IO
Place cap near pin 1 C1935
1 C1904 [LAYOUT] VDDIO12_GRPx: Isolation >= 2.5nH
2.2UF
0.1UF 998-22473 20% from other nets on the same domain
20% 2 6.3V
2 6.3V
X5R-CERM ROOM=SOC U1000 X5R-CERM
0201 OMIT
01005
ROOM=SOC_FILT
SICILY-4GB-1YNM-M ROOM=SOC_FILT
XW1901
SHORT-10L-0.1MM-SM
CSP
SYM 18 OF 21 PP1V2_IO_GRP3 2 1 PP1V2_IO 30
30 PP1V2_S2 VOLTAGE=1.2
OMIT_TABLE
Place cap near pin 1 C1900 F22 VDD12_USB VDDIO12_GRP1_S2 CG12
NO_XNET_CONNECTION
RADAR #: 54364908
VDD12 2.2UF
0.1UF F24 VDD12_USB_DEBUG_S2 20%
PLACE NEAR SOC 20% VDDIO12_GRP3 AY56 2 6.3V
6.3V
2 X5R-CERM X5R-CERM OMIT
OMIT To ANE VDDIO12_GRP3 BD56 0201
XW1930 14
01005
ROOM=SOC_FILT
VDDIO12_GRP3 BL56
ROOM=SOC_FILT
XW1902
SHORT-10L-0.1MM-SM
SHORT-20L-0.05MM-SM CG16 PP1V2_IO_GRP4 2 1 PP1V2_IO
1 2 AP44 VDDIO12_GRP4 30
PP1V2_SOC PP1V2_SOC_FILT VOLTAGE=1.2 VDD12_PLL_PCPU VOLTAGE=1.2
30
CG20
ROOM=SOC_FILT Place 01005 caps 1 C1926 1 C1927 1 C1928
VDDIO12_GRP4
VDDIO12_GRP4 CG23
NO_XNET_CONNECTION
near pins 2.2UF
2.2UF 0.1UF 0.1UF VDDIO12_GRP5 AH8 20%
(incl. ANE) 20% 20% 20%
AM8 2 6.3V
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM AY37 VDDIO12_GRP5 X5R-CERM
0201
0201 01005 01005 VDD12_PLL_ECPU AT8
VDDIO12_GRP5 ROOM=SOC_FILT
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
VDDIO12_GRP5 AY8
PP1V2_IO
VDDIO12_GRP5 BD8 30
B 30 PP1V2_S1 1
FL1950
2 PP1V2_S1_XTAL
VOLTAGE=1.2 AE39
1 C1948 B
1 C1946 240-OHM-25%-0.20A-1.0DCR 1 C1903 VDD12_PLL_GPU
VDD12_PCIE J14
2.2UF
20%
4UF 01005 0.1UF 2 6.3V
20% ROOM=SOC_FILT
155S0755 20% VDD12_PCIE J18 X5R-CERM
2 4V 2 6.3V 0201
X5R X5R-CERM ROOM=SOC_FILT
0201 01005
ROOM=SOC_FILT ROOM=SOC_FILT F7 VDD12_XTAL_S1 PP1V2_SOC 30
30 PP1V2_S2 CL9 VDD12_AMUX_S2 VDD12_MTR CH60 PP1V2_SOC 30
30 PP1V2_IO CG54 VDD12_MIPIC 1 C1937 1 C1955 1 C1950

PP1V2_S1 CK53 VDD12_MIPID_S1 2.2UF 0.1UF 4UF
30
VDD12_LPDP_TX L50 20% 20% 20%
2 6.3V 2 6.3V 2 4V
1 C1998 1 C1999 1 C1997 1 C1996 AM41 VDD12_TSADC_CPU0
VDD12_LPDP_TX L54 X5R-CERM
0201
X5R-CERM
01005
X5R
0201
2.2UF 0.1UF 2.2UF 0.1UF ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
20% 20% 20% 20% AT39 VDD12_TSADC_CPU1
6.3V
2 X5R-CERM 2 6.3V 2 6.3V 2 6.3V
X5R-CERM X5R-CERM X5R-CERM GND
0201 01005 0201 01005 30
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT AP35 VDD12_TSADC_SOC0
AC52 VDD12_TSADC_SOC1
VDD12_LPDP_RX CG35 PP1V2_IO
PP1V2_IO R12 VDD12_TSADC_SOC2
30
30
CG39
VDD12_LPDP_RX
VDD12_LPDP_RX CG44
1 C1931 1 C1932 1 C1933
PP1V2_S2 J27 VDDIO12_AOP_S2 0.01UF 0.1UF 4UF
30
VDD12_LPDP_RX CG48 10% 20% 20%
J31 2 6.3V 2 6.3V 2 4V
Place cap near pins 1 C1923 1 C1924 J35
VDDIO12_AOP_S2
VDDIO12_AOP_S2
VDD12_LPDP_RX CG37 X5R
01005
X5R-CERM
01005
X5R
0201
2.2UF 0.1UF ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
20% 20% J39 VDDIO12_AOP_S2 VDD12_EFUSE1 N50
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM J44 W18
0201 01005 VDDIO12_AOP_S2 VDD12_EFUSE2
ROOM=SOC_FILT
J48 VDDIO12_AOP_S2 VDD12_EFUSE3 AM39
ROOM=SOC_FILT
N48 Used for SoC fusing

BF27 VDD12_EFUSE4
VDD12_PLL_SOC_S1 AP37 GND on all systems
BH29 VDD12_EFUSE5
A R19602
PP1V2_S1 VDD12_PLL_SOC_S1
A
30
R14 49.9 1
1% MF
1 C1963 1 C1964 VDD12_FMON PP1V2_VDD12_FMON
VOLTAGE=1.2 01005 1/32W
PP1V2_IO 30
PAGE TITLE
2.2UF 0.1UF VDD12_PCIE_REFBUF L12 ROOM=SOC_FILT
PP1V2_SOC 30
20% 20% SOC: Power (Fixed & 1V2)
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM VDD12_ULPPLL_S2 L33 PP1V2_VDD12_ULPPLL_S2
49.9 1
R19612 1% MF
PP1V2_S2 DRAWING NUMBER SIZE
0201 01005 VOLTAGE=1.2
30
ROOM=SOC_FILT
ROOM=SOC_FILT 01005 1/32W
051-05170 D
K60
Apple Inc.
ROOM=SOC_FILT
VDD12_ADC_SOC_S1 PP1V2_S1 30
REVISION
PP1V2_S1 CE14 VDDIO12_PLL_DDR0_S1
30
Shares decap with other S1 rails BM60 VDDIO12_PLL_DDR1_S1 1 C1938 1 C1995 1 C1936 [LAYOUT] VDD12_PCIE_REFBUF: Inductance from 10.0.0
AC8 4UF 0.1UF 2.2UF C1995.1 to PP1V2_SOC plane >1.5nH @ 100MHz NOTICE OF PROPRIETARY PROPERTY: BRANCH
VDDIO12_PLL_DDR2_S1
M60 VDDIO12_PLL_DDR3_S1
20%
2 4V
20%
2 6.3V
20%
2 6.3V
crb-1
X5R X5R-CERM X5R-CERM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
0201 01005 0201
14 PP1V2_SOC_FILT CC35 VDD12_PLL_ANE
ROOM=SOC_FILT
ROOM=SOC_FILT ROOM=SOC_FILT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
19 OF 138
Share cap with VDD12_PLL_ECPU/_PCPU/_GPU III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: DDR
998-22473
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 16 OF 21
OMIT_TABLE
30 PP_DCS_S1 BR10 VDD_DCS_DDR0_S1 DDR VDD2_DDR0_S2 BA2 PP1V06_S2 30
138S00321 138S00321
CE10 BP1
1 C2088 1 C2087 1 C2086 1 C2085 VDD_DCS_DDR0_S1 VDD2_DDR0_S2
VDD2_DDR0_S2 BV1
1 C2080 1 C2081 1 C2082 1 C2083
4UF 4UF 2.7UF 2.7UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% BR54 VDD_DCS_DDR1_S1 VDD2_DDR0_S2 CB1 20% 20% 20% 20%
D
2 4V
X5R
0201
2 4V
X5R
0201
2 4V
X5R
0201
2 4V
X5R
0201
CE54 VDD_DCS_DDR1_S1 VDD2_DDR0_S2 CL3 2 6.3V
X5R-CERM
0201
2 6.3V
X5R-CERM
0201
2 6.3V
X5R-CERM
0201
2 6.3V
X5R-CERM
0201 D
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
2020-MLCC 2020-MLCC
AA10 VDD_DCS_DDR2_S1 VDD2_DDR1_S2 BA62
L10 VDD_DCS_DDR2_S1 VDD2_DDR1_S2 BM63
PLACE CAPS ON SOC CORNERS BT63 PLACE CAPS ON SOC CORNERS
VDD2_DDR1_S2
AC54 VDD_DCS_DDR3_S1 VDD2_DDR1_S2 BY63
R54 VDD_DCS_DDR3_S1 VDD2_DDR1_S2 CL61
ANALOG_DCS_SENSE_SE AD62 VDD_DCS_SENSE

96 OUT
VDD2_DDR2_S2 AB1
VDD2_DDR2_S2 AN2
PP0V6_VDDQL_S1 BE1 VDDQL_DDR0_S1
30
VDD2_DDR2_S2 D3
BJ1
1 C2093 1 C2092 1 C2091 1 C2090 BM1
VDDQL_DDR0_S1
VDDQL_DDR0_S1
VDD2_DDR2_S2 P1
2.2UF 2.2UF 2.2UF 2.2UF VDD2_DDR2_S2 V1
20% 20% 20% 20% BU8 VDDQL_DDR0_S1
2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM CE8
0201 0201 0201 0201 VDDQL_DDR0_S1 AN62
CF1 VDD2_DDR3_S2
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
VDDQL_DDR0_S1 D61
CJ1 VDD2_DDR3_S2
VDDQL_DDR0_S1 M63
CL1 VDD2_DDR3_S2
PLACE CAPS ON SOC CORNERS VDDQL_DDR0_S1 T63
VDD2_DDR3_S2
VDD2_DDR3_S2 Y63
BC63 VDDQL_DDR1_S1
BG63 VDDQL_DDR1_S1
BK63 VDDQL_DDR1_S1
BR56 VDDQL_DDR1_S1
VDDIO11_RET_DDR0_S2 CJ4
CC56 VDDQL_DDR1_S1
VDDIO11_RET_DDR1_S2 BT60
CD63 VDDQL_DDR1_S1
VDDIO11_RET_DDR2_S2 K4
CH63 VDDQL_DDR1_S1
VDDIO11_RET_DDR3_S2 Y60
CK63 VDDQL_DDR1_S1
C AD1
C
VDDQL_DDR2_S1 BA1
AG1 VDD1_DDR0_S2 PP1V8_S2 30
VDDQL_DDR2_S1 CM2
AL1 VDDQL_DDR2_S1
VDD1_DDR0_S2 1 C2096 1 C2097 1 C2098 1 C2099
E1 VDDQL_DDR2_S1 0.22UF 0.22UF 0.22UF 0.22UF
VDD1_DDR1_S2 BA63 10% 10% 10% 10%
G1 VDDQL_DDR2_S1 2 6.3V 2 6.3V 2 6.3V 2 6.3V
VDD1_DDR1_S2 CM62 CER-X5R CER-X5R CER-X5R CER-X5R
K1 VDDQL_DDR2_S1 01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
L8 VDDQL_DDR2_S1
VDD1_DDR2_S2 AN1
W8 VDDQL_DDR2_S1
VDD1_DDR2_S2 C2 PLACE CAPS ON SOC CORNERS
AB63 VDDQL_DDR3_S1
VDD1_DDR3_S2 AN63
AE56 VDDQL_DDR3_S1
VDD1_DDR3_S2 C62
AF63 VDDQL_DDR3_S1
AJ63 VDDQL_DDR3_S1
D63 VDDQL_DDR3_S1
F63 VDDQL_DDR3_S1
H63 VDDQL_DDR3_S1
R56 VDDQL_DDR3_S1
96 ANALOG_VDDQL_SENSE_SE AD60 VDDQL_SENSE

OUT
PP0V7_VDD_LOW_S2
SOC: AOP/AVE/ISP/USB
30
1 C2000 1 C2001 998-22473

2.2UF 2.2UF
20%
2 6.3V
20%
2 6.3V
ROOM=SOC U1000
X5R-CERM X5R-CERM
1 C2020 0201 0201 SICILY-4GB-1YNM-M
R2021
CSP
0.1UF
B B
SYM 15 OF 21
10 20%
1 2 2 6.3V
X5R-CERM OMIT_TABLE
01005 PLACE AT SOC BALLS J25 CG10 PP1V8_IO
5%
1/32W 1 C2050 ROOM=SOC_FILT
L29
VDD_LOW_S2 VDDIO18_GRP1 30
MF
01005
20%
0.47UF
L37
VDD_LOW_S2
VDD_LOW_S2 VDDIO06_GRP1_1 CK9 PP0V6_VDDIO06_GRP1_1
1 C2073
4UF
R2022
ROOM=SOC_FILT
2 6.3V
X5R L41 VOLTAGE=0.6 20%
VDD_LOW_S2
49.9 01005 2 4V
1 2 ROOM=SOC_FILT L46 VDD_LOW_S2
LOW/AVE/DISP
VDDIO06_GRP1_2 CK11 PP0V6_VDDIO06_GRP1_2
VOLTAGE=0.6
1 C2010 X5R
0201
4UF ROOM=SOC_FILT
1%
1/32W
MF
1 C2052 J23 VDD_LOW_USB_DEBUG_S2 1 C2011
20%
2 4V
01005 4UF X5R
ROOM=SOC_FILT 20% PP0V7_VDD_LOW_FLPPLL VOLTAGE=0.7 J33 VDD_LOW_FLPPLL_S2 4UF 0201
ROOM=SOC_FILT
2 4V
X5R
20%
0201 L31 2 4V
X5R
ROOM=SOC_FILT
PP0V7_VDD_LOW_ULPPLL VOLTAGE=0.7 VDD_LOW_ULPPLL_S2 0201
ROOM=SOC_FILT
BW23 VDD_AVE_S1 VDDIO06_GRPx RADAR #: 48907718
BW27 VDD_AVE_S1 Cmin = 4.7uF
BW31 VDD_AVE_S1 Loop R < 0.2 ohm
30 PP_AVE_S1 CA29 VDD_AVE_S1 Loop L < 1nH
1 C2026 1 C2025 1 C2024 CC23 VDD_AVE_S1
20UF 20UF 15UF CC27 VDD_AVE_S1
20% 20% 20%
2 6.3V 2 6.3V 2 6.3V CC31 VDD_AVE_S1
CERM-X5R CERM-X5R X5R
0402-0.1MM 0402-0.1MM 0402-0.1MM-1 CE20 VDD_AVE_S1
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
CE25 VDD_AVE_S1
PACK_OPTION=D54
CG27 VDD_AVE_S1
30 PP_DISP_S1 BF10 VDD_DISP_S1

BF14
1 C2033 1 C2030 ROOM=SOC_FILT
BH16
VDD_DISP_S1
VDD_DISP_S1
20%
20UF
20%
20UF C2032 BH8 VDD_DISP_S1
A 2 6.3V 2 6.3V 14UF
CERM-X5R
0402-0.1MM
ROOM=SOC_FILT
CERM-X5R
0402-0.1MM
ROOM=SOC_FILT
20%
4V
X5R
BL10
BL14
VDD_DISP_S1
VDD_DISP_S1
A
0402-D2X-1 PAGE TITLE
BN12 VDD_DISP_S1
1 3 SOC: Power (DDR & AOP/AVE/ISP/USB)
BR14 VDD_DISP_S1
DRAWING NUMBER SIZE
2 4 BU16 VDD_DISP_S1
051-05170 D
BW14
BW18
VDD_DISP_S1 Apple Inc. REVISION
VDD_DISP_S1
CA20 VDD_DISP_S1
10.0.0
CC14 NOTICE OF PROPRIETARY PROPERTY: BRANCH
VDD_DISP_S1
CC18 VDD_DISP_S1
crb-1
20 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: GND
998-22473 998-22473 998-22473
U1000 U1000 U1000
SICILY-4GB-1YNM-M SICILY-4GB-1YNM-M SICILY-4GB-1YNM-M
CSP CSP CSP
SYM 19 OF 21 SYM 20 OF 21 SYM 21 OF 21
OMIT_TABLE OMIT_TABLE OMIT_TABLE
A13 VSS VSS BH10 BY62 VSS VSS CK13 D7 VSS VSS U29
D
ROOM=SOC ROOM=SOC ROOM=SOC
D A17
A61
VSS
VSS
VSS
VSS
BH14
BH18
C1
C11
VSS
VSS
VSS
VSS
AF61
CK2
E11
E13
VSS
VSS
VSS
VSS
U33
U46
AP50 VSS VSS BH23 C15 VSS VSS CK21 E15 VSS VSS U50
AP54 VSS VSS AA33 C19 VSS VSS CK22 E17 VSS VSS V4
AR1 VSS VSS BH31 C22 VSS VSS CK26 AE16 VSS VSS V61
AR4 VSS VSS BH35 C26 VSS VSS CK3 E21 VSS VSS V62
AR60 VSS VSS BH39 C28 VSS VSS CK30 E22 VSS VSS V63
AR63 VSS VSS BH56 AC23 VSS VSS CK34 E24 VSS VSS AE8
AT10 VSS VSS BJ63 C3 VSS VSS CK38 E26 VSS VSS W10
AT14 VSS VSS BK1 C30 VSS VSS CK4 E61 VSS VSS W14
AT18 VSS VSS BK60 C32 VSS VSS CK42 E63 VSS VSS W23
AT23 VSS VSS CH2 C38 VSS VSS AC56 E7 VSS VSS W27
A62 VSS VSS BL12 C4 VSS VSS CK45 F1 VSS VSS W31
AT27 VSS VSS BL16 C40 VSS VSS CK51 F17 VSS VSS W44
AT31 VSS VSS AA46 C42 VSS VSS CK57 F21 VSS VSS W48
AT35 VSS VSS BL20 C43 VSS VSS CK60 AE20 VSS VSS Y1
AT56 VSS VSS BL25 C45 VSS VSS CK7 F32 VSS VSS Y62
AT44 VSS VSS AE33 C47 VSS VSS CL19 F38 VSS VSS A26
AT48 VSS VSS BL41 AC27 VSS VSS CL21 F4 VSS VSS AF1
CF61 VSS VSS BL46 C49 VSS VSS CL24 F43 VSS VSS AF60
AU63 VSS VSS BL50 C5 VSS VSS CL28 F49 VSS VSS AG63
AV12 VSS VSS BL54 C51 VSS VSS CL32 F55 VSS VSS AH10
AV16 VSS VSS BL8 C53 VSS VSS AD4 F59 VSS VSS AH14
A9 VSS VSS BM4 C55 VSS VSS CL36 G63 VSS VSS AH18
AV20 VSS VSS BM61 C57 VSS VSS CL40 H1 VSS VSS AH23
AV25 VSS VSS A2 C58 VSS VSS CL43 H3 VSS VSS BF29
AV29 C59
C
AA50 CL45 AE25 AH31
C AV33
VSS
VSS
VSS
VSS BM62 C6
VSS
VSS
VSS
VSS CL63 H4
VSS
VSS
VSS
VSS AH35
AV37 VSS VSS BN10 C60 VSS VSS CM1 H61 VSS VSS A3
AV54 VSS VSS BN14 AC31 VSS VSS CM17 J29 VSS VSS AH39
AV8 VSS VSS BN18 C61 VSS VSS CM19 J37 VSS VSS AH44
AW1 VSS VSS BN23 C63 VSS VSS CM22 J41 VSS VSS AH48
AW63 VSS VSS BN27 C7 VSS VSS CM26 J46 VSS VSS AH52
AY10 VSS VSS BN31 C9 VSS VSS BB25 J50 VSS VSS AH56
AA12 VSS VSS BN35 CA14 VSS VSS CM30 J54 VSS VSS AJ1
AY14 VSS VSS BN39 CA18 VSS VSS CM34 J8 VSS VSS AJ4
AY18 VSS VSS BN44 CA23 VSS VSS CM38 K2 VSS VSS AJ60
AY23 VSS VSS AA8 CA27 VSS VSS CM42 AE29 VSS VSS AK12
AY27 VSS VSS BN48 CA31 VSS VSS CM45 K63 VSS VSS AK16
BB56 VSS VSS BN52 CA39 VSS VSS CM47 L14 VSS VSS A32
B1 VSS VSS BN56 AC35 VSS VSS CM49 L18 VSS VSS AK20
B13 VSS VSS BP61 CB62 VSS VSS CM51 L23 VSS VSS AK25
B17 VSS VSS BP62 CB63 VSS VSS CM53 L27 VSS VSS AK29
B21 VSS VSS BP63 CC12 VSS VSS CM55 L35 VSS VSS AK33
B24 VSS VSS BR16 CC16 VSS VSS AT52 L39 VSS VSS AK37
AA16 VSS VSS BR20 CC20 VSS VSS CM57 L44 VSS VSS AK41
B26 VSS VSS BR25 CC25 VSS VSS CM58 L48 VSS VSS AK46
B32 VSS VSS AB61 CC33 VSS VSS CM60 AE37 VSS VSS AK54
B51 VSS VSS BR37 CC46 VSS VSS CM63 M1 VSS VSS A38
B61 VSS VSS BR41 A21 VSS VSS CN1 M3 VSS VSS AL63
B63 VSS VSS BR46 AC39 VSS VSS CN13 M4 VSS VSS AM10
B B9 VSS VSS BR50 CC50 VSS VSS CN17 M61 VSS VSS AM14 B
BA4 VSS VSS BR8 CC54 VSS VSS CN4 M62 VSS VSS AM18
BA60 VSS VSS BT1 CD1 VSS VSS W52 N12 VSS VSS AM23
AA20 VSS VSS BT61 CD4 VSS VSS CN45 N20 VSS VSS AM27
BA61 VSS VSS BT62 CD62 VSS VSS CN57 N25 VSS VSS AM31
BB12 VSS VSS BU10 CE18 VSS VSS CN61 N29 VSS VSS AM35
BB16 VSS VSS AB60 CE23 VSS VSS CN63 AE46 VSS VSS AP41
BB20 VSS VSS BU14 CE27 VSS VSS CN7 N33 VSS VSS AM44
BB37 VSS VSS BU18 CE31 VSS VSS CP17 N41 VSS VSS A51
BB54 VSS VSS BU23 CE35 VSS VSS CP2 N54 VSS VSS AM48
BB8 VSS VSS BU27 AC44 VSS VSS CP21 P61 VSS VSS AM52
BC1 VSS VSS BU31 CE39 VSS VSS CP24 P62 VSS VSS BF25
BD10 VSS VSS BU35 CE48 VSS VSS CP28 P63 VSS VSS AP12
BD14 VSS VSS BU39 CE56 VSS VSS AD63 R18 VSS VSS BL29
AA25 VSS VSS BV4 CF62 VSS VSS CP3 R23 VSS VSS AP20
BD18 VSS VSS BV61 CF63 VSS VSS CP32 R27 VSS VSS AP25
BD23 VSS VSS BV62 CG14 VSS VSS CP36 R31 VSS VSS AP29
BD27 VSS VSS AC14 CG25 VSS VSS CP40 AE50 VSS VSS AP33
BD39 VSS VSS BV63 CG33 VSS VSS CP43 R35 VSS VSS BR12
BE63 VSS VSS BW12 CG41 VSS VSS CP45 R39 VSS
VSS_SENSE AP18 ANALOG_SOC_SENSE_N
BF12 VSS VSS BW16 CG46 VSS VSS CP57 R44 VSS OUT 96
BF16 BW20 AC48 CP61 R48 VSS_X: Corner ball test pins, GND on MLB
VSS VSS VSS VSS VSS CP1
BF20 BW25 CG50 CP62 R52 VSS_1 GND 20
VSS VSS VSS VSS VSS CP63
BF33 BW29 CG8 D1 T1 VSS_2 GND 20
VSS VSS VSS VSS VSS A1
VSS_3 GND
AA29 VSS VSS BW33 CH1 VSS VSS A24 T60 VSS
VSS_4 A63 GND
20
BF37 BW37 CH3 AE12 T61 20
A BF54
VSS
VSS
VSS
VSS BW50 CH4
VSS
VSS
VSS
VSS D11 T62
VSS
VSS AD61 ANALOG_DDR_SENSE_SE
A
BF8 BY1 CH61 D15 U16 VSS_DDR_SENSE OUT 96
PAGE TITLE
VSS VSS VSS VSS VSS
BG1
BG4
VSS VSS AC18
BY60
CJ2
CJ63
VSS VSS D19
D22
AE54
U20
VSS VSS_GPU_SENSE AH27 ANALOG_GPU_SENSE_N OUT 96 SOC: Power (GND)
VSS VSS VSS VSS VSS BL35 DRAWING NUMBER SIZE
VSS_PCPU_SENSE ANALOG_PCPU_SENSE_N
BG60 VSS VSS BY61 CK1 VSS VSS D26 U25 VSS OUT 96
051-05170 D
Apple Inc. REVISION
VSS_DDR_SENSE: Common GND for VDD_DCS_SENSE
and VDDQL_SENSE
10.0.0

crb-1
21 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AP/ISP I2C
AP I2C0 (Unused)
D D
AP I2C1 (Unused)
AP I2C2
30 17 3
PP1V2_IO
R2340 1 R2341 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF MASTER AP NUMBER I2C2 DIAGS NUMBER 2 SPEED 1MHz
01005 2 01005 2
ROOM=SOC ROOM=SOC
DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
9 I2C2_AP_SCL MAKE_BASE=TRUE I2C2_AP_SCL OUT 63
Top Spk Amp 1.2V 0x40 0x80, 0x81 1MHz MLB
9 I2C2_AP_SDA MAKE_BASE=TRUE I2C2_AP_SDA BI 63
C 88 55 49 30 26
PP1V8_IO C
R2390 1 R2391 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
MASTER AP NUMBER I2C3 DIAGS NUMBER 3 SPEED 400kHz

9 I2C3_AP_SCL_1V8 MAKE_BASE=TRUE I2C3_AP_SCL_1V8 OUT 68 88 89 90
9 I2C3_AP_SDA_1V8 MAKE_BASE=TRUE I2C3_AP_SDA_1V8 BI 68 88 89 90 Touch EEPROM 1.8V 0x51 0xA2, 0xA3 400kHz Touch Flex
Babbage (TFE) 1.8V 0x4B 0x96, 0x97 1MHz Touch Flex D52/D54 only
NOTE: For D52/D54, bus can either be mastered by SoC or Ada
Roswell 1.8V 0x10 0x20, 0x21 400kHz Touch Flex D53 only
NOTE: Roswell is I2C for D53-only (AID for D52/D54)
AP I2C4 (Legacy 1.8V)

MASTER AP NUMBER I2C4 DIAGS NUMBER 4 SPEED 400kHz
9 I2C_DISPLAY_SCL_1V8 MAKE_BASE=TRUE I2C_DISPLAY_SCL_1V8 OUT 69 87 90
9 I2C_DISPLAY_SDA_1V8 MAKE_BASE=TRUE I2C_DISPLAY_SDA_1V8 BI 69 87 90 DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
MAKE_BASE for Display PMIC intentional, test feature only Display PMIC 1.8V 0x50 0xA0, 0xA1 400kHz MLB
SI2C0 NOTE: SoC is master for FCT *ONLY*, DDIC is master for normal operation
B 30 17 3 PP1V2_IO
B
1
R2310 1
R2311
4.7K 4.7K
1% 1%
1/32W 1/32W
MF MF
2 01005
ROOM=SOC
2 01005
ROOM=SOC
9 I2C0_S_SCL MAKE_BASE=TRUE I2C0_S_SCL OUT 12
9 I2C0_S_SDA MAKE_BASE=TRUE I2C0_S_SDA BI 12
ISP I2C0
7 NC_I2C0_ISP_SCL MAKE_BASE=TRUE NC_I2C0_ISP_SCL NO_TEST=1
7 NC_I2C0_ISP_SDA MAKE_BASE=TRUE NC_I2C0_ISP_SDA NO_TEST=1

A ISP I2C1 (Unused) A
PAGE TITLE
7 NC_I2C1_ISP_SCL MAKE_BASE=TRUE NC_I2C1_ISP_SCL NO_TEST=1
SOC: Aliases: I2C AP/ISP
7 NC_I2C1_ISP_SDA MAKE_BASE=TRUE NC_I2C1_ISP_SDA NO_TEST=1
DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0

crb-1
23 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AOP I2C0
AOP/SMC I2C
PP1V2_S2 PP1V8_S2
30 18
PP1V2_S2 18 30 18 30 84
MASTER AOP NUMBER I2C0 DIAGS NUMBER 5 SPEED 400kHz
R2422 1 C2420 R2424 R2425 1 1

R2426 DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
R2420 1
R2421 1
33.2 U2420 0.1UF 33.2 2.2K 2.2K
4.7K 4.7K 1 2 20% 1 2 5% 5% Prox 1.8V 0x58 0xB0, 0xB1 1MHz Sensor Flex
1% 1% LSF0101 2 6.3V
X5R-CERM 1/32W 1/32W
1/32W 1/32W 1% 1% MF MF
MF MF 1/32W X2SON 01005 1/32W 01005 2 01005 ALS 1.8V 0x29 0x52, 0x53 1MHz Sensor Flex
01005 2 01005 2 MF MF 2
VBIAS 6 ROOM=LVL_SENSOR ROOM=LVL_SENSOR ROOM=LVL_SENSOR
D
ROOM=SOC ROOM=SOC 01005 01005
D
ROOM=LVL_SENSOR ROOM=LVL_SENSOR Grievous 1.8V 0x33 0x66, 0x67 1MHz Sensor Flex
11
I2C0_AOP_SDA MAKE_BASE=TRUE
R2423 I2C0_AOP_SDA_R 2 SDAA SDAB
311S00233
5 I2C0_AOP_SDA_1V8_R
I2C0_AOP_SDA_1V8 I2C0_AOP_SDA_1V8 BI 84 Compass 1.8V 0x0E 0x1C, 0x1D 1MHz Sensor Flex
I2C0_AOP_SCL 1
33.2 2
CKPLUS_WAIVE=I2C_PULLUP
I2C0_AOP_SCL_R 3 SCLA 4
I2C0_AOP_SCL_1V8 MAKE_BASE=TRUE
11 MAKE_BASE=TRUE SCLB I2C0_AOP_SCL_1V8 OUT 84
CKPLUS_WAIVE=I2C_PULLUP ROOM=LVL_CHARGER MAKE_BASE=TRUE
1%
1/32W GND
MF
01005
1
AOP I2C1 ROOM=LVL_SENSOR
30 18
PP1V2_S2
R2430 1 R2431 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC MASTER AOP NUMBER I2C1 DIAGS NUMBER 6 SPEED 400kHz
11
I2C1_AOP_SCL I2C1_AOP_SCL OUT 86 DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
MAKE_BASE=TRUE
11
I2C1_AOP_SDA I2C1_AOP_SDA BI 86
MAKE_BASE=TRUE
Eiger 1.2V 0x76 0xEC, 0xED 1MHz Dock
I2C1_AOP_SCL OUT 86 Arc EEPROM 1.2V 0x50 0xA0, 0xA1 1MHz Arc Flex
I2C1_AOP_SDA BI 86
Jarvis 1.2V 0x0F 0x1E, 0x1F 1MHz MLB
I2C1_AOP_SCL OUT 58 59
I2C1_AOP_SDA BI 58 59
C C
AOP I2C2
30 18
PP1V2_S2
R2440 1 R2441 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
29 11
I2C2_AOP_SCL I2C2_AOP_SCL OUT 66
MAKE_BASE=TRUE
I2C2_AOP_SDA MASTER AOP NUMBER I2C2 DIAGS NUMBER 7 SPEED 1MHz
11
MAKE_BASE=TRUE
I2C2_AOP_SDA BI 66

I2C2_AOP_SCL OUT 65
Sakonnet 1.2V 0x08 0x10, 0x11 1MHz MLB
I2C2_AOP_SDA BI 65
SMC I2C0 I2C2_AOP_SCL OUT 62

Codec 1.2V 0x4A 0x94, 0x95 1MHz MLB
Arc Amp 1.2V 0x42 0x84, 0x85 1MHz MLB

30 18 PP1V2_S2 I2C2_AOP_SDA BI 62
Bot Spk Amp 1.2V 0x40 0x80, 0x81 1MHz MLB

R2450 1 R2451 1 I2C2_AOP_SCL OUT 61
2.2K 2.2K I2C2_AOP_SDA
5% 5% BI 61
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
MASTER SMC NUMBER I2C0 DIAGS NUMBER 8 SPEED 400kHz
11 I2C0_SMC_SCL MAKE_BASE=TRUE I2C0_SMC_SCL OUT 71
11 I2C0_SMC_SDA MAKE_BASE=TRUE I2C0_SMC_SDA BI 71 DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
B CCG2B 1.2V 0x12 0x24, 0x25 1MHz MLB

B
SMC I2C1
30 18 PP1V2_S2
R2460 1 R2461 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 01005
ROOM=SOC 2 ROOM=SOC 2
97 11 I2C1_SMC_SCL MAKE_BASE=TRUE I2C1_SMC_SCL OUT 70

97 11 I2C1_SMC_SDA MAKE_BASE=TRUE I2C1_SMC_SDA BI 70

I2C1_SMC_SCL OUT 73
I2C1_SMC_SDA BI 73 Kraken 1.2V 0x1A 0x34, 0x35 1MHz MLB

I2C1_SMC_SCL OUT 72 Parrot 1.2V 0x21 0x42, 0x43 1MHz MLB
I2C1_SMC_SDA BI 72 DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
Gecko2 1.2V 0x52 0xA4, 0xA5 1MHz MLB
Yangtze 1.8V 0x71 0xE2, 0xE3 400kHz MLB
SMC I2C2 Veridian 1.8V 0x0B 0x16, 0x17 400kHz Battery Flex
PP1V2_S2 18 PP1V8_S2
30 18 PP1V2_S2 30 18 30 84
ROOM=LVL_CHARGER
R2474 1 C2470 R2475 R2472 1 1

R2473
R2470 1 R2471 1 33.2 U2470 0.1UF 33.2 2.2K 2.2K
4.7K 4.7K 1 2 20% 1 2 5% 5%
1% 1% LSF0101 2 6.3V
X5R-CERM 1/32W 1/32W
1/32W
MF
01005
1/32W
MF
01005
1%
1/32W
MF
X2SON 01005 1%
1/32W
MF
MF
01005 2 2
MF
01005 SYNCING: D52, D53, D54
ROOM=SOC 2 ROOM=SOC 2 6 ROOM=LVL_CHARGER
A VBIAS
A
01005 01005 ROOM=LVL_CHARGER ROOM=LVL_CHARGER
ROOM=LVL_CHARGER
11 I2C2_SMC_SDA MAKE_BASE=TRUE
R2476 I2C2_SMC_SDA_R 2 SDAA SDAB
311S00233
5 I2C2_SMC_SDA_1V8_R
I2C2_SMC_SDA_1V8 I2C2_SMC_SDA_1V8
BI 31
PAGE TITLE
I2C2_SMC_SCL 1
33.2 2
I2C2_SMC_SCL_R 3 SCLA 4
I2C2_SMC_SCL_1V8 MAKE_BASE=TRUE I2C2_SMC_SCL_1V8 SOC: Aliases: I2C AOP/SMC

11 MAKE_BASE=TRUE SCLB OUT 31
CKPLUS_WAIVE=I2C_PULLUP ROOM=LVL_CHARGER MAKE_BASE=TRUE
1% DRAWING NUMBER SIZE
1/32W GND I2C2_SMC_SDA_1V8
MF BI 76
051-05170 D
01005 I2C2_SMC_SCL_1V8 Apple Inc.
1
OUT 76
ROOM=LVL_CHARGER REVISION
10.0.0

crb-1
24 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AOP GPIOs
* All AOP GPIOs tie into SCM block
AP GPIOs
AP_GPIO0 10
GPIO_BOARD_REV3 GPIO_BOARD_REV3 3
IN
SPMI0 SPI AOP_FUNC0 11 GPIO_SCM_AOP_FROM_IMU_DATARDY GPIO_SCM_AOP_FROM_IMU_DATARDY IN 57
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO1 10
IN
SPMI0 SPI AOP_FUNC1 11 GPIO_SCM_AOP_TO_IMU_SPI_CS_L GPIO_SCM_AOP_TO_IMU_SPI_CS_L OUT 57
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO2 10
IN
SPMI0 SPI AOP_FUNC2 11 GPIO_AOP_FROM_PEARL_B2B_DETECT GPIO_AOP_FROM_PEARL_B2B_DETECT IN 83
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO3 10
IN
NC_DEV_AOP_FUNC3 NC_DEV_AOP_FUNC3
D
MAKE_BASE=TRUE
D
SPMI0 SPI AOP_FUNC3 11 21
AP_GPIO4 10
GPIO_AP_CANARY1 GPIO_AP_CANARY1 98
IN
SPMI1 SPI AOP_FUNC4 GPIO_SCM_AOP_FROM_R1_INT GPIO_SCM_AOP_FROM_R1_INT MAKE_BASE=TRUE
11
MAKE_BASE=TRUE
IN 101
GPIO_AP_CANARY2
AP_GPIO5 10 GPIO_AP_CANARY2 IN 98
SPMI1 SPI AOP_FUNC5 11 GPIO_AOP_TO_R1_COREDUMP_TRIGGER GPIO_AOP_TO_R1_COREDUMP_TRIGGER OUT 101

MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO6 10
GPIO_AP_BI_CCG2B_SWDIO GPIO_AP_BI_CCG2B_SWDIO 71 96
BI
SPMI1 SPI AOP_FUNC6 11 GPIO_AOP_TO_R1_TIME_SYNC_L GPIO_AOP_TO_R1_TIME_SYNC_L OUT 101
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO7 10
GPIO_AP_TO_CCG2B_SWCLK GPIO_AP_TO_CCG2B_SWCLK 71 96
OUT
SPMI1 SPI AOP_FUNC7 11 GPIO_AOP_TO_CODEC_RESET_L GPIO_AOP_TO_CODEC_RESET_L OUT 61 96
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO8 10
GPIO_AP_FROM_DISPLAY_PANEL_ID GPIO_AP_FROM_DISPLAY_PANEL_ID 87 90
IN
SPI AOP_FUNC8 11 GPIO_AOP_TO_BB_FORCE_PWM GPIO_AOP_TO_BB_FORCE_PWM OUT 99
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO9 10
GPIO_AP_FROM_WLAN_TIME_SYNC GPIO_AP_FROM_WLAN_TIME_SYNC 98
IN
SPI AOP_FUNC9 11 GPIO_AOP_FROM_IRCAM_B2B_DETECT GPIO_AOP_FROM_IRCAM_B2B_DETECT IN 82
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO10 10
GPIO_AP_TO_BB_PEAK_PWR_IND GPIO_AP_TO_BB_PEAK_PWR_IND 99
OUT
SPI AOP_FUNC10 11 GPIO_SCM_AOP_TO_R1_SPI_CS_L GPIO_SCM_AOP_TO_R1_SPI_CS_L OUT 101
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO11 10
GPIO_AP_TO_BB_COREDUMP GPIO_AP_TO_BB_COREDUMP 99
OUT
SPI AOP_FUNC11 11 NC_AOP_FUNC11 NC_AOP_FUNC11 20
MAKE_BASE=TRUE
AP_GPIO12 10
GPIO_AP_FROM_BB_RESET_DETECT_L GPIO_AP_FROM_BB_RESET_DETECT_L 99
IN
I2C0 SPI AOP_FUNC12 11 GPIO_AOP_TO_ALS_COEX GPIO_AOP_TO_ALS_COEX OUT 84
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO13 10
GPIO_AP_FROM_CODEC_INT_L GPIO_AP_FROM_CODEC_INT_L 61 96
IN
I2C0 SPI AOP_FUNC13 11 GPIO_AOP_TO_NFC_IRONMAN_EN GPIO_AOP_TO_NFC_IRONMAN_EN OUT 100
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO14 10
NC_AP_GPIO14 NC_AP_GPIO14 20
I2C0 SPI AOP_FUNC14 11 NC_GPIO_AOP_FROM_TOUCH_CTS NC_GPIO_AOP_FROM_TOUCH_CTS IN 21 88
AP_GPIO15 10
GPIO_AP_TO_SPKRAMP_TOP_RESET_L GPIO_AP_TO_SPKRAMP_TOP_RESET_L 63
OUT
I2C1, I2C0 SPI AOP_FUNC15 11 GPIO_SCM_AOP_BI_PROX_INT_L GPIO_SCM_AOP_BI_PROX_INT_L IN 75
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO16 10
GPIO_AP_FROM_BT_AUDIO_SYNC GPIO_AP_FROM_BT_AUDIO_SYNC 98
IN
I2C1 I2C0 AOP_FUNC16 GPIO_SCM_AOP_FROM_ALS_INT_L GPIO_SCM_AOP_FROM_ALS_INT_L MAKE_BASE=TRUE
C
11 IN 84
C GPIO_AP_TO_AMUX_PMU_SYNC
MAKE_BASE=TRUE
AP_GPIO17 10 GPIO_AP_TO_AMUX_PMU_SYNC OUT 21
I2C1 I2C0 AOP_FUNC17 11 GPIO_SCM_AOP_FROM_EIGER_INT_L GPIO_SCM_AOP_FROM_EIGER_INT_L IN 86

MAKE_BASE=TRUE
AP_GPIO18 10
NC_DEV_AP_GPIO18 NC_DEV_AP_GPIO18 21
I2C1 I2C0 AOP_FUNC18 11 GPIO_SCM_AOP_FROM_COMPASS_INT GPIO_SCM_AOP_FROM_COMPASS_INT IN 75

MAKE_BASE=TRUE
AP_GPIO19 10
I2C1 AOP_FUNC19 11 GPIO_SCM_AOP_FROM_JARVIS_INT GPIO_SCM_AOP_FROM_JARVIS_INT IN 58 59 96 Great Dane

MAKE_BASE=TRUE
AP_GPIO20 10
I2C1 AOP_FUNC20 11 GPIO_AOP_FROM_TOUCH_INT_L GPIO_AOP_FROM_TOUCH_INT_L IN 68 88

MAKE_BASE=TRUE
AP_GPIO21 10
I2C1 AOP_FUNC21 11 NC_AOP_FUNC21 NC_AOP_FUNC21 20
AP_GPIO22 10
I2C1 AOP_FUNC22 11 NC_DEV_AOP_FUNC22 NC_DEV_AOP_FUNC22 21
AP_GPIO23 10
AP_GPIO24 10
AP_GPIO25 10
GPIO_AP_TO_BB_TIME_MARK GPIO_AP_TO_BB_TIME_MARK 99
OUT
MAKE_BASE=TRUE
AP_GPIO26 10
B B

A A
PAGE TITLE
SOC: Aliases: GPIOs

DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0

crb-1
25 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Misc. SoC Aliases 70

UART: KRAKEN
UART0_AP_TO_KRAKEN_DEBUG_TXD UART0_AP_TO_KRAKEN_DEBUG_TXD
MAKE_BASE=TRUE
9 96 SOC: PCIe
70 UART0_AP_FROM_KRAKEN_DEBUG_RXD UART0_AP_FROM_KRAKEN_DEBUG_RXD 9 96 6
NC_DEV_PCIE_GP0_AP_CLKREQ_L NC_DEV_PCIE_GP0_AP_CLKREQ_L
MAKE_BASE=TRUE MAKE_BASE=TRUE
NO_TEST=1
70 UART4_AP_TO_KRAKEN_ACC_TXD UART4_AP_TO_KRAKEN_ACC_TXD 9 96 6 NC_DEV_PCIE_GP0_AP_REFCLK_P NC_DEV_PCIE_GP0_AP_REFCLK_P

70 UART4_AP_FROM_KRAKEN_ACC_RXD UART4_AP_FROM_KRAKEN_ACC_RXD NO_TEST=1
MAKE_BASE=TRUE
9 96
6 NC_DEV_PCIE_GP0_AP_REFCLK_N NC_DEV_PCIE_GP0_AP_REFCLK_N
NAND + USB & MISC
MAKE_BASE=TRUE
NO_TEST=1
NC_DEV_PCIE_GP0_AP_RX_P
DISPLAY 6 NC_DEV_PCIE_GP0_AP_RX_P
D
MAKE_BASE=TRUE
D PP1V2_IO NO_TEST=1
5 PP1V2_IO NC_DEV_PCIE_GP0_AP_RX_N
MAKE_BASE=TRUE
20 26 30
6 NC_DEV_PCIE_GP0_AP_RX_N
5 PP1V2_IO MAKE_BASE=TRUE
NO_TEST=1
6
NC_DEV_PCIE_GP0_AP_TX_P NC_DEV_PCIE_GP0_AP_TX_P
MAKE_BASE=TRUE
NO_TEST=1
6
NC_DEV_PCIE_GP0_AP_TX_N NC_DEV_PCIE_GP0_AP_TX_N
MAKE_BASE=TRUE
94 5 IO_SOC_FROM_PMU_KRAKEN_FORCE_DFU IO_SOC_FROM_PMU_KRAKEN_FORCE_DFU NC_DEV_PCIE_GP0_AP_RESET_L

NO_TEST=1
MAKE_BASE=TRUE
27
6 NC_DEV_PCIE_GP0_AP_RESET_L
MAKE_BASE=TRUE
IO_SOC_FROM_PMU_KRAKEN_FORCE_DFU 70 NO_TEST=1
5 NC_DEV_AP_TMR32_PWM0 NC_DEV_AP_TMR32_PWM0
MAKE_BASE=TRUE
SOC: Serial
NO_TEST=1
NC_UART1_AP_CTS_L NC_UART1_AP_CTS_L
5 NC_DEV_AP_TMR32_PWM1 NC_DEV_AP_TMR32_PWM1 9
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=1 9
NC_UART1_AP_RTS_L NC_UART1_AP_RTS_L NO_TEST=1
5 NC_DEV_AP_TMR32_PWM2 NC_DEV_AP_TMR32_PWM2 NC_UART1_AP_RXD

MAKE_BASE=TRUE
MAKE_BASE=TRUE 9 NC_UART1_AP_RXD NO_TEST=1
NO_TEST=1 MAKE_BASE=TRUE
8 NC_SOC_DWI_CLK NC_SOC_DWI_CLK NC_UART1_AP_TXD
5 NC_DEV_PAD_MTR_VREF_P NC_DEV_PAD_MTR_VREF_P MAKE_BASE=TRUE 9 NC_UART1_AP_TXD NO_TEST=1
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE

8 NC_SOC_DWI_DATA NC_SOC_DWI_DATA NC_UART2_AP_CTS_L
NO_TEST=1
NC_UART2_AP_CTS_L NO_TEST=1
5 NC_DEV_PAD_MTR_VREF_N NC_DEV_PAD_MTR_VREF_N MAKE_BASE=TRUE

NO_TEST=1
9
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=1 9
NC_UART2_AP_RTS_L NC_UART2_AP_RTS_L NO_TEST=1
8 NC_TOUCH_BSYNC1_DISP NC_TOUCH_BSYNC1_DISP MAKE_BASE=TRUE
MAKE_BASE=TRUE 9
NC_UART2_AP_RXD NC_UART2_AP_RXD NO_TEST=1
PP1V2_IO PP1V2_IO 8 NC_EDP_HPD_DISP NC_EDP_HPD_DISP NO_TEST=1 MAKE_BASE=TRUE

5
MAKE_BASE=TRUE
20 26 30
MAKE_BASE=TRUE 9
NC_UART2_AP_TXD NC_UART2_AP_TXD NO_TEST=1
8 NC_SOC_DISP_I2C_SCL NC_SOC_DISP_I2C_SCL NC_UART3_AP_CTS_L
MAKE_BASE=TRUE 9 NC_UART3_AP_CTS_L NO_TEST=1
8 NC_SOC_DISP_I2C_SDA NC_SOC_DISP_I2C_SDA
94 27 IO_PMU_TO_SYSTEM_RESET_L IO_PMU_TO_SYSTEM_RESET_L 5 MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
MAKE_BASE=TRUE
8 NC_SOC_DISP_POL NC_SOC_DISP_POL NC_UART3_AP_RXD
C
IO_PMU_TO_SYSTEM_RESET_L 11
8 NC_SOC_DISP_AGPIO NC_SOC_DISP_AGPIO
MAKE_BASE=TRUE
NO_TEST=1
9 NC_UART3_AP_RXD
MAKE_BASE=TRUE C
IO_PMU_TO_SYSTEM_RESET_L 11 MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
8 NC_SOC_DISP_EXT_HPD NC_SOC_DISP_EXT_HPD NC_I2S1_AP_MCLK
MAKE_BASE=TRUE 9 NC_I2S1_AP_MCLK
8 NC_SOC_DISP_TOUCH_EB NC_SOC_DISP_TOUCH_EB
19 NC_AP_GPIO14 NC_AP_GPIO14 NO_TEST=1
NC_DEV_SOC_THROTTLE_TRIGGER0 MAKE_BASE=TRUE NC_DEV_SOC_THROTTLE_TRIGGER0 5

MAKE_BASE=TRUE
NO_TEST=1 NO_TEST=1
NC_DEV_PMU_CPU_TRIGGER0 MAKE_BASE=TRUE NC_DEV_PMU_CPU_TRIGGER0 27

8 NC_DEV_LPDP_AP_TX0P NC_DEV_LPDP_AP_TX0P
NO_TEST=1
8 NC_DEV_LPDP_AP_TX0N NC_DEV_LPDP_AP_TX0N MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
8 NC_DEV_LPDP_AP_TX1P NC_DEV_LPDP_AP_TX1P
96 IO_AP_FROM_PMU_SW_SHDN_L IO_AP_FROM_PMU_SW_SHDN_L NC_DEV_LPDP_AP_TX1N
5
8 NC_DEV_LPDP_AP_TX1N MAKE_BASE=TRUE
NC_I2S2_AP_MCLK
MAKE_BASE=TRUE NO_TEST=1
NC_I2S2_AP_MCLK
IO_AP_FROM_PMU_SW_SHDN_L NC_DEV_LPDP_AP_TX2P
MAKE_BASE=TRUE
NO_TEST=1
9
27
8 NC_DEV_LPDP_AP_TX2P NC_SSPI0_MISO_AP
MAKE_BASE=TRUE
NC_DEV_LPDP_AP_TX2N NC_SSPI0_MISO_AP NO_TEST=1
96 IO_AP_FROM_PMU_PRE_UVLO_L IO_AP_FROM_PMU_PRE_UVLO_L 5
8 NC_DEV_LPDP_AP_TX2N MAKE_BASE=TRUE
NO_TEST=1
9
MAKE_BASE=TRUE
NC_SSPI0_SCLK_AP NC_SSPI0_SCLK_AP NO_TEST=1
IO_AP_FROM_PMU_PRE_UVLO_L 27
8 NC_DEV_LPDP_AP_TX3P NC_DEV_LPDP_AP_TX3P NO_TEST=1 9
MAKE_BASE=TRUE
8 NC_DEV_LPDP_AP_TX3N NC_DEV_LPDP_AP_TX3N MAKE_BASE=TRUE
NO_TEST=1 9
NC_SSPI0_MOSI_AP NC_SSPI0_MOSI_AP NO_TEST=1
NC_DEV_SOC_THROTTLE_TRIGGER3 MAKE_BASE=TRUE NC_DEV_SOC_THROTTLE_TRIGGER3 5

8 NC_DEV_LPDP_AP_AUXP NC_DEV_LPDP_AP_AUXP NO_TEST=1
9 NC_UART6_AP_RXD_1V8 NC_UART6_AP_RXD_1V8 NO_TEST=1
NO_TEST=1
8 NC_DEV_LPDP_AP_AUXN NC_DEV_LPDP_AP_AUXN MAKE_BASE=TRUE MAKE_BASE=TRUE
NC_DEV_PMU_GPU_TRIGGER0 MAKE_BASE=TRUE NC_DEV_PMU_GPU_TRIGGER0 27

NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
8 NC_DEV_LPDP_AP_RCALP NC_DEV_LPDP_AP_RCALP NO_TEST=1
NC_DEV_SOC_THROTTLE_TRIGGER4 MAKE_BASE=TRUE
NO_TEST=1
NC_DEV_SOC_THROTTLE_TRIGGER4 5
8 NC_DEV_LPDP_AP_RCALN NC_DEV_LPDP_AP_RCALN MAKE_BASE=TRUE
NO_TEST=1 SOC: AOP
NC_DEV_PMU_GPU_TRIGGER1 MAKE_BASE=TRUE NC_DEV_PMU_GPU_TRIGGER1 27
MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
IO_SOC_TO_PMU_SOCHOT_RESET_L IO_SOC_TO_PMU_SOCHOT_RESET_L 11 GPIO_AOP_TO_WLAN_CONTEXT_A GPIO_AOP_TO_WLAN_CONTEXT_A

96 5
MAKE_BASE=TRUE
27
8 NC_LPDP_EXT_AP_TX0_P NC_LPDP_EXT_AP_TX0_P MAKE_BASE=TRUE
98
96 5 CLK_AP_TO_PMU_TST_CLKOUT CLK_AP_TO_PMU_TST_CLKOUT 27 8 NC_LPDP_EXT_AP_TX0_N NC_LPDP_EXT_AP_TX0_N MAKE_BASE=TRUE

NO_TEST=1 11 GPIO_AOP_TO_WLAN_CONTEXT_B GPIO_AOP_TO_WLAN_CONTEXT_B 98
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
AMUX_SOC_TO_PMU_AMUX_OUT AMUX_SOC_TO_PMU_AMUX_OUT NC_LPDP_EXT_AP_TX1_P NC_LPDP_EXT_AP_TX1_P NO_TEST=1

NC_AOP_FUNC11 NC_AOP_FUNC11
B B
5 27 8 19
MAKE_BASE=TRUE
8 NC_LPDP_EXT_AP_TX1_N NC_LPDP_EXT_AP_TX1_N MAKE_BASE=TRUE MAKE_BASE=TRUE
11 GND NO_TEST=1
MAKE_BASE=TRUE 19 NC_AOP_FUNC21 NC_AOP_FUNC21 NO_TEST=1
8 NC_LPDP_EXT_AP_TX2_P NC_LPDP_EXT_AP_TX2_P NO_TEST=1 MAKE_BASE=TRUE
5 GND NO_TEST=1
8 NC_LPDP_EXT_AP_TX2_N NC_LPDP_EXT_AP_TX2_N MAKE_BASE=TRUE

NO_TEST=1
GND MAKE_BASE=TRUE
NUB
5
8 NC_LPDP_EXT_AP_TX3_P NC_LPDP_EXT_AP_TX3_P NO_TEST=1
8 NC_LPDP_EXT_AP_TX3_N NC_LPDP_EXT_AP_TX3_N MAKE_BASE=TRUE

NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1 11 NC_NUB_GPIO5 NC_NUB_GPIO5
96 11 IO_AON_TO_AP_XTAL_CFSB IO_AON_TO_AP_XTAL_CFSB 5 8 NC_LPDP_EXT_AP_AUX_P NC_LPDP_EXT_AP_AUX_P MAKE_BASE=TRUE
MAKE_BASE=TRUE
CKPLUS_WAIVE=SINGLE_COMP_NET 8 NC_LPDP_EXT_AP_AUX_N NC_LPDP_EXT_AP_AUX_N MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1 11 GND
8 NC_LPDP_EXT_AP_RCAL_P NC_LPDP_EXT_AP_RCAL_P
NC_DEV_JTAG_TDI NC_DEV_JTAG_TDI
8 NC_LPDP_EXT_AP_RCAL_N NC_LPDP_EXT_AP_RCAL_N MAKE_BASE=TRUE 11
90_EUSB_DBG_PARROT_BI_AP_N 90_EUSB_DBG_PARROT_BI_AP_N NO_TEST=1 MAKE_BASE=TRUE

96 73 MAKE_BASE=TRUE 11 MAKE_BASE=TRUE
NC_DEV_JTAG_TDO NC_DEV_JTAG_TDO NO_TEST=1
96 73 90_EUSB_DBG_PARROT_BI_AP_P MAKE_BASE=TRUE 90_EUSB_DBG_PARROT_BI_AP_P 11

NO_TEST=1 11
MAKE_BASE=TRUE
ISP NC_DEV_JTAG_TRST_L NC_DEV_JTAG_TRST_L NO_TEST=1

11
9 NC_SOC_S_GPIO1 NC_SOC_S_GPIO1 MAKE_BASE=TRUE
MAKE_BASE=TRUE 11 PP1V2_S2 PP1V2_S2 NO_TEST=1

26 30 57 72 82 83 87 88 90 99 100
NO_TEST=1
7 NC_ISP_GPIO_1 NC_ISP_GPIO_1 MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=1
7 NC_ISP_GPIO_2 NC_ISP_GPIO_2 96 68 11 SWD_NUB_TO_PMU_TOUCH_SWCLK SWD_NUB_TO_PMU_TOUCH_SWCLK 27

NO_TEST=1
7 NC_SENSOR2_CLK_AP NC_SENSOR2_CLK_AP
MAKE_BASE=TRUE
NO_TEST=1
NC_SENSOR3_CLK_AP NC_SENSOR3_CLK_AP
VSS CORNER BALLS
7
MAKE_BASE=TRUE
NO_TEST=1

A
16 GND SPI (AP) A
16 GND
9 SPI0_AP_FROM_S5E_MISO_BOOT_CONFIG2 SPI0_AP_FROM_S5E_MISO_BOOT_CONFIG2 3 22 96
16 GND PAGE TITLE
16 GND 9
9
SPI0_AP_TO_S5E_MOSI_BOOT_CONFIG1
SPI0_AP_TO_S5E_SCLK_BOOT_CONFIG0
SPI0_AP_TO_S5E_MOSI_BOOT_CONFIG1 MAKE_BASE=TRUE
SPI0_AP_TO_S5E_SCLK_BOOT_CONFIG0 MAKE_BASE=TRUE
3 22
3 22
SOC: Aliases: Misc
MAKE_BASE=TRUE DRAWING NUMBER SIZE
SPI3_AP_FROM_CODEC_MISO 051-05170 D
9
SPI3_AP_TO_CODEC_MOSI
SPI3_AP_FROM_CODEC_MISO 61 96 Apple Inc. REVISION
9 SPI3_AP_TO_CODEC_MOSI MAKE_BASE=TRUE
9 SPI3_AP_TO_CODEC_SCLK SPI3_AP_TO_CODEC_SCLK MAKE_BASE=TRUE

61 96
61
10.0.0
SPI3_AP_TO_CODEC_CS_L SPI3_AP_TO_CODEC_CS_L MAKE_BASE=TRUE
9
MAKE_BASE=TRUE
61 96
crb-1
26 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GND_VOID
C2700
ROOM=SOC
1 2 0.22UF
CER-X5R 10% 6.3V 01005 12 90_MIPI_AP_TO_DISPLAY_CLK_P 90_MIPI_AP_TO_DISPLAY_CLK_P
90_PCIE_ST0_AP_FROM_NAND_C_RX_P 90_PCIE_ST0_AP_FROM_NAND_RX_P 86
10 OUT
GND_VOID
IN 26
12 90_MIPI_AP_TO_DISPLAY_CLK_N 90_MIPI_AP_TO_DISPLAY_CLK_N MAKE_BASE=TRUE
90_PCIE_ST0_AP_FROM_NAND_C_RX_N 90_PCIE_ST0_AP_FROM_NAND_RX_N 86
C2701
10 OUT ROOM=SOC IN 26 MAKE_BASE=TRUE
1 2 0.22UF 12 90_MIPI_AP_TO_DISPLAY_D0_P 90_MIPI_AP_TO_DISPLAY_D0_P 86
CER-X5R 10% 6.3V 01005
90_MIPI_AP_TO_DISPLAY_D0_N 90_MIPI_AP_TO_DISPLAY_D0_N MAKE_BASE=TRUE
D
12 86
D
MAKE_BASE=TRUE
12 90_MIPI_AP_TO_DISPLAY_D1_P 90_MIPI_AP_TO_DISPLAY_D1_P 86
12 90_MIPI_AP_TO_DISPLAY_D1_N 90_MIPI_AP_TO_DISPLAY_D1_N MAKE_BASE=TRUE

86
MAKE_BASE=TRUE
10 OUT
90_PCIE_GP2_AP_FROM_BB_RX_P MAKE_BASE=TRUE 90_PCIE_GP2_AP_FROM_BB_RX_P IN 96 12 90_MIPI_AP_TO_DISPLAY_D2_P 90_MIPI_AP_TO_DISPLAY_D2_P 86
10 OUT
90_PCIE_GP2_AP_FROM_BB_RX_N MAKE_BASE=TRUE 90_PCIE_GP2_AP_FROM_BB_RX_N IN 96 12 90_MIPI_AP_TO_DISPLAY_D2_N 90_MIPI_AP_TO_DISPLAY_D2_N MAKE_BASE=TRUE
86
MAKE_BASE=TRUE
12 90_MIPI_AP_TO_DISPLAY_D3_P 90_MIPI_AP_TO_DISPLAY_D3_P 86
12 90_MIPI_AP_TO_DISPLAY_D3_N 90_MIPI_AP_TO_DISPLAY_D3_N MAKE_BASE=TRUE

86
GND_VOID MAKE_BASE=TRUE
C2710
ROOM=SOC
1 2 0.1UF
X5R-CERM 20% 6.3V 01005
96 IN
90_PCIE_GP1_AP_FROM_WLAN_RX_P 90_PCIE_GP1_AP_FROM_WLAN_C_RX_P OUT 10
GND_VOID
90_PCIE_GP1_AP_FROM_WLAN_RX_N 90_PCIE_GP1_AP_FROM_WLAN_C_RX_N
C2711
96 IN ROOM=SOC OUT 10
1 2 0.1UF
X5R-CERM 20% 6.3V 01005
Kobol
23 NC_DEV_AOP_FUNC22 NC_DEV_AOP_FUNC22
MAKE_BASE=TRUE
23 NC_DEV_AOP_FUNC3 NC_DEV_AOP_FUNC3
23 NC_GPIO_AOP_FROM_TOUCH_CTS NC_GPIO_AOP_FROM_TOUCH_CTS NO_TEST=1
CKPLUS_WAIVE=MULTI_PIN_NC_NETS
23 GPIO_AP_TO_AMUX_PMU_SYNC GPIO_AP_TO_AMUX_PMU_SYNC
NO_TEST=1
31 92
NO_TEST=1
MAKE_BASE=TRUE
23
NC_DEV_AP_GPIO18 NC_DEV_AP_GPIO18
MAKE_BASE=TRUE
23
NC_DEV_AP_GPIO19 NC_DEV_AP_GPIO19 NO_TEST=1
AP I2C0 (Unused) C
MAKE_BASE=TRUE
C 23
MAKE_BASE=TRUE
13 NC_I2C0_AP_SCL MAKE_BASE=TRUE NC_I2C0_AP_SCL NO_TEST=1 23

13 NC_I2C0_AP_SDA NC_I2C0_AP_SDA NC_DEV_AP_GPIO22

MAKE_BASE=TRUE
23 NC_DEV_AP_GPIO22 NO_TEST=1
AP I2C1 (Unused)
MAKE_BASE=TRUE
23
MAKE_BASE=TRUE
13 NC_I2C1_AP_SCL MAKE_BASE=TRUE NC_I2C1_AP_SCL NO_TEST=1 23

13 NC_I2C1_AP_SDA NC_I2C1_AP_SDA NC_DEV_AP_GPIO26

MAKE_BASE=TRUE
23 NC_DEV_AP_GPIO26 NO_TEST=1
MAKE_BASE=TRUE
AP SPMI2
NO_TEST=1
13 NC_UART3_AP_RTS_L NC_UART3_AP_RTS_L
MAKE_BASE=TRUE
NO_TEST=1
13 NC_UART3_AP_TXD NC_UART3_AP_TXD
13 NC_DEV_AP_SPMI2_SCLK MAKE_BASE=TRUE NC_DEV_AP_SPMI2_SCLK NO_TEST=1 MAKE_BASE=TRUE
13 NC_DEV_AP_SPMI2_SDATA MAKE_BASE=TRUE NC_DEV_AP_SPMI2_SDATA NO_TEST=1 12 NC_DEV_SOC_DP_WAKEUP NC_DEV_SOC_DP_WAKEUP

NO_TEST=1
MAKE_BASE=TRUE
SPI (AP)
NO_TEST=1
15 NC_NUB_GPIO6 NC_NUB_GPIO6
MAKE_BASE=TRUE
NO_TEST=1
12 NC_TOUCH_BSYNC0_DISP NC_TOUCH_BSYNC0_DISP
13 NC_SPI1_MISO_1V8 NC_SPI1_MISO_1V8 NO_TEST=1 MAKE_BASE=TRUE
13 NC_SPI1_MOSI_1V8 NC_SPI1_MOSI_1V8 MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1
13 NC_SPI1_CS_L_1V8 NC_SPI1_CS_L_1V8 MAKE_BASE=TRUE

NO_TEST=1
13 NC_SPI1_SCLK_1V8_R NC_SPI1_SCLK_1V8_R MAKE_BASE=TRUE

NO_TEST=1
CKPLUS_WAIVE=MULTI_PIN_NC_NETS
13 NC_SPI1_SCLK_1V8_R MAKE_BASE=TRUE
13 SPI2_AP_FROM_TOUCH_MISO SPI2_AP_FROM_TOUCH_MISO 65 92
13 SPI2_AP_TO_TOUCH_MOSI SPI2_AP_TO_TOUCH_MOSI MAKE_BASE=TRUE

65 92
MAKE_BASE=TRUE
13 SPI2_AP_TO_TOUCH_SCLK SPI2_AP_TO_TOUCH_SCLK 65 92
13 SPI2_AP_TO_TOUCH_CS_L SPI2_AP_TO_TOUCH_CS_L MAKE_BASE=TRUE

65 92
B B
MAKE_BASE=TRUE
LPDP LPDP
ISP: LPDP Lanes ISP: LPDP Aux
11 90_LPDP_ISP_FROM_WIDE_RX_D0_N 90_LPDP_ISP_FROM_WIDE_RX_D0_N 75
CKPLUS_WAIVE=DIFFPAIR_BADTERM MAKE_BASE=TRUE
11 90_LPDP_ISP_FROM_WIDE_RX_D0_P 90_LPDP_ISP_FROM_WIDE_RX_D0_P 75 11 NC_LPDP_ISP_AUX_RX_D0P NC_LPDP_ISP_AUX_RX_D0P
CKPLUS_WAIVE=DIFFPAIR_BADTERM MAKE_BASE=TRUE MAKE_BASE=TRUE
11 90_LPDP_ISP_FROM_WIDE_RX_D1_N 90_LPDP_ISP_FROM_WIDE_RX_D1_N 75
NO_TEST=1
CKPLUS_WAIVE=DIFFPAIR_BADTERM MAKE_BASE=TRUE NC_LPDP_ISP_AUX_RX_D1P NC_LPDP_ISP_AUX_RX_D1P

11 90_LPDP_ISP_FROM_WIDE_RX_D1_P 90_LPDP_ISP_FROM_WIDE_RX_D1_P 75
11
MAKE_BASE=TRUE
CKPLUS_WAIVE=DIFFPAIR_BADTERM MAKE_BASE=TRUE NO_TEST=1
11 90_LPDP_ISP_FROM_WIDE_RX_D2_N 90_LPDP_ISP_FROM_WIDE_RX_D2_N
75
11 LPDP_ISP_BI_SWIDE_AUX_RX_D2P LPDP_ISP_BI_SWIDE_AUX_RX_D2P 76
MAKE_BASE=TRUE
11 90_LPDP_ISP_FROM_WIDE_RX_D2_P 90_LPDP_ISP_FROM_WIDE_RX_D2_P 75
11 90_LPDP_ISP_FROM_FCAM_RX_D0_N 90_LPDP_ISP_FROM_FCAM_RX_D0_N 78 11
NC_LPDP_ISP_AUX_RX_D3P NC_LPDP_ISP_AUX_RX_D3P
CKPLUS_WAIVE=DIFFPAIR_BADTERM MAKE_BASE=TRUE MAKE_BASE=TRUE
11 90_LPDP_ISP_FROM_FCAM_RX_D0_P 90_LPDP_ISP_FROM_FCAM_RX_D0_P 78
NO_TEST=1
CKPLUS_WAIVE=DIFFPAIR_BADTERM MAKE_BASE=TRUE NC_LPDP_ISP_AUX_RX_D4P NC_LPDP_ISP_AUX_RX_D4P

11 90_LPDP_ISP_FROM_FCAM_RX_D1_N 90_LPDP_ISP_FROM_FCAM_RX_D1_N 78
11
MAKE_BASE=TRUE
CKPLUS_WAIVE=DIFFPAIR_BADTERM MAKE_BASE=TRUE NO_TEST=1
11 90_LPDP_ISP_FROM_FCAM_RX_D1_P 90_LPDP_ISP_FROM_FCAM_RX_D1_P
78
11 NC_LPDP_ISP_AUX_RX_D5P NC_LPDP_ISP_AUX_RX_D5P
MAKE_BASE=TRUE
11 90_LPDP_ISP_FROM_TELE_RX_D0_P 90_LPDP_ISP_FROM_TELE_RX_D0_P 76 NO_TEST=1
MAKE_BASE=TRUE
11 90_LPDP_ISP_FROM_TELE_RX_D0_N 90_LPDP_ISP_FROM_TELE_RX_D0_N NC_LPDP_ISP_AUX_RX_D6P
MAKE_BASE=TRUE
76
11 NC_LPDP_ISP_AUX_RX_D6P
MAKE_BASE=TRUE
11 90_LPDP_ISP_FROM_TELE_RX_D1_P 90_LPDP_ISP_FROM_TELE_RX_D1_P 76 NO_TEST=1
MAKE_BASE=TRUE
11 90_LPDP_ISP_FROM_TELE_RX_D1_N 90_LPDP_ISP_FROM_TELE_RX_D1_N NC_LPDP_ISP_AUX_RX_D7P
76
NC_LPDP_ISP_AUX_RX_D7P
11 90_LPDP_ISP_FROM_TELE_RX_D2_P
MAKE_BASE=TRUE
90_LPDP_ISP_FROM_TELE_RX_D2_P 76
11
MAKE_BASE=TRUE
NO_TEST=1
SYNCING: NONE
A 11 90_LPDP_ISP_FROM_TELE_RX_D2_N MAKE_BASE=TRUE
MAKE_BASE=TRUE
90_LPDP_ISP_FROM_TELE_RX_D2_N 76
11
NC_LPDP_ISP_AUX_RX_D8P NC_LPDP_ISP_AUX_RX_D8P A
MAKE_BASE=TRUE
11 90_LPDP_ISP_FROM_SWIDE_RX_D2_N 90_LPDP_ISP_FROM_SWIDE_RX_D2_N 76 NO_TEST=1
PAGE TITLE
11
CKPLUS_WAIVE=DIFFPAIR_BADTERM
90_LPDP_ISP_FROM_SWIDE_RX_D2_P
MAKE_BASE=TRUE
90_LPDP_ISP_FROM_SWIDE_RX_D2_P 76 11 NC_LPDP_ISP_AUX_RX_D9P NC_LPDP_ISP_AUX_RX_D9P SOC: Aliases: FF-Specific
CKPLUS_WAIVE=DIFFPAIR_BADTERM MAKE_BASE=TRUE MAKE_BASE=TRUE DRAWING NUMBER SIZE
90_LPDP_ISP_FROM_SWIDE_RX_D0_P 90_LPDP_ISP_FROM_SWIDE_RX_D0_P NO_TEST=1
051-05170 D
Apple Inc.
11 76
11 90_LPDP_ISP_FROM_SWIDE_RX_D0_N MAKE_BASE=TRUE
90_LPDP_ISP_FROM_SWIDE_RX_D0_N 76 11
NC_LPDP_ISP_AUX_RX_D10P NC_LPDP_ISP_AUX_RX_D10P REVISION
11 90_LPDP_ISP_FROM_SWIDE_RX_D1_N
CKPLUS_WAIVE=DIFFPAIR_BADTERM
MAKE_BASE=TRUE
MAKE_BASE=TRUE
90_LPDP_ISP_FROM_SWIDE_RX_D1_N 76
MAKE_BASE=TRUE
NO_TEST=1 10.0.0
NC_LPDP_ISP_AUX_RX_D11P NOTICE OF PROPRIETARY PROPERTY: BRANCH
90_LPDP_ISP_FROM_SWIDE_RX_D1_P 90_LPDP_ISP_FROM_SWIDE_RX_D1_P NC_LPDP_ISP_AUX_RX_D11P
11
76 11
MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE
crb-1
11 90_LPDP_ISP_FROM_JASPER_RX_D0_P 90_LPDP_ISP_FROM_JASPER_RX_D0_P 77
NO_TEST=1
11 90_LPDP_ISP_FROM_JASPER_RX_D0_N MAKE_BASE=TRUE
MAKE_BASE=TRUE
90_LPDP_ISP_FROM_JASPER_RX_D0_N 77
27 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
S5E NAND SUBSYSTEM SPECIFIC BOM TABLES

ZQ Resistor
TABLE_5_HEAD

TABLE_5_ITEM
I_VCC = 1150mA MAX (1us PEAK POWER) 118S0784 1 RES,300OHM,1%,1/32W,01005 R2901 CRITICAL S5E
26 PP2V625_NAND
Note: Dev Board adds an S4E option
1 C2913 1 C2916 1 C2919 1 C2921 1 C2949 1 C2950 1 C2951 1 C2952 1 C2953 1 C2954
15UF 15UF 15UF 15UF 2.2UF 2.2UF 2.2UF 2.2UF 330PF 330PF
20% 20% 20% 20% 20% 20% 20% 20% 10% 10%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 16V 2 16V
D
X5R
0402-0.1MM-1
ROOM=NAND
X5R
0402-0.1MM-1
ROOM=NAND
X5R
0402-0.1MM-1
ROOM=NAND
X5R
0402-0.1MM-1
ROOM=NAND
X5R-CERM
0201
ROOM=NAND
X5R-CERM
0201
ROOM=NAND
X5R-CERM
0201
ROOM=NAND
X5R-CERM
0201
ROOM=NAND
CER-X7R
01005
ROOM=NAND
CER-X7R
01005
ROOM=NAND
D
1 C2936 1 C2937 1 C2934 1 C2938 1 C2935 1 C2939

220PF 220PF 47PF 47PF 22PF 22PF
5% 5% 5% 5% 5% 5%
2 25V 2 25V 2 16V 2 16V 16V
2 C0G 2 16V
COG
01005
COG
01005
NP0-C0G
01005
NP0-C0G
01005 01005
C0G
01005 U2900
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND H23BFG8127AEQ-BC NOTES:
LGA
SYM 2 OF 2 INT PU = internal pull up to VDDIO_1
D3 A12 INT PD = internal pull down to VSS
E12 A2 Internal pulls are 40kOhm (min), 80kOhm (typ), 165kOhm (max)
G4 B1
VCC
L12 B13
R2
335S00436
C12 U2900
C2 H23BFG8127AEQ-BC
D1 LGA
SYM 1 OF 2
I_VDDIO1 (@ 1.2V) = 72mA MAX D13
ROOM=NAND CLK_AP_TO_NAND_24M M3 CLK_IN (INT PU)EXT_D0/BOOT0 B3 GPIO_PMU_TO_NAND_LOW_BATT_BOOT_L
PP1V2_IO F1 5 IN IN 29 96
30 23
(INT PD) EXT_D1/BOOT1 C4 IO_AP_TO_NAND_FW_STRAP
F11 L4 IN 5 96
1 C2941 1 C2924 1 C2926 1 C2910 1 C2911 1 C2955 J2 F13
96 5 IN
IO_AP_TO_NAND_RESET_L RESET*
EXT_D2/BOOT2/SPINAND_SCLK/SPI_SCLK B5 SPI0_AP_TO_S5E_SCLK_BOOT_CONFIG0 IN 3 20
2.2UF 2.2UF 2.2UF 0.1UF 220PF 220PF OMIT_TABLE GND G10 TRST* (INT PD) EXT_D3/SPINAND_MISO/SPI_MISO/SWD_UID C6 SPI0_AP_FROM_S5E_MISO_BOOT_CONFIG2
20% 20% 20% 20% 5% 5% K9 F7 23 OUT 3 20 96
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 25V 2 25V VDDIO_1 EXT_D4/SPI_CS B7 GND

X5R-CERM X5R-CERM X5R-CERM X5R-CERM COG COG T5 F9 335S00436
23
0201 0201 0201 01005 01005 01005 EXT_D5/SPINAND_MOSI/SPI_MOSI/SWD_UID1 C8 SPI0_AP_TO_S5E_MOSI_BOOT_CONFIG1
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND H1 IN 3 20
90_PCIE_ST0_AP_TO_NAND_REFCLK_P K11 PCIE_REFCLK_P EXT_D6/BOOT3 B9 GND

H11 96 6 IN 23
90_PCIE_ST0_AP_TO_NAND_REFCLK_N J12 PCIE_REFCLK_N EXT_D7/SPF_N B11 IO_PMU_TO_NAND_SYSTEM_ALIVE

H13 96 6 IN
ROOM=NAND IN 27 96
C FL2925
10-OHM-1.1A
H3
H5
6 BI
PCIE_ST0_AP_BI_NAND_CLKREQ_L P5 PCIE_CLKREQ* (INT PU) EXT_DQS/BCM_N D11 NC_DEV_NAND_BCM_L 23 C
(VCCQ_IO)
2 1 PP_NAND_VDDIO1_F J6 PCIE_AVDD_H H9 OMIT_TABLE
VOLTAGE=1.8 J10 M11 D7
C2956 C2957 C2958 C2925 90_PCIE_ST0_AP_TO_NAND_TX_P PCIE_RX0_P EXT_NRE/JTAG_TMS SWD_AP_BI_NAND_SWDIO
01005 (INT PU)
1 1 1 ROOM=NAND 1 6 IN BI 5 96
155S0876 K1 90_PCIE_ST0_AP_TO_NAND_TX_N N12 PCIE_RX0_N

330PF 47PF 22PF 2.2UF 6 IN
(INT PU) EXT_NWE/JTAG_TCK E6 SWD_AP_TO_MANY_SWCLK
10% 5% 5% 20% VSS K13 IN 5 99 101
2 16V
CER-X7R
16V
2 NP0-C0G 2 16V
C0G 2 6.3V
X5R-CERM K5 E4
EXT_RNB/JTAG_TDO GND
R2963
01005 01005 01005 0201 23
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND K7

2.0 90_PCIE_ST0_AP_FROM_NAND_RX_P R12 PCIE_TX0_P (INT PU) EXT_CLE/JTAG_TDI D5 NC_DEV_NAND_JTAG_TDI
2 1 PP_NAND_VDDIO1_R L2 AVDD1X_PLL L10 21 OUT 23
VOLTAGE=1.8 90_PCIE_ST0_AP_FROM_NAND_RX_N T11 PCIE_TX0_N

M1 21 OUT D9
5%
1/32W
MF
1 C2963 M13
(INT PD) EXT_ALE/JTAG_SEL GND 23
01005 2.2UF PCIE_ST0_AP_TO_NAND_PERST_L E8 EXT_NCE/PERST* DROOP* T3

ROOM=NAND 20% M5 6 IN
2 6.3V
X5R-CERM E10 M7 G2
0201 VDDIO_2 WP* PP1V2_IO 23
ROOM=NAND E2 VDDIO_2 N10

ANALOG_NAND_PCIE_RESREF H7 PCIE_RESREF
I_VDDIO2 (@ 1.2V) = 384mA MAX N2 VDDIO_2 (VCCQ_ANI) N4
(for dev)
23 PP1V2_IO P9 VDDIO_2 P1
P11
1
C2920
1
R2904
200
1 C2931 1 C2929 1 C2943 1 C2945 1 C2947 P13 10PF 0.5%
15UF 15UF 2.2UF 2.2UF 2.2UF 2
5%
16V
1/32W
TK C10 ZQ_0 ANI0_VREF G12 ANALOG_NAND_ANI0_VREF
20% 20% 20% 20% 20% P3 NP0/C0G
96
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 01005 2 01005 K3 ZQ_1 ANI1_VREF J4 ANALOG_NAND_ANI1_VREF
X5R X5R X5R-CERM X5R-CERM X5R-CERM P7 ROOM=NAND
ROOM=NAND 96
0402-0.1MM-1 0402-0.1MM-1 0201 0201 0201
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND G6 VDD R10
G8 VDD T1 Keep ZQ trace DCR < 200mOhm
1 C2959
330PF
10%
1 C2960
10%
330PF
1
5%
C2912
220PF
1
5%
C2915
47PF
1
5%
C2917
22PF
L6
L8
R6
VDD
VDD
VDD
T13
T7
T9
ANALOG_NAND_ZQ_0
ANALOG_NAND_ZQ_1
NAND Capacities
R8 U12 (for dev)
2 16V 2 16V 2 25V 2 16V 2 16V VDD
CER-X7R CER-X7R COG NP0-C0G C0G 1
R2900 1
R2901
B U2
B
TABLE_5_HEAD
01005 01005 01005 01005 01005 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND 300 300
1% 1% TABLE_5_ITEM
A10 1/32W 1/32W 335S00436 1 HYNIX,3Dv5,64Gb,Ultimate U2900 CRITICAL NAND:ULTIMATE

(VDD) MF MF
A4 2 01005-1 01005-1
2 ROOM=NAND
TABLE_5_ITEM
1 C2961 1 C2918 1 C2914 1 C2962 J8 PCIE_VDD A6

ROOM=NAND
OMIT_TABLE
335S00437 1 HYNIX,3Dv5,128Gb,Supreme U2900 CRITICAL NAND:SUPREME
220PF 47PF 22PF 2.2UF

TABLE_5_ITEM
5% 5% 5% 20% M9 A8 335S00438 1 HYNIX,3Dv5,256Gb,Extreme U2900 CRITICAL NAND:EXTREME

PCIE_VDD
2 25V
COG 2 16V
NP0-C0G 2 16V
C0G 2 6.3V
X5R-CERM N6 VSS_R U10
TABLE_5_ITEM
01005 01005 01005 0201 PCIE_VDD 335S00439 1 HYNIX,3Dv5,512Gb,Max U2900 CRITICAL NAND:MAX
N8 PCIE_VDD U4
I_VDD = 820mA MAX ROOM=NAND
PACK_IGNORE=TRUE
ROOM=NAND
PACK_IGNORE=TRUE
ROOM=NAND
PACK_IGNORE=TRUE
ROOM=NAND
PACK_IGNORE=TRUE U6
PP0V83_NAND PACK_OPTION=D52,D53 PACK_OPTION=D52,D53 PACK_OPTION=D52,D53 PACK_OPTION=D52 TABLE_ALT_HEAD

26
U8 PART NUMBER
1 C2948 1 C2902 1 C2905 FL2923 TABLE_ALT_ITEM
15UF 15UF 15UF 10-OHM-1.1A 335S00461 335S00436 NAND:ULTIMATE U2900 KIOXIA,BiCS4.5,64Gb,Ultimate

20% 20% 20%
2 1 R4
TABLE_ALT_ITEM
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R PP0V83_NAND_PLL VDD_PLL 335S00469 335S00436 NAND:ULTIMATE U2900 WD,BiCS4.5,64Gb,Ultimate
VOLTAGE=0.83 F3
0402-0.1MM-1 0402-0.1MM-1 0402-0.1MM-1 NC_DEV_NAND_VPP 23
C2923 VPP
01005
1
TABLE_ALT_ITEM
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND 335S00462 335S00437 NAND:SUPREME U2900 KIOXIA,BiCS4.5,128Gb,Supreme

2.2UF 155S0876 F5
20% VQPS GND 23 TABLE_ALT_ITEM
335S00470 335S00437 NAND:SUPREME U2900 WD,BiCS4.5,128Gb,Supreme

2 6.3V
X5R-CERM
0201 VQPS used for fuse TABLE_ALT_ITEM
335S00464 335S00438 NAND:EXTREME U2900 KIOXIA,BiCS4.5,256Gb,Extreme

ROOM=NAND programming, GND in system TABLE_ALT_ITEM
335S00472 335S00438 NAND:EXTREME U2900 WD,BiCS4.5,256Gb,Extreme

TABLE_ALT_ITEM
1 C2900 1 C2901 1 C2922 1 C2927 1 C2940 1 C2942 1 C2944 1 C2946 335S00467 335S00439 NAND:MAX U2900 KIOXIA,BiCS4.5,512Gb,Max
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF

TABLE_ALT_ITEM
20% 20% 20% 20% 20% 20% 20% 20% 335S00475 335S00439 NAND:MAX U2900 WD,BiCS4.5,512Gb,Max
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201 0201 0201 0201 0201 0201 0201 0201
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND

A A
1 C2907 1 C2903 1 C2908 1 C2904 1 C2909 1 C2906 PAGE TITLE
330PF
10% 5%
220PF
5%
47PF
5%
22PF
10%
330PF
5%
220PF NAND
2 16V
CER-X7R 2 25V
COG 2 16V
NP0-C0G 2 16V
C0G 2 16V
CER-X7R 2 25V
COG DRAWING NUMBER SIZE
01005 01005 01005 01005 01005 01005 051-05170 D
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
PACK_IGNORE=TRUE
ROOM=NAND
PACK_IGNORE=TRUE
Apple Inc. REVISION
PACK_OPTION=D52,D53 PACK_OPTION=D52,D53
10.0.0

crb-1
29 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DEV BOARD COMPATIBILITY
22 GND
22 GND
D
22
22
GND
GND
D
22 GND
22 GND
MAKE_BASE=TRUE
22 NC_DEV_NAND_JTAG_TDI NC_DEV_NAND_JTAG_TDI
MAKE_BASE=TRUE
NO_TEST=1
22 NC_DEV_NAND_VPP NC_DEV_NAND_VPP
MAKE_BASE=TRUE
NO_TEST=1
22 NC_DEV_NAND_BCM_L NC_DEV_NAND_BCM_L
MAKE_BASE=TRUE
NO_TEST=1
VDDIO2 C
C
30 22 PP1V2_IO PP1V2_IO 22
PP1V2_IO 22
B B

A A
PAGE TITLE
NAND: Aliases
DRAWING NUMBER SIZE
051-05170 D
Apple Inc. REVISION
10.0.0

crb-1
31 OF 138
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PMU DOCUMENTS RADAR #: 62945546
998-19244
CRITICAL
U3300 ROOM=PMU
TMLL69A0
L3340 WLCSP L3300
VOLTAGE=1.0625 (DEFAULT, DVC = 0.98V - 1.1V)
0.47UH-3.7A-0.034OHM SYM 2 OF 5 1UH-20%-3.6A-0.062OHM (0.528V - 1.061V) VOLTAGE=1.061
30
PP1V06_S2 2 1 LX_BUCK4 A10 BUCK4_LX BUCK0_LX0 F18 LX_BUCK0_P0 1 2 PP_CPU_PCORE 30 94
138S00313
B10
C3343 C3342 C3341 C3340 BUCK4_LX
C3300 C3301 C3302
PIJD16140H-SM PIWE20160H-SM
2.2A MAX
BUCK4
1 1 1 1 ROOM=PMU ROOM=PMU 1 1 1
152S00984 152S00876
20UF 20UF 20UF 220PF 220PF 16UF 20UF
20% 20% 20% 5%
OMIT
L3301
0.1UH-20%-6.1A-0.019OHM
5% 20% 20%
2 6.3V 2 6.3V 2 6.3V 2 25V 2 25V 2 4V 2 6.3V
BUCK4
CERM-X5R CERM-X5R CERM-X5R COG COG X5R CERM-X5R
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
01005
ROOM=PMU XW3340
SHORT-20L-0.05MM-SM BUCK0_LX1 B17
ROOM=PMU 01005
ROOM=PMU
0402-0.1MM-1
ROOM=PMU
0402-0.1MM
ROOM=PMU
1 3 2020-MLCC
2 1 ANALOG_FB_BUCK4 D10 BUCK4_FB BUCK0_LX1 B18 LX_BUCK0_P1
D ROOM=PMU
NO_XNET_CONNECTION
C10 BUCK4_VSS_FB
UPPER_COIL_IN UPPER_COIL_OUT
D
LOCAL FEEDBACK BUCK0_LX3 D17 LX_BUCK0_P3 2 4
LOWER_COIL_IN LOWER_COIL_OUT
BUCK0_LX3 D18
MTFE2016-2SM
13.8A MAX
152S00897
BUCK0
2 OMIT
L3350 L3302
0.1UH-20%-6.1A-0.019OHM XW3301
VOLTAGE=0.763 (0.614V - 0.763V)
0.47UH-3.7A-0.034OHM ROOM=PMU
SHORT-20L-0.05MM-SM
ROOM=SOC
30
PP_AVE_S1 2 1 LX_BUCK5 A12 BUCK5_LX BUCK0_LX2 H17 1
NO_XNET_CONNECTION
B12 H18 LX_BUCK0_P2 1 3

C3351 C3350 C3354 BUCK5_LX BUCK0_LX2
PIJD16140H-SM
2.0A MAX
BUCK5
I_LOAD = 1.7A (MAX) 1 1 1 ROOM=PMU UPPER_COIL_IN UPPER_COIL_OUT <--- ANALOG_FB_BUCK0_R

152S00984
15UF 15UF 220PF
BUCK5
BUCK0
20%
2 6.3V
20%
2 6.3V
5%
2 25V OMIT BUCK0_LX4 K17 LX_BUCK0_P4 2 4
1
R3300
X5R X5R COG 499
0402-0.1MM-1
ROOM=PMU
0402-0.1MM-1
ROOM=PMU
01005
ROOM=PMU XW3350
SHORT-20L-0.05MM-SM
BUCK0_LX4 K18 LOWER_COIL_IN
MTFE2016-2SM
LOWER_COIL_OUT
1%
1/32W
PACK_OPTION=D54 PACK_OPTION=D54
D12 152S00897 MF
2 1 ANALOG_FB_BUCK5 BUCK5_FB 01005
2 118S00026
OMIT
ROOM=PMU
NO_XNET_CONNECTION
C12 BUCK5_VSS_FB ROOM=PMU XW3300
SHORT-20L-0.05MM-SM
1 C3351 1 C3350 MID-PLANE FEEDBACK BUCK0_FB H15 ANALOG_FB_BUCK0 1 2 ANALOG_PCPU_SENSE_P IN 13 96
20UF 20UF BUCK0_VSS_FB J16 ROOM=SOC
20% 20% NO_XNET_CONNECTION
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
0402-0.1MM 0402-0.1MM DIE SENSE; PLACE XW NEAR U1000.BL37
ROOM=PMU ROOM=PMU
PACK_IGNORE=TRUE PACK_IGNORE=TRUE
PACK_OPTION=D52,D53,DEV PACK_OPTION=D52,D53,DEV
L3360
VOLTAGE=1.2 (DEFAULT)
0.47UH-3.7A-0.034OHM
100 99 98 30
PP1V2_S4 2 1 LX_BUCK6 A2 BUCK6_LX
101
C
B2
C C3364 C3363 C3362 C3361 C3360 BUCK6_LX
PIJD16140H-SM
1 1 1 1 1
2.1A MAX
ROOM=PMU
BUCK6
152S00984
20UF 20UF 20UF 2.2UF 220PF L3310
BUCK6
20% 20% 20% 20% 5%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 25V OMIT 1UH-20%-3.6A-0.062OHM (0.542V - 1.044V) VOLTAGE=1.044
CERM-X5R CERM-X5R CERM-X5R X5R-CERM COG
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
0201
ROOM=PMU
01005
ROOM=PMU XW3360
SHORT-20L-0.05MM-SM
BUCK1_LX0 Y13 LX_BUCK1_P0 1 2 PP_GPU 30 94
C3310 C3311 C3312

PIWE20160H-SM
2 1 ANALOG_FB_BUCK6 D2 BUCK6_FB ROOM=PMU 1 1 1
152S00876
ROOM=PMU C2 BUCK6_VSS_FB 220PF 20UF 20UF
NO_XNET_CONNECTION 5% 20% 20%
L3311
25V
2 COG 2 6.3V 2 6.3V
LOCAL FEEDBACK CERM-X5R CERM-X5R
0.1UH-20%-6.1A-0.019OHM 01005 0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
BUCK1
ROOM=PMU ROOM=PMU
BUCK1_LX1 W17
10.0A MAX
BUCK1_LX1 Y17 LX_BUCK1_P1 1 3
BUCK1
UPPER_COIL_IN UPPER_COIL_OUT
L3370 BUCK1_LX2 W15 LX_BUCK1_P2 2 4

VOLTAGE=0.769 (DEFAULT)
0.47UH-20%-4.0A-0.05OHM BUCK1_LX2 Y15 LOWER_COIL_IN LOWER_COIL_OUT
PP_SRAM_S1 T17 MTFE2016-2SM

30
2 1 LX_BUCK7 BUCK7_LX 152S00897
T18
1 C3371 1 C3371 1 C3370 PIJD2012-SM BUCK7_LX
XW3310
OMIT
2.2A MAX
ROOM=PMU
152S00985
BUCK7
20UF 15UF 220PF
BUCK7
20% 20% 5% SHORT-20L-0.05MM-SM

2 6.3V 2 6.3V 2 25V OMIT BUCK1_FB U13 ANALOG_FB_BUCK1 1 2
CERM-X5R X5R COG
0402-0.1MM
ROOM=PMU
0402-0.1MM-1
ROOM=PMU
01005
ROOM=PMU XW3370
SHORT-20L-0.05MM-SM
BUCK1_VSS_FB V13 ROOM=PMU
NO_XNET_CONNECTION
PACK_IGNORE=TRUE
T15 REMOTE FEEDBACK; PLACE NEAR SOC
PACK_OPTION=D52,D53,DEV PACK_OPTION=D54 2 1 ANALOG_FB_BUCK7 BUCK7_FB
T16 BUCK7_VSS_FB
L3320
ROOM=PMU
NO_XNET_CONNECTION
MID-PLANE FEEDBACK 1UH-20%-2.2A-0.06OHM (0.612V - 0.79V) VOLTAGE=0.79
BUCK2_LX0 Y9 LX_BUCK2_P0 1 2 PP_SOC_S1 30
C3320 C3321
PIJR20120H-SM
B ROOM=PMU
152S00821
1
220PF
1
15UF B
L3321 5%
2 25V
20%
2 6.3V
L3380 0.22UH-20%-5.8A-0.04OHM COG
01005
X5R
0402-0.1MM-1
VOLTAGE=0.75 (0.585V - 0.75V)
0.47UH-2.9A-0.072OHM A14 BUCK8_LX BUCK2_LX1 W11 LX_BUCK2_P1 1 2 ROOM=PMU
4.9A MAX
ROOM=PMU
PP_DISP_S1
BUCK2
30
2 1 LX_BUCK8 B14 BUCK8_LX BUCK2_LX1 Y11 1608
ROOM=PMU
152S00818
C3382 C3381 C3380
2.2A MAX
PIJD1608FE-SM
BUCK8
1 1 1 ROOM=PMU
152S00982
BUCK8
BUCK2
15UF 20UF 220PF OMIT OMIT
20% 20% 5%
2 6.3V
X5R
6.3V
2 CERM-X5R 2 25V
COG XW3380
SHORT-20L-0.05MM-SM
XW3320
SHORT-20L-0.05MM-SM
0402-0.1MM-1 0402-0.1MM 01005
ROOM=PMU
ROOM=PMU ROOM=PMU 2 1 ANALOG_FB_BUCK8 D14 BUCK8_FB BUCK2_FB U9 ANALOG_FB_BUCK2 1 2
ROOM=PMU C14 BUCK8_VSS_FB BUCK2_VSS_FB V9 ROOM=PMU
NO_XNET_CONNECTION NO_XNET_CONNECTION
MID-PLANE FEEDBACK MID-PLANE FEEDBACK
L3330
1UH-20%-2.2A-0.06OHM VOLTAGE=1.8
BUCK3_LX V3 LX_BUCK3 1 2 PP1V8_S4 101
L3390
30 34 98
99 100
1.2A MAX
W3
BUCK3_LX
C3330 C3331 C3332 C3333 C3334
PIJR20120H-SM
BUCK3
ROOM=PMU 1 1 1 1 1
VOLTAGE=1.1 1UH-20%-2.2A-0.06OHM BUCK3_LX Y3 152S00821
220PF 20UF 20UF 20UF 20UF
90 87 PP1VX_DISPLAY_S2 2 1 LX_BUCK9 Y5 BUCK9_LX 5% 20% 20% 20% 20%
2 25V
COG 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
6.3V
2 CERM-X5R 2 6.3V
CERM-X5R
C3392 C3391 C3390
PIJR20120H-SM
1 1 1 01005 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM
0.6A MAX
I_LOAD = 0.2A (MAX) ROOM=PMU

BUCK9
BUCK3
BUCK9
152S00821 ROOM=PMU
20UF 15UF 220PF OMIT OMIT
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU

Iphone 12 Pro Max Schematic (Phonelumi - Com)

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Iphone 12 Pro Max Schematic (Phonelumi - Com)

Uploaded by

Copyright:

Available Formats

8 7 6 5 4 3 2 1

C6591 C6507 C312_R C322_R

J10200 18 R2423 189

C7005 C7010 C10207

C2900 C7095 U5930

C10513 R2471 R2450 R1410 R1013

SB0802 JUAT2 R0712

C9000 C9021 C9010 C1955 539 C24 B24

CP24 CN24 CM24 CL24 CK24 F24 E24 D24 A24

C1830 538 C1113

C1810 C3301 233

PP12888 PP12885 PP12856 516

L9130 L9100 C8324 C8306 511

SH0800 503 PP12820 PP12816

R9100 C3380 C9564 C3640 C3462

TP12631 490 273

C4008 C4023 C10004 482

C3482 C3508 C3651 C3652 R3661 PP12843 287

R11710 C11709 C11700 468

C11819 454 C3601_E

TP12638 TP12635 TP12617 362

C2010_E R2008_E R2002_E R2005_E

407 379 371

A iPhone 12 Pro Max SYNC_DATE=18/10/2021 A

D54AP CRB MLB LAYOUT

THE INFORMATION CONTAINED HEREIN IS THE

U_WLAN_W C7541_S PP205_W

C721_E C787_E C752_E C728_E C1804_E 603 3

207 C725_E 2 PP4714_E

221 FL_ISG_L_W C901_E

226 C732_E 537

C778_E 533 PP4684_E

233 L401_E L406_E L405_E C713_E 530

242 C513_E TP12611 TP012600 PP4744_E

243 R5602_E R5601_E

517 TP12612 TP12603

C528_E C524_E FD0915

251 L403_E C511_E C503_E

252 C427_E 511 PP4656_E

270 C1102_E 491

XW1184_E XW1151_E XW1181_E PP4708_E

C1232_E PP4702_E PP4701_E

XW1190_E C1106_E C1113_E

281 XW1163_E C1129_E

282 C1230_E 481 PP4642_E

284 C1202_E XW1228_E

285 C1203_E XW1214_E

286 C1236_E XW1112_E C1213_E

R0907 C1131_E 476

C4403_E C4404_E C1128_E

297 L1407_E 467

C2313_E C2302_E C2305_E C2314_E 444

C3301_E 443 TP12610

366 362 C3302_E L3302_E PA_LMB_E 437

368 FD0900 431

A iPhone 12 Pro Max SYNC_DATE=18/10/2021 A

D54BB CRB MLB LAYOUT

THE INFORMATION CONTAINED HEREIN IS THE

D54 MLB TOP

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

825-7691 1 EEEE FOR 639-08572 MPYK CRITICAL EEEE:08572

825-7691 1 EEEE FOR 639-10112 NY8W CRITICAL EEEE:10112

825-7691 1 EEEE FOR 639-10113 NY9G CRITICAL EEEE:10113