QA, Define intertac 1. LeDs overcome the disadvantages inthe conventional LED displays, 2 Their costis les compared wo LEDS. 3. Unlike LEDs, LCDs hae he bility wo dispay numbers, shaacters and eepis. 4__Unc in LEDs, LCDs include aretesing conor that ciinstes the refeshing ask of CPU. OH Witeescsenta MICROPROCESSORS AND MICROCONTROLLERS [JNTU-HYDERARAp, (PARTA) ‘stort questions wir soLUTIONS a witha lroecnptr system elle interfacing, {LCD sds for Liguid Crystal Display. Thy are poplar dito the following reasons, ° ‘Te remount in which asf of infomation oo fom any random memory location wsesame aces tim isknons | ‘Random Access Memory (RAM) Its volatile str 2 ‘The RAM in which store information vali nly when pow is av . % valid only when powet is avaiable is known a static RAM. It is made wp of Dy 7 iar information is stored as electicharge a as electric charge or capacitors is own as dynamic RAM. The dacharge capacitor with time leads to e ion e< esto sth ime las tothe dsctarg of sored afomaton. By recharging the apt the sae htt cat WARRING i Ae yw Ep JD rt notes on RAM and ROM, NO a) ‘Gio. Explain the importance of memory int Dac ‘G12, Define monotonocity. Ans: Monotoociys defined as fntheanalog output fora ines ercynM ALLINONEJOURHAL FOR ENGINEERING STUDENTS) esr Fees nae Aericooens Deis Tassos -Afalogtdigial convener (ADC) san imerfse circuit hich converts the analog input to its equivalent digital ouput erfacing ‘Tega wo alg coment DAC) is arse cone th cil ip ee togmicROPROCESSORS AND MICROCONTROLLERS [JNTU-HYDERAB AG) x , AnLCD sa bardvare device at vies dp oft. . | * sey IE 2 Z .PCiscapableofhandling multiple master comm by providing arbitration and communication col detection. 6. Ikean support maximum speed of S Mbps and short, ‘G16. What are the advantages of ‘wansfer : ‘scheme? . ‘The benefits of USB interface are, 4, "eonsumes es powers ico ig ein igh pend ath fees LED dps. ans: 1.» Loweost . “1 Thecare ever py cn ta LC npn alah oe ya LCD nsraton “The whi of seta Gs afi: he etre 4, The LCDI 8 ast prim ee opts which ar wet ew f ace 3. Auto-configuration x Bias Cote Description, 1. requ lessumber of cables for interconnection. a ‘OL | Tanai dare poem 2. Tdoes not require much synchronization on both sides 4 Hot plugging and wi 02 H__| This instructice retums the cursr to home position {i.e address 0). of communication. 5. Excellent perfomance. Lb fun | Mist st beeen yn phe recreate ae 3. The timing is not critical for synchronous transmission. ier 05H | This instruction shifts the display tothe right. meted enc ner oen eo ce | senator copier te ‘in significant. te 4 ea a 07H | Thisistruction shifts he display wo the lef. ee ae can | Rstrnt ote ‘GHE What are the merits and demerits of SPI? a OAH: | Thisisrecion pts omar ‘GiB. What are the merits and demerits of SPI? . | oa | Brinton ty me OF pin ‘Ans: ode Papa) se Tarim step OND ir oa Merits ‘ Tear | nr ts cn ON dt en 1. Off fl dplex communication. 10H | aa a ra 2.” Higher throughput than PC bs. =e ae aH, | Tiss cd ee 3, Simple beware imine i Ce beret Or a qr cel on a 1 ayaa 5.” Nombiratin or acid flue modes ‘ tense te con | Tsim Turse x7 CMT ; 0 eae | & Need of pein cco, se snes we se ltr & 38 | Ris ton tet aise | 7, Transcivers ae no required. ’ ba yng rox anc Tunes enemas —_? igpecrauit ALL A —JOCESSORS AND MICROCONTROLLER: ar a A Ted wih MOV A LNIT-3 (UO 2nd Memory rac, gj Trae Ter I tal FAD UR il Carmina, Or tn explain its operation l MOV, sre ei ras) a7 | ACALL COMMANI ittagon yg | aa Ono Mae MOV JA,#0EH CLR mo tees RH % There re two methods to identify whether any Key 1 : Peel ed wich has en Pee ACALL COMMANI omaiingh SETB Poa % Wersherowsandcolumns are connected a output port Mov A, =: er en sedip por one ACALL, COMMAN ‘ee ie 4 teokeyspnt tenga pn wit forcolamas MOV A #06H aes Sere tye ome Vn owe we an | Mepytigg | SSL edo ay red he sk ‘ F226" adit aeueg | ___POEOHE for columns eset eds he pai 1 ACALL COMMAND rere MOV. A,#80% Met “Dismal eda wht hey need cated Sanaa cere Teeprntimabodee, Mee cad 1. Mak tte cola ine low seg om sa ACALL DISPLAY * 2” Check whether status ofall the return fines is high or MOV As # Alwinadinmesindpaiendniettente| 2 sea incre o micoconaes yee < ACALL “DisPLAY Wb bp te ey pind MOV. KA. Keyboard is wed to ovis apa we coco aS ete pane tole system. stow hens MOV 4,aR "Thee te vain etna ene, | Mtns ACALL DISPLAY tutte aio Aa Tei which Key preted, below ses a MOV AHO “The 44 atx eon sown foe oo ACALL DISPLAY, 1, Make ny one eau tin 0. HERE; SIMP. HERE ‘user to pass the data that is to be af ed on the LCD af 12 The aro from any rerum ine iacates thatthe Key mer peat COMMAND: ACALL. READY nee qari Enable pinis used tte the data supplied tothe daa | Coho fhe sat of al emis is. ei ie ea Wi tS pid in Moy PLA stint ey ot pre a at ech. the enable pia, 3 cR P20 4, altberetentinesin step ae high then pet te Sinha performs write (Dan cine with en) 2 <5 Asahi RIES 0) and performs read CLR. Pat f “GOA With a neat reultdlagram explain how a4 Le Wo) Teypadininfrtaced wih 6051 mlcrocentol the parameter passed SETB P22 ° Enables} tend write 8051 ALP for Keypad scanning ine isthe starting address of an CLR 722” sEmble=0 tt {ASCI sting in ROM and splays the string on RET tae” : ase Fir ove aie fen the alapiay wot (LCD). DISPLAY; ACALL READY Checks the LCD is Pea Feeney aoe as ‘ans: i seady or ot 9 Fie siow stn Tat | _ ext tpn han nati = onsite ing “MICRO” which sto be dsplayed over Mov PLA asuedaatoLcD Te coe et veyboart 8081, LCD and the subroutine forthe given specifications is SETB P20. ‘Data register is ities ete en wen teen oe seenbem selected (RS ~1) recat paris oO smo iecrenane Rea eaS Assuming, CLR "P21... {Wetes data on LCD. * rate eys aeons DS Por PI= daa mW) conection ern SHEETS yada | Aa : : Pin F20=RS sere p22, iEmbleAT * pe tes “pe neriig of 4 ni eos wih ae ACALL DELAY ;Delay for LCD Torming shor ceskbowe™ et | atin foe Faw cA BAA wey oan ee ease Pin P22=EN RET ‘corresponding 10% li s0uRMAL : | arene ee3.1 EPROM, 2 ne (A) end VRAM. 1 ate zac nged . Deen s, Commes the al fet men hy 158 wh eae nese BSL Ades ADAIR wa comedy ee owen AAT ERAS xe os ae hoa sensing Ion of FEM BARA erent eos ne pee Adres mpc EPROM md RAMer saat agezess map of FROM For § KB & EX(Esereal Acces lapecs: Ths pis bs eseced pod cable aes Gr $51 Sev bE pons Eom eee EPROM CSS Wii “Ce pees es east pee Sey Bo ESE OOO. Bier EX-1 Sememerninesibmieml EPROM or G8 RAM fox = sites OOCGEE TFPI, Pe metee Tes pasate eet DN-DIE omc end ads Bos (AD-A7. Pa Qhece 2 This pin met as ORE Kighr onder steer SAS-AIS), ALE (Address Lane Eeabey Tsp seed ch Seles tye of ee adress ch Se matin spe © SEN (hrogram Store Beatle) Tas ps & wed to seers eae ROM by easing UE (expe eat) Secml eomen S cplaed inte folowing so “The rocedce fir ering 851 mcrae CComnce: EA pin to ground for intetcing = © Latch A 74375 bach is met to exact esses from Popes (G26. Disease the lteracing of extemal RAM with microcontroller. ede, 8.088) ton ‘The steps to interface 4 KB EPROM and 8 KB! Explain the interfacing of 6051 with extemal ‘with 8051 areas follows. . jmemory. 1. Connect EA pin to ground for interfacing wit The inertacing cl of $051 with external dat sScmoy (he, Esta RAM isn to ht of ex ‘Reps memo (ie Fecal ROM, Was tas RD and ‘WE pnw acc canal RAM ison pre 2 3 cexteral EPROM chip. ‘Comet the data bus, DO-DT to the data lines memon chips, ‘Connect PSEN to OE of EPROM and RD/ WE | ‘corresponding pins of RAM, (SR wre: carne ot sce ta pty Lt tat acreage | (ex address | AIS | ats] au | an] um] ave [a9] as [av] as | AS] # [as] Az] Ad | Ae c000H ofovTevoteteteletotojete joretete orrra_ | ofofofetitritii:}+tst sjils acdes tap of RAM [[iesadares Ais | ave Tap yiam [an Tam [as [as] Das [as] ae [ST ST At Ae smo 1 fe fofistetetetefofoiotelofotete FFF ofetetetrteieyt te Inthe Adios my he vera far rpren he ct est comets of tres nes es emery SSI. “The ars ins which agit evr ne ecm mye dems a of SSE “The adres fins Whi ete pen ae comet he memy ep trees ip se PR Hore he NAD getisen sain es sntertcig ctv of EPROM sat RAM wi SOS ee sven gescaton as own SE csAns: MICROPROCES: gaz AA ADC Fe cesin ADC and OAC speentons ne, 80, 088) sre eet peroaner specications o performance parameter 1 Wat Ac me lo, rary Acc eine ste ine SSS ce tnd etal upto sc eect of mee ot of Sere bal pt ‘one sc eo manu devin he SERS Sa fom te scala. esa of cove xed in pce of isa vote inaction of of tL Relves refer to he asin deviation Sterccung nad oft or The scaey Spl ind shsofDAC lacey Linearity The nary of DAC i eid 4 ine acu tess bw else ‘measured output appears (its ideal (actual) transfer characteristics. For an ideal DAC, the output nese increases for 8 linear increase inthe applied input Ina practical DAC the output is not that Tinear even ‘though thee an equal increment inthe output. This ‘du othe presence of pain and offset eros, ‘Thedifferene between measured output curve and ideal ‘uiput curve analyze the static error ati performance of he converter - nother words, he deviation of the measured tp fom: fetta cane dey re $} The linesry of converte is expressed as percentage ofits fl sale volage signal or in ations of LSB. ‘Apia tineriy eco good conyers vay B0K —rownise. po 15 nc osovosos ee : t 17] foe (eat oe cK clock divider Cp A cw Ge ae Figo Pin Diagram of ADC 09080808 IC “Tb below desrives ADC 0608 ins and thei utions Pins Pin Fonaton ‘Do-DT | These are te digital dats utp is. ALE wRISo) OF (RD) ABC GND | Wis ogi ground pin. (CS. | Chip select pin ian ssive low input sgn used to activate ADC cu | extemal lok signal is applied this pin sno 107 | These ate 8 analog np signals pis pin ends tart of conversion signal to ADC Ouipueabl pin eas the converted data present on the data inputs dares ach enable in is sed 1 enable the latch dress on ABC into the ADC “These are the address ines used o select one input out the 8 analog inputs Zipain about the Interfacing of ADG with 8051 microcontroller (0 Explain the interfacing of ADG 0808/0809 to 8051. ns| nal ns} “Te neraciog circuit of ADC OBOB/OED9 with 2051 wierocontler is shown i fg. From he gat, ican be observe ths, Pins PLA-P17 are connected to Data ns of ADC. Pins Y20 - 722 ce connec owes lines ABC spectively. Fins 23. Vo ate esos 0 BOC, OF, SE and NE especie, Chock sop te piven exrennaly by cxyeiah ‘vty sod cock vie. "Ye sds its wer patsy te mag ips sgt anoinen, ‘bust ont ledges cocito, the gn Yi sets tow high sisal 0 ALE vt te deta “Then, ia 2.5 wes Sow inf sina so (WR) HC a NOC to ithe cnreTiom, toe wooverson acm, Fos cadion toe ya eae iow ents tc crevice bn te hip, igure artigo ADC CBRE 1 BOSS ‘he UK pin wats who end of comnerson salsa pi P23. aE Wie OTA ra ao ao in (ADC 0808 and dlapay Kon LeD,, ‘An ALPtoreadthe datum (ADCO on LEDs given teow ney ‘ORG 00H MOV, F0FFH : Ain ra a ies smi pt Fi Festa Bk gr fal hai Car The a be eda cc wich ac 8 tia Moy eae proces naire Tea a i opt Tis alg upto eit ca i onage vra I te cof Spi © ‘See cvener i woe then the ue voip em ‘metic pw nrg ered ter Ring at r Ses norr micROPROCESSO! Se Bawendi ane a casos 1s steven in ge paige of DAC OS ger Pn diagram of DAC 0808 12 ‘Ttetelow desribes DAC OS pins ad the fonctions Tins ie function ‘Do-D7 | These re Si dat input pine Voc | Ris the +5V suply voltage pin. Vg___ | tis an input pin used forthe reference voltage GND _ | ttisaigiatNogi ground pin, Comp | isa compensation pin, ta, [ isthe oupur current. 38. Draw aneat sketch of DAC tobe interfaced with £8051 microcontroller, NowDec-48 (10), Gt: (o) Explain the intirfacing of DAC to 8051. Ans: ‘The interfacing circuft of DACO8O8 with 8051 microcontroller Figur: Intrtcng of A tw 9051 TBAG 0808. in ang pian te : RS ANU menue: - os “Fron te ret : {0st are connested to the digital ‘re oa Dae Mace the deta and produces Dac preset i caret ta Ee ep Scnveten which comers thecurentap ey on “The naog output genera fom DAC ea reference cme passing tte ree {Sina epand hats othe datas $ —Theanalog output voltage can be determined methods. » | stethoa.t Determine curent output, and calculate th using = 28 [B7, D6, DS, DA, D3, Dt!) fa he ae 6 32 64387 Where, D0-LSB DI-MSB. Method 5 DDatermieresoion of DAC and mui ey Sigal ord : “ ile, = Resolution « (D7 ~ 0g, Where, Resolution = “a Application (G39. Write an 8051 ALP to generate the fo «waveforms using DAC (Sawtooth (i) Square and’ 4 (i) Tanguiar. | Ans: Se © Saw tootn 4 arent» oth wiv DAC ‘percmr comin) fom Oona WARNING: xeruetcpi ot ea Clie ie ys UAL oA odie PD - Renita a A ALP wp sao bacierbane Pa MOV" A, #00H_ ; Take the intial value as Ot AGAR MOY FLA Cop ea asa | EA gem Soar aca © Square : Pian pts em 3 Memory interac, AT AIST ALP pote eee Cotton and us reace) sat a ae it Wacanm ae ‘ IAC sas Tow REPEAT: MOVPILAOFRL guru sk inter LCALL DELAY fered MOVPI.H00tt Les lin UCALL, DELAY pet LIMP REPEAT DELAY: MOV RO, Hori BACK: » DINZRO, BACK. RET Reumto main peor (oy Tlongular For generating «Wagar nave fo 004 ‘An 8051 ALP ogee tings vavfon sting DAC ea flows START: MOV A, sTdeteintatwne come ur: MOV PLLA Copy ein va sore a oP INCA acres Ait ‘CINE A #FFHLUP check hed for pak oat fat jump to UP DOWN: MOVPLLA copy das fom API DECA Desens Al “CINEA, 0H, DOWN ‘Serial commuiication standards, Deseret deck wet delay sero i ot repeat the operation Yom. he DAC mst increment cotiasouly om OOH to FFH a oll down Soa FEHL es cir nin a i i sei = a RSC RS22 RS485 a Re ie [RE ec ctor [etme stare ee le ee ae ae vanes” me mn wee en a le Fut ply, Haar duptex_| ait depen on Teena avesee av 1 6Y (man) sv ven smrroumomn forerey eek) fsvaave S esc ct ae = ymmunication. Oct-20, (RIE), 84a) Send caps nn [ene 0 | tee ce x [eee coc | Seber «Beceem | [aera nn + [prmemesenaaie ode, 280) at len ore to enn wh iin saben erie racer vue nan ced Sve: Tey a, major pe oF Som a we JoAL FOR ENGINEERING STUDENTS In an embedded sytem and with outside world. Tee a¢ aoe soaspecrrum ALLAH° MIcROPROCES* een serial and pall the compo 5 Ta csSrone gas are rans ingle wansmision in ‘he sigals (i) te tans $e specd of data anes nischeaper as only one ay required The munber of dt si af sock pulses equi Ihisarcliabe form probability of eg devices perfonn operations only after receiving ‘ommands fom the maser device ‘Master and save devices can at as ianamier o r= Mas device generates sy cack pulse iespectve ofthe evi sng ats Sasniot orci ‘GAT Explain the working of bus. » cman re, a) (or) Explain the sequence of operations for com- unicating with an 2C slave device, ir Between master an sa le, SCLSDA Ne Weng wet soe nous Figure: Itertcig of FC Bus sequence of operations foe communica withen Be device isas follows, ly the master device send stat condition te onnected slave devices for transferring databy SDA and SCL bus lines low and high respectively, = the master device send the -bit or 10-bit, D of he desired slave device and an RWB ss per | earement over the SDA line. “The slave devices compare the recived adress will © he adares assigned to them. The slave device with te | matched address sends an acawowledgement Bit te _spasier device over the SDA ie, ‘Ifthe acknowledgement bit is (write to device), he ‘aster device sends an 8-bit data vie SDA lin to sine “Aevice and it ir (ced fom device), the slave deve | Sends data tothe master va SDA line E - Themaster device ater finishing the ead oprationsends 9 acknowledgment bit 2nd wats or the same rave device, the maser device makes the SDA line high © ip the data wansfer when SCL is se high (Note: PC bus operates in three different modes 3 tabulated below Mode Seandard anode Fastmode | 400 Kbps High speed miode | _3.4 Mbps : Data rate 100 Kbps WTI: St CRA yy LE pn ND ‘Wiite a note on Serlal peripheral interface bus. SPLisa synchronous bi-directional full duplex four wie serial interface bas. It works on the principle of shit register, It consists of single master device and multiple save ‘evices. * comp srecaou Linon q Hone Se i gage re tc) at (MISO), Serial C Tok 0p Maser ig ‘Ste | % We dita seam sans wath» war bi SI) and ede a Master OM Slo nMOS ipa eo Le Tran Me ae AMON palin eabereyy | TB st es te aia of at seem he 2 deer ass menet | fer The cee chks nese Ie wet slave vie asl ‘it requires any service corresponding to the baud 1 4+ Matern Slav O65) get ey ‘etn. eee rrp Slave Data Ca (Sore ene © lve baa rate isx bits/sec then, the time slot available data fromslave device tomaser dare» t= 7 Seti lok sigan cai sce foros twit cipestfitsboutracie, se Slave seetis an atvelow siatuoee So, the receiver checks the receive tine thar ime device. wed to vlet save ‘slot available. “The connection of master 204 save de © In this communication, if parity i allowed. the transimé jis shown in figure, 0d slave devices on SPI ts, ter UART sends a bit for parity (1 for odd mumber of Sse sa. "sand for even ember of the arsed dita in ‘ Thetis UAT teins ater ofan ts Ho cived and cc it with the received parity brt to us check the errors. Then, it removes the start, stop 20d ra ee Pay, cae SSeraing sts we ous Hel fis ae come AT =] noe The interfacing of UART is shown in figure. | am: | ah as Se oo a Fig: nth pete master eve prec gs ‘sels deed evenly mise | GER, Explain about the architecture f UART 1 Be sve SS signal ow enc apanirsne de: |" connected to BtSt microcontroller. ibscleted he SO ipa ne oes ra Moat at hgh mpedice se. Ans: man vanes dt in se edo ot nn ‘Re VARTisa mae cd ish line i Sos capa oT UART own ‘What is UART? Discuss its working. en se 98.) (on i Wt anotoon Univers Anetreous Recer Sranemiter. Ans: s © UART (Unive Anes Rees Temi Sanaryechenusstalamemerses iss 2 needle Se “fi 1 depends on the preeint pxol bee erating nt E © Tetmmisinmeshocsctetemcse | | TF |= ‘ting for teh mead ee So = Sem IF ‘amber oye, I ne ny oF cone ison of comune igre Soc Dlg of DART The inition and ein pet ae sane onby seg oma Fo ensince Tones =a _—_—_ MmicROPROCESSORS AND 322 ACT ART ras eT CoP io srpnsonPaai epg Paral) Fee CPU ates he oh footer Revived andthe piso-sbil rit reefing and inserting the panty it “Tae ESM also takes the responsibility ra ncorporaed in pes rein the dstatanser ry Out andthe other isSIPO ‘patae ntrnemiterand eect arcter transmission BY “The FSM (inte State Machine) to each of the character ra sent to PISO SR (ie of "The packets eld by the Fae tough isn chanel witha baud ae st eum aud ate emerson se TaRcady flag is st after the completion of whole hut UART is free and ready to receive charters presenti dat-i-bufer representing further character, The heared immediatly fe iting nt tbe a, ‘ut bufer, UARTs wall ipl charaters canbe supported by ‘hth grater hilobyte capacities. fave a single characte ber, but more advanced UARTS, ‘The SIPO sresctby Sending valid star bitbefore being received and it's loaded withthe packets that are transite “Se conol FSM does removing of abit and tp bt fom 1. CPU interoce “ Fier siro Sk and clears the party bit afer completing 2. Chock triacs _prty ches operation. Final, te esvedcharertri paced as cali Pvue-in buffer. The RxReady wil get cleared automatically ecice z 4,» CPU Interiace i ; fer reading the atin buffer and the ry partying ror. Inthe reception proces theres 2 an error to occur and is called 'eception poor" overran errr” which s ue to fst filing of characters the CPU results in loss of som he CPU. Ths problem can be avoided {poping dati bles tat has multrcharace capa aaaeerne CPU needs to remove the characters immediatly possibility’chance 10 into dain buer'then | characters received by ff eceving them tliminate “Thetransmitingand receiving lok for PISO SR and SIPO SR respectively, thefeby o date rates for tansmisson and reception tae the sta ofthe ans reer anders ify 24 Tepmuncte of VART ae composedby consol we TS ats reste is based on Ne the module parameters uesion of convo repisters and ‘apabilies of UART. The following ae party gis se ifthe "The stats ‘Shich ci by et by the intemal contol Bi", 1, Length ofthe character 2. Type of parity 3, Parity Enableisable 4, Length ofstop bit 5, Baud fate yale “Tueclane| andthe nats of eve can be determined enh hd ren nds fa 2 | ogg rl a ae ground GND) SOM, ‘overrun flag, framing flag and parity fiag. The status register uti yc he ei ut THD ine wee ee cane wie we etentaseeses. | HARAD Se 'SiPo-sR inp on a kD Sea data or register MICROCONTROLLERS, [JNTUHYDERABAD | “GST, What are the features of UART interfach 4 a ing Mogg 7 of 8-bit data with odd, even, or mon-parity _ (ceca naman ae Siemans Builtin idle-tine and address-bit communtca, protools for mutipocestor systems 3 1 Masha mane ti . Sot 9.__Independent interrupt forrecciveand want | ‘952, Explain UART interface and its configuration. ‘Ans: rhe UART interface is made up ofthe following interfaces. ‘Teeomes fat the picture while iaterfacing UART to ‘cp adds buses cone buses andor the data ses by wi crit bidirectional dat ines in oder fotansfer te dat Th aa has interrupt request ines ats CPU interface sie i eae io putsrviceequestto CPU enable inept bt cae nd eC adopter. Te demand for TRO, lines ter gest Line) is toly based onthe pe OFUART ue De Ret ee mae invisible on the MCU chip inthe ea te loss of dt. Shen UART are embeded Jocks are wedtoprovide | 2, Clock Interface . | 4c deals with the ime base signals whic eH seovide anion and eepion bu te. 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