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Tanne prs RO, (R2,_#OsSI: (Hote. @ STRAype Rt, [Rey Sen SrRSE RO. e010) epee he ue essed Fee Oy af epi in ad insucton, Ra ee Serena noes Sie oer e th el pe eget ls he $ Rate ORE aya fw fot Soteae e Sqentctn {ni at eaten it Stmraaras 2 Un end Tm Reger Of Teton ence aimee Tee trance moe ve tee Get cet we ese oe ome (UR fore) RAR, Ra LS fuampc LORD” RO,(H2, RS} ) StRigge) Re (Re, Re, StF eae STRSOD (RRS. ISLA 3m te ft ey LSE a pet tgciet mine y arsed on expo ‘Stes a asad in ges noo Eoptomen Tie tapememey aes canbe kody Tipe enon nls + Oe wee Shit bits, rnges fom 03. 3 LDR,PCRelative ‘The function of this instruction mode i similar to ‘meine fet dressing bt ir in Base adress repiter ie PC relative addressing mode uses cutest PC alu base adres reper. Syne © LDR (ope) RA. (PC, somber: Example: LDRB— RO, PC, 0:30} () LDRD (ype) Ra, RAZ, IPC, Hols Example LDRD RO, RI, (PC, #03200}; ‘Here, Ra, R&D ace te destination registers. In LDR Snstuction, target adres obtained by the sum of PC snd offic vale leaded int destination eit, R. ® Tn LDRD instruction, aget adress obtained double word. othe lower werdisstredin Rand higher word Ws sore in Ra register. [LDM and STM: Load and Store Multiple Registers ‘These aston ar used to Jad and store the mule ‘exists into the adress register. {TT WARNING:tecxhatoconying of ths ois aCRINMAL se Ame fend uty LADLE face LEGAL paces [AND MICROCONTROLLERS [JNTU-HYDERABAt Syma (6) LDM mode). Ro (1) relists Example: LOM ROL, (RI,R2,R3};, (a) sta fe) (eh ieample:STMDORI!, {RB-R6,RIL|RI2}, cats eine o Seer a TEE neo ete load or oop see nM aston the ta RI RE Stepoe is anded in RO aes rege {nSTDM instr the da in RR, RII and IZ Sorin Rass eps Tee exclamation mae () exceptional adit SSA de te tck ef the data odd oy Sets wien ck theses reise. FUSH and POF st iasnaion tore a ine menor eer Tu POP isan fonds he dain he eter ‘memory. : sya (©) PUSE{cns (els sample: PUSH {O,R3-R5, RO); POPeond) (rai: sample: POP (82, RS}; LLDREX and STREX: Lo Eacuse Tsensrcio awed abate devel {yom whch sy scesand shares tom seen ree The ld rier exclave aid ore rexiteencste ict sh dentin rpc Ra hoe ape sce (fom the mil ores) aces reno deve, 5 Sytner (©) UDREX RR sat Examples LDREX ROR [R2, 4012] ()STREKRA,Ry Ro Ae, Fxample STREXRO, Ri, R2 #08) (© LDREX® (Re: Example: LDREXB. RO, (Rt STREXB. aR (Ra: Example: STREXD- RO RS, (Rs (© LDREXE Re Rt Example: LDREXH Ro, {8 () STREXI Ra Rua Example: STREXH_ RO, Ri (R2; ADR: Load PCat Adres and Store Reyster ‘oad the program counter (PC) reative ads 32-bit constant Ino destination register, Ri, | | | | | ee reer UNS (0044 Pec Fi emssoiee ae Trims ite ‘ can tn a Teg : entre cond, sot, is imma fe ot operat te i l emery screens with mnt fie ly ae @ These instructions do ot ate fag Examples (0) Shift and Rotate instructions. Ans: © Data Moving Yastrictions (“Mata moving Instructions without Meory Access 1. MOVR¢, Rt ‘Moves te exe int reser Resource eoitr to Rd detnation ter 2. MOVS Rd, Rt ‘Moves te cones for Rito Rd and afects NZ nd C tas 3. MOV RG, Hrtet ‘Moves te cores fet aes Rd. 4. MOVS Rd, Host ‘Move te cnet fet ress oR nd affects NZ ad C fags 5. MOVWR4,fimmlS _sMoverte bit duno R, tales N, 2 ind C Bags. 6. MOVTRA, immi6 ‘Moves te 16 dao upper 6s of 7. MRS Rd, Rs ‘Moves speci reper Rs to Ra 8. MSRRs Rt ‘Moves sate reper special reps. W affects N, Zand Ags. 9°. bivnnd me ‘Moves the pie vale of Rtto Rd fects NZ and C Flags. © Data Moving tastruction mith Memory Accs 1. LDR RR foie) Lode cota tet as 1 2 LDRO tents) xine cto 3-4 ad aitine etatneiser 5. LORIN, here} eee 2 ord in eine, Ra A LDREE RA tee tt) tos develo RA ffl no repie Rdand pas eee nt sei rineneh Soerdecedainie aie. Rin tetas tat, Oa tS Rin on wR Fa Rin her wt, te cone ml eit Rn. 7 LOM Rat, (regis) an fore and then loads the routt Rn. © Lowe not tegisy) abdomen emp raise ie "gre ie ei ses Rn nd he oct 57M Rat, (east “erent Be the mu reteset a. ps erhene ie, (nal ve JOURWAL FOR ENGINEERING STUDENTS) i iE ‘spECTRUM ALLINOME memesLyNIT-5_ (Advanced ARM p, , 14 mucnoPRocessORS AND MICROCONTROLLERS [INTU-HYDERAG, | oa ERR Pelee asians are ne eal ime cot systens, Inte of hing. Human interface devices, Tec lse en Dneoe 130. List and discuss the features of OMAP processor ny Yor wan nna OUP138 100 ANEDSP POH : FEE a cn tl tan peli s ‘Tae configurable 64-ipeeral purpose ines and on. coniguable 64-bit genera pus Rea Tims Cock (RTC) wit 32 Hz osilntor an spare owe a ‘hal ere SOC wits 32. RISC ARM926ELS MIPU processor and C674x VLIW DSP. {RISC supports bath 16 and 32-bit thumb instructions (}Thememey cor of ARMS26EI-S MPU processor bas 4 KB ETB, 16 KB data and 16 KB instruction caches, 8K RAM and (4 KB ROM, ‘The C614x DSP suppor 8, 16,32 and 64-bit DSP instrctons with extensions i. byte “The memory core of C67éx DSP has 32 KB LI Program (LIPYCache, 32 KB Lt Data (L1D)Cache and 256 KB 12 uatfed mapped RAMLCace. “pnhaned Dist Memon Acces Conler WEDMAS),, “Sthas2 canal onl, 3 wneerconole, 64 independent DMA channels a ‘Ser inerfces suchas mutichamef bulleted seal ports (MeBSPS),13C, SPI and UART. 7 addressable, 2 1116 quickDIMA channel LED display contol 7 ‘ideo pot itecce(VPIF) with 0 8, single 1-it single aw Aigh pec Univers parallel port (PP) interface wit 8 o 16-bit dia, 128KB ofintermal RAM 7 ‘Aprogranmable eal ine uni subyitem (PRUSS) as Customizable itrfe ‘© Uhastwo programmable realtime unit (PRU) cores with 32-bit lod/store RISC architecture. © Wha 512 bytes of daa and 4 KB instruction per core. Control timers: 2 enhanc high esluion pulse widh modaltors(¢PWM) and3 32-bit enhanced capture (¢CAP) modes Sco {oF slower memories or peripherals; anda high! eral deve for. (A) witha mange dato ODO oe esr itl (Sedan Sea aed sop the main features of rocessor em ‘OMAP pr With a neat diagram, explain the architecture of OMAP leo capture channels ind display chitinls” Meyisune-t, R160 (on) Draw and explain the architecture of OMAP processor. (on) =xplain the functional description of OMAP4L138 C6000 ARM-DSP processor. ‘The functional 5.15 & i= = a fee B= Sie) Ses "os et a ene 5% Sea toes eae tn ti FIAG Interface © IAG interface consists ofa bitin 11 poe Of in TAG pore which faites communication between the debugger application and Tis also a sexi nterice and uses To Saree 3, TDU,TCK, TMS and TRST a signal Hines. Tis the following boss, : iet/Sleep controller olan cn ino twit poe dk nt conta _ Itprovides granular power control for o2-chip modules. a 7 8 Rasen ol tr gina ml cect mee tan CPU sl ae # TEMPO apne tr nein ion ig © Upnrecting rns om ha mrntepuon te | Dyers inchs ads aint te ean pfminbl regina 6 ae awe sta ay ito = ieee tenon ctw ay ge genta nerve #2 Naggora mip pen iter ngou ev wn td oe jeg eae a privileges. $ _Itprotects Memory Mapped Reiser (MMR) aces Fa multiplexing control #,° Waclets the periph ia ition cro of he pin 10 blr which have ouput data. and ouput enable a ts detaut value is noe ining ha ti i's 10 balers sted, rine eatin lack (RTC) and 32k Orie RTC counts seconds, mines, Bou, mons and yer 10 provide time reference ton application rnning ona force, * What an exer yt 32.768 4. supp aor dk nae 248 sme Igoe Ann trap Pee erga Sener the CPU £ tgenates Alam ner Po Tehas an independent isolated power sor eroiPhotocapying ‘aa WARNING: et oot CRMANAL st. Ayes found pty ABLE fac LEGAL proeeig. SPECTRUM ALLI-ONE JOURNAL FOR ENGINEERING STUDENTSMICROPROCESSORS AND. igROCONTROLLERS TINTU-HYDERA Serial teres channel Buffered Serial Port (MEBSP) > LUNIT-5 (Advanced ARM [ico Display Controtesucng, 5.16 “General Parpove Timer ed to time and count General purpone nes Frat the CPU and send ecm generate pulses, interop te ‘Jectroization events othe DMA PLLCIockgeneratarf0SC or put genres kis te assem LL gee anki, agnmen, 894 (ung forthe ste clocks tothe ciP- ARM Subsystem hs the ftiowing te, ‘e ARNO26E)S RISC procesior with 32-bit ARM and ‘ein sructons & Litleeadinn and MMU SyreaContt Co Prcesr15(CPIS) configures Sot te incon of ARM abn sem 4 16KB nsneton ache a6 KB data cache 1S Wie Buri sed forall writes 10 a no-cacable ‘flr eon and write shrough resion 9 nabedied Trace Module and Embedded Trace, ulfer (EnWETB) 4 ARM nteupt conte. Dspsubsystem Ins the flowing eases, Carta DSPCPU & S2KBLI Program (LIPYCache (op 032 KB) & 32KBLI Daa (L1DyCache (op 1032 KB) 4 2S6KB Unified Mapped RAMICache (12) "Boot ROM (esnot be used fer application code) © Litleentian Swit Centra Resoore (SCR) Mprovier connection beeen intera-xteral masters andthe resources inside the RUSS. Peripheral Subystem Enhanced Diet Memory Access Controller (EDMA) % eonuols the wansfer of data between the slave espera snd the memories onthe deve. Ava Port channel Aud SerialPort (MeASPIFIFO) ‘nisused formutistansel audi applications. Ihasthe folowing Festus ° ‘© Feuble clock and fame syne generation logic an on- hip dividers * LUptosixeen transmit or receive dtp and seriaiers $ Extensive eorebeckng and mite generation loge & Transmit & Receive FIFO Buffersenable the audio post to opeate ata higher sample ates hat it ean tolerate to DMA lnteney. eeeeee * * @ Dynamic Adjustment of Clock Divides WARNING: ex Pitenog ths bski CRNA stp fo yi ABLE EDA pce ‘has the following Features. Fullduplex communi Double buted daa registers for 2 continuo 4, Tadependent framing and clocking f0 receive ag Direct interface to industry-standard codecs, A Pie tcp (AICS), and other sel ome ‘RtalogtoDigital (AD) and Digtal-4-Analog (iy eviews External shit clock oF an internal, programma {Sequency shift clock for data transfer “Transmit & Receive FIFO Buffers enable the audio pg to operat higher sample rate 0 that can ol to DMA lnteny: . Inter integrated cireult 120) Iehas the ellowing features. Fast Mode up 0400 Khpe (n failsafe VO bute) ‘Noise Filter fo emove narrowband Noise (50 nl) “Tan 10-Bit Device Addessing Modes Acts a both Master and Slave Evens: DMA, interunt, or Polling Cam also be ued as General-Purpose HO (ifnotuslas no; Serial peripheral Interface (SPD) . ‘Wisalhigh peed synchronous serial WO portand prvi interface to mirocontllers, data converters and ed EPROMs. 3 ‘SPI functions both maser and slave. Inslv mode, tacts as an optional ouput and ives ‘sau of internal est bute In master mode, it ace as an optiogal input and configured o provide ely has L6-bishitregister, 16-bit, 8-itbaud generate. Universal Asynchronous Receiver Tronsmitter (UARD) performs convcisioni, serial to parallel and pal! to seri orm peripheral devices internal bis Tehas the following features, bye storage space for anamiter and eceivt FF DMA signaling capability for both received tt ‘wansmined data Programmable Baud Rate upto 12. MBS Frequency pre-scae values om bo 65,535 tose appropriate ba ates Prono interupts Programmable seria data formate False star bit detection, Line break generation * detection p Pinay 3 tase onwe tem $bits Sena atta, Sue ner 2 Non Sr i Opa Viescune ce teens = ope Wie ina sve Pa or ay & Itisa mulichanne, highapeed Np ell neice with dts ata es nd minal eon iz ‘Wis wed to intertice highspeed ac ser DACS,FPGAtor other uPPs rrogrammable ResLTine Unt Sibosem @RUSS) eae e nludes two progr bl el tin nits (PRUs), an nt contoller anda switched central resource. PRUs are used opt enbedde sk that require packed me a structure manipula 4 Wemanages evens shat have tigre ine consis, ania oh pai 4 Roan be used to iterice witherema contro Timers es iced High Resolution Pulse Wid Modulator (HRPWMS) ‘9+ Tels used 6 gendate compe pe width wavefrs wid ver less CPU overhead © thas to dedicated 16-bit time-base counter wth period and frequency contro. [Bahanced capture ((CAP) module © eis used in ster where acute tining is ipo parame. Peripheral devices for eonectvs) {USB 20 OTG controller itis an acronym for Univeral sil bus sania on-the-go contol © tacts as host at high, lla low ses ‘acts ts peripheral at igh and fl pets, . apts cont ak hms ert er ode USB 1.1 OHCI controller "© tis an acronym for Univers! serial bas bost controller, © eis used to connect devices for daa tone ata matimiom speed of2 Mbps. ‘Ethernet Media Access Controller (EMAC) ® _Atprovides an efficient interfve between device andthe network, ‘thandles the data flow ftom the device tothe physical layer device tines bt moto crm vie per device, Hast Peripheral Interface (HPD) a heb eur iy Prin sda mena eeaaaane ae aman n iinet wesc of crn Seren ° ° * a sentndoe pec I cnc for meta tg ns tis used to provide both ie JOURWAL FOR ENGINEERING STUDENTS ope ispecrmua ALLIEN @ ———5.18 MiCROPROCESSORS AND MICROCONTROLLERS [JNTU-HYDERABA\ ‘Seat Advanced Technology Attachment (SATA) Interface ‘© Nisasingl HBA port md o provide both high sped and low apeed HDD connectivity for large storage plications, -& supports Gen (15 Gbps) and Gen 26.0 Gps fine sped & _Extermal memory interfices External Memory Interface AENIFA) | Wisprimaly wed inericeayntrinos memory te (NOR and NAND flash Arynsironos SRAM and als se to niece SDRAM. has 16 abs and spp 25 ares ics, 2 external waiter inputs, | DDR2/mDDR controler . “isa dedicated interface to DDR mDDR SDRAM. thins 256MB memory spice for DDR2 and 256 MB memory spc for MDDR © supports JESDY9-24 standard compat DDR2 SDRAM. thas page sis of 256, 512, 1024 and 2048, ‘G32, What is cache memory? What Is Its use in microcomputer. '. Ans: c.-29, ni, 286) Ccuene Memory . Coch Memory i mall memory, which stationed inbetween the CPU and main memory. The principle regiment of cache memory isto speed up the processor atthe same time allowing the frequently used data to be stored in it Tis acompromise ‘between the sped of processor an the min memory . 5 ‘Use of Cache Memory in Mlerocompater: © Cachememory has been nrodoced because ofthe inconsistent sped of main memory and processor The processor accesses remary either for fetching the incuctions operands ofr storing the results. The rate of execution of insrutons ie limited by the memery yee “This limitation eases ditncnesin the speed of main memory ad procesor Algo the spect of the processor as bees ‘increased over yeas when compared tothe speed ofthe memory. “Hence the man memory must be create with the same technique used fo he eration of processor reser, Howevet this stategy becomes cost & ‘Thisprolem canbe overcome by utilizing the principle of locality. ‘® This is done by allocating a cache memory between processor and main memory. ‘The tem cate is also used wit those buffers that hold commonly accustng data, For example ‘commonly occurring data. For example, file caches and name ‘oshe. Whenever CPU needs word, itacesses the ache memary to check whether the requested word is available o not IKE requested word is present then tis fetched rom a cache. Tiss refered ab “cache hit”. On the contr, the unavailability Of ‘the requested word in the cache leads toa cache miss Since CPU references cache when it needs a word therfore itis necesio") thatthe speed of cache mast match wih the speed of the CPU. On eache miss, the block sa fxed-size collection of data thst has the requested item. Its moved from main memory to cache and the CPU gets the requested tem. Cache andleé by the hardware Bets the req ‘Cache misses are hand “Thetime taken process ca msi dependent on memory bandwidth mena ad 1 nena bandit menry nd memory ney. Memory en? i etme taken tf te fist word fom Hoek. Memnry tanh sth tne ent fc he ein wets at the lek in ech. Duet thee fora cache mis consumes ore CPU tine ts seach Mt Inne of te eton recess, a ache mis can even pus the pecxr wl equ tack nt bin soe WARNING: XeraxPatecopring os books CRIMINAL ae. Aoyae fund uy is ABLE to fee LEGAL poets In aditon to cei ote probability of using pene fut. ub tbe requested item i ‘be pee containing the pe CPU can access i guickly Block (pode inthe software, (as they in te main memory ceed Instead of wal. the CPU pe IIS) tt pres OCs ae Fane faut are Seiomeas ch beck i rlegalaton a be ral yg ere te eed ad nor int, eon itand cache ad cache in, ini te near lovee Venti CPU ns wat Pi 0 pan Pinay ee CPU Wews ca ache mg ib cus Tr one pe of operation ty Fad. the ste intracton the blacks the subsequent to which tbe performance degrades However. the lve! soe hr erst CPU fos being passed whe the pase ful ae ‘SPECTRUM ALLINO! ner sks te pages are moved fm dik ota momen. cpu JOURNAL FOR ENGINEERING STUDENTS$.20 MICROPROCESSORS AND MICROCONTROLLERS [JNTU-HYDERABIp "Frequently Asked & Important Questions * Qi. Discuss the block diagram of CORTEX processor. Ans: Refer QUIS, (Bee.-19, (RIG), AIO | NoviDec-18, (R16), Att 2.” What is a super scalar processor? Explain. Ans: Refer Q28 (MayZdune-t9, (RIE), AA0{E) | May-18, (RAC), Qa) QS" List the main features of OMAP processor. With a neat diagram, explain the architecture of OMAP processor. Ans: Refér Q31. _ (MayiJune-t9, (R16), Qtt | NowDec.-18, (R16), Qt0)) Q4. Discuss the main features of CORTEX processor. Ans: Refer Q7, tnportant Oo Q5. Explain the register set of Cortex-M3 processor. Ans: Refer Q20. mnporant Oa Q6. Write short notes on program status register. Ans: Refer Q21 mnportst Os Q7. Explain memory processing and commands used in CORTEX processor. Ans: Refer Q22. : mnportnt ut Q8. Discuss briefly the following instructions, (i) Data Moving Instructions (i) Shift and Rotate Instructions. ~ Ans: Refer Q23. report Q9. Explain the different applications of CORTEX processor in detail. “Ans: Refer Q29. i Q10. Explain the functional description of OMAP-L138 C6000 ARM-DSP processor. Ans: Refer Q30. import OueS Q11. What is cache memory? What is its use in microcomputer. Ans: Refer Q32 i