Digital System Design

Digital System Design
Semiconductor
SEMICONDUCTOR MATERIALS
Semiconductors are a group of materials having conductivities between those of metals and insulators.
Silicon is by far the most common semiconductor used in integrated circuits and will be emphasized to a great
extent.
Gallium arsenide is one of the more common of the compound semiconductors. Its good optical properties
make it useful in optical devices. GaAs is also used in specialized applications in which, for example, high
speed is required.
Semiconductor
TYPES OF SOLIDS
Amorphous, polycrystalline, and single crystals are the three general types of solids.
The single-crystal regions are called grains and are separated from one another by grain boundaries.
Single-crystal materials, ideally, have a high degree of order, or regular geometric periodicity,
throughout the entire volume of the material.
The advantage of a single-crystal material is that, in general, its electrical properties are superior
Semiconductor
SPACE LATTICES
A representative unit, or a group of atoms, is repeated at regular
intervals in each of the three dimensions to form the single crystal. The
periodic arrangement of atoms in the crystal is called the lattice.
Basic Crystal Structures
Figure shows the simple cubic, body-centered cubic, and face-centered
cubic structures.
Semiconductor
THE DIAMOND STRUCTURE
Silicon is referred to as a group IV element and has a diamond crystal structure.
Germanium is also a group IV element and has the same diamond structure.
Semiconductor
Atomic Bonding
The interaction that occurs between atoms to form a solid and to reach the minimum total energy
depends on the type of atom or atoms involved.
The type of bond, or interaction, between atoms, then, depends on the particular atom or atoms in the
crystal. If there is not a strong bond between atoms, they will not “stick together” to create a solid.
Semiconductor
IMPERFECTIONS AND IMPURITIES IN SOLIDS
• In a real crystal, the lattice is not perfect, but contains imperfections or defects; that is, the perfect
geometric periodicity is disrupted in some manner.
• Imperfections tend to alter the electrical properties of a material and, in some cases, electrical
parameters can be dominated by these defects or impurities.
Semiconductor
Imperfections in Solids
• One type of imperfection that all crystals have in common is atomic thermal vibration.
• The atoms in a crystal, however, have a certain thermal energy, which is a function of temperature.
The thermal energy causes the atoms to vibrate in a random manner about an equilibrium lattice
point.
• This random thermal motion causes the distance between atoms to randomly fluctuate, slightly
disrupting the perfect geometric arrangement of atoms. This imperfection, called lattice
vibrations, affects some electrical parameters.
Semiconductor
• Second type of defect is called a point defect.
• In an ideal single-crystal lattice, the atoms are arranged in a perfect periodic arrangement.
However, in a real crystal, an atom may be missing from a particular lattice site. This defect is
referred to as a vacancy.
• In another situation, an atom may be located between lattice sites. This defect is referred to as an
interstitial.
• In the case of vacancy and interstitial defects, not only is the perfect geometric arrangement of
atoms broken but also the ideal chemical bonding between atoms is disrupted, which tends to
change the electrical properties of the material.
Semiconductor
• The point defects involve single atoms or single-atom locations. In forming single-crystal
materials, more complex defects may occur.
• A line defect, for example, occurs when an entire row of atoms is missing from its normal lattice
site. This defect is referred to as a line dislocation
Semiconductor
Impurities in Solids
• Foreign atoms, or impurity atoms, may be present in a crystal lattice. Impurity atoms may be
located at normal lattice sites, in which case they are called substitutional impurities.
• Impurity atoms may also be located between normal sites, in which case they are called interstitial
impurities.
• Some impurities, such as oxygen in silicon, tend to be essentially inert; however, other impurities,
such as gold or phosphorus in silicon, can drastically alter the electrical properties of the material.
Semiconductor
Impurities in Solids
• The technique of adding impurity atoms to a semiconductor material in order to change its
conductivity is called doping. There are two general methods of doping: impurity diffusion and
ion implantation.
Diffusion Process
• Impurity diffusion occurs when a semiconductor crystal is placed in a high temperature (1000ºC)
gaseous atmosphere containing the desired impurity atom.
• At this high temperature, many of the crystal atoms can randomly move in and out of their single-
crystal lattice sites. Vacancies may be created by this random motion so that impurity atoms can
move through the lattice by hopping from one vacancy to another.
• Impurity diffusion is the process by which impurity particles move from a region of high
concentration near the surface to a region of lower concentration within the crystal.
• When the temperature decreases, the impurity atoms become permanently frozen into the
substitutional lattice sites.
• Diffusion of various impurities into selected regions of a semiconductor allows us to fabricate
complex electronic circuits in a single semiconductor crystal.
Semiconductor
Ion Implementation
• Ion implantation generally takes place at a lower temperature than diffusion.
• A beam of impurity ions is accelerated to kinetic energies in the range of 50 keV or greater and
then directed to the surface of the semiconductor.
• The high-energy impurity ions enter the crystal and come to rest at some average depth from the
surface.
• One advantage of ion implantation is that controlled numbers of impurity atoms can be introduced
into specific regions of the crystal.
• A disadvantage of this technique is that the incident impurity atoms collide with the crystal atoms,
causing lattice-displacement damage.
• The lattice damage can be removed by thermal annealing, in which the temperature of the crystal
is raised for a short time. Thermal annealing is a required step after implantation.
Semiconductor
Ion Implementation
• Ion implantation generally takes place at a lower temperature than diffusion.
• A beam of impurity ions is accelerated to kinetic energies in the range of 50 keV or greater and
then directed to the surface of the semiconductor.
• The high-energy impurity ions enter the crystal and come to rest at some average depth from the
surface.
• One advantage of ion implantation is that controlled numbers of impurity atoms can be introduced
into specific regions of the crystal.
• A disadvantage of this technique is that the incident impurity atoms collide with the crystal atoms,
causing lattice-displacement damage.
• The lattice damage can be removed by thermal annealing, in which the temperature of the crystal
is raised for a short time. Thermal annealing is a required step after implantation.
ELECTRICAL CONDUCTION IN SOLIDS
The Energy Band and the Bond Model
• Figure shows a two dimensional representation of the covalent bonding in a single-crystal silicon
lattice at T= 0K
• The splitting of the discrete silicon energy states into bands of allowed energies as the silicon
crystal is formed is shown in Fig.
As the temperature increases above 0 K, a few valence band electrons may gain enough thermal
energy to break the covalent bond and jump into the conduction band.
• The semiconductor is neutrally charged. This means that, as the negatively charged electron
breaks away from its covalent bonding position, a positively charged “empty state” is created in
the original covalent bonding position in the valence band.
• As the temperature further increases, more covalent bonds are broken, more electrons jump to the
conduction band, and more positive “empty states” are created in the valence band.
• The energy states in the valence band are completely full and the states in the conduction band are
empty.
• For T > 0 K, in which some electrons have gained enough energy to jump to the conduction band
and have left empty states in the valence band. At this point there is no external forces are applied
so the electron and “empty state” distributions are symmetrical with k .
Each crystal has its own energy-band structure.
• If an electric field is applied, there are no particles to move, so
there will be no current in Fig. (a).
• Figure (b) shows another allowed energy band whose energy states
are completely full of electrons. A completely full energy band will
also not give rise to a current.
• A material that has energy bands either completely empty or
completely full is an insulator.
• The resistivity of an insulator is very large or, conversely, the
conductivity of an insulator is very small.
• There are essentially no charged particles that can contribute to a
drift current.
• Figure (c) shows a simplified energy-band diagram of an insulator.
The bandgap energy Eg of an insulator is usually on the order of
3.5 to 6 eV or larger, so that at room temperature.
• Figure (a) shows an energy band with relatively few electrons

near the bottom of the band. Now, if an electric field is applied,
the electrons can gain energy, move to higher energy states, and
move through the crystal. The net flow of charge is a current.
• Figure (b) shows an allowed energy band that is almost full of
electrons, which means that we can consider the holes in this
band. If an electric field is applied, the holes can move and give
rise to a current.
• Figure (c) shows the simplified energy-band diagram for this
case. The bandgap energy may be on the order of 1 eV.
• This energy-band diagram represents a semiconductor for T=0 K.
The k -Space Diagrams of GaAs
• The valence band maximum and the conduction band
minimum both occur at k=0.
• In GaAs, the minimum conduction band energy and
maximum valence band energy occur at the same k
value.
• A semiconductor with this property is said to be a direct
bandgap semiconductor; transitions between the two
allowed bands can take place with no change in crystal
momentum.
• This direct nature has significant effect on the optical
properties of the material.
• GaAs and other direct bandgap materials are ideally
suited for use in semiconductor lasers and other optical
devices
The k -Space Diagrams of Si
• The maximum in the valence band energy occurs at k=0.
• The minimum in the conduction band energy occurs not at
k=0, but along the [100] direction.
• The difference between the minimum conduction band energy
and the maximum valence band energy is still defined as the
bandgap energy Eg .
• A semiconductor whose maximum valence band energy and
minimum conduction band energy do not occur at the same k
value is called an indirect bandgap semiconductor.
• When electrons make a transition between the conduction and
valence bands, we must invoke the law of conservation of
momentum.
• Germanium is also an indirect bandgap material.
• GaP and AlAs, have indirect bandgaps.
Statistical Laws
There are three distribution laws determining the distribution of particles among available energy
states.
(1) Maxwell–Boltzmann probability function.
In this case, the particles are considered to be distinguishable by being numbered, for example, from
1 to N, with no limit to the number of particles allowed in each energy state.
The behavior of gas molecules in a container at fairly low pressure is an example of this distribution.
(2) Bose–Einstein function.
The particles in this case are indistinguishable and, again, there is no limit to the number of particles
permitted in each quantum state.
The behavior of photons, or black body radiation, is an example of this law.
(3) Fermi–Dirac probability function.
In this case, the particles are again indistinguishable, but now only one particle is permitted in each
quantum state.
Electrons in a crystal obey this law.
The Fermi–Dirac Probability Function
Figure shows the ith energy level with gi quantum states.
• A maximum of one particle is allowed in each quantum state by the Pauli exclusion principle.
• There are gi ways of choosing where to place the first particle, ( gi-1) ways of choosing where to
place the second particle, ( gi-2) ways of choosing where to place the third particle, and so on.
• Then the total number of ways of arranging Ni particles in the i th energy level (where Ni ≤ gi ) is
The Fermi–Dirac Probability Function
The number density N (E) is the number of particles per unit volume per unit energy and the function
g (E) is the number of quantum states per unit volume per unit energy.
The function fF (E) is called the Fermi–Dirac distribution or probability function and gives the
probability that a quantum state at the energy E will be occupied by an electron.
The energy EF is called the Fermi energy.

The Distribution Function and the Fermi Energy
Case 1: let T=0 K and consider the case when E<EF .
exp [( E-EF ) / kT ] → exp (-∞) = 0.
The resulting distribution function is fF( E<EF ) = 1.
Case 2: Again let T=0 K and consider the case when E > EF .
exp [( E-EF ) / kT ] → exp (∞) = + ∞.
The resulting Fermi–Dirac distribution function now becomes fF( E>EF ) = 0.
This result shows that, for T = 0 K, the electrons are in their lowest possible energy states. The
probability of a quantum state being occupied is unity for E<EF and the probability of a state being
occupied is zero for E>EF.
• Figure shows how these electrons are distributed among
the various quantum states at T=0 K.
• The electrons will be in the lowest possible energy
state, so the probability of a quantum state being
occupied in energy levels E1 through E4 is unity, and
the probability of a quantum state being occupied in
energy level E5 is zero.
• The Fermi energy, for this case, must be above E4 but
less than E5 .
• The Fermi energy determines the statistical distribution
of electrons and does not have to correspond to an
allowed energy level.
• When the temperature increases above T=0 K.
• Electrons gain a certain amount of thermal energy so
that some electrons can jump to higher energy levels,
which means that the distribution of electrons among
the available energy states will change.
The change in the electron distribution among energy levels for T=0 K can be seen by plotting the
Fermi–Dirac distribution function.
If we let E=EF and T=0 K,
The probability of a state being occupied at E=EF is ½.

The probability of a state being occupied, fF(E ), and the probability of a state being empty, 1-fF(E ).
Dopant Atoms And Energy Levels
The intrinsic semiconductor may be an interesting material, but the real power of semiconductors is
realized by adding small, controlled amounts of specific dopant, or impurity, atoms.
Two-dimensional representation of the Two-dimensional representation of the

intrinsic silicon lattice. silicon lattice doped with a phosphorus
atom.
• If a small amount of energy, such as thermal energy, is added to the donor electron, it can be
elevated into the conduction band, leaving behind a positively charged phosphorus ion.
• The electron in the conduction band can now move through the crystal generating a current,
while the positively charged ion is fixed in the crystal.
• This type of impurity atom donates an electron to the conduction band and so is called a donor
impurity atom.
• The donor impurity atoms add electrons to the conduction band without creating holes in the
valence band. The resulting material is referred to as an n-type semiconductor
• Adding a group III element, such as boron, as a substitutional impurity to silicon.
• The electron occupying this “empty” position does not have sufficient energy to be in the
conduction band, so its energy is far smaller than the conduction-band energy.
• The group III atom accepts an electron from the valence band and so is referred to as an acceptor
impurity atom.
• The acceptor atom can generate holes in the valence band without generating electrons in the
conduction band.
• This type of semiconductor material is referred to as a p type material
The Extrinsic Semiconductor
• An intrinsic semiconductor as a material with no impurity atoms present in the crystal.
• An extrinsic semiconductor is defined as a semiconductor in which controlled amounts of

specific dopant or impurity atoms have been added so that the thermal-equilibrium electron and
hole concentrations are different from the intrinsic carrier concentration
Degenerate and Nondegenerate Semiconductors
• The concentration of dopant atoms added is small when compared to the density of host or
semiconductor atoms.
• The small number of impurity atoms are spread far enough apart so that there is no interaction
between donor electrons, for example, in an n-type material.
• We have assumed that the impurities introduce discrete, noninteracting donor energy states in the
n-type semiconductor and discrete, noninteracting acceptor states in the p-type semiconductor.
• These types of semiconductors are referred to as nondegenerate semiconductors.
• If the impurity concentration increases, the distance between the impurity atoms decreases and a
point will be reached when donor electrons, for example, will begin to interact with each other.
• When this occurs, the single discrete donor energy will split into a band of energies. As the donor
concentration further increases, the band of donor states widens and may overlap the bottom of
the conduction band.
• This overlap occurs when the donor concentration becomes comparable with the effective density
of states. When the concentration of electrons in the conduction band exceeds the density of
states, the Fermi energy lies within the conduction band.
• This type of semiconductor is called a degenerate n-type semiconductor.
energy-band diagrams for degenerately doped (a) n-type and (b) p-type
semiconductors.
Energy-band diagram at T=0 K for (a) n-type and (b) p-type semiconductors.
PN-Junction
• The entire semiconductor is a single-crystal material in which one region is doped with acceptor
impurity atoms to form the p region and the adjacent region is doped with donor atoms to form the n
region.
• The interface separating the n and p regions is referred to as the metallurgical junction.
• Initially, at the metallurgical junction, there is a very large density gradient in both electron and
hole concentrations.
• Majority carrier electrons in the n region will begin diffusing into the p region, and majority
carrier holes in the p region will begin diffusing into the n region.
PN-Junction
• If we assume there are no external connections to the semiconductor, then this diffusion process
cannot continue indefinitely.
• As electrons diffuse from the n region, positively charged donor atoms are left behind. Similarly,
as holes diffuse from the p region, they uncover negatively charged acceptor atoms.
• The net positive and negative charges in the n and p regions induce an electric field in the region
near the metallurgical junction, in the direction from the positive to the negative charge, or from
the n to the p region.
PN-Junction
• The net positively and negatively charged regions are shown in Figure.
• These two regions are referred to as the space charge region. Essentially all electrons and holes
are swept out of the space charge region by the electric field. Since the space charge region is
depleted of any mobile charge, this region is also referred to as the depletion region.
PN-Junction
Zero Applied Bias
Built-in Potential Barrier
• If we assume that no voltage is applied across the pn junction, then the junction is in thermal
equilibrium—the Fermi energy level is constant throughout the entire system.
• Figure shows the energy-band diagram for the pn junction in thermal equilibrium.
• The conduction and valance band energies must bend as we go through the space charge region,
since the relative position of the conduction and valence bands with respect to the Fermi energy
changes between p and n regions.
PN-Junction
Built-in Potential Barrier
• Electrons in the conduction band of the n region see a potential barrier in trying to move into the
conduction band of the p region. This potential barrier is referred to as the built-in potential
barrier and is denoted by Vbi.
• The built-in potential barrier maintains equilibrium between majority carrier electrons in the n
region and minority carrier electrons in the p region, and also between majority carrier holes in the
p region and minority carrier holes in the n region.
• This potential difference across the junction cannot be measured with a voltmeter because new
potential barriers will be formed between the probes and the semiconductor that will cancel Vbi.
The potential Vbi maintains equilibrium, so no current is produced by this voltage.
PN-Junction
PN-Junction
Electric Field
• An electric field is created in the depletion region by the
separation of positive and negative space charge densities.
• We will assume that the space charge region abruptly ends in
then region at x=xn and abruptly ends in the p region at x=-xp.
• The electric fi eld is determined from Poisson’s equation
where φ(x) is the electric potential, E(x) is the electric field, ρ(x)
is the volume charge density, and εs is the permittivity of the
semiconductor
PN-Junction
Electric Field
From Figure, the charge densities are
The electric field in the p region is found by integrating above

Equation
The constant of integration is determined by setting E=0

at x=xp. The electric field in the p region is then given by
PN-Junction
Electric Field
In the n region, the electric field is determined from
where C2 is again a constant of integration and is determined by

setting E=0 at x=xn, since the E-field is assumed to be zero in the
n region and is a continuous function. Then
The electric field is also continuous at the metallurgical junction, or at x=0.
Above equation states that the number of negative charges per unit area in the p region is equal to the
number of positive charges per unit area in the n region.
PN-Junction
Electric Field
• The electric field direction is from the n to the p region, or in

the negative x direction for this geometry.
• For the uniformly doped pn junction, the E-fi eld is a linear
function of distance through the junction, and the maximum
(magnitude) electric field occurs at the metallurgical junction.
• An electric field exists in the depletion region even when no
voltage is applied between the p and n regions.
PN-Junction
Electric Field
• The electric field direction is from the n to the p region, or in

the negative x direction for this geometry.
• For the uniformly doped pn junction, the E-fi eld is a linear
function of distance through the junction, and the maximum
(magnitude) electric field occurs at the metallurgical junction.
• An electric field exists in the depletion region even when no
voltage is applied between the p and n regions.
PN-Junction
Space Charge Width
The distance that the space charge region extends into the p and n regions from the metallurgical
junction. This distance is known as the space charge width.
PN-Junction
PN-Junction
PN-Junction
REVERSE APPLIED BIAS
• If we apply a potential between the p and n regions, we will no longer be in an equilibrium
condition—the Fermi energy level will no longer be constant through the system.
• Figure shows the energy-band diagram of the pn junction for the case when a positive voltage is
applied to the n region with respect to the p region.
• As the positive potential is downward, the Fermi level on the n side is below the Fermi level on the
p side. The difference between the two is equal to the applied voltage in units of energy.
PN-Junction
• In this case the total potential barrier, indicated by Vtotal , has increased.
PN-Junction
Space Charge Width and Electric Field
• E is electric field in the space charge region and the electric field Eapp, induced by the applied
voltage.
• The electric fields in the neutral p and n regions are essentially zero, or at least very small, which
means that the magnitude of the electric field in the space charge region must increase above the
thermal-equilibrium value due to the applied voltage.
• The electric field originates on positive charge and terminates on negative charge; this means that
the number of positive and negative charges must increase if the electric field increases.
For given impurity doping concentrations, the

number of positive and negative charges in the
depletion region can be increased only if the space
charge width W increases.
The space charge width W increases, therefore, with
an increasing reverse-biased voltage VR.
PN-Junction
PN-Junction
PN-Junction
PN-Junction
• The magnitude of the electric field in the depletion region increases with an applied reverse-biased
voltage.
• The electric field is still a linear function of distance through the space charge region.
• The xn and xp increase with reverse-biased voltage, the magnitude of the electric field also
increases.
• The maximum electric field still occurs at the metallurgical junction.
PN-Junction
PN-Junction
PN-Junction
Junction Breakdown
• At some particular voltage, the reverse-biased current will increase rapidly. The applied voltage at
this point is called the breakdown voltage
• Two physical mechanisms give rise to the reverse-biased breakdown in a pn junction:
1. Zener effect and
2. Avalanche effect.
PN-Junction
Junction Breakdown
Zener breakdown
• Zener breakdown occurs in highly doped pn
junctions through a tunneling mechanism.
• In a highly doped junction, the conduction and
valence bands on opposite sides of the junction
are sufficiently close during reverse bias that
electrons may tunnel directly from the valence
band on the p side into the conduction band on
the n side.
PN-Junction
Junction Breakdown
Avalanche breakdown
• The avalanche breakdown process occurs when
electrons and/or holes, moving across the space
charge region, acquire sufficient energy from the
electric field to create electron–hole pairs by
colliding with atomic electrons within the
depletion region.
• The newly created electrons and holes move in
opposite directions due to the electric field and
thereby create a reverse-biased current.
PN-Junction
Forward Bias
• Applying Forward Bias lowers the potential barrier for carriers to diffuse (i.e. electron on n-side
see’s a lower barrier to diffuse to p-side and holes on p-side also see a lower barrier to diffuse to n-
side)
• the difference in two quasi fermi level is the amount of forward applied voltage.
φfn – φfp = qVa
PN-Junction
Forward Bias
PN-Junction
PN-Junction
Tunnel Diode
• The tunnel diode is a pn junction in which
both the n and p regions are degenerately
doped.
• In degenerately doped semiconductors the
Fermi level is in the conduction band of a
degenerately doped n-type material and in
the valence band of a degenerately doped p-
type material.
• Then, even at T=0 K, electrons will exist in
the conduction band of the n-type material,
and holes (empty states) will exist in the p-
type material.
Tunnel Diode
Figure shows the energy-band diagram at zero bias, which produces zero current on the I–V diagram.
All energy states are filled below EF on both sides of the junction.
Tunnel Diode
Figure shows the situation when a small forward-bias voltage is applied to the junction.
Electrons in the conduction band of the n region are directly opposite to empty states in the valence
band of the p region.
There is a finite probability that some of these electrons will tunnel directly into the empty states,
producing a forward-bias tunneling current as shown.
Tunnel Diode
With a slightly larger forward-bias voltage, the maximum number of electrons in the n region will be
opposite the maximum number of empty states in the p region; this will produce a maximum tunneling
current.
Tunnel Diode
As the forward-bias voltage continues to increase, the number of electrons on the n side directly
opposite empty states on the p side decreases, and the tunneling current will decrease.
Tunnel Diode
In Figure, there are no electrons on the n side directly opposite to available empty states on the p side.
For this forward-bias voltage, the tunneling current will be zero and the normal ideal diffusion current
will exist in the device as shown in the I–V characteristics.
Tunnel Diode
simplifi ed energy-band diagram of the tunnel diode with an applied reverse biased voltage is shown in
Figure.
The Two-terminal MOS Structure
• The metal may be aluminum or some other type of metal, it is actually a high-conductivity
polycrystalline silicon that has been deposited on the oxide
• The parameter tox in the figure is the thickness of the oxide and εox is the permittivity of the oxide.
Energy Band Diagram
• Figure shows a parallel-plate capacitor with the top plate at a negative voltage with respect to the
bottom plate.
• An insulator material separates the two plates. With this bias, a negative charge exists on the top
plate, a positive charge exists on the bottom plate, and an electric field is induced between the two
plates as shown.
• The capacitance per unit area for this geometry is
•
Energy Band Diagram
• Figure shows a MOS capacitor with a p-type semiconductor substrate.
• The top metal gate is at a negative voltage with respect to the semiconductor substrate. A negative
charge will exist on the top metal plate and an electric field will be induced.
• If the electric field were to penetrate into the semiconductor, the majority carrier holes would
experience a force toward the oxide– semiconductor interface.
• An accumulation layer of holes at the oxide–semiconductor junction corresponds to the positive
charge on the bottom “plate” of the MOS capacitor.
Energy Band Diagram
• Figure shows the same MOS capacitor in which the polarity of the applied voltage is reversed.
• A positive charge now exists on the top metal plate and the induced electric field is in the opposite
direction as shown. If the electric field penetrates the semiconductor in this case, majority carrier
holes will experience a force away from the oxide–semiconductor interface.
• As the holes are pushed away from the interface, a negative space charge region is created because
of the fixed ionized acceptor atoms. The negative charge in the induced depletion region
corresponds to the negative charge on the bottom “plate” of the MOS capacitor.
Energy Band Diagram
Figure shows the ideal case when zero bias is applied across the MOS device. The energy bands in the
semiconductor are flat indicating no net charge exists in the semiconductor. This condition is known as
flat band.
Energy Band Diagram
• Figure shows the energy-band diagram for the case when a negative bias is applied to the gate.
(Remember that positive electron energy is plotted “upward” and positive voltage is plotted
“downward.”)
• The valence-band edge is closer to the Fermi level at the oxide–semiconductor interface than in the
bulk material, which implies that there is an accumulation of holes.
• The semiconductor surface appears to be more p-type than the bulk material. The Fermi level is a
constant in the semiconductor since the MOS system is in thermal equilibrium and there is no
current through the oxide.
Energy Band Diagram
• Figure shows the energy-band diagram of the MOS system when a positive voltage is applied to the
gate.
• The conduction- and valence-band edges bend as shown in the figure, indicating a space charge
region similar to that in a pn junction.
• The conduction band and intrinsic Fermi levels move closer to the Fermi level. The induced space
charge width is xd.
Energy Band Diagram
• A larger positive voltage is applied to the top metal gate of the MOS capacitor. In this case the
induced electric field to increase in magnitude and the corresponding positive and negative charges
on the MOS capacitor to increase.
• A larger negative charge in the MOS capacitor implies a larger induced space charge region and
more band bending.
• The conduction band at the surface is now close to the Fermi level, whereas the valence band is
close to the Fermi level in the bulk semiconductor.
• This result implies that the surface in the semiconductor adjacent to the oxide–semiconductor
interface is n type.
Work Function Differences
• Vacuum level be the minimum energy required
for an electron to free itself from the material.
• The work function is the minimum amount of
energy needed to eject an electron from the
surface of a metal.
• The difference between the vacuum level and the
Fermi level (E0-Ef) is called the work function,
and the difference between the vacuum level and
the conduction band edge (E0-Ec) is called the
electron affinity.
• The electron affinity is fixed for a semiconductor
material, while the work function varies with the
position of the fermi level (function of doping
type and concentration).
Work Function Differences
is known as the metal–semiconductor work function

difference
Flat-Band Voltage
• The flat-band voltage is defined as the applied gate voltage such that there is no band bending in the
semiconductor and, as a result, zero net space charge in this region.
• We assuming that there is zero net charge density in the oxide material. This assumption may not be
valid—a net fixed charge density, usually positive, may exist in the insulator.
• Q’ss is located in the oxide directly adjacent to the oxide–semiconductor interface.
For zero applied gate voltage,
If a gate voltage is applied, the potential drop across the oxide and the surface potential will change. We
can then write
Flat-Band Voltage
There is zero net charge in the semiconductor, and we can assume that an equivalent fixed surface
charge density exists in the oxide. The charge density on the metal is Q’m , and from charge neutrality
we have
Threshold Voltage
Threshold Voltage (PMOS)
The MOSFET Transistor
• The MOSFET is a four terminal device. The voltage applied to the gate terminal determines if and
how much current flows between the source and the drain ports.
• The body represents the fourth terminal of the transistor. Its function is secondary as it only serves
to modulate the device characteristics and parameters.
• The transistor can be considered to be a switch. When a voltage is applied to the gate that is larger
than a given value called the threshold voltage VT, a conducting channel is formed between drain
and source.
• The conductivity of the channel is modulated by the gate voltage the larger the voltage difference
between gate and source, the smaller the resistance of the conducting channel and the larger the
current.
• When the gate voltage is lower than the threshold, no such channel exists, and the switch is
considered open.
• The NMOS transistor consists of n+ drain and source regions, embedded in a p-type substrate. The
current is carried by electrons moving through an n-type channel between source and drain.
• In pn-junction diode, where current is carried by both holes and electrons.
• MOS devices can also be made by using an n-type substrate and p+ drain and source regions. In
such a transistor, current is carried by holes moving through a p-type channel. The device is called a
p-channel MOS, or PMOS transistor.
• In a complementary MOS technology (CMOS), both devices are present.
Resistive Operation
Assume now that VGS > VT and that a small voltage, VDS, is applied between drain and source. The
voltage difference causes a current ID to flow from drain to source
The current is given as the product of the drift

velocity of the carriers ʋn and the available charge.
Resistive Operation
Integrating the equation over the length of the channel L yields the voltage-current relation of the
transistor.
The product of the process transconductance and the (W/L) ratio of an (NMOS) transistor is called the
gain factor kn of the device.
For smaller values of VDS, the quadratic factor in above Eq. can be ignored, and we observe a linear
dependence between VDS and ID.
Saturation Operation
• As the value of the drain-source voltage is further increased, the assumption that the channel
voltage is larger than the threshold all along the channel ceases to hold.
• This happens when VGS - V(x) < VT. At that point, the induced charge is zero, and the conducting
channel disappears or is pinched off.
No channel exists in the vicinity of the drain region.

Obviously, for this phenomenon to occur, it is
essential that the pinch-off condition be met at the
drain region, or
Under those circumstances, the transistor is in the

saturation region.
The voltage difference over the induced channel (from the
pinch-off point to the source) remains fixed at VGS - VT,
and consequently, the current remains constant (or
saturates).
Channel-Length Modulation
• The equation shows that the transistor in the saturation mode acts as a perfect current source — or
that the current between drain and source terminal is a constant, independent of the applied voltage
over the terminals.
• This not entirely correct. The effective length of the conductive channel is actually modulated by
the applied VDS: increasing VDS causes the depletion region at the drain junction to grow, reducing
the length of the effective channel.
• The current increases when the length factor L is decreased.
with ID’ the current expressions derived earlier, and λ an

empirical parameter, called the channel-length
modulation.
Velocity Saturation
• The behavior of transistors with very short channel lengths (called short-channel devices) deviates
considerably from the resistive and saturated models.
• The main culprit for this deficiency is the velocity saturation effect states that the velocity of the
carriers is proportional to the electrical field, independent of the value of that field.
• In other words, the carrier mobility is a constant. However, at high field strengths, the carriers fail
to follow this linear model.
• In fact, when the electrical field along the channel reaches a critical value Ec, the velocity of the
carriers tends to saturate due to scattering effects (collisions suffered by the carriers).
Velocity Saturation
• This effect has a profound impact on the operation of the transistor.
Velocity Saturation
k is a measure of the degree of velocity saturation, since VDS/L can be interpreted as the average field
in the channel.
In case of long-channel devices (large values of L) or small values of VDS, k approaches 1
Above Eq. simplifies to the traditional current equation for the resistive operation mode.
For short-channel devices, k is smaller than 1, which means that the delivered current is smaller than
what would be normally expected.
Velocity Saturation
When increasing the drain-source voltage, the electrical field in the channel will ultimately reach the
critical value, and the carriers at the drain become velocity saturated.
The saturation drain voltage VDSAT can be calculated by equating the current at the drain to the current
given by above Eq. for VDS = VDSAT.
Velocity Saturation
Velocity Saturation
• The velocity saturates abruptly at ξc, and is approximated by the following expression:
• The drain-source voltage VDSAT at which the critical electrical field is reached and velocity
saturation comes into play is constant
This model is truly first-order and empirical.

The simplified velocity model causes substantial deviations in
the transition zone between linear and velocity-saturated
regions.
Drain Current versus Voltage Charts
Subthreshold Conduction
• Current does not drop abruptly to 0 at VGS = VT.
• It becomes apparent that the MOS transistor is already partially conducting for voltages below the
threshold voltage. This effect is called subthreshold or weak-inversion conduction.
• The onset of strong inversion means that ample carriers are available for conduction.
From Fig. the current does not drop to zero
immediately for VGS < VT, but actually decays in an
exponential fashion, similar to the operation of a
bipolar transistor.
In the absence of a conducting channel, the n+ (source)
- p (bulk) - n+ (drain) terminals actually form a
parasitic bipolar transistor. The current in this region
can be approximated by the expression
ID current versus VGS

(on logarithmic scale),
Dynamic Behavior
• The dynamic response of a MOSFET transistor is a sole function of the time it takes to (dis)charge
the parasitic capacitances that are intrinsic to the device, and the extra capacitance introduced by
the interconnecting lines.
• They originate from three sources:
The basic MOS structure,
The channel charge, and
The depletion regions of the reverse-biased pn-junctions of drain and source.
MOS Structure Capacitances
• The gate of the MOS transistor is isolated from the conducting channel by the gate oxide that has a
capacitance per unit area equal to Cox = εox / tox.
• The total value of this capacitance is called the gate capacitance Cg and can be decomposed into
two elements, each with a different behavior.
• One part of Cg contributes to the channel charge. Another part is solely due to the topological
structure of the transistor.
• In reality, both source and drain tend to extend somewhat below the oxide by an amount xd, called
the lateral diffusion.
• It gives rise to a parasitic capacitance between gate and source (drain) that is called the overlap
capacitance. This capacitance is strictly linear and has a fixed value.
Channel Capacitance
• The gate-to-channel capacitance CGC varies in both magnitude and in its division into three
components CGCS, CGCD, and CGCB (being the gate-to-source, gate-to-drain, and gate-to-body
capacitances, respectively) depending upon the operation region and terminal voltages.
• When the transistor is in cut-off (a), no channel exists, and the total capacitance CGC appears
between gate and body.
• In the resistive region (b), an inversion layer is formed, which acts as a conductor between source
and drain. Consequently, CGCB = 0 as the body electrode is shielded from the gate by the channel.
• Symmetry dictates that the capacitance distributes evenly between source and drain.
• Finally, in the saturation mode (c), the channel is pinched off. The capacitance between gate and
drain is approximately zero, and so is the gate-body capacitance.
Channel Capacitance
The gate-capacitance
components are
nonlinear and
varying with the
operating voltages
Junction Capacitances
Capacitive Device Model
Example
Example
The CMOS Inverter
The CMOS Inverter
The CMOS Inverter
For a dc operating points to be valid, the currents through the NMOS and PMOS devices must be equal. Graphically, this
means that the dc points must be located at the intersection of corresponding load lines
The CMOS Inverter
The CMOS Inverter
The CMOS Inverter
The CMOS Inverter
The CMOS Inverter
The CMOS Inverter
The CMOS Inverter
The CMOS Inverter
The CMOS Inverter
The CMOS Inverter
The CMOS Inverter
Switching Threshold
• The switching threshold, VM, is defined as the point where Vin = Vout. Its value can be obtained
graphically from the intersection of the VTC with the line given by Vin = Vout.
• In this region, both PMOS and NMOS are always saturated, since VDS = VGS. An analytical
expression for VM is obtained by equating the currents through the transistors
The CMOS Inverter
Switching Threshold
The CMOS Inverter
Switching Threshold
The effect of changing the Wp/Wn ratio is to

shift the transient region of the VTC. Increasing
the width of the PMOS or the NMOS moves
VM towards VDD or GND, respectively.
Changing the switching threshold by a considerable amount is however not easy, to move the threshold
to 1.5 V requires a transistor ratio of 11, and further increases are prohibitively expensive.
The CMOS Inverter
Noise Margins
Since on-chip interconnects are generally prone to signal noise, the output signal of the first inverter will
be perturbed during transmission.
The CMOS Inverter
Noise Margins
• The voltage level at the input of the second inverter will be either larger or smaller than VOL.
• If the input voltage of the second inverter is smaller than VOL' this signal will be interpreted correctly
as a logic "0" input by the second inverter.
• On the other hand, if the input voltage becomes larger than VIL as a result of noise, then it may not be
interpreted correctly by the inverter.
• Thus, we conclude that VIL is the maximum allowable voltage at the input of the second inverter,
which is low enough to ensure a logic "1" output.
The CMOS Inverter
Noise Margins
• Now consider the signal transmission from the output of the second inverter to the input of the third
inverter, assuming that the second inverter produces an output voltage level of VOH.
• Due to the noise interference, If the input voltage of the third inverter is larger than VOH, this signal
will be interpreted correctly as a logic " 1 " input by the third inverter.
• If the voltage level drops below VIH due to noise, however, the input cannot be interpreted as a logic
"1.“ Consequently, VIH is the minimum allowable voltage at the input of the third inverter which is
high enough to ensure a logic "0" output.
The CMOS Inverter
Noise Margins
VIH is the minimum allowable voltage at the input of the third inverter which is high enough to ensure a
logic "0" output.
The CMOS Inverter
Noise Margins
The CMOS Inverter
Device Variations
Impact of device variations on static CMOS inverter VTC. The “good” device has a smaller oxide
thickness (- 3nm), a smaller length (-25 nm), a higher width (+30 nm), and a smaller threshold (-60
mV). The opposite is true for the “bad” transistor.
The CMOS Inverter
Scaling the Supply Voltage
The CMOS Inverter
Performance of CMOS inverter: Dynamic Behaviour
The propagation delay of the CMOS inverter is determined by the time it takes to charge and discharge
the load capacitor CL through the PMOS and NMOS transistors, respectively.
CL = 2Cgd12 + Cdb1 + Cdb2 + Cw + Cg4 + Cg3

The CMOS Inverter
Gate capacitances Cgd,p and Cgd,n:

Just after the input switches(t = 0+), what regions are transistors in?
– One is in cutoff: Cgd = Overlap Cap

– One is in Saturation: Cgd = Overlap Cap
– Therefore, gate-to-drain capacitance is due to overlap capacitance :
Cgd,n= Cgd,p = CoxWLd

The CMOS Inverter
The CMOS Inverter
Junction capacitances Cdb,p and Cdb,n:

– Equation for junction cap:
– Non-linear, depends on voltage across junction

– Use Keq factor to get equivalent capacitance for a voltage transition
The CMOS Inverter
Wiring Capacitance Cw
The capacitance due to the wiring depends upon the length and width of the connecting wires, and is a
function of the distance of the fanout from the driving gate and the number of fanout gates.
Gate Capacitance of Fanout Cg3 and Cg4

The CMOS Inverter
Logic Circuit Delay

The CMOS Inverter
The propagation delay times are defined as the time
delay between the 50% crossing of the input and the
corresponding 50% crossing of the output.
The rise time and the fall time of the output signal
are defined as the time required for the voltage to
change from its 10% level to its 90% level (or vice
versa).
The CMOS Inverter
Logic Circuit Delay

• Suppose ideal voltage step at input
• Assume: Current charging or discharging capacitance Cload is nearly constant Iavg
• tPHL = Cload (Vdd - Vdd/2) / Iavg
• tPLH = Cload (Vdd/2 - Vss) / Iavg
The CMOS Inverter
Inverter Delay: Falling

The CMOS Inverter
The CMOS Inverter
The CMOS Inverter
Delay calculation in terms of resistance

The CMOS Inverter
How can we improve the performance ?
• Reduce CL: Remember that three major factors contribute to the load capacitance: the internal
diffusion capacitance of the gate itself, the interconnect capacitance, and the fanout.
• Increase the W/L ratio of the transistors: This is the most powerful and effective performance
optimization tool in the hands of the designer.
Increasing the transistor size also raises the diffusion capacitance and hence CL. In fact, once
the intrinsic capacitance (i.e. the diffusion capacitance) starts to dominate the extrinsic load
formed by wiring and fanout, increasing the gate size does not longer help in reducing the
delay, and only makes the gate larger in area. This effect is called “self-loading”.
• Increase VDD. The delay of a gate can be modulated by modifying the supply voltage.
The CMOS Inverter
Power Consumption
Dynamic Power Consumption

Dynamic Dissipation due to Charging and Discharging Capacitances
• Each time the capacitor CL gets charged through the PMOS transistor, its voltage rises from 0 to
VDD, and a certain amount of energy is drawn from the power supply. Part of this energy is
dissipated in the PMOS device, while the remainder is stored on the load capacitor.
• During the high-to-low transition, this capacitor is discharged, and the stored energy is dissipated in
the NMOS transistor
The CMOS Inverter
Power Consumption
Energy Calculations:
The values of the energy EVDD, taken from the supply during the transition,
as well as the energy EC, stored on the capacitor at the end of the transition,
can be derived by integrating the instantaneous power over the period of
interest.
During the discharge phase, the charge is removed from the capacitor, and its
energy is dissipated in the NMOS device.
The CMOS Inverter
Power Consumption
To compute the power consumption, we have to take into account how often the device is switched. If
the gate is switched on and off f 0→1 times per second, the power consumption equals
The CMOS Inverter
Power Dissipation Due to Direct-Path Currents
• In actual designs, the assumption of the zero rise and fall times of the input wave forms is not
correct. During the input switching, NMOS and the PMOS transistors are conducting
simultaneously.
• Under the (reasonable) assumption that the resulting current spikes can be approximated as
triangles and that the inverter is symmetrical in its rising and falling responses, we can compute the
energy consumed per switching period,
The CMOS Inverter
Static Power Dissipation
Ideally, the static current of the CMOS inverter is equal to zero, as the PMOS and NMOS devices are
never on simultaneously in steady-state operation.
There is, unfortunately, a leakage current flowing through the reverse-biased diode junctions of the
transistors, located between the source or drain and the substrate.
The CMOS Inverter
Static Power Dissipation
Contribution od static power dissipation is very small and can be ignored.

For the device sizes under consideration, the leakage current per unit drain area typically ranges
between 10-100 pA/mm² at room temperature. For a die with 1 million gates, each with a drain area of
0.5 mm² and operated at a supply voltage of 2.5 V, the worst-case power consumption due to diode
leakage equals 0.125 mW, which is clearly not much of an issue.
However, be aware that the junction leakage currents are caused by thermally generated carriers. Their
value increases with increasing junction temperature, and this occurs in an exponential fashion. At
85°C (a common junction temperature limit for commercial hardware), the leakage currents increase
by a factor of 60 over their room-temperature value.
The CMOS Inverter
Combinational Circuits
Static CMOS Design
• The static CMOS style is really an extension of the static CMOS inverter to multiple inputs.
• The primary advantage of the CMOS structure is robustness (i.e, low sensitivity to noise), good
performance, and low power consumption with no static power dissipation.
• The complementary CMOS circuit style falls under a broad class of logic circuits called static
circuits in which at every point in time (except during the switching transients), each gate output is
connected to either VDD or Vss via a low-resistance path.
Static CMOS Design
Complementary CMOS
• A static CMOS gate is a combination of

two networks, called the pull-up network
(PUN) and the pull-down network
(PDN).
• The function of the PUN is to provide a
connection between the output and VDD
anytime the output of the logic gate is
meant to be 1 (based on the inputs).
• Similarly, the function of the PDN is to
connect the output to VSS when the
output of the logic gate is meant to be 0.
• The PUN and PDN networks are
constructed in a mutually exclusive
fashion such that one and only one of the
networks is conducting in steady state.
Static CMOS Design
Complementary CMOS : 2 Input NAND gate
Example
Example
Static CMOS Design
Threshold voltage of transistor M2 will be higher than transistor M1 due to the body effect.
Static CMOS Design
Static CMOS Design
Delay = 0.69 (RnCint + (Rn+Rn) CL)

Static CMOS Design
4-Input NAND gate
Assuming that all NMOS devices have an equal size

Static CMOS Design
Ratioed logic
• The clear advantage of pseudo-NMOS is the reduced number of transistors (N+1 versus 2N for
complementary CMOS).
• The nominal high output voltage (VOH) for this gate is VDD since the pull-down devices are
turned off when the output is pulled high.
• On the other hand, the nominal low output voltage is not 0 V since there is a fight between the
devices in the PDN and the grounded PMOS load device.
• This results in reduced noise margins and more importantly static power dissipation.
Static CMOS Design
Ratioed logic
• Ratioed logic is an attempt to reduce the number of transistors required to implement a given
logic function, at the cost of reduced robustness and extra power dissipation.
• In ratioed logic, the entire PUN is replaced with a single unconditional load device that pulls up
the output for a high output.
• Instead of a combination of active pull-down and pull-up networks, such a gate consists of an
NMOS pull-down network that realizes the logic function, and a simple load device.
• Figure shows an example of ratioed logic, which uses a grounded PMOS load and is referred to as
a pseudo-NMOS gate.
Static CMOS Design
Ratioed logic
Static CMOS Design
Differential Cascode Voltage Switch Logic (or DCVSL)
• To eliminates the static currents and provides rail-to-rail swing in ratoed logic.
• A differential gate requires that each input is provided in complementary format, and produces
complementary outputs in turn. The feedback mechanism ensures that the load device is turned
off when not needed.
2-input NAND-AND gate

Static CMOS Design
Pass Transistor Logic
A popular and widely-used alternative to complementary CMOS is pass-transistor logic, which
attempts to reduce the number of transistors required to implement logic by allowing the primary
inputs to drive gate terminals as well as source/drain terminals
Static CMOS Design
Pass-transistor gates cannot be cascaded by connecting the output of a pass gate to the gate
input of another pass transistor
Static CMOS Design
Static CMOS Design
Transmission gate Logic
Transmission gates enable rail-to-rail switching

Static CMOS Design
Transmission gate Logic
Static CMOS Design
Dynamic Logic
Precharge
When CLK = 0, the output node Out is precharged to VDD by the
PMOS transistor Mp. During that time, the evaluate NMOS transistor
Me is off, so that the pull-down path is disabled.
The evaluation FET eliminates any static power that would be
consumed during the precharge period.
Evaluation
For CLK = 1, the precharge transistor Mp is off, and the evaluation
transistor Me is turned on. The output is conditionally discharged based
on the input values and the pull-down topology. If the inputs are such
that the PDN conducts, then a low resistance path exists between Out
and GND and the output is discharged to GND.
If the PDN is turned off, the precharged value remains stored on the
output capacitance CL.
Static CMOS Design
Dynamic Logic
• The logic function is implemented by the NMOS pull-down network. The construction of the PDN
proceeds just as it does for static CMOS.
• The number of transistors (for complex gates) is substantially lower than in the static case: N + 2
versus 2N.
• It is non-ratioed. The sizing of the PMOS precharge device is not important for realizing proper
functionality of the gate. The size of the precharge device can be made large to improve the low-
to-high transition time (of course, at a cost to the high-to-low transition time). There is however, a
trade-off with power dissipation since a larger precharge device directly increases clock-power
dissipation.
• It only consumes dynamic power. Ideally, no static current path ever exists between VDD and
GND. The overall power dissipation, however, can be significantly higher compared to a static
logic gate
• The logic gates have faster switching speeds.

Digital System Design

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Digital System Design

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Digital System Design

• Figure (a) shows an energy band with relatively few electrons

The energy EF is called the Fermi energy.

The probability of a state being occupied at E=EF is ½.

Two-dimensional representation of the Two-dimensional representation of the

• An extrinsic semiconductor is defined as a semiconductor in which controlled amounts of

• The electric fi eld is determined from Poisson’s equation

The electric field in the p region is found by integrating above

The constant of integration is determined by setting E=0

where C2 is again a constant of integration and is determined by

The electric field is also continuous at the metallurgical junction, or at x=0.

• The electric field direction is from the n to the p region, or in

• The electric field direction is from the n to the p region, or in

For given impurity doping concentrations, the

is known as the metal–semiconductor work function

The current is given as the product of the drift

No channel exists in the vicinity of the drain region.

Under those circumstances, the transistor is in the

with ID’ the current expressions derived earlier, and λ an

This model is truly first-order and empirical.

ID current versus VGS

The effect of changing the Wp/Wn ratio is to

CL = 2Cgd12 + Cdb1 + Cdb2 + Cw + Cg4 + Cg3

Gate capacitances Cgd,p and Cgd,n:

– One is in cutoff: Cgd = Overlap Cap

– Therefore, gate-to-drain capacitance is due to overlap capacitance :

Cgd,n= Cgd,p = CoxWLd

Junction capacitances Cdb,p and Cdb,n:

– Non-linear, depends on voltage across junction

Gate Capacitance of Fanout Cg3 and Cg4

Logic Circuit Delay

Logic Circuit Delay

Inverter Delay: Falling

Delay calculation in terms of resistance

Dynamic Power Consumption

Contribution od static power dissipation is very small and can be ignored.

• A static CMOS gate is a combination of

Delay = 0.69 (RnCint + (Rn+Rn) CL)

Assuming that all NMOS devices have an equal size

2-input NAND-AND gate

Transmission gates enable rail-to-rail switching

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