PID Controller Modifications to Improve Steady-State Performance of Digital
Controllers for Buck and Boost Converters
Liping Guo, John Y. Hung, and R. M. Nelms
Department of Electrical & Computer Engineering
Auburn University, AL 36849-5201
Abstract: The sensitivity of the analog-to-digital converter and
inherent time delay in a digital controller can degrade the
steady-state performance of a DC-DC converter. Analog PID
controllers were designed for prototype buck and boost
converters and then implemented on a TI DSP. Three
modifications to the digital PID controllers were investigated to
improve their steady-state performance. The modifications
were a dead zone, an averaging digital filter and two sets of
gains. The digital controller monitors the output voltage error
to determine if a modification should be employed to calculate
the next duty cycle. Experimental results from both prototype
converters indicates that a stable and accurate steady-state
response can be obtained while maintaining a good transient
response.
I. INTRODUCTION
Digital signal processors (DSPs), microprocessors, and
microcontrollers have been utilized in motor drives and
uninterruptible power supplies for a number of years.
Traditionally, regulation of the output voltage of DC-DC
converters has been achieved through the use of analog
control techniques. An analog control system operates in real
time and can have a high bandwidth. In addition, the voltage
resolution for an analog system is theoretically infinite [1].
However, an analog system is usually composed of discrete
hardware that must be modified to change controller gains or
algorithms. In addition, the implementation of advanced
control algorithms requires an excessive number of
components. An examination of the literature indicates that
interest is growing in the application of digital control
techniques for regulating DC-DC converter output voltage [2-
18]. The complexity of a digital control system is contained
mostly in software. Once working properly, software is more
consistent and reliable than a complex analog system. Digital
processors also have the advantage of being less susceptible
to aging and environmental or parameter variations. In
addition, the processor can monitor the system, perform self-
diagnostics and tests, and communicate status to a display or
a host computer [2-3].
Technological advances have yielded microcontrollers and
DSPs with the necessary on-board features to allow
implementation of a digital controller for a DC-DC converter
using a single chip. An analog-to-digital converter (ADC)
measures the output voltage and converts it to a
corresponding binary number. A new duty cycle is calculated
by the CPU using an algorithm stored in memory and passed
to a PWM module, which controls the main switch or
switches in the DC-DC converter. The measurement of the
output voltage, calculation of the new duty cycle, and update
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of the duty cycle require a finite amount of time, so there is
an inherent time delay in a digital controller for a DC-DC
converter. In addition, most microcontrollers and DSPs only
allow the new duty cycle to take effect at the beginning of the
next switching cycle after its calculation. As a result, the
minimum time delay for the digital controller is equal to one
switching period for the converter.
In comparison to an analog controller, numerical values in
the digital controller are restricted to a finite set of values
depending on the number of bits utilized in the
microcontroller or DSP. For example, an 8-bit ADC converts
the output voltage of the DC-DC converter into 256 discrete
values. A 10-bit PWM module can only realize 1024
different duty cycles. The computations within the digital
control algorithm are also affected by binary representations
for all numbers.
Both the inherent time delay and finite number
representations of the digital controller must be considered in
the design of the control algorithm to achieve stable
operation. Different approaches to these issues have been
proposed in the literature. A window circuit was utilized in
[5] to increase the ADC resolution in a digital controller
implemented with an 8-bit microcontroller. The authors of
[10] introduced a double PWM scheme to improve the PWM
resolution. Simple predictive schemes were investigated in
[8] to compensate for the inherent time delay.
Presented in this paper are the results of an investigation
into the effects of a digital controller on the steady-state
performance of prototype buck and boost converters. The
output voltage of both converters was monitored to determine
if the digital controller caused any steady-state error or
increased the ripple in the output voltage. A proportional-
integral-derivative (PID) controller was implemented for the
converters using a TMS320F240 evaluation module from
Texas Instruments. This module features a 16-bit fixed point
DSP controller with flash memory which operates at 20
MIPS with an instruction cycle time of 50 ns. The DSP
controller has three 16-bit, 6-mode, general purpose timers,
12 PWM channels and dual 10-bit, 8-channel ADCs. The 10-
bit ADC converts an analog voltage into 1024 (210) discrete
levels. For operation from a 5 V supply, the discrete levels
are separated by approximately 5 mV (5/1024). A ripple of
50 mV in the converter output voltage produces a change of
10 discrete levels in the ADC output. A fast responding
control algorithm will react to these changes in ADC value
and may actually increase the amount of ripple in the output
voltage.
381
 The PID controllers for the prototype converters were
designed based on the small signal model for each converter
and then transformed into difference equations for
implementation on the DSP. Both the sampling frequency
and switching frequency were selected to be 20 kHz for this
investigation. The digital controller acquires a sample once
every sampling period (50 µs), utilizes a PID algorithm to
calculate a new duty cycle, and updates the new duty cycle at
the start of the next switching period. So the duty cycle is
only able to be updated after a one switching period delay.
Operation of both prototype converters with digital
implementations of a PID controller verified that the output
voltage ripple was increased by the inherent time delay in the
digital system and the sensitivity of the ADC. Four different (a). Synchronized sampling.
controller modifications were examined to minimize the
output ripple induced by the digital controller. These are: 1)
change the instant when the ADC samples the output voltage,
2) utilize two sets of gains for the PID controller, 3) introduce
a dead zone into the PID controller, and 4) introduce an
averaging digital filter into the PID controller. Results from
these modifications are discussed in the following sections.
II. SAMPLING INSTANT
The first modification to the digital PID controller is to
change the instant when the ADC samples the output voltage
in relation to the each time a switch changes state in the
converter. The switching action of the semiconductor
devices in a converter will produce spikes in the converter
output voltage. If the output voltage is sampled at the (b) Non-synchronized sampling.
switching instant, the ADC may actually capture the
switching spike. This would result in an erroneous input to Fig. 1. Duty cycle variations with sampling instant.
the PID controller algorithm. Top waveform: Converter output voltage ripple - 100 mV/div
Bottom waveform: Switch control signal – 5 V/div
The effect of changing the sampling instant is illustrated in
Time: 50 µs/div
Fig. 1. In parts (a) and (b) of this figure, the top waveform is
an expanded version of the converter output voltage to iin L RL
observe the ripple. The bottom waveform is the signal
produced by the PWM module on the DSP controller which
controls the switch in the buck converter. Sampling at the + Gate C +
beginning of a switching period is designated as synchronized Vin
Drive
R Vo
Diode
sampling. Note the variations in the duty cycle in Fig. 1a due RC
- -
to the synchronized sampling. Fig. 1b shows that the
variations in the duty cycle can be reduced by using what is
referred to as non-synchronized sampling. Here the output
voltage was sampled 3 µs after the beginning of the switching
period. In both cases, the output voltage is sampled once Fig. 2. Buck converter.
each switching period; only the instant at which the sample The variable D is the duty cycle. The circuit parameters for
taken was changed.
this converter are Vin = 20 V, V0 = 12 V, L = 150 µH, C =
III. PID CONTROLLER DESIGN FOR A BUCK CONVERTER 1000 µF, and R = 10 Ω. The parasitic elements RC and RL
A PID controller design is designed for the buck converter were estimated to be 30 mΩ and 10 mΩ, respectively. The
shown in Fig. 2. The design began with the very familiar switching frequency is 20 kHz. Fig. 3 is a Bode plot for the
small-signal model for this converter [20]: small signal model of (1) at the buck converter’s nominal
operating point. This plot was verified on the actual buck
 
vˆ0 ( s )  Vo   1 + sRCC . (1) converter using a Model 102B analog network analyzer by
=    AP Instruments. The one switching period delay between
ˆ
d ( s )  D   1 + s  RCC + R // RL C + L  2  R + R 
  [ ]  + s LC 
C
 sampling the converter output voltage and updating the duty
 R + RL   R + RL  

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 − Ts range of 45° to 60° to meet the transient response
cycle is modeled by the function e , where T is the
sampling period for the digital controller (50 µs). Fig. 4 is requirements [20].
the Bode plot for the buck converter and time delay. Note The compensator in this investigation was a PID controller
that this model for the time delay only impacts the phase plot. which is described by the following transfer function:
KI
GC ( s ) = Kp + + K Ds (2)
40
s
In this equation, KP is the proportional gain, KI is the integral
20
gain, and KD is the derivative gain. This controller has one
0 pole at the origin and two zeros. The goal of the first design,
labeled PID Design I, is to improve the transient response by
GaindB

-20
improving the phase margin. The two zeros were placed at
-40 approximately 260 radians/second and 2600 radians/second
yielding (3).
-60
2 3 4 5 6
1.3413*102
GC ( s ) = 5.6746 *10-1 + + 1.9841*10-4 s .
10 10 10 10 10
Frequency(rad/sec) (3)
s
0 Fig. 5 is a Bode plot for the compensated system. The phase
margin is about 55°, and the bandwidth is approximately
-50
22,000 radians/second.
The PID controller was designed in the continuous time
Phase deg

-100
domain and then converted to the discrete time domain using
-150
the backward integration method (Euler rule) [19]. The
following difference equation can be produced from the
-200 discrete time transfer function.
2 3 4 5 6
10 10 10 10 10 k
KD
Frequency(rad/sec) u ( k ) = KPe( k ) + KIT ∑ e( i ) + T
[ e( k ) − e( k − 1)] . (4)
i=0
Fig. 3. Bode plot of the buck converter small signal model.
In this equation, u(k) is the new duty cycle calculated from
the kth sample, and e(k) is the error of the kth sample. The
40

30
error e(k) is calculated as e(k) = Ref-ADC(k), where ADC(k)
20
is the converted digital value of the kth sample, and Ref is the
10 digital value corresponding to the desired output voltage.
Gain dB

0 The second term in the equation is the sum of the errors and
-10 e(k)-e(k-1) is the difference between the error of the kth
-20 sample and the error of the (k-1)th sample.
-30
IV. PID CONTROLLER MODIFICATIONS
2 3 4 5
10 10 10 10
Frequency (rad/sec)

0 Equation (4) was implemented on the TMS320F240

evaluation module, which produced the gating signal applied
-100
to the MOSFET of the buck converter. The output voltage of
the buck converter was measured using a TDS754D
Phase (deg)

-200
-300
-400
10
2 3
10
4
10
Frequency (rad/sec)
Fig. 4. Bode plot for the buck converter and time delay.
Examination of the Bode plot in Fig. 4 indicates that this
system has a very small phase margin. A compensator must
be designed to ensure that the gain at low frequencies is high
enough to minimize the steady-state error and that the
crossover frequency should be as high as possible but about
an order of magnitude below the switching frequency to
allow the power supply to respond to transients quickly. The
phase margin of the compensated system should be in the
oscilloscope during a start-up transient. The output voltage
had a rise time of approximately 1 ms with no overshoot.
Observation of the duty cycle and output voltage in steady
10
5
state revealed that the duty cycle oscillated between 22% and
85%. The magnitude of the ripple in the output voltage was
250 mV with a steady-state error of 120 mV. In comparison,
the magnitude of the ripple under open loop converter
operation was measured to be only 80 mV. Three algorithm
modifications were investigated to reduce the steady-state
ripple and error while maintaining a fast transient response.
A. Two sets of gains
PID Design I produced a system with a phase margin of
55°. The resulting start-up transient in the output voltage was
characterized by a rise time of 1 ms and no overshoot.
However, the steady-state ripple in the output voltage was

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increased from 80 mV to 250 mV. One approach to maintain 100

the transient response and improve steady-state response is to 80

utilize two sets of controller gains. One set can be utilized 60
during the transient, and the other used in steady state.

GaindB
A second PID controller, labeled PID Design II, was 40

designed with a higher phase margin and a lower bandwidth. 20

This design yielded a system with a slower transient response 0

but a better steady-state response. In this design, a set of -20
complex conjugate zeros is placed close to the complex 10
-1 0
10 10
1
10
2 3
10
4
10
5
10
conjugate poles of the buck converter small signal model. Frequency (rad/sec)

The complex conjugate zeros approximately cancel out the -50

phase shift from the complex conjugate poles at the cutoff
-100
frequency. The transfer function for this PID controller is
-150
3.8462*102
GC ( s) = 2.1144*10-2 + + 5.7808*10-5 s . (5)

Phase deg
-200
s
The Bode plot for the system compensated with this PID -250

controller is displayed in Fig. 6. This design yields a -300

bandwidth of 8000 radians/second and a phase margin of 80°. -350

-1 0 1 2 3 4 5
The bandwidth is lower than the one in Design I, which slows 10 10 10 10 10 10 10
Frequency (rad/sec)
down the system. The phase margin is larger than Design I,
which makes the system more stable. Fig. 6. Bode plot for PID Design II.
The decision to switch between the gains of PID Design I
B. Dead zone
and PID Design II can be based on e(k), the error at the kth
The dead zone is a nonlinear function described as follows:
sample. If e(k) is less than or equal to some predefined
level ε, then the gains of PID Design II are utilized. If e(k)
> ε, then the gains of PID Design I are used to determine the e ( k ), when e(k ) > ε
new duty cycle. This permits the controller to respond
p(k ) =  . (6)
0, when e( k ) ≤ ε
rapidly to changes in the load or input voltage while
Variable p(k) is the value supplied to the PID controller. If
maintaining good steady-state performance.
the value of ε is too small, the number of transitions between
the levels defined in (6) will be very frequent resulting in
increased oscillation in the output voltage during steady state.
On the other hand, a large lag in the system response will
result if the value of ε is too large. For this modification, the
PID algorithm with the gains from PID Design I is executed
100

80
with either the actual error e(k) or 0 depending on ε.
60
C. Averaging digital filter
Gain dB

40
For the averaging digital filter, the last five error values are
20
added together and divided by 5 as shown in (7).
0

-20 e(k ) + e(k − 1) + e(k − 2) + e(k − 3) + e(k − 4)

e(k ) avg = . (7)
-1 0 1 2 3 4 5
10 10 10 10 10 10 10
Frequency (rad/sec) 5
0 If e(k) ≤ ε, the average error as calculated by (7) is
-50 supplied to the PID controller. If e(k) > ε, then e(k) is
-100 passed to the PID controller. The gains from PID Design I
-150 are utilized to calculate the new duty cycle with either e(k) or
Phase deg

-200 e(k)avg.
-250

-300
D. Selection of ε
-350
All three PID algorithm modifications are based on the
10
-1
10
0
10
1
10
2 3
10
4
10
5
10 adjustable parameter ε. This parameter was determined
Frequency (rad/sec)
experimentally using the buck converter prototype. A
Fig. 5. Bode plot for PID Design I. comparison of the steady-state performance of the buck
converter for ε = 100 mV, 150 mV, and 200 mV is shown in
Table I.

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 TABLE I. SYSTEM PERFORMANCE FOR DIFFERENT VALUES OF ε. The reference change tests the system’s response to a
ε = 200 mV PWM Ripple Steady State disturbance. The transient response for a reference change
oscillation Error with the dead zone algorithm is shown in Fig. 8. The
Dead Zone 59%~60% 100 mV 3 mV averaging digital filter and the two sets of gains algorithms
Average Filter 56.9%~ 62% 150 mV -10 mV
Two Sets of Gains 56.6%~63.6% 100 mV -6 mV
produced very similar responses, so they have not been
included. The settling time for all three algorithm
ε = 150mV PWM Ripple Steady State modifications is about 2 ms. There is little overshoot when
oscillation Error the output voltage rises from 0 V to 10V or from 10 V to 14
Dead Zone 58% ~ 60% 60 mV 7 mV V. When the output voltage decreases from 14 V to 10 V, the
Average Filter 56% ~ 63% 175 mV 20 mV settling time is about 12 ms for all three modifications, which
Two sets of Gains 56.5% ~ 62.2% 100 mV 37 mV
is much longer than the settling time for a change to a higher
voltage. This is because the output capacitor needs to
ε = 100 mV PWM Ripple Steady State
oscillation Error discharge when the output voltage decreases. When
Dead Zone Not Stable decreasing from 14 V to 10 V, the overshoot is about 10% for
Average Filter 56% ~ 63% 175 mV 20 mV the dead zone and the averaging digital filter and about 15%
Two sets of Gains 56.5% ~ 60% 100 mV 20 mV for the two sets of gains. The switch from the set of gains
with a faster response to the set of gains with a slower
For the dead zone, the controller is the most stable when response results in the higher overshoot for this
ε =200 mV; the smallest oscillation of the PWM signal and modifications.
steady state error were obtained. When ε = 150 mV, the
ripple is smaller. The duty cycle is stable most of the time,
but occasionally oscillates for a very short time. This may be
because of the frequent transitions between the levels of the
dead zone. When ε is 100 mV, the system becomes unstable.
Therefore, an optimal value of ε =200 mV was chosen for
the dead zone. For the averaging digital filter, the oscillation
of the PWM signal was very similar when ε varies from 200
mV to 100 mV. However, the ripple and the steady state error
were the smallest when ε is 200 mV, so ε =200 mV was also
chosen for the averaging digital filter. For the two sets of
gains modification, the PWM oscillation and the ripple were
very similar as ε varies, but the steady-state error was
smallest when ε =200 mV, so this value of ε was chosen. Fig. 7. Start-up transients for the three modifications.
Based on the results in Table I, ε was selected to be 200 mV (2 V/div,10 ms/div)
for all algorithm modifications.
E. Buck converter experimental results
The performance of the buck converter with the PID
controller and three algorithm modifications was evaluated
for a start-up transient, reference change, and a steady-state
performance. Fig. 7 shows the start-up transient for the three
modifications. R1 is the waveform for the dead zone, R2 is
the waveform for the averaging digital filter and R3 is the
waveform for the two sets of gains algorithm. The settling
time is about 2 ms for all three algorithm modifications. For
the dead zone and averaging digital filter, there is no
overshoot. For the two sets of gains algorithm, there is a little
overshoot; switching gains may slow down the system to
Fig. 8. Reference change response for the dead zone modification.
cause the overshoot. Since the dead zone takes any error (5 V/div,10 ms/div)
under 200 mV to be zero, there is some oscillation of the
output voltage after it goes to steady state. A more detailed The ripple of the output voltage of the buck converter
examination of this waveform at a time scale of 10 ms/div operating open loop is shown in Fig. 9. The magnitude of the
revealed that this oscillation disappears after 200 ms. ripple is under 80 mV. The ripple of the output voltage of the
Next the output voltage reference in the software was buck converter under closed-loop operation with the different
changed from 10 V to 14 V every 20 ms. This is a 17% algorithm modifications is shown in Figs. 10, 11 and 12,
change from the nominal value of the output voltage (12 V). respectively. The magnitude of the ripple is under 100 mV

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for both the dead zone and two sets of gains, and is under 150
mV for the averaging digital filter. The ripple for the
averaging digital filter has a frequency of 1 kHz. However,
the ripple with the other two techniques is random. In
comparison, the magnitude of the ripple with the averaging
digital filter is the highest among the three PID algorithm
modifications. The ripple with the other two algorithm
modifications is only a little higher than the open loop ripple.
Fig. 9. Ripple of the buck converter under open loop operation.
(50 mV/div,500 µs/div)
Fig. 10. Steady-state ripple with the dead zone.
(50 mV/div,500 µs/div)
Fig. 11. Steady-state ripple with the averaging digital filter.
(100 mV/div,500 µs/div)
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Fig. 12. Steady-state ripple with the two sets of gains.
(50 mV/div,500 µs/div)
V. PID CONTROLLER FOR A BOOST CONVERTER
A PID controller was also designed and implemented for a
boost converter using the same ideas presented in the
previous two sections. A prototype boost converter was
designed and constructed to produce an output voltage of 12
V from an input voltage of 5V. The circuit parameters for the
boost converter were C = 1056 µF, L = 250 µH, and R = 25 Ω
(load resistance). The parasitic elements RC and RL were
estimated to be 30 mΩ and 10 mΩ, respectively. The
switching frequency for the boost converter was 20 kHz, and
the sampling frequency for the digital PID controller was also
20 kHz.
The frequency response of the boost converter was also
measured using a Model 102B analog network analyzer by
AP Instruments. Both the magnitude and phase plots change
with the duty cycle. The crossover frequency for the boost
converter was approximately one decade below that for the
buck converter. As a result, the phase delay from the one
switching period delay between sampling the output voltage
and updating the duty cycle is quite small and was not
considered in the design of the PID controller for the boost
converter.
The zeros of the PID controller for the boost converter
were placed at 260 radians/second and 2600 radians/second
yielding the transfer function in (3). The Bode plot for the
compensated system is shown in Fig. 13. The bandwidth and
phase margin are approximately 2000 radians/second and
50°, respectively.
The three algorithm modifications discussed previously
were also applied to the implementation of the PID controller
for the boost converter. It was determined experimentally
that only the dead zone with ε = 200 mV worked
satisfactorily. The start-up transient, shown in Fig. 14, has a
settling time of 15 ms and no overshoot. The output voltage
reference in the software was changed from 10 V to 14 V
every 50 ms, and the response is shown in Fig. 15. Note that
it takes about 8 ms for the output voltage to increase from 10
V to 14 V, and about 20 ms to decrease from 14 V to 10 V.
The steady-state performance of the boost converter was
also examined. The ripple in the output voltage under open
loop operation is shown in Fig. 16; the magnitude of this
ripple is approximately 80 mV. Fig. 17 is a plot of the ripple
in the output voltage under closed-loop operation. The
magnitude of the ripple is approximately 100 mV, which is
comparable to the open loop ripple magnitude.

60

40

20
Gain dB

-20
Fig. 16. Steady-state ripple under open loop operation.
-40
1 2 3 4 5 6 7
(100 mV/div,20 µs/div)
10 10 10 10 10 10 10
Frequency (rad/sec)

-60

-80
Phase deg

-100

-120

-140
1 2 3 4 5 6 7
10 10 10 10 10 10 10
Frequency (rad/sec)

Fig. 13. Bode plot of the compensated system for the boost converter.
Fig. 17. Steady-state ripple under closed loop operation.
(100 mV/div,20 µs/div)

Fig. 14. Start-up transient response for the boost converter.
(5 V/div,5 ms/div)
Fig. 15. Reference change transient response of the boost converter.
(5 V/div,20 ms/div)
VI. SUMMARY
The steady-state performance of digital controllers for DC-
DC converters can be impacted by the sensitivity of the ADC
and an inherent time delay. Sampling the converter output
voltage, calculating a new duty cycle, and then updating the
duty cycle require a finite amount of time. The minimum
delay is equal to one switching period. A sensitive ADC may
be able to track the ripple in the output voltage. As a result,
the digital controller may actually increase the ripple in the
output voltage in steady state.
Approaches to improve the steady-state performance of
digital PID controllers for buck and boost converters have
been presented in this paper. One approach utilized two sets
of gains for the PID controller. One set of gains is utilized to
provide a fast transient response, while the other set yields
better steady-state performance such as reduced controller-
induced oscillations. A digital controller can easily switch
between the gains based on the output voltage error. A
second approach employs a dead zone. When the output
voltage error is smaller than a preset value, it is set to zero. If
the error is larger than this value, a standard PID controller
uses the error to calculate the new duty cycle. Another
approach averages the last five values of the output voltage
error as the input to the PID controller.
All three approaches have been implemented and tested
with prototype buck and boost converters. The standard PID
algorithm is utilized until the magnitude of the output voltage

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error is less than 200 mV. Then the PID algorithm is
modified to incorporate one of the modifications. The results
of this investigation indicate that a good steady-state
performance can be achieved while maintaining a good
transient response. The output voltage ripple under closed
loop control is comparable to that under open loop control.
ACKNOWLEDGMENT
This research was supported by the Center for Space Power
and Advanced Electronics with funds from NASA grant
NCC3-511, Auburn University, and the Centers' industrial
partners.
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