HT9200A/HT9200B

DTMF Generators
Features
· Operating voltage: 2.0V~5.5V · Low total harmonic distortion
· Serial mode for the HT9200A · 3.58MHz crystal or ceramic resonator
· Serial/parallel mode for the HT9200B · HT9200A: 8-pin DIP/SOP package
· Low standby current HT9200B: 14-pin SOP package

General Description
The HT9200A/B tone generators are designed for MCU
interfaces. They can be instructed by a MCU to gener-
ate 16 dual tones and 8 single tones from the DTMF pin.
The HT9200A provides a serial mode whereas the
HT9200B contains a selectable serial/parallel mode in-
terface for various applications such as security sys-
tems, home automation, remote control through
telephone lines, communication systems, etc.

Selection Table
Function Operating OSC
Interface Package
Part No. Voltage Frequency

HT9200A 2V~5.5V 3.58MHz Serial 8 DIP/SOP

HT9200B 2V~5.5V 3.58MHz Serial/Parallel 14 SOP

Block Diagram

X 1 3 .5 8 M H z
D T M F D T M F
C r y s ta l/R e s o n a to r
G e n e ra to r
X 2 O s c illa to r

D A T A S e r ia l D a ta C o n tro l P a r a l l e lD a t a
In p u t C ir c u it C ir c u it I n p u tC ir c u it
C L K

C E S /P D 3 D 2 D 1 D 0

Rev. 1.10 1 October 2, 2002

 HT9200A/HT9200B

Pin Assignment

C E 1 1 4 V D D
X 2 2 1 3 D T M F
X 1 3 1 2 D A T A
C E 1 8 V D D V S S 4 1 1 C L K
X 2 2 7 D T M F N C 5 1 0 S /P
X 1 3 6 D A T A D 0 6 9 D 3
V S S 4 5 C L K D 1 7 8 D 2

H T 9 2 0 0 A H T 9 2 0 0 B
8 D IP -A /S O P -A 1 4 S O P -A

Pad Assignment Pad Coordinates Unit: mm

C E V D D Pad Pad
X Y X Y
No. No.
1 3 1 2
X 2 1
1 1 D T M F
1 -553.30 430.40 8 553.30 -523.50
2 -553.30 -133.50 9 553.30 -190.30
(0 ,0 ) 3 -553.30 -328.50 10 553.30 4.70
1 0 D A T A
X 1 2 4 -553.30 -523.50 11 553.30 340.30
9 C L K
V S S 3
5 -220.10 -523.50 12 374.90 523.50
6 -25.10 -523.50 13 -279.30 523.50
D 0 4 5 6 7 8
7 308.10 -523.50
D 1 D 2 D 3 S /P

Chip size: 1460 ´ 1470 (mm)2

* The IC substrate should be connected to VSS in the PCB layout artwork.

Pin Description
Internal
Pin Name I/O Description
Connection
CMOS IN
CE I Chip enable, active low
Pull-high
X2 O The system oscillator consists of an inverter, a bias resistor, and the required load
capacitor on chip.
Oscillator
X1 I The oscillator function can be implemented by Connect a standard 3.579545MHz
crystal to the X1 and X2 terminals.
VSS ¾ ¾ Negative power suppl, ground

NC ¾ ¾ No connection
Data inputs for the parallel mode
CMOS IN
When the IC is operating in the serial mode, the data input terminals (D0~D3) are
D0~D3 I Pull-high
included with a pull-high resistor. When the IC is operating in the parallel mode,
or Floating
these pins become floating.
Operation mode selection input
S/P I CMOS IN S/P=²H²: Parallel mode
S/P=²L²: Serial mode
Data synchronous clock input for the serial mode
CMOS IN
When the IC is operating in the parallel mode, the input terminal (CLK) is included
CLK I Pull-high
with a pull-high resistor. When the IC is operating in the serial mode, this pin be-
or Floating
comes floating.

Rev. 1.10 2 October 2, 2002

 HT9200A/HT9200B

Internal
Pin Name I/O Description
Connection
Data input terminal for the serial mode
CMOS IN
When the IC is operating in the parallel mode, the input terminal (DATA) is included
DATA I Pull-high
with a pull-high resistor. When the IC is operating in the serial mode, this pin be-
or Floating
comes floating.
DTMF O CMOS OUT Output terminal of the DTMF signal
VDD ¾ ¾ Positive power supply, 2.0V~5.5V for normal operation

Approximate internal connection circuits

C M O S IN C M O S O U T C M O S IN (F o r D 0 ~ D 3 , C M O S IN
P u ll- h ig h V D D
C L K , D A T A )
V D D
V D D

O S C IL L A T O R

X 1 X 2

2 0 p F 1 0 M 1 0 p F

E N

Absolute Maximum Ratings

Supply Voltage ............................................-0.3V to 6V Storage Temperature ............................-50°C to 125°C
Input Voltage ................................VSS-0.3 to VDD+0.3V Operating Temperature...........................-20°C to 75°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.

Rev. 1.10 3 October 2, 2002

 HT9200A/HT9200B

Electrical Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾ ¾ 2 ¾ 5.5 V

2.5V S/P=VDD,D0~D3=VSS, ¾ 240 2500

IDD Operating Current mA
5.0V CE=VSS, No load ¾ 950 3000
VIL ²Low² Input Voltage ¾ ¾ VSS ¾ 0.2VDD V
VIH ²High² Input Voltage ¾ ¾ 0.8VDD ¾ VDD V

2.5V ¾ ¾ 1
ISTB Standby Current S/P=VDD,CE=VDD, no load mA
5.0V ¾ ¾ 2
2.5V 120 180 270
RP Pull-high Resistance VOL=0V kW
5.0V 45 68 100
DTMF Output Delay Time
tDE 5V ¾ ¾ tUP+6 tUP+8 ms
(Parallel Mode)
2V~
VTDC DTMF Output DC Level DTMF Output 0.45VDD ¾ 0.75VDD V
5.5V
ITOL DTMF Sink Current 2.5V VDTMF=0.5V -0.1 ¾ ¾ mA
VTAC DTMF Output AC Level 2.5V Row group, RL=5kW 0.12 0.15 0.18 Vrms
ACR Column Pre-emphasis 2.5V Row group=0dB 1 2 3 dB
RL DTMF Output Load 2.5V tHD £-23dB 5 ¾ ¾ kW
tHD Tone Signal Distortion 2.5V RL=5kW ¾ -30 -23 dB
fCLK Clock Input Rate (Serial Mode) ¾ ¾ ¾ 100 500 kHz
The time from CE falling
Oscillator Starting Time
tUP 5.0V edge to normal oscillator ¾ ¾ 10 ms
(When CE is low)
operation
fOSC System Frequency ¾ Crystal=3.5795MHz 3.5759 3.5795 3.5831 MHz

Rev. 1.10 4 October 2, 2002

 HT9200A/HT9200B

Functional Description
The HT9200A/B are DTMF generators for MCU inter-
faces. They are controlled by a MCU in the serial mode
or the parallel mode (for the HT9200B only).
Serial mode (HT9200A/B)
The HT9200A/B employ a data input, a 5-bit code, and a
synchronous clock to transmit a DTMF signal. Every
digit of a phone number to be transmitted is selected by
a series of inputs which consist of 5-bit data. Of the 5
bits, the D0(LSB) is the first received bit. The
HT9200A/B will latch data on the falling edge of the
clock (CLK pin). The relationship between the digital
codes and the tone output frequency is shown in Table
1. As for the control timing diagram, refer to Figure 1.
When the system is operating in the serial mode a
pull-high resistor is attached to D0~D3 (for parallel
mode) on the input terminal.

Table 1: Digits vs. input data vs. tone output frequency (serial mode)
Digit D4
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
0 0
* 0
# 0
A 0
B 0
C 0
D 0
¾ 1
Tone Output
D3 D2 D1 D0
Frequency (Hz)
0 0 0 1 697+1209
0 0 1 0 697+1336
0 0 1 1 697+1477
0 1 0 0 770+1209
0 1 0 1 770+1336
0 1 1 0 770+1477
0 1 1 1 852+1209
1 0 0 0 852+1336
1 0 0 1 852+1477
1 0 1 0 941+1336
1 0 1 1 941+1209
1 1 0 0 941+1477
1 1 0 1 697+1633
1 1 1 0 770+1633
1 1 1 1 852+1633
0 0 0 0 941+1633
0 0 0 0 697

¾ 1 0 0 0 1 770

¾ 1 0 0 1 0 852

¾ 1 0 0 1 1 941

¾ 1 0 1 0 0 1209

¾ 1 0 1 0 1 1336

¾ 1 0 1 1 0 1477

¾ 1 0 1 1 1 1633
DTMF OFF 1 1 1 1 1 ¾
Note: The codes not listed in Table 1 are not used D4 is MSB

Rev. 1.10 5 October 2, 2002

 HT9200A/HT9200B

For the HT9200B, the S/P pin has to be connected low for
serial mode operation.
Parallel mode ( HT9200B)
The HT9200B provides four data inputs D0~D3 to gener-
ate their corresponding DTMF signals. The S/P has to be
connected high to select the parallel operation mode.
Then the input data codes should be determined. Finally,
the CE is connected low to transmit the DTMF signal from
the DTMF pin.
The TDE time (about 6ms) will be delayed from the CE fall-
ing edge to the DTMF signal output.
The relationship between the digital codes and the tone
output frequency is illustrated in Table 2. As for the control
timing diagram, see Figure 2.
When the system is operating in the parallel mode,
D0~D3 are all in the floating state. Thus, these data in-
put pins should not float.

S /P

X 2
( O s c illa to r )
tU P

C E

C L K

L S B M S B L S B M S B L S B M S B
D A T A 1 1 1 1 1

D ig it 1 D ig it 2 S to p c o d e

D T M F
D ig it 1 D ig it 2
D T M F s ig n a l D T M F s ig n a l

Figure 1

Table 2: Digits vs. input data vs. tone output frequency (parallel mode)
Digit D3
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 1
9 1
0 1
* 1
# 1
A 1
B 1
C 1
D 0
D2 D1
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
Tone Output
D0
Frequency (Hz)
1 697+1209
0 697+1336
1 697+1477
0 770+1209
1 770+1336
0 770+1477
1 852+1209
0 852+1336
1 852+1477
0 941+1336
1 941+1209
0 941+1477
1 697+1633
0 770+1633
1 852+1633
0 941+1633

Rev. 1.10 6 October 2, 2002

 HT9200A/HT9200B

S /P

X 2
( O s c illa to r )

C E

D 0 ~ D 3

D T M F
tD E tD E

N o te : T h e d a ta ( D 0 ~ D 3 ) s h o u ld b e r e a d y b e fo r e th e C E b e c o m e s lo w .
Figure 2

Tone frequency
Output Frequency (Hz)
%Error
Specified Actual
697 699 +0.29%
770 766 0.52%
852 847 0.59%
941 948 +0.74%
1209 1215 +0.50%
1336 1332 0.30%
1477 1472 0.34%

% Error does not contain the crystal frequency drift

Rev. 1.10 7 October 2, 2002

 HT9200A/HT9200B

Application Circuits
Serial mode

V D D V D D

V D D 3 .5 7 9 5 4 5 M H z 1 8
C E C E V D D
2 D T M F 7 T o n e
C L K X 2
3 6 O u tp u t
D A T A 2 0 p F X 1 D A T A
V S S 2 0 p F 4 C L K 5
V S S
M C U H T 9 2 0 0 A

Serial/parallel mode

V D D
V D D

3 .5 7 9 5 4 5 M H z 1 1 4
C E C E V D D
V D D 2 0 p F 2
D 0 D T M F 1 3 T o n e
X 2
D 1 3 1 2 O u tp u t
X 1 D A T A
D 2 4 1 1
2 0 p F V S S C L K
D 3 5
S /P 1 0
S /P N C
V S S 6 9
V S S C L K D 0 D 3
D A T A 7 8
D 1 D 2
M C U H T 9 2 0 0 B

Rev. 1.10 8 October 2, 2002

 HT9200A/HT9200B

Package Information
8-pin DIP (300mil) outline dimensions

8 5
B
1 4

D
= I
E G

Dimensions in mil
Symbol
Min. Nom. Max.
A 355 ¾ 375
B 240 ¾ 260
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I 335 ¾ 375
a 0° ¾ 15°

Rev. 1.10 9 October 2, 2002

 HT9200A/HT9200B

8-pin SOP (150mil) outline dimensions

8 5
A B
1 4

C '
G
D H

E F =

Dimensions in mil
Symbol
Min. Nom. Max.
A 228 ¾ 244
B 149 ¾ 157
C 14 ¾ 20
C¢ 189 ¾ 197
D 53 ¾ 69
E ¾ 50 ¾
F 4 ¾ 10
G 22 ¾ 28
H 4 ¾ 12
a 0° ¾ 10°

Rev. 1.10 10 October 2, 2002

 HT9200A/HT9200B

14-pin SOP (150mil) outline dimensions

1 4 8
A B
1 7

C '
G
D H

E F =

Dimensions in mil
Symbol
Min. Nom. Max.
A 228 ¾ 244
B 149 ¾ 157
C 14 ¾ 20
C¢ 336 ¾ 344
D 53 ¾ 69
E ¾ 50 ¾
F 4 ¾ 10
G 22 ¾ 28
H 4 ¾ 12
a 0° ¾ 10°

Rev. 1.10 11 October 2, 2002