Total No.

of Questions :8]
SEAT No. :
P4106 [Total No. of Pages : 2
[5255]-604
M.E. (Electronics) (Digital Systems)
DESIGN FOR TESTABILITY
(2013 Pattern) (Semester - II)

Time : 3 Hours] [Max. Marks : 50

Instructions to the candidates:
1) Answer any five questions.
2) Neat diagrams must be drawn wherever necessary.
3) Figures to the right side indicate full marks.
4) Use of calculator is allowed.
5) Assume Suitable data if necessary.

Ql) a) Show how the function f (w1, w2, w3) = can be implemented using a 3 to 8
binary decoder and an OR gate.
b) Implement f (w , w , w ) =  m (0, 4, 6, 7) using 2:1 multiplexer, use
1 2 3
Shanon’s expansion similarly use 4:1 Mux for the same.

Q2) a) What is meant by design for testability? What are the characteristics of DFT.
b) Design a single - input and single -output Moore-type FSM that produces an
output of 1 if in the input sequence it detects either 110 or 101 patterns.
Overlapping sequences should be detected.

Q3) a) An SR flip-flop is a flip-flop that has set and reset inputs like a gated SR latch
show how an SR flip-flop can be constructed using a D flip-flop and other
logic gates.
b) Derive a Mealy-type FSM that can act as a sequence detector that produces
z=1 when the previous two values of w were 00 or 11; otherwise z=0.

Q4) a) Consider the Function f=(w1,w2,w3,w4)=m(0,1,3,6,8,9,14,15) Derive a circuit

that implements f using the minimal number of three input LUTs.
b) Write VHDL code to expand 8-to-1 multiplexer using component 2-to-1
multiplexer.

P.T.O
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Q5) a) Show how a JK flip -flop can be constructed using a T flip flop and
other logic gates.
b) Explain the BIST architecture for sequential circuit.

Q6) a) Explain the significance of enable input in digital circuits with example.
b) Derive a table to show the coverage of various stuck - at - 0 and stuck - at-1 faults
by the eight possible tests. Find a minimal test set for this circuit.

Q7) a) Consider the function Use the truth table to derive a circuit that uses 2- to-1
multiplexer.
b) Explain the steps involved in Scan Path Technique.

Q8) a) Explain what are static and dynamic hazard.

b) Explain control path and data path in ASM chart.

a a

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Total No. of Questions : 8]
SEAT No. :
P4107 [Total No. of Pages : 2
[5255]-605
M.E. (Electronics - Digital
Systems) PLD'S AND ASIC
DESIGN (2013 Pattern)
(Semester - II)
Time : 3 Hours] [Max. Marks : 50
Instructions to the candidates:
1) Solve any 5 questions.
2) Neat diagrams must be drawn wherever necessary.
3) Figures to the right indicate full marks.
4) Assume suitable data if necessary.

Ql) a) What are the different examinations are carried out in the static timing
analysis. [4]
b) Explain the state diagram optimization. [4]
c) What are data path and control path? [2]

Q2) a) Explain the architecture and functional block of Cool Runner. [5]
b) What are the problems caused by multiple activation of a process
statement during one real time point? Explain remedy for these problems.
[5]

Q3) a) Explain behavioural and data flow VHDL modelling techniques with
example. [4]
b) Differentiate between the function and procedure in VHDL. [4]
c) Explain the significance of Chipscope Pro. [2]

Q4) a) Explain the boundary scanning mechanism. [4]

b) What are different ASIC Design tools? Describe any one in detail. [4]

P.T.O
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 c) What are the top down approaches to design a system? [2]
Q5) a) Draw and describe Xilinx Virtex - II architecture. [4]
b) Explain the difference between simulation and synthesis. [4]
c) Write a note on hardware and software codesign. [2]

Q6) a) Classify and explain Gate array based ASICs. [4]

b) Why FPGAs are often used to implement pipelining effectively? [4]
c) Enlist applications of CPLDs. [2]

Q7) a) Write a note on IP core. [4]

b) Explain RTL to GDS - II flow in detail. [4]
c) What is the operator inference? [2]

Q8) a) Explain the three phases of simulation of VHDL code. [5]

b) Explain the ASIC design flow in detail. [5]

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