Apple MacBook Pro M1 A2338 - 820-02020 Schematic Diagram

T668 MLB
PAGE CSA CONTENTS SYNC DATE PAGE CSA CONTENTS SYNC DATE
1 1 TABLE OF CONTENTS 61 158 USB-C: SUPPORT T585_REF_USBC_ACE2_0.23.0
2 2 REFERENCE DESIGN SYNC TABLES T668_MLB 07/17/2019 62 200 WIFI/BT: MODULE REF_WIRELESS_RASPUTIN 02/01/2020
3 4 PD PARTS T668_KSAITO_MLB_0.11.1 63 201 WIFI/BT: ANTENNA and GND REF_WIRELESS_RASPUTIN 02/01/2020
4 5 SOC: Support T585_REF_SOC_H13G_0.56.0 64 220 STORAGE: SSD0 S5E <0> REF_STORAGE_S5E 04/27/2020
5 6 SOC: CIO, USB, RESETS, CLOCKS, SWD AITKEN_T668_MLB 10/08/2019 65 221 STORAGE: SSD0 S5E <1> REF_STORAGE_S5E 04/27/2020
6 7 SOC: AP I/Os T585_REF_SOC_H13G_0.56.0 66 224 STORAGE: NON OCARINA SUPPORT REF_STORAGE_NON_OCARINA_SUPPORT

02/25/2020
7 8 SOC: LPDP & MIPI AITKEN_T668_MLB 10/08/2019 67 230 STORAGE: SSD SUPPORT WUDI_T668_MLB 01/28/2020
8 9 SOC: PCIE ANDREW_T668_MLB 10/09/2019 68 231 SECDIS: MIPI MUX T585_REF_SECDIS_MIPIMUX_0.7.0
9 10 SOC: AOP T585_REF_SOC_H13G_0.56.0 69 236 DISPLAY: CONNECTOR, PWR AITKEN_T668_MLB 10/02/2019
10 11 SOC: POWER (DDR,SRAM) T585_REF_SOC_H13G_0.56.0 70 237 DISPLAY POWER SEQUENCER REF_PANELPWR_BNJ 04/22/2020
11 12 SOC: POWER (IO) T585_REF_SOC_H13G_0.56.0 71 238 BEN: CONTROLLER REF_BLC_BEN 11/21/2019
12 13 SOC: POWER (SOC, CPU, GPU) T585_REF_SOC_H13G_0.56.0 72 239 BEN: KEYBOARD REF_BLC_BEN 11/21/2019
13 14 SOC: POWER (SRAM) T585_REF_SOC_H13G_0.56.0 73 242 SECDIS: AMR T585_REF_SECDIS_AMR_0.9.0
14 15 SOC: POWER (Fixed, PLL's, Filtered) T585_REF_SOC_H13G_0.56.0 74 243 SECDIS: FPGA REF_SECDIS_SAK 04/22/2020
15 16 SOC: GND 7
7 T585_REF_SOC_H13G_0.56.0 75 244 AUDIO SUPPORT REF_SPKRAMP_TAS5770 04/16/2020
16 17 SOC: GND-2 T585_REF_SOC_H13G_0.56.0 76 245 AUDIO JACK CODEC REF_CODEC_CLIFDEN 04/13/2020
17 19 SPI NOR REF_SOC_H13G 01/27/2020 77 246 AUDIO AMPLIFIERS (1/2) REF_SPKRAMP_TAS5770 04/16/2020
18 21 PROJECT SUPPORT (1/2) AITKEN_T668_MLB 09/18/2019 78 247 AUDIO AMPLIFIERS (2/2) REF_SPKRAMP_TAS5770 04/16/2020
19 22 PROJECT SUPPORT (2/2) AITKEN_T668_MLB 11/11/2019 79 248 AUDIO CONNECTORS: AMPS KELVIN_T668_MLB 09/18/2019
20 50 Secure Element REF_SE_CERES 02/26/2020 80 249 AUDIO CONNECTORS: DMIC, JACK KELVIN_T668_MLB 09/24/2019
21 51 BATTERY CONNECTORS AITKEN_T668_MLB 09/18/2019 81 250 KEYBOARD BLC CONNECTORS T668_MLB 05/16/2019
22 52 PBUS SUPPLY & BATTERY CHARGER REF_CHARGER_SUONA 02/25/2020 82 251 KEYBOARD IOX, SUPPORT REF_KBD_SUPPORT 02/01/2020
23 53 BATTERY CHARGER SUPPORT REF_CHARGER_SUONA 04/01/2020 83 252 KEYBOARD SIGNAL CONNECTOR, ESD WUDI_T668_MLB 01/28/2020
24 57 POWER: 3V8 AON (1/2) REF_VR_ICEMAN 04/09/2020 84 253 TRACKPAD SUPPORT WUDI_T668_MLB 04/16/2020
25 58 POWER: 3V8 AON (2/2) REF_VR_ICEMAN 03/30/2020 85 254 TRACKPAD CONNECTOR WUDI_T668_MLB 04/16/2020
26 59 POWER: 3V8 AON SUPPORT T585_REF_VR_ICEMAN_0.36.0 86 256 TOUCHID SUPPORT T585_REF_MESA_SUPPORT_0.11.0
27 77 PMU: SLAVE INPUT PWR & BUCKS KEI_T668_MLB 04/07/2020 87 257 DFR SUPPORT 1 T585_REF_DFR_V3_SUPPORT_0.25.0
28 78 PMU: SLAVE LDO 88 258 DFR SUPPORT 2

www.teknisi-indonesia.com
KEI_T668_MLB 04/07/2020 T585_REF_DFR_V3_SUPPORT_0.25.0
29 79 PMU: SLAVE GPIO & GND KEI_T668_MLB 04/07/2020 89 266 FCT KELVIN_T668_MLB 01/29/2020
30 80 PMU: SLAVE SUPPORT KEI_T668_MLB 01/27/2020 90 270 DEBUG: BUTTONS T668_MLB 06/20/2019
31 81 PMU: MASTER INPUT PWR & BUCKS KEI_T668_MLB 04/02/2020 91 271 DEBUG: MISC T668_MLB 06/20/2019
32 82 PMU: MASTER BUCKS & GND KEI_T668_MLB 04/26/2020 92 278 DEBUG: LEDS (1/3) T668_MLB 07/24/2019
33 83 PMU: MASTER LDO & GPIO KEI_T668_MLB 04/23/2020 93 279 DEBUG: LEDS (2/3) T668_MLB 07/24/2019
34 84 PMU: MASTER SUPPORT KEI_T668_MLB 04/16/2020 94 280 DEBUG: LEDS (3/3) T668_MLB 07/24/2019
35 121 POWER: EXTERNAL LDO KEI_T668_MLB 09/23/2019 95 282 DEBUG: P3V8AON ISENSE T668_MLB 06/20/2019
36 123 POWER: 5V S2 REF_VR_5V_TPS62135 04/16/2020 96 294 DEBUG: VITAMIN-C MANAN_T668_MLB 02/03/2020
37 124 POWER: 5V S2 SUPPORT T668_MLB 03/26/2020 97 300 DESENSE (1/3) KEI_T668_MLB 11/04/2019
38 127 POWER: 3V3 S2 REF_VR_3V3_TPS62135 01/09/2020 98 301 DESENSE (2/3) KEI_T668_MLB 09/30/2019
39 128 POWER: FETS KEI_T668_MLB 09/10/2019 99 302 DESENSE (3/3) KEI_T668_MLB 09/30/2019
40 129 POWER: SUPPORT KEI_T668_MLB 09/10/2019 100 310 EMC KEI_T668_MLB 10/02/2019
41 130 I2C: SIO, DISP T668_MLB 06/20/2019 101 400 POWER ALIASES 1 KEI_T668_MLB 11/06/2019
42 131 I2C: ISP, AOP T668_MLB 06/20/2019 102 401 POWER ALIASES 2 KEI_T668_MLB 11/06/2019
43 132 I2C: SMC KEI_T668_MLB 12/20/2019 103 402 POWER ALIASES 3 T668_MLB 06/05/2019
44 135 SENSORS: POWER HIGH SIDE (1/2) KEI_T668_MLB 04/04/2020 104 403 POWER ALIASES 4 KEI_T668_MLB 11/06/2019
45 136 SENSORS: POWER HIGH SIDE (2/2) KEI_T668_MLB 03/10/2020 105 404 POWER ALIASES 5 KEI_T668_MLB 09/12/2019
46 138 SENSORS: POWER LOW SIDE (1/2) KEI_T668_MLB 03/10/2020 106 405 SIGNAL ALIASES 1 AITKEN_T668_MLB 09/18/20 9
47 139 SENSORS: POWER LOW SIDE (2/2) KEI_T668_MLB 01/23/2020 107 406 SIGNAL ALIASES 2 T668_MLB 05/29/2019
48 140 SENSORS: POWER SUPPORT KEI_T668_MLB 02/04/2020 108 500 17.2 RULES T668_MLB 05/13/2019
49 141 SENSORS: THERMAL (1/2) KEI_T668_MLB 04/02/2020 109 501 17.2 PHYSICAL CSETS T668_MLB 05/13/2019
50 142 SENSORS: THERMAL (2/2) KEI_T668_MLB 01/23/2020 110 502 17.2 SPACING CSETS, ISO T668_MLB 05/13/2019
51 144 SENSORS: MOTION WUDI_T668_MLB 09/23/2019 111 503 17.2 SPACING CSETS, CLASS-CLASS T668_MLB 05/13/2019
52 145 FAN AITKEN_T668_MLB 09/18/2019 112 600 BOM VARIANT TABLES T668_MLB 06/05/2018
53 150 USB-C: High Speed ATC0 REF_USBC_ACE2 02/14/2020 113 601 BOM OPTION TABLES T668_MLB 06/05/2018
54 151 USB-C: High Speed ATC1 REF_USBC_ACE2 02/14/2020 114 602 T668_MLB 06/05/2018
55 152 USB-C: Support 1 ATC01 REF_USBC_ACE2 02/01/2020 115 610 BOM ALTERNATES T668_MLB 06/05/2018
56 153 USB-C: Support 2 ATC01 REF_USBC_ACE2 02/01/2020 116 700 T668_MLB 06/05/2018
57 154 USB-C: Port Controller ATC0 REF_USBC_ACE2 02/01/2020 117 999 CHECKPLUS SUPPORT T668_MLB 08/29/2019
58 155 USB-C: Port Controller ATC1 REF_USBC_ACE2 02/01/2020
59 156 USB-C: Connector(s) KEI_T668_MLB 02/01/2020
60 157 USB-C: HS Level Shifters REF_USBC_ACE2 02/04/2020

D REFERENCE DESIGNS J293 SYNCS FROM
HARD/
SOURCE PROJECT SUB-DESIGN NAME SUB-DESIGN PAGES VERSION SOFT SYNC_DATE/TIME
T585 REF_VR_ICEMAN 57,58 1.14.0 2020/04/27
T585 REF_CHARGER_SUONA 52,53 0.36.0 2020/04/27
T585 REF_STORAGE_NON_OCARINA_SUPPORT 224 0.5.0 2020/04/27
T585 245 1.6.0 2020/04/27
T585 REF_SPKRAMP_TAS5770 244,246,247 0.8.0 2020/04/27
T585 REF_VR_3V3_TPS62135 127 0.8.0 2020/04/27
T585 REF_VR_5V_LT8642S 123 0.13.0 2020/04/27
T585 REF_SECDIS_MIPIMUX 231 0.7.0 2020/04/27
T585 REF_DFR_V3_SUPPORT 257,258 0.25.0 2020/04/27
T585 REF_SE_CERES 50 0.13.0 2020/04/27
T585 REF_PANELPWR_BNJ 237 0.9.0 2020/04/27
REF_SECD S_ AK 243 40.0 2 20/04/27
T585 REF_STORAGE_S5E 220,221 0.34.0 2020/04/27
REFERENCE DESIGNS NO LONGER SYNCS FROM

HARD/
SOUR E PROJECT SUB-DES GN N ME SUB-DESIGN P G S VERSION SOFT YNC_DATE/TIME
T585 REF_SOC_H13G 5-17,19 <-- WE STOPPED SYNCING SOC AT 0.56.0 DUE TO REF DESIGN DESENSE CAP ADDITIONS CONFLICTING WITH DESENSE TEAM'S REQUESTS FOR J293
T585 REF_PMU_SERA_SIMETRA 77-79,81-83 <-- WE STOPPED SYNCING PMU AT 0.57.0 DUE TO SLOW UPDATES AND REF DESIGN IS OFF GRID
T585 REF_BLC_BEN 238,239 <-- WE STOPPED SYNCING BLC AT 0.16.0 TO RELAX PLACE NEARS
T585 REF DEBUG_STUFF 294 <-- WE STOPPED SYNCING VITAMIN C AT 0.1.0 SINCE THE REF DESIGN IS INCOMPLETE ND MANY CHANGES ARE NEEDED TO SUPPORT VIT C MK II
T585 REF_SECDIS_AMR 242 <-- WE STOPPED SYNCING AMR REF SINCE THE REF HAS A DIFFERENT APN FOR AMR FOOTPRINT THAN PD USES IN J293'S MCO
T 85 REF_USBC_ACE2
150-155,157 <-- WE STOPPED SYNCING USB AT 0.31.0 AS THE 50V CC CAPS WHICH ARE 2.8X MORE EXPENSIVE THAN THE 25V ONES, ALSO LSF0 02 COMBO ADDED
T585 REF_WIRELESS_ ASPUTIN 200-201 <-- WE STOPPED SYNCING RASPUTIN TO ADD RF CONN BOM OPT ON, CHANGE 100M CLK TPS TO PPS, AND FIX OVERLAPPING IPU TEXT NOTES
T585 REF_MESA_SUPPORT 256 <-- WE STOPPED SYNCING MESA SUPPORT AT 0.11.0 SINCE THE REF DESIGN REMOVED A PULL UP AND WE NEED 1V85 ON THE LDO
T585 REF_KBD_SUPPORT 251 <-- WE STOPPED SYNCING KBD AT 0.25.0 TO FIX CREF GENERATION ERROR ON PIN Y8
REFERENCE DESIGNS WHERE NET NUDGE WAS NEEDED TO REMOVE CREFER ERRORS B
S5E, USBC, SECDIS SAK
SYNC_MASTER T668_MLB
PAGE TITLE
SYNC_DA E=07/17/2019 A
REFERENCE DESIGN SYNC TABLES
8 7 6 5 4 3
4 3 2
TOP SIDE STANDOFFS USB-C BOSS TRACKPAD BOSS DISPLAY BOSS SHIELD CAN ALIGNMENT HOLES
ALLOW_APPLE_PREFIX=Z ALLOW_APPLE_PREFIX=Z ALLOW_APPLE_PREFIX=Z ALLOW_APPLE_PREFIX=Z OMIT
ALLOW_APPLE_PREFIX=Z
Z0400 CRITICAL CRITICAL CRITICAL
2.8OD1.2ID-1.49H-SM Z0420 Z0440 Z0450 Z04A0
TH-NSP
3.4OD1.75ID-1.12H-SM 3.5OD1.85ID-1.41H-SM 2.7X1.8R-1.4ID-0.84H-SM
860-01216 998-04440
860-00392 860-00381 SL-1.2X0.4-1.5X0.7
CRITICAL
OMIT
CRITICAL
CRITICAL
CRITICAL Z04A1 D
Z0401 Z0421 Z0441 Z0451
TH-NSP
2.8OD1.2ID-1.49H-SM
3.4OD1.75ID-1.12H-SM 3.5OD1.85ID-1.41H-SM 2.7X1.8R-1.4ID-0.84H-SM SL-1.2X0.4-1.5X0.7
998-04440
860-01216 860-00392 860-00381 OMIT
CRITICAL
Z04A2
TH-NSP
Z0402 998-04440
2.8OD1.2ID-1.49H-SM DFR BOSS FAN MTG HOLE 2.0X2.6 MM
SL-1.2X0.4-1.5X0.7
CPU THERM STAGE HOLE 3.15 MM OMIT OMIT
OMIT
860-01216 CRITICAL
CRITICAL
ALLOW_APPLE_PREFIX=ZT
CRITICAL
Z04A3
CRITICAL
Z0430 ZT0400 ZT0430 TH-NSP
3.4OD1.75ID-1.5H-SM TH-NSP
3P9R3P15
998-0845 1 998-04440
ALLOW_APPLE_PREFIX=Z 860-01484 SL-2.6X2.0-4.7X4.1
SL-1.2X0.4-1.5X0.7
Z0403 CORNER NEAREST KEYBOARD

OMIT
2.8OD1.2ID-1.49H-SM ALLOW_APPLE_PREFIX=Z
Z04A4
860-01216 TH-NSP
CRITICAL
MLB MTG HOLES 2.1X3.51 MM 998-04440
CPU THERM STAGE HOLES 3.6 MM OMIT SL-1.2X0.4-1.5X0.7
BOTTOM SIDE STANDOFFS OMIT
CRITICAL OMIT
CRITICAL ZT0420 ALLOW_APPLE_PREFIX=Z
Z0404 ALLOW_APPLE_PREFIX=Z
ZT0401 TH-NSP
2.8OD1.2ID-1.49H-SM Z0410 4.0R3.6-NSP 1 Z04A5
TH-NSP
2.8OD1.2ID-3.15H-SM 998-03850 SL-2.1X3.51-4.6X6.01
998-04440
860-01216 860-01485 OMIT SL-1.2X0.4-1.5X0.7 C
CRITICAL OMIT
CRITICAL
CRITICAL ZT0421
CRITICAL ZT0402 TH-NSP
4.0R3.6-NSP 1
Z0405 ALLOW_APPLE_PREFIX=Z 998-03850 SL-2.1X3.51-4.6X6.01
2.8OD1.2ID-1.49H-SM
Z0411 OMIT POGO PINS
2.8OD1.2ID-3.15H-SM
860-01216 ALLOW_APPLE_PREFIX=ZT
CRITICAL
CRITICAL
860-01485 ZT0422
TH-NSP
ALLOW_APPLE_PREFIX=PP
1 PP0400
POGO-2.3OD-4.0H-SM
CRITICAL
CPU THERM STAGE HOLE OVAL SL-2.1X3.51-4.6X6.01 SM-1
ALLOW_APPLE_PREFIX=Z www.teknisi-indonesia.com
OMIT 870-09667
DFR WASHER Z0412 CRITICAL
2.8OD1.2ID-3.15H-SM ZT0403
TH-NSP
CRITICAL
860-01485 998-21974 ALLOW_APPLE_PREFIX=PP
Z0431
SL-3.65X3.15-4.5X4.0
WIFI WASHER PP0401
4.75OD2.73ID-H0.2 POGO-2.3OD-4.0H-SM
RING-TH CRITICAL ALLOW_APPLE_PREFIX=Z SM-1
CRITICAL
860-01519 ALLOW_APPLE_PREFIX=Z
Z0432
4.75OD2.73ID-H0.2
870-09667
Z0413 RING-TH
2.8OD1.2ID-3.15H-SM WIFI COAX STANDOFF
860-01485 CRITICAL
PP0402
Z0498
5.25X2.8R-1.4ID-1.5H-SM POGO-2.3OD-4.0H-SM
SM-1
B
CRITICAL
860-01704 870-09667
AJ FLEX COWLING BOSS

CRITICAL PP0403
POGO-2.3OD-4.0H-SM
Z0470 SM-1
3.5OD1.85ID-1.92H-SM
870-09667
FENCE SPMU
PART NUMBER DESCRIPTION REFERENCE DES CRITICAL
806-24457 FENCE,SPMU,X1727 FENCE_SPMU CRITICAL FENCE_SPMU_C770 LANDING CLIP
806-24550 FENCE,SPMU,SUS,SBP,X1727 FENCE_SPMU CRITICAL FENCE_SPMU_SUS PART NUMBER DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
PAGE TITLE
A
806-25216 CLIP,LAND NG,MLB,X1727 CLIP CRITICAL CL P:YES
FENCE COMBO PD PARTS
PART NUMBER DESCRIPTION REFERENCE DES CRITICAL LANDING CLIP SMALL
806-24549 FENCE,COMBO,X1727 FENCE_COMBO CRITICAL FENCE_COMBO PART NUMBER DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
806-25217 CLIP,LANDING,SMALL,MLB,X1727 CLIP_SMALL CRITICAL CLIP_SMALL:YES
FENCE USBC
PART NUMBER DESCRIPTION REFERENCE DES CRITICAL METAL SLED
806-24455 FENCE,BURNSIDE BRIDGE,X1727 FENCE_USBC CRITICAL FENCE_USBC_C770 PART NUMBER DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
806-24548 FENCE,BURNSIDE BRIDGE,SUS,SBP,X1727 FENCE_USBC CRITICAL FENCE_USBC_SUS 806-24419 SLED,METAL,X1727 SLED1,SLED2 CRITICAL SLED:YES
BOM_COST_GROUP=MECHANICALS
4 3
BOOT CONFIG ID
102 11 8 6 5 4 PP1V25_AWAKE_IO
BOOT_CONFIG2 BOOT_CONFIG1 BOOT_CONFIG0
1 1 1
R0502 R0501 R0500
4.7K 4.7K 4.7K
5% 5% 5%
1/20W 1/20W 1/20W
MF MF MF
2 201 2 201 2 20
R0533
SPI_DFR_MISO 1
10K 2 SOC_JTAG_SEL
88 6 OUT OUT 9 18
18 6 OUT SPI_DFR_MOSI_R 5%
1/20W
18 6 OUT SPI_DFR_CLK_R MF
201
R0534
10K SOC_TESTMODE
BOOT_CFG[2:0] 1 2 OUT 5
MODE 5%
000 SPI1 NOR (12 MHZ) 1/20W
MF
S/W READ FLOW
001 SPI1 NOR (12 MHZ) TESTMODE 201
010 SPI0 NAND 1. SET GPIO AS INPUT R0535
011 SPI0 NAND TESTMODE 2. DISABLE PU AND ENABLE PD
1
10K 2 SOC_HOLD_RESET
OUT 5
POR ---> 100 SPI1 NOR (40 MHZ) 3. READ
5%
101 SPI1 NOR (40 MHZ) TESTMODE 1/20W
MF
110 SPI1 NOR (6 MHZ) 201
111 SPI1 NOR (6MHZ) TESTMODE R0536
1
10K 2 SOC_KIS_DFU_SELECT OUT 5
5%
1/20W
MF
201
BOARD ID
2 11 8 6 5 4 PP1V25_AWAKE_IO
BOARDID4 BOARDID3 BOARDID2 BOARDID1 BOARDID0
1 1 1 1 1
R0514 R0513 R0512 R0511 R0510
1K 1K 1K 1K 1K
5% 5% 5% 5% 5%
1/20W
MF
2 201
1/20W
MF
2 201
1/20W
MF
2 201
1/20W
MF
2 201
1/20W
MF
2 201
SEP EEPROM (128-Kbit)
(Write: 0xA2, Read 0xA3)
A1 PER <RDAR://590 9073>
6 OUT BOARD_ID4
6 OUT BOARD_ID3 PP1V8_AWAKE
6 BOARD_ID2
OUT
BOARD_ID1 PP1V25_AWAKE_IO
1 C0500
6 OUT 1.0UF
6 OUT BOARD_ID0 20%
2 4V
X6S
1 1 0201
R0540 R0541
2.2K 2.2K VCC
BOARD_ID[7:0] IS 8 TOTAL BITS 5% 5%
1/20W 1/20W
BOARD_ID[7:5] ARE SET INSIDE THE SOC MF MF U0500
BOARD_ID[4:0] ARE SET WITH THESE RESISTORS 2 201 2 201 STOCT
DFN
BOARD_ID[0] IS 0 FOR FORM FACTOR AND 1 FOR DEV PLATFORM
I2C_SEEPROM_SCL 7 SCL VIO 5
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BOARD_ID[7:0] FOR J293 IS 0B00100100 6
<RDAR://53744986>
6 I2C_SEEPROM_SDA 6 SDA 2
NC
3
NC NC
4
S/W READ FLOW NC
VSS EPAD
1. SET GPIO AS INPUT
2. DISABLE PU AND ENABLE PD
3. READ
BOARD REVISION NOTE: STUFFING RESISTOR MEANS 0

6 OUT BOARD_REV0
OUT BOARD_REV1
6 OUT BOARD_REV2
6 OUT BOARD_REV3
BOARD_REV3 BOARD_REV2 BOARD_REV1 BOARD_REV0
1 1 1 1
R0523 R0522 R0521 R0520
1K 1K 1K 1K
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
2 201 2 201 2 201 2 201
board rev should start at 0b0000 and increment each rev.

S/W READ FLOW
1. SET GPIO AS INPUT

2. ENABLE PU AND DISABLE PD
3. READ
J293 BOARD_REV [3:0] = 0000 : PRE P1

0001 : P1 A0
0010 : P1 A1
0011 : P1 A1 AUDIO PAGE TITLE
0100 : P2 SOC: Support

0101 : EVT
BOM_COST_GROUP=SOC
8 7 3
SOC: CIO, USB, DRAM, RESETS, CLOCKS, SWD, FPWM
OMIT_TABLE
U0600
TMLR68A0-B09
BGA
SYM 1 OF 23
100 90 89 74 33 9 IN PMU_RESET_L R2 LP4_IN_RESET_N
90 89 56 33 5 IN SOC_FORCE_DFU AA49 FORCE_DFU DFU_STATUS V51 SOC_DFU_STATUS OUT 19 56 89 94
19 5 SOC_REQUEST_DFU1 AK55 REQUEST_DFU1

5 SOC_REQUEST_DFU2 AJ54 REQUEST_DFU2
RESET
4 IN SOC_TESTMODE AD TESTMODE IPD
89 55 33 IN PMU_ACTIVE_READY AL54 CFSB
4 IN SOC_HOLD_RESET AC1 HOLD_RESET IPD

AMUX_OUT can go to TP or to AMUX_IN on PMU
4 IN SOC_KIS_DFU_SELECT AB49 KIS_DFU_SELECT
18 BI EUSB_ATC0_P BB54 ATC0_USB_EDP

18 BI EUSB_ATC0_N BB55 ATC0_USB_EDM
60 IN CIO_ATC0_LSRX_1V2 BE18 USB_C0_LSRX CLOCKS XI0 BE36 SOC_XTAL24M_IN

60 OUT CIO_ATC0_LSTX_1V2 BE13 USB_C0_LSTX XO0 BF36 SOC_XTAL24M_OUT
5 SOC_ATC0_USB_RESREF BB53 ATC0_USB_RESREF TST_CLKOUT P54 TP_TST_CLKOUT 18
107 NC_ATC0_HPD V48 USB_C0_HPD/TMU_CLK_OUT0 ANALOGMUX_OUT AL48 TP_SOC_AMUX_OUT OUT 18 106 R0651 1
99
1% CRITICAL
18 BI EUSB_ATC1_P BC54 ATC1_USB_EDP 1/20
18 BI EUSB_ATC1_N BC55 ATC1_USB_EDM SWD_TCK_OUT1 AJ1 SWD_NAND0_SWCLK OUT 67 107
MF
201 2 Y0600
1.60X1.20MM
SWD_TMS2 U54 SWD_NAND0_SWDIO BI 67 10 24.000MHZ-20PPM-9.5PF-60OHM
SWD
60 IN CIO_ATC1_LSRX_1V2 BD3 USB_C1_LSRX SWD_TMS3 V54 NC_SWD_TMS3 106 OC_24M_O_R 1 3
60 OUT CIO_ATC1_LSTX_1V2 BE10 USB_C1_LSTX SWD_TMS4 AH3 TP_SWD_TMS4 CRITICAL 2 4
CRITICAL
1 C0650 1 C0651
5 SOC_ATC1_USB_RESREF BC53 ATC1_USB_RESREF IPD 15PF 15PF
SOC_ATCPHY0_RCAL_POS 5% 5%
FPWM0/MASTER_SYNC_GEN_0 V50 WLAN_TIME_SYNC IN 62 2 50V
C0G 2 50V
C0G
1 107 NC_ATC1_HPD R48 USB_C1_HPD/TMU_CLK_OUT1 FPW FPWM1 Y49 KBD_BKLT_PWM OUT 72
0201 0201
R0600 FPWM2 U50 TP_FPWM2
200 USB_VBUS_DETECT AG1
1% 5 EUSB_VBUS_DETECT
1/20W
MF
2 201
SOC_ATCPHY0_RCAL_ EG
53 BI USBC_ATC0_D2R_P<1> GND_VOID=TRUE BE50 ATCPHY0_RX0_P
1 C0600 53 BI USBC_ATC0_D2R_N<1> GND_VOID=TRUE BF50 ATCPHY0_RX0_N
10PF 53 OUT USBC_ATC0_R2D_C_P<1> GND_VOID=TRUE BC49 ATCPHY0_TX0_P
5% ATC
2 25V
C0G 53 OUT USBC_ATC0_R2D_C_N<1> GND_VOID=TRUE BD49 ATCPHY0_TX0_N
0201
53 BI USBC_ATC0_D2R_P<2> GND_VOID=TRUE BE48 ATCPHY0_RX1_P

53 BI USBC_ATC0_D2R_N<2> GND_VOID=TRUE BF48 ATCPHY0_RX1_N
SOC_ATCPHY1_RCAL_POS 53 OUT USBC_ATC0_R2D_C_P<2> GND_VOID=TRUE BC47 ATCPHY0_TX1_P
102 11 8 6 5 4 PP1V25_AWAKE_IO
53 OUT USBC_ATC0_R2D_C_N<2> GND_VOID=TRUE BD47 ATCPHY0_TX1_N
1
R0601
200 53 BI USBC_ATC0_AUX_P AY51 ATCPHY0_AUX_P 1
R0630 1
R0631
1%
1/20W 53 BI USBC_ATC0_AUX_N AY52 ATCPHY0_AUX_N 10K 10K
MF 5% 5%
2 201 1/20W
MF
1/20W
MF
SOC_ATCPHY1_RCAL_NEG 5 SOC_ATCPHY0_RCAL_POS BE52 ATCPHY0_RCAL_P 2 201 2 201
5 SOC_ATCPHY0_RCAL_NEG BF52 ATCPHY0_RCAL_N
1 C0601 19 5 SOC_REQUEST_DFU1 5 SOC_REQUEST_DFU2 90 89 56 33 5 SOC_FORCE_DFU
10PF
5% 54 BI USBC_ATC1_D2R_P<1> GND_VOID=TRUE BF44 ATCPHY1_RX0_P
2 25V
C0G
0201 54 BI USBC_ATC1_D2R_N<1> GND_VOID=TRUE BE44 ATCPHY1_RX0_N 1
54 OUT USBC_ATC1_R2D_C_P<1> GND_VOID=TRUE BD43 ATCPHY1_TX0_P R0632
USBC_ATC1_R2D_C_N<1> BC43 47K
54 OUT GND_VOID=TRUE ATCPHY1_TX0_N 5%
1/20W
MF
54 USBC_ATC1_D2R_P<2> GND_VOID=TRUE BF46 ATCPHY1_RX1_P 2 201
BI
54 BI USBC_ATC1_D2R_N<2> GND_VOID=TRUE BE46 ATCPHY1_RX1_N
54 OUT USBC_ATC1_R2D_C_P<2> GND_VOID=TRUE BD45 ATCPHY1_TX1_P
54 OUT USBC_ATC1_R2D_C_N<2> GND_VOID=TRUE BC45 ATCPHY1_TX1_N
54 BI USBC_ATC1_AUX_P BA52 ATCPHY1_AUX_P

54 BI USBC_ATC1_AUX_N BA51 ATCPHY1_AUX_N
5 SOC_ATC0_USB_RESREF 5 SOC_ATC1_USB_RESREF
5 SOC_ATCPHY1_RCAL_POS BF4 ATCPHY1_RCAL_P
5 SOC_ATCPHY1_RCAL_NEG BE4 ATCPHY1_RCAL_N R0641 1
R0640
200 200
1% 1%
1/20W 1/20W
MF MF
102 11 8 6 5 4 PP1V25_AWAKE_IO 2 201 2 201
1
R0639
0
5%
1/20W
MF
2 0201
SYNC_MASTER=AITKEN_T6 8_MLB
PAGE TITLE
SYNC_DATE=10/08/2019 A
SOC: CIO, USB, RESETS, CLOCKS, SWD
5 USB_VBUS_DETECT
AB E_ LT_HE D
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
AB E_ LT_IT M
197S0590 197S0591 Y0600 EPSON,24MHZ.XTAL

AB E_ LT_IT M
197S0588 197S0591 Y0600 TXC,24MHZ,XTAL
BOM_COST_GROUP=SOC
6 5 4 3
**OK2INTEGRATE**
all signals are 1.2 unless otherwise specified.
all signals on this page reference PP1V2_AWAKE_GRP if they are 1.2V
if they are 1.8V they reference PP1V8_AWAKE_GRP SOC: I/Os
U0600
TMLR68A0-B09
BGA
SYM 3 OF 23
18 UT TDM_SPKRAMP_L_BCLK_R AK4 I2S0_BCLK IPD SPI0_MISO AL4 SPI_DFR_MISO IN 4
18 IN TDM_SPKRAMP_L_D2R AJ3 I2S0_DIN IPD SPI0_MOSI AK2 SPI_DFR_MOSI_R OUT 4
18 OUT TDM_SPKRAMP_L_R2D_R AJ5 I2S0_DOUT SPI0_SCLK AK1 SPI_DFR_CLK_R OUT 4
18 OUT TDM_SPKRAMP_L_FSYNC_R AJ4 I2S0_LRCK

106 NC_SOC_I2S0_MCK AK3 I2S0_MCK IPD SPI1_MISO AD4 SPI_SOCROM_MISO IN 17
SPI1_MOSI AE4 SPI_SOCROM_MOSI_R 17

OUT
18 OUT TDM_SPKRAMP_R_BCLK_R AG3 I2S1_BCLK SPI1_SCLK AF4 SPI_SOCROM_CLK_R OUT 17
1 IN TDM_SPKRAMP_R_D2R AF3 I2S1_DIN IPD SPI1_SSIN AE3 SPI_SOCROM_CS_L OUT 17
1 OUT TDM_SPKRAMP_R_R2D_R AG4 I2S1_DOUT

I2S SPI
18 OUT TDM_SPKRAMP_R_FSYNC_R AF2 I2S1_LRCK IPD SPI2_MISO AF53 SPI_TOUCHID_MISO IN 80
6 NC_SOC_I2S1_MCK AG2 I2S1_MCK SPI2_MOSI AF54 SPI_TOUCHID_MOSI_R OUT 18

AF55 SPI_TOUCHID_CLK_R 1.8V IO
SPI2_SCLK OUT 18
18 OUT TDM_CODEC_BCLK_R AK5 I2S2_BCLK SPI2_SSIN AF52 NC_SOC_SPI2_SSIN 106
76 IN TDM_CODEC_D2R AL6 I2S2_DIN IPD

18 OUT TDM_CODEC_R2D_R AJ7 I2S2_DOUT IPD SPI3_MISO Y1 SPI_IPD_MISO IN 84
18 OUT TDM_CODEC_FSYNC_R AM4 I2S2_LRCK SPI3_MOSI W1 SPI_IPD_MOSI_R OUT 18
TP_SOC_I2S2_MCK AK6 I2S2_MCK SPI3_SCLK AB1 SPI_IPD_CLK_R OUT 18
SPI3_SSIN AA1 SPI_IPD_CS_L 84

OUT
106 NC_I2S3_BCLK AH6 I2S3_BCLK
6 NC_I2S3_D2R AH4 I2S3_DIN IPD SPI4_MISO AC4 SPI_TCON_MISO IN 69
6 NC_I2S3_R2D AG5 I2S3_DOUT SPI4_MOSI AB4 SPI_TCON_MOSI_R OUT 69
106 NC_I2S3_LRCLK AJ6 I2S3_LRCK SPI4_SCLK AA4 SPI_TCON_CLK_R OUT 69
106 NC_I2S3_MCLK AF5 I2S3_MCK SPI4_SSIN AB3 SPI_TCON_CS_L OUT 69
41 OUT I2C_UPC_SCL W52 I2C0_SCL SGPIO0 AC3 DBL_CLICK_DET IN 33
1 BI I2C_UPC_SDA V52 I2C0_SDA SGPIO1 AC2 DISABLE_STROBE OUT 74
1 OUT I2C_SPKRAMP_L_SCL AA48 I2C1_SCL SI2C0_SCL Y5 I2C_SEEPROM_SCL OUT 4
41 BI I2C_SPKRAMP_L_SDA Y48 I2C1_SDA SEP SI2C0_SDA Y4 I2C_SEEPROM_SDA BI
41 OUT I2C_CODEC_SCL AB50 I2C2_SCL SSPI0_MISO AC5 FTCAM_DISABLE_L OUT 74
41 BI I2C_CODEC_SDA Y50 I2C2_SDA SSPI0_MOSI AD5 NC_SSPI0_MOSI 106
SSPI0_SCLK AD6 DMIC_DISABLE_L 74

OUT
41 OUT I2C_SPKRAMP_R_SCL AF6 I2C3_SCL
41 BI I2C_SPKRAMP_R_SDA AE6 I2C3_SDA
THROTTLE AK52
SOCHOT1 SOC_SOCHOT_L OUT 6 33 89 91 96 100
IPU FOR ALL
4 OUT I2C_DFR_SCL AF50 I2C4_SCL THROTTLE_TRIGGER
1.8V IO I2C_DFR_SDA AG49 AK53 BUCK1_THERMAL_THROTTLE_L PP1V25_AWAKE_IO
1 BI I2C4_SDA THROTTLE_TRIGGER0/MTR_ADC_DOUT IN 33 34 11 8 5 4
SPMI
THROTTLE_TRIGGER1/MTR_ADC_CLKOUT
THROTTLE_TRIGGER2/PLL_DIGOBS_0
AL53
AJ55 www.teknisi-indonesia.com
BUCK0_THERMAL_THROTTLE_L
SOC_THROTTLE_TRIGGER2
IN
IN
33 34
19
1
106 NC_SPMI2_CLK AK7 AP_SPMI2_SCLK THROTTLE_TRIGGER3/PLL_DIGOBS_1 AJ53 PMU_VDDHI_UVWARN_L IN 106
R0790
TP_SPMI2_DATA AL7 AJ49 PMU_VDDMAIN_UVWARN_L 47K
AP_SPMI2_SDATA THROTTLE_TRIGGER4 IN 33 34 5%
1/20W
MF
2 201
100 96 91 89 33 6 SOC_SOCHOT_L
U0600
TMLR68A0-B09
BGA
SYM 2 OF 23
107 IN UPC_I2C_INT_L AJ51 GPIO[0] IPU IPD UART0_RXD AB53 UART_DEBUGPRT_D2R IN 18 56 89
106 NC_SOC_GPIO01 AA50 GPIO[1] UART0_TXD AC53 UART_DEBUGPRT_R2D OUT 18 56 89
79 IN SPKR_ID0 V53 GPIO[2] IPU

UPC_FORCE_PWR will likely be 89
SPKR_ID1 U53 AC54 DFR_1V8_TOUCH_RESET_L
89 79 IN GPIO[3] IPU UART1_CTSN OUT 87 88 89
removed in the future SPKRAMP_RESET_L T53 AA53 DFR_1V8_DISP_RESET_L
107 OUT GPIO[4] UART1_RTSN OUT 87 88 89
SPKRAMP_INT_L W53 AA54 DFR_1V8_DISP_INT 1.8V IO

80 78 77 IN GPIO[5] IPU IPD UART1_RXD IN 87 8 89
76 IN CODEC_INT_L W50 GPIO[6] IPU IPD UART1_TXD AC55 BT_TIME_SYNC_1V8 IN 62 63
55 OUT SWD_UPC_SWCLK U52 GPIO[7]

106 NC_SOC_GPIO08 AC48 GPIO[8] IPU UART2_CTSN W55 UART_WLAN_D2R_CTS_L IN 62
TP_SOC_GPIO09 R53 GPIO[9] UART2_RTSN Y54 UART_WLAN_R2D_RTS_L OUT 62 s UART2 if your wireless module is 1.2V IO
TP_SOC_GPIO10 R52 GPIO[10] IPU UART2_RXD Y53 UART_WLAN_D2R IN 62
4 IN BOARD_REV0 N55 GPIO[11] UART2_TXD Y55 UART_WLAN_R2D OUT 62
4 IN BOARD_REV1 AH54 GPIO[12]

4 IN BOARD_REV2 Y52 GPIO[13] UART3_CTSN AC51 NC_UART3_D2R_CTS_L 106
TOUCHID_PWR_EN gets BOARD_REV3 AA51 AC52 NC_UART3_R2D_RTS_L
4 IN GPIO[14] UART3_RTSN 106
pulled up to S2 on NC_SOC_GPIO15 R54 AF48 NC_UART3_D2R
106 GPIO[15] GPIO UART UART3_RXD 106
TOUCHID page NC_SOC_GPIO16 AC50 AB52 NC_UART3_R2D
106 GPIO[16] UART3_TXD 106
This is OK because SWD_UPC_SWDIO0 U51
55 BI GPIO[17]
the GPIO is failsafe TP_SWD_UPC_SWDIO1 AK50 AJ48 NC_UART4_D2R_CTS_L
1 6 BI GPIO[18] UART4_CTSN 106
IN DFR_TOUCH_INT_L T52 GPIO[19] UART4_RTSN AK48 NC_UART4_R2D_RTS_L 106
84 OUT IPD_SPI_EN V49 GPIO[20] UART4_RXD AL52 NC_UART4_D2R 106
86 IN TOUCHID_INT AJ52 GPIO[21] IPD UART4_TXD AL50 NC_UART4_R2D 106
94 86 OUT TOUCHID_PWR_EN AJ50 GPIO[22]

61 58 57 OUT UPC_FORCE_PWR AC49 GPIO[23] UART6_RXD AF51 UART_TCON_HDMI_D2R IN 69 89
PD needed on DFR PAGE 88 87

94 OUT DFR_PWR_EN R51 GPIO[24] UART6_TXD AG50 UART_TCON_HDMI_R2D OUT 69 89 1.8V IO R2D is for desktop only
106 88 OUT SPI_DFR CS_L AL49 GPIO[25]
106 IN NC_ENET_SYNC_1588 AF49 GPIO[26] IPD UART7_RXD AM2 NC_UART7_RXD 106
UART7_TXD AJ2 NC_UART7_TXD 106
67 65 64 6 NAND0_RESET_L PAGE TITLE

OARD ID NAND NOSTUFF
4 IN BOARD_ID0 W49 BOARD_ID0/SOC_DEBUG1 NAND_SYS_CLK0 AG52 NAND0_CLK24M_0_R OUT 67
1
R0791
SOC: AP I/Os
4 IN BOARD_ID1 R55 BOARD_ID1/SOC_DEBUG2 NAND_SYS_CLK1 AH53 NAND0_CLK24M_1_R OUT 67
BOARD_ID2 T55 47K

4 IN BOARD_ID2/SOC_DEBUG3 5%
1/20W
4 IN BOARD_ID3 V55 BOARD_ID3/SPI0_SSIN SSD_BFH AH51 NAND_BFH OUT 64 65 67 MF
4 BOARD_ID4 U55 BOARD_ID4 SSD_RESETN AG53 NAND0_RESET_L 6 64 65 67
2 201
IN OUT
BOM_COST_GROUP=SOC
**OK2INTEGRATE**
SOC: LPDP & MIPI
U0600 U0600
TMLR68A0-B09 TMLR68A0-B09
BGA BGA
SYM 4 OF 23 SYM 5 OF 23
GND_VOID=TRUE
106 NC_LPDPRX_AUX0 AP7 LPDPRX_AUX_D0_P LPDP_TX0P AR55 LPDP_INT_DATA_C_P<0>
OUT 69 106 NC_ISP_I2C0_SCL Y2 ISP_I2C0_SCL/ISP_GPIO_8 MIPI0C_DPCLK L15 NC_MIPI0C_CLK_POS 106
106 NC_LPDPRX_AUX1 AR7 LPDPRX_AUX_ _P LPDP_TX0N AR54 LPDP_INT_DATA_C_N<0>

OUT 69 106 NC_ISP_I2C0_SDA Y3 ISP_I2C0_SDA/ISP_GPIO_9 MIPI0C_ NCLK L14 NC_MIPI0C_CLK_NEG 106
106 NC_LPDPRX_AUX2 AT7 LPDPRX_AUX_D2_P GND_VOID=TRUE

1 6 NC_LPDPRX_AUX3 AV7 LPDPRX_AUX_D3_P LPDP_TX1P AT55 LPDP_INT_DATA_C_P<1>
OUT 69 106 NC_ISP_I2C1_SCL AA5 ISP_I2C1_SCL/ISP_GPIO_10 MIPI0C_DPDATA0 K15 NC_MIPI0C_DATA_0_POS 106
106 NC_LPDPRX_AUX4 AW7 LPDPRX_AUX_D4_P LPDP_TX1N AT54 LPDP_INT_DATA_C_N<1>

UT 69 106 NC_ISP_I2C1_SDA AA6 ISP_I2C1_SDA/ISP_GPIO_11 MIPI0C_DNDATA0 K14 NC_MIPI0C_DATA_0_NEG 106
1 6 NC_LPDPRX_AUX5 AY7 LPDPRX_AUX_D5_P GND_VOID=TRUE

106 NC_LPDPRX_AUX6 AP8 LPDPRX_AUX_D6_P LPDP_TX2P AU54 LPDP_INT_DATA_C_P<2>
OUT 69 42 OUT I2C_CAM_SCL AA3 ISP_I2C2_SCL MIPI0C_DPDATA1 M14 NC_MIPI0C_DATA_1_POS 106
106 NC_LPDPRX_AUX7 AR8 LPDPRX_AUX_D7_P LPDP_TX2N AU55 LPDP_INT_DATA_C_N<2>

OUT 69 42 BI I2C_CAM_SDA AA2 ISP_I2C2_SDA MIPI0C_DNDATA1 M15 NC_MIPI0C_DATA_1_NEG 106
106 NC_LPDPRX_AUX8 AT8 LPDPRX_AUX_D8_P GND_VOID=TRUE GND_VOID=TRUE

106 NC_LPDPRX_AUX9 AV8 LPDPRX_AUX_D9_P LPDP_TX3P AV55 LPDP_INT_DATA_C_P<3>
OUT 69 106 NC_ISP_I2C3_SCL AA7 ISP_I2C3_SCL MIPI1C_DPCLK L11 MIPI_FTCAM_CLK_P
IN 68
106 NC_LPDPRX_AUX10 AW8 LPDPRX_AUX_D10_P LPDP_TX3N AV54 LPDP_INT_DATA_C_N<3>

OUT 69 106 NC_ISP_I2C3_SDA
AB7 ISP_I2C3_SDA MIPI1C_DNCLK L12 MIPI_FTCAM_CLK_N
IN 68
GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE
106 NC_LPDPRX_AUX11 AY8 LPDPRX_AUX_ 1_P M12 MIPI_FTCAM_DATA_P<0>
AW55 NC_LPDP_TX4POS MIPI1C_DPDATA0 IN 68
LPDP_TX4P 06
M11 MIPI_FTCAM_DATA_N<0>
AW54 NC_LPDP_TX4NEG MIPI1C_DNDATA0 IN 68
LPDP_TX4N 06 106 OUT NC_FTCAM_RESET_L Y6 ISP_GPIO_0 GND_VOID=TRUE
107 NC_LPDPRX_RX_P_0 AP1 LPDPRX_RX_D0_P 106 NC_ISP_GPIO1
W6 ISP_GPIO_1 K11 NC_MIPI_FTCAM_DATA_POS1
MIPI1C_DPDATA1 IN 106
107 NC_LPDPRX_RX_N_0 AP2 LPDPRX_RX_D0_N LPDP_TX5P AY55 NC_LPDP_TX5POS 106 TP_ISP_GPIO2 Y7 ISP_GPIO_2 K12 NC_MIPI_FTCAM_DATA_NEG1
AY54 MIPI1C_DNDATA1 IN 106
LPDP_TX5N NC_LPDP_TX5NEG 106 TP_ISP_GPIO3 W7 ISP_GPIO_3
107 NC_LPDPRX_RX_P_1 AR1 LPDPRX_RX_D1_P
GND_VOID=TRUE
107 NC_LPDPRX_RX_N_1 AR2 LPDPRX_RX_D1_N LPDP_AUX_P AU52 LPDP_INT_AUX_C_P BI 69 106 NC_ISP_SPMI0_CLK AG7 ISP_SPMI0_SCLK/ISP_GPIO_5 K9
AU51 MIPID_DPCLK MIPI_DFR_CLK_P OUT 87
LPDP_AUX_N LPDP_INT_AUX_C_N BI 69 106 NC_ISP_SPMI0_DATA
AF7 ISP_SPMI0_SDATA/ISP_GPIO_4 K8
MIPID_DNCLK MIPI_DFR_CLK_N OUT 87
107 NC_LPDPRX_RX_P_2 AT1 LPDPRX_RX_D2_P GND_VOID=TRUE
GND_VOID=TRUE
10 NC_LPDPRX_RX_N_2 AT2 LPDPRX_RX_D N LPDP_RCAL_P AV52 SOC_LPDP_INT_RCAL_POS 7 10 NC_ISP_SPMI1_CLK AG6 ISP_SPMI1_SCLK/ISP_GPIO_7 L9
AV51 MIPID_DPDATA0 MIPI_DFR_DATA_P<0> OUT 87
LPDP_RCAL_N SOC_LPDP_INT_RCAL_NEG 106 NC_ISP_SPMI1_DATA
AH7 ISP_SPMI1_SDATA/ISP_GPIO_6 L8 MIPI_DFR_DATA_N<0>
MIPID_DNDATA0 OUT 87
107 NC_LPDPRX_RX_P_3 AV1 LPDPRX_RX_D3_P ISP SPMI GND_VOID=TRUE
107 NC_LPDPRX_RX_N_3 AV2 LPDPRX_RX_D3_N TP_SENSOR0_CLK AD1 SENSOR0_CLK
AG55 MIPI_D
DISP_HPD LPDP_INT_HPD IN 69 89 106 NC_SENSOR1_CLK
AE1 SENSOR1_CLK
107 NC_LPDPRX_RX_P_4 AW1 LPDPRX_RX_D4_P 106 NC_SENSOR2_CLK
AD3 SENSOR2_CLK
107 NC_LPDPRX_RX_N_4 AW2 LPDPRX_RX_D4_N DISP_POL AH55 NC_DISPLAY_POL 106 106 NC_SENSOR3_CLK
AF1 SENSOR3_CLK MIPI0C_REXT K17
MIPI1C_REXT L17 SOC_MIPI1C_REXT 7
107 NC_LPDPRX_RX_P_5 AY1 LPDPRX_RX_D5_P IPD DISP_SPI_MISO/DWI_CLK AC6 NC_SPI_DISP_BKLT_MISO 106 MIPID_REXT M9 SOC_MIPID_REXT 7
IN
107 NC_LPDPRX_RX_N_5 AY2 LPDPRX_RX_D5_N DISP_SPI_MOSI/DWI_DO AC7 NC_SPI_DISP_BKLT_MOSI_R 106
OUT
DISP_SPI_SCLK/DISP_I2C_SCL AD7 I2C_DISP_BKLT_SCL 41 1
OUT
107 NC_LPDPRX_RX_P_6 AP4 LPDPRX_RX_D6_P DISP_SPI_SSIN/DISP_I2C_SDA AB6 I2C_DISP_BKLT_SDA 41 106
BI
NC_LPDPRX_RX_N_6 AP5
107 LPDPRX_RX_D6_N
DISP_SPMI_SCLK W4 NC_DISP_SPMI_CLK 106
107 NC_LPDPRX_RX_P_7 AR4 LPDPRX_RX_D7_P DISP_SPMI_SDATA W3 NC_DISP_SPMI_DATA 106
107 NC_LPDPRX_RX_N_7 AR5 LPDPRX_RX_D7_N

DISP_FSYNC T49 NC_DISP_FSYNC 106
107 NC_LPDPRX_RX_P_8 AT4 LPDPRX_RX_D8_P

107 NC_LPDPRX_RX_N_8 AT5 LPDPRX_RX_D8_N DISP_LSYNC R50 NC_DISP_BKLT_LSYNC 106
OUT
10 NC_LPDPRX_RX_P_9 AV4 LPDPRX_RX_D P DISP_TOUCH_BSYNC0 T50 NC_DISP_TOUCH_BSYNC0 106
107 NC_LPDPRX_RX_N_9 AV5 LPDPRX_RX_D9_N DISP_TOUCH_BSYNC1 R49 NC_DISP_TOUCH_BSYNC1 06
DISP_TOUCH_EB U49 NC_DISP_TOUCH_EB 06
107 NC_LPDPRX_RX_P_10 AW4 LPDPRX_RX_D10_P

107 NC_LPDPRX_RX_N_10 AW5 LPDPRX_RX_D10_N DFR_BSYNC/DISP_INT AM5 NC_BKLT_FAULT_INT_L IN 106
107 NC_LPDPRX_RX_P_11 AY4 LPDPRX_RX_D11_P DFR_DISP_TE AL51 DFR_DISP_TE IN 88
107 NC_LPDPRX_RX_N_11 AY5 LPDPRX_RX_D11_N
19 LPDPRX0_RCAL_POS AU1 LPDPRX0_RCAL_P

19 LPDPRX0_RCAL_NEG AU2 LPDPRX0_RCAL N
19 LPDPRX1_RCAL_POS AU4 LPDPRX1_RCAL_P

7 SOC_MIPI1C_REXT
19 LPDPRX1_RCAL_NEG AU5 LPDPRX1_RCAL_N
7 SOC_MIPID_REXT
PLACE_NEAR=U0600.K17:6MM PLACE_NEAR=U0600.L17:6MM
PACK_OPTION=DFR PACK_OPTION=FTCAM
1 1
R0800 R0820
200 200
1% 1%
1/20W 1/20W
MF MF
2 201 2 201
7 SOC_LPDP_INT_RCAL_POS
1
R0895 SYNC_MASTER=AITKEN_T668_MLB
PAGE TITLE
SYNC_DATE=10/08/2019
200
1%
1/20W
MF
SOC: LPDP & MIPI
2 201
7 SOC_LPDP_INT_RCAL_NEG
1 C0895
10PF
5%
2 25V
C0G
0201
BOM_COST_GROUP=SOC
SOC: PCIE
U0600
PER PCISIG SPEC, AC COUPLING CAPS SHOULD BE BETWEEN TMLR68A0-B09
75 NF AND 265 NF FOR GEN1/2 AND BETWEEN BGA
SYM 6 OF 23
176 NF AND 265 NF FOR GEN 3/4
GND_VOID=TRUE GND_VOID=TRUE
64 IN PCIE_NAND0_D2R_P<0> BE26 ST_PCIE_RX0_P GP_PCIE_RX0_P BE30 PCIE_WLBT_D2R_P IN 62
64 IN PCIE_NAND0_D2R_N<0> BF26 ST_PCIE_RX0_N GP_PCIE_RX0_N BF30 PCIE_WLBT_D2R_N IN 62

64 OUT PCIE_NAND0_R2D_C_P<0> BC27 ST_PCIE_TX0_P GP_PC E_TX0_P BC31 PCIE_WLBT_R2D_C_P OUT 62
R0970 IS NEEDED DUE TO RDAR://53793006 64 OUT PCIE_NAND0_R2D_C_N<0> BD27 ST_PCIE_TX0_N GP_PCIE_ X0_N BD31 PCIE_WLBT_R2D_C_N OUT 62
67 64 OUT PCIE_CLK100M_NAND0_0_P BB37 ST_PCIE_REF_CLK0_P GP_PCIE_REF_CLK0 P BE40 PCIE_CLK100M_WLBT_P OUT 62
67 64 OUT PCIE_CLK100M_NAND0_0_N BC37 ST_PCIE_REF_CLK0_N GP_PCIE_REF_CLK0_N BF40 PCIE_CLK100M_WLBT_N OUT 62
102 11 6 5 4 PP1V25_AWAKE_IO 67 8 BI NAND0_CLKREQ0_L AH50 ST_PCIE_CLKREQ0_N GP_PCIE_CLKREQ0_N AB55 WLBT_CLKREQ_L BI 8 62 63
1 1 1 1
R0930 R0940 R0950 R0970 67
64 8 OUT NAND0_PCIE_RESET_L AH52 ST_PCIE_PERST0_N GP_PCIE_PERST0_N AA52 WLBT_RESET_L OUT 8 62 63
47K 47K 47K 47K 65
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
2 201 2 201 2 201 2 201
GND_VOID=TRUE
65 IN PCIE_NAND0_D2R_P<1> BE28 ST_PCIE_RX1_P GP_PCIE_RX1 P BE32 NC_PCIE_USBHC_D2R_POS IN 1 6
67 8 NAND0_CLKREQ1_L 65 IN PCIE_NAND0_D2R_N<1> BF28 ST_PCIE_RX1_N GP_PCIE_RX1_N BF32 NC_PCIE_USBHC_D2R_NEG IN 106

GND_VOID=TRUE
63 62 8 WLBT_CLKREQ_L GND_VOID=TRUE
67 8 NAND0_CLKREQ0_L 65 OUT PCIE_NAND0_R2D_C_P<1> BC29 ST_PCIE_TX1_P GP_PCIE_TX1_P BC33 NC_PCIE_USBHC_R2D_C_POS OUT 106
65 OUT PCIE_NAND0_R2D_C_N<1> BD29 ST_PCIE_TX1_N GP_PCIE_TX1_N BD33 NC_PCIE_USBHC_R2D_C_NEG OUT 106

GND_VOID=TRUE
8 USBHC_CLKREQ_L
67 65 OUT PCIE_CLK100M_NAND0_1_P BB38 ST_PCIE_REF_CLK1_P GP_PCIE_REF_CLK1_P BE38 NC_PCIE_CLK100M_USBHC_POSOUT 106
67 65 OUT PCIE_CLK100M_NAND0_1_N BC38 ST_PCIE_REF_CLK1_N GP_PCIE_REF_CLK1_N BF38 NC_PCIE_CLK100M_USBHC_NEGOUT 106
NAND0_CLKREQ1_L AH49 AA55 USBHC_CLKREQ_L

67 8 BI ST_PCIE_CLKREQ1_N GP_PCIE_CLKREQ1_N 8
106 NC_NAND0_PCIE_RESET1_L AH48 ST_PCIE_PERST1_N GP_PCIE_PERST1_N P55 NC_USBHC_RESET_L OUT 106
GP_PCIE_RX2_P BE34 NC_PCIE_ENET_D2R_POS 106

IN
GP_PCIE_RX2_N BF34 NC_PCIE_ENET_D2R_NEG 106
IN
GP_PCIE_TX2_P BC35 NC_PCIE_ENET_R2D_C_POS 106

OUT
GP_PCIE_TX2_N BD35 NC_PCIE_ENET_R2D_C_NEG 106
OUT
GP_PCIE_REF_CLK2_P BE39 NC_PCIE_CLK100M_ENET_POS OUT 106
GP_PCIE_REF_CLK2_N BF39 NC_PCIE_CLK100M_ENET_NEG OUT 106
GP_PCIE_CLKREQ2_N AH1 NC_ENET_CLKREQ_L 106

BI
TO BE CHECKED WITH SEG- DO NOT MATCH WITH SILVAL GP_PCIE_PERST2_N AE7 NC_ENET_RESET_L 106
OUT
IS THE PULL-UP VOLTAGE CORRECT?
8 SOC_ST_PCIE_RCAL_POS 8 SOC_ST_PCIE_RCAL_POS BC24 ST_PCIE_RCAL_P GP_PCIE_RCAL_P BC25 SOC_GP_PCIE_RCAL_POS 8
8 SOC_ST_PCIE_RCAL_NEG BB24 ST_PCIE_RCAL_N GP_PCIE_RCAL_N BB25 SOC_GP_PCIE_RCAL_NEG 8

1
R0990
200
1%
1/20W
MF
2 201 106 NC_MTR_VREF_ANAP AM3 PAD_MTR_ANALOG_TEST_P
8 SOC_ST_PCIE_RCAL_NEG 106 NC_MTR_VREF_ANAN AL3 PAD_MTR_ANALOG_TEST_N
1 C0990 NC_MTR VREF_POS AL1 PAD_MTR_VREF_P
10PF 106
5% 106 NC_MTR_VREF_NEG AM1 PAD_MTR_VREF_N
2 25V
C0G
0201
8 SOC_GP_PCIE_RCAL_POS
1 67 65 64 8 NAND0_PCIE_RESET_L
R0991 63 62 8 WLBT_RESET_L
200
1%
1/20W SYNC_MASTER=ANDREW_T668_MLB SYNC_DATE=10/09/2019
MF 1 1 PAGE TITLE
2 201 R0941 R0951
8 SOC_GP_PCIE_RCAL_NEG
5%
47K
5%
47K SOC: PCIE
1/20W 1/20W
1 C0991 MF MF
10PF 2 201 2 201
5%
2 25V
C0G
0201
BOM_COST_GROUP=SOC
**OK2INTEGRATE**
AOP, NUB, AND SMC GPIO'S ARE REFERENCED TO PP1V25_S2_AOP
SOC: AOP
U0600
TMLR68A0-B09
BGA
SYM 7 OF 23
NC_R1_DUMP_TRIG BB18 BA17 DFR_TOUCH_CLK32K_RESET_L DOC_ATTENTION should be a TP

106 OUT AOP_FUNC[0] NUB_CLK_OUT0 OUT 88
NC_AOP_FUNC1 BC16 BC15 TP_SOC_DOCK_ATTENTION for non dev programs,

106 AOP_FUNC[1] NUB_DOCK_ATTENTION/CTM_TRIGGER 18 106
106 OUT NC_R1_RTC_SYNC BC12 AOP_FUNC[2] NUB_DOCK_CONNECT BC17 SOC_DOCK_CONNECT IN 9 96
106 IN NC_R1_INT BC13 AOP_FUNC[3] IPD

106 OUT NC_SPI_R1_CS_L BA16 AOP_FUNC[4] NUB_GPIO_0/AOP_FUNC15/NUB_CLK_OUT1 BD14 NC_BKLT_PWR_ON_SMC_LED_SEL OUT 106 SOC_SW_DBG SHOULD GO TO
106 NC_AOP_FUNC5 BA13 AOP_FUNC[5] NUB_GPIO_1/AOP_PDM_IN_CLK0 BD15 CODEC_RESET_L OUT 76 80 A LED IF POSSIBLE.
output if gyro, input for radar 106 51 OUT SPI_GYRO_CS_L BA15 AOP_FUNC[6] NUB_GPIO_2/AOP_PDM_IN_DATA0 BD21 SOC_SW_DBG OUT 94 NEEDS A TEST POINT AT MINIMUM
106 51 IN GYRO_INT BD13 AOP_FUNC[7] NUB_GPIO_3/AOP LEAP_MADI_IN BD17 IPD_SPI_INT_L N 106
AOP GPIO
106 51 IN GYRO_MOTION_INT BD16 AOP_FUNC[8] IPU NUB_GPIO_4/AOP_LEAP_MADI_OUT BB13 SMC_FIXTURE_MODE_L IN 18 89
74 IN LID_OPEN BA14 AOP_FUNC[9] IPD NUB_GPIO_5/AOP_PDM_OUT_CLK0 BD19 CHGR_INT_L IN 106
NC_AOP_FUNC10 BB12 BD22 NC_ENET_I2C_LOM_INT_L FIXTURE_MODE_L should be aliased to a TP

106 AOP_FUNC[10] NUB_GPIO_6/AOP_PDM_OUT_DATA0/AOP_FUNC16 IN 106
WLAN_CONTEXT_A BD20 BB10 NC_ACDC_ID for non dev programs,

63 62 OUT AOP_FUNC[11] NUB_GPIO_7/A P_ U C17 IN 106
WLAN_CONTEXT_B BA11 BD12 NC_ACDC_BURST_EN_L The TP is required

63 62 OUT AOP_FUNC[12] NUB_GPIO_8/AOP_FUNC18 OUT 106
NUB GPIO
106 IN NC_ALS_INT_L BD18 AOP_FUNC[13] IPU NUB_GPIO_9/AOP_FUNC19 BD11 NC_SPI_DP2HDMI_HOLD_L OUT 106
106 NC_AOP_FUNC14 BA10 AOP_FUNC[14] NUB_GPIO_10/AOP_FUNC20 BC10 NC_HDMI_CEC_AOP_TX OUT 106
NUB_GPIO_11/KIS_GPIO0/AOP_FUNC21 BB7 NC_HDMI_CEC_AOP_RX 106

IN
I2C0 is ALS for portables 106 OUT I2C_AOP_ALS_SCL BC20 AOP_I2CM0_SCL NUB_GPIO_12/KIS_GPIO1/AOP_FUNC22 BD10 NC_HDMI_HPD_AOP IN 106
106 BI I2C_AOP_ALS_SDA BB19 AOP_I2CM0_SDA

AOP I2C NUB_SPMI0_SCLK BB15 SPMI_NUB_MPMU_CLK_R 18
OUT
106 OUT NC_I2C_AOP_ENET_SCL BB16 AOP_I2CM1_SCL NUB_SPMI0_SDATA BC14 SPMI_NUB_MPMU_DATA_R BI 18
106 BI NC_I2C_AOP_ENET_SDA BE15 AOP_I2CM1_SDA NUB SPMI

NUB_SPMI1_SCLK BA12 SPMI_NUB_SPMU_CLK_R 1
OUT
106 NC_PDM_CLK1 BB9 AOP_PDM_IN_CLK1/AOP_I2S1_BCLK NUB_SPMI1_SDATA BC11 SPMI_NUB_SPMU_DATA_R BI 18
106 NC_PDM_CLK2 BC9 AOP_PDM_IN_CLK2/AOP_I2S0_MCK

74 OUT PDM_DMIC_CLK3 BC6 AOP_PDM_IN_CLK3/AOP_I2S0_LRCK NUB_SWD_TCK_OUT0 BC18 SWD_NUB_SWCLK OUT 29 33
74 OUT PDM_DMIC_CLK4 BD9 AOP_PDM_IN_CLK4/AOP_I2S0_DOUT NUB SWD NUB_SWD_TMS0 BC19 SWD_NUB_PMU_SWDIO BI 29 33
106 NC_PDM_CLK5 BC8 AOP_PDM_IN_CLK5/AOP_I2S0_DIN NUB_SWD_TMS1 BC21 NC_SWD_NUB_R1_SWDIO BI 106

AOP PDM
106 NC_PDM_CLK6 BD8 AOP_PDM_IN_CLK6/AOP_I2S0_BCLK
106 NC_PDM_DATA1 BE21 AOP_PDM_IN_DATA1/AOP_I2S1_MCK JTAG_SEL BE4 SOC_JTAG_SEL IN 4 18
106 NC_PDM_DATA2 BE16 AOP_PDM_IN_DATA2/AOP_I2S1_LRCK IPU JTAG_TCK BF5 SWD_SOC_SWCLK IN 18 56 89

IPD
74 IN PDM_DMIC_DATA3 CKP S_W IVE=CLK_DATA_CON BE19 AOP_PDM_IN_DATA3/AOP_I2S1_DOUT/AOP_PDM_IN_CLK7 IPU JTAG_TDI BF16 TP_JTAG_SOC_TDI 18
IPD JTAG
74 IN PDM_DMIC_DATA4 CKPLUS_WAIVE=CLK_DATA_CON BD5 AOP_PDM_IN_DATA4/AOP_I2S1_DIN/AOP_PDM_IN_CLK8 JTAG_TDO BC1 TP_JTAG_SOC_TDO 18
IPU JTAG_TMS BB1 SWD_SOC_SWDIO 18 56 89

BI
51 IN SPI_AOP_GYRO_R1_MISO BF15 AOP_SPI0_MISO IPD JTAG_TRSTN BF7 TP_JTAG_SOC_TRST_L 18
18 OUT SPI_AOP_GYRO_R1_MOSI_R BF14 AOP_SPI0_MOSI AOP SPI

18 OUT SPI_AOP_GYRO_R1_CLK_R BF17 AOP_SPI0_SCLK
SMC_I2CM0_SCL BC3 I2C_SMC_PWR_SCL 106
O T
106 NC_AOP_SPMI0_SCLK BF18 AOP_SPMI0_SCLK/AOP_UART0_TXD SMC_I2CM0_SDA BC2 I2C_SMC_PWR_SDA 106
BI
106 NC_AOP_SPMI0_SDATA BF19 AOP_SPMI0_SDATA/AOP_UART0_RXD
18 OUT SPMI_SE_CLK_R BF20 www.teknisi-indonesia.com

AOP_SPMI1_SCLK/AOP_UART1_TXD
AOP SPMI SMC_I2CM1_SCL/SMC_UART1_TXD
SMC_I2CM1_SDA/SMC_UART1_RXD
BD4
BB2
I2C_SMC_UPC_SCL
I2C_SMC_UPC_SDA
OUT
BI
43 89
18 BI SPMI_SE_DATA_R BF21 AOP_SPMI1_SDATA/AOP_UART1_RXD

SMC_I2CM2_SCL BD6 I2C_SMC_SNS1_SCL 43
OUT
106 NC_AOP_UART2_D2R BB3 AOP_UART2_RXD SMC I2C SMC_I2CM2_SDA BC5 I2C_SMC_SNS1_SDA 43
BI
106 NC_AOP_UART2_R2D BB4 AOP_UART2_TXD
AOP UART BC7
SMC_I2CM3_SCL I2C_SMC_IPD_SCL OUT 106
102 11 9 PP1V25_S2 SMC_I2CM3_SDA BD7 I2C_SMC_IPD_SDA 106

I
R1083 1 33 18 IN PMU_CLK32K_SOC BE6 RT_CLK32768 SMC_I2CM4_SCL BE7 I2C_SMC_SNS0_SCL OUT 43
10K AOP RESET SMC_I2CM4_SDA BF9 I2C_SMC_SNS0_SDA 43

BI
5% BF10
/2 W CFSB_AON
MF BF4
201 2 IPU SMC_UART0_RXD UART_SMC_DEBUGPRT_D2R IN 56 89
SMC UART
100 90 89 74 33 5 IN PMU_RESET_L BB5 COLD_RESETN SMC_UART0_TXD BF8 UART_SMC_DEBUGPRT_R2D OUT 56 89
18 TP_AON_SLEEP1_RESET_L BB21 AON_SLEEP1_RESETN IPU SMC_GPIO0 BF11 UPC_SMC_I2C_INT_L IN 107
SMC_GPIO1 BF13 NC_SMC_GPIO1 106
100 33 OUT SOC_WDOG BF12 WDOG SMC GPIO

SMC_FPWM0 BE12 SMC_FAN_PWM 52 106
OUT
XW1022
SHORT-14L-0.1MM SM SMC_FPWM1 BE9 SMC_FAN_TACH IN 52
102 11 9 PP1V25_S2 1 2 SOC_DBG_PROBE_VALID BF6 DBG_PROBE_VALID
60 18 BI EUSB_DBG_P BF24 DBG_USB_EDP AOP DEBUG

60 18 BI EUSB_DBG_N BE24 DBG_USB_EDM
SOC_USBDBG_RESREF BE23 DBG_USB_RESREF
1
R1042
200
1%
1/20W
MF
2 1
PAGE TITLE
SOC: AOP
SOC_DOCK_CONNECT 9 96
1
R1066
47K
5%
1/20W
MF
2 201
BOM_COST_GROUP=SOC
**OK2INTEGRATE**
SOC: POWER (DDR,SRAM)

104 PP1V8_S2SW_VDD1 U0600 PP0V6_S1_VDDQL
80UM_STEN 80UM_STEN
10 101
TMLR68A0-B09
1CRITICAL
C1100 1CRITICAL
C1101 1CRITICAL
C1102 1 C1103 1 C1104
1.0UF 1.0UF 1.0UF 12PF 3.0PF
BGA C1131 C1132 1 C1150
SYM 9 OF 23 4.3UF 4.3UF 12PF
20%
2 4V
20%
2 4V
20%
2 4V
5%
2 25V
+/-0.1PF
2 25V
U0600 20%
2.5V
20%
2.5V 5%
X6S X6S X6S NP0-C0G NP0-C0G TMLR68A0-B09 X6T X6T 2 25V
0201 0201 0201 0201 0201 D21 VDD1_S2 VDD2_S2 B30 PP1V06_S2SW_DRAM 10 101 BGA 0402 0402 NP0-C0G
0201
D22 VDD1_S2 VDD2_S2 B31 SYM 8 OF 23 1 3 1 3
80UM_STEN 80UM_STEN 80UM_STEN D48 VDD1_S2
D49 B52 AA14 K53 2 4 2 4
C1105 C1106 C1107 D7
VDD1_S2 VDD2_S2
F23 AA16
VDDQL_S1 VDDQL S1 VDDQL_S1
L23
11UF 11UF 11UF VDD1_S2 VDD2_S2 VDDQL_S1 VDDQL_S1
20% 20% 20% D8 F25 AA40 L25
2.5V 2.5V 2.5V VDD1_S2 VDD2_S2 VDDQL_S1 VDDQL_S1
X6T X6T X6T E21 F50 AB15 L31
0402 0402 0402 VDD1_S2 VDD2_S2 VDDQL_S1 VDDQL_S1
1 3 1 3 1 3 E35 VDD1_S2 VDD2_S2 F52 AB41 VDDQL_S1 VDDQL_S1 L33
E48 G24 AC16 L4 80UM_STE 80UM_STEN 80UM_STEN 80UM_STEN
VDD1_S2 VDD2_S2 VDDQL_S1 VDDQL_S1
2 4 2 4 2 4 E8 VDD1_S2 VDD2_S2 G26 AC40 VDDQL_S1 VDDQL_S1 L50 C1133 C1134 C1135 C1136
D34 VDD1_S2 VDD2_S2 G51 AD15 VDDQL_S1 VDDQL_S1 L52 4.3UF
20%
4.3UF
20%
4.3UF
20%
4 3UF
20%
1 C1151
2.5V 5V 2.5V 5 3.0PF
D35 VDD1_S2 VDD2_S2 G53 AE16 VDDQL_S1 VDDQL_S1 L6 X6T X6T X6T X6T +/-0.1PF
H23 AF15 M24 0402 0402 0402 0402 2 25V
NP0-C0G
VDD2_S2 VDDQL_S1 VDDQL_S1 1 3 1 3 1 3 1 3 0201
102 PP1V2_AWAKE_PLL AJ19 VDDIO12_PLL_DDR0 VDD2_S2 H25 AG14 VDDQL_S1 VDDQL_S1 M26
AG19 VDDIO12_PLL_DDR1 VDD2_S2 H50 AH15 VDDQL_S1 VDDQL_S1 M3 2 4 2 4 2 4 2 4
AE13 VDDIO12_PLL_DDR2 VDD2_S2 H52 AK15 VDDQL_S1 VDDQL_S1 M30
1 C1113 1 C1112 1 C1110 1 C1114 T25 VDDIO12_PLL_DDR3 VDD2_S2 J24 AL14 VDDQL_S1 VDDQL_S1 M32
0.22UF 0.1UF 0.1UF 0.01UF
20% 10% 10% 10% AA29 VDDIO12_PLL_DDR4 VDD2_S2 J26 AL16 VDDQL_S1 VDDQL_S1 M5
2 6.3V
X6S-CERM 2 6.3V
X6S 2 6.3V
X6S 2 25V
X7R Y31 J51 AM15 M51
0201 0201 0201 0201 VDDIO12_PLL_DDR5 VDD2_S2 VDDQL_S1 VDDQL_S1
T33 J53 AM17 M53 80UM_STEN 80UM_STEN 80UM_STEN
VDDIO12_PLL_DDR6 VDD2_S2 VDDQL_S1 VDDQL_S1
AC43 VDDIO12_PLL_DDR7 VDD2_S2 P5 B21 VDDQL_S1 VDDQL_S1 N25 C1140 C1141 C1142
P24 B23 N31 4.3UF 4 3UF 4.3UF
VDD2_S2 VDDQL_S1 VDDQL_S1 20% 20% 20%
2.5V 2.5V 2.5V
1 C1111 1 C1115 AJ14 VDDIO11_RET_DDR0_S2 VDD2_S2 P32 B33 VDDQL_S1 VDDQL_S1 N4 X6T
0402
X6T
0402
X6T
0402
2.2UF 1.0UF AH14 VDDIO11_RET_DDR1_S2 VDD2_S2 P51 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN B35 VDDQL_S1 VDDQL_S1 N52
20% 20% 1 3 1 3 1 3
2 4V 2 4V AC14 B4 B50 T16
X6S-CERM
0201
X6S
0201 R25
VDDIO11_RET_DDR2_S2 VDD2_S2
B3
C1120 C1121 C1122 C1123 C1124 B6
VDDQL_S1 VDDQL_S1
T18
VDDIO11_RET_DDR3_S2 VDD2_S2 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF VDDQL_S1 VDDQL_S1 2 4 2 4 2 4
T29 B25 20% 20% 20% 20% 20% B8 T20
VDDIO11_RET_DDR4_S2 VDD2_S2 2.5V 2.5V 2.5V 2.5V 2.5V VDDQL_S1 VDDQL_S1
T30 B26 X6T X6T X6T X6T X6T C22 T22
VDDIO11_RET_DDR5_S2 VDD2_S2 0402 0402 0402 0402 0402 VDDQL_S1 VDDQL_S1
T36 VDDIO11_RET_DDR6_S2 VDD2_S2 B53 1 3 1 3 1 3 1 3 1 3 C24 VDDQL_S1 VDDQL_S1 T26
101 1 PP1V06_S2SW_DRAM AA42 VDDIO11_RET_DDR7_S2 VDD2_S2 F4 C3 VDDQL_S1 VDDQL_S1 T28
F6 2 4 2 4 2 4 2 4 2 4 C32 T32
VDD2_S2 VDDQL_S1 VDDQL_S1
10 DDR0_RREF J1 DDR0_RREF VDD2_S2 F31 C34 VDDQL_S1 VDDQL_S1 T38
10 DDR1_RREF H1 DDR1_RREF VDD2_S2 F33 C49 VDDQL_S1 VDDQL_S1 T40
10 DDR2_RREF G1 DDR2_RREF VDD2_S2 G3 C5 VDDQL_S1 VDDQL_S1 U14
A26 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN
10 DDR3_RREF DDR3_RREF VDD2_S2 G5 C51 VDDQL_S1 VDDQL_S1 U15
10 DDR4_RREF A31 DDR4_RREF VDD2_S2 G30 C1125 C1126 C1127 C1128 C1129 C53 VDDQL_S1 VDDQL_S1 U17
DDR5_RREF A32 G32 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF C7 U19
10 DDR5_RREF VDD2_S2 20% 20% 20% 20% 20% VDDQL_S1 VDDQL_S1
G55 H4 2.5V 2.5V 2.5V 2.5V 2.5V
10 DDR6_RREF DDR6_RREF VDD2_S2 X6T X6T X6T X6T X6T D23 VDDQL_S1 VDDQL_S1 U21
H55 H6 0402 0402 0402 0402 0402
10 DDR7_RREF DDR7_RREF VDD2_S2 1 3 1 3 1 3 1 3 1 3
D25 VDDQL_S1 VDDQL_S1 U23
H31 D31 U25
VDD2_S2 VDDQL_S1 VDDQL_S1
10 DDR0_ZQ A5 DDR0_ZQ[0] VDD2_S2 H33 2 4 2 4 2 4 2 4 2 4 D33 VDDQL_S1 VDDQL_S1 U27
10 DDR1_ZQ A7 DDR1_ZQ[0] VDD2_S2 J3 D4 VDDQL_S1 VDDQL_S1 U29
VDD2_S2 J32 D6 VDDQL_S1 VDDQL_S1 U35
10 DDR0_ZQ1 A6 DDR0_ZQ[1] VDD2_S2 P6 E24 VDDQL_S1 VDDQL_S1 U37
10 DDR1_ZQ1 A8 DDR1_ZQ[1] VDD2_S2 P23 E26 VDDQL_S1 VDDQL_S1 U39
10 DDR4_ZQ1 A34 DDR4_ZQ[1] VDD2_S2 P33 E3 VDDQL_S1 VDDQL_S1 V16
10 DDR5_ZQ1 A36 DDR5_ZQ[1] VDD2_S2 P50 E30 VDDQL_S1 VDDQL_S1 V22
E32 VDDQL_S1 VDDQL_S1 V24
K24 VDDQL_S1 VDDQL_S1 V34
K26 VDDQL_S1 VDDQL_S1 V40
K3 VDDQL_S1 VDDQL_S1 W14
101 10 PP0V6_S1_VDDQL K30 W40
VDDQL_S1 VDDQL_S1
K32 VDDQL_S1 VDDQL_S1 Y15
1 1 1 1 1 1 1 1
R1161 R1162 R1163 R1164 R1165 R1166 R1167 R1168 K5 VDDQL_S1
240 240 240 240 240 240 240 240 K51
% 1% % 1% % 1% % 1% VDDQL_S1
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF MF MF MF
2 201 2 201 2 201 2 201 2 201 2 201 2 201 2 201
10 DDR0_ZQ PLACE_NEAR=U0600 A5:5MM

10 DDR0_ZQ1 PLACE_NEAR=U0600 A6:5MM

101 10 PP0V6_S1_VDDQL
1 1 1 1 1 1 1 1
R1169 R1170 R1171 R1172 R1173 R1174 R1175 R1176
240 240 240 240 240 240 240 240
1% 1% 1% 1% 1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF MF MF MF
2 201 2 201 2 201 2 201 2 201 2 201 2 201 2 201
10 DDR0_RREF PLACE_NEAR=U0600 J1: MM
10 DDR1_RREF PLACE_NEAR=U0600 H1: MM
10 DDR2_RREF PLACE_NEAR=U0600.G1:5MM PAGE TITLE
DDR3_RREF
10
10 DDR4_RREF
PLACE_NEAR=U0600 A26:5MM
PLACE_NEAR=U0600 A31:5MM
SOC: POWER (DDR,SRAM)
10 DDR5_RREF PLACE_NEAR=U0600 A32:5MM
10 DDR6_RREF PLACE_NEAR=U0600 G55:5MM
10 DDR7_RREF PLACE_NEAR=U0600.H55:5MM
BOM_COST_GROUP=SOC
2 1
**OK2INTEGRATE**
SOC: POWER (IO)
Internally generated rail

VOLTAGE=0.6V
PP0V6_S2_GRP1
PP0V6_S2_GRP2 VOLTAGE=0.6V
C1200 1
4UF C1201 1
20%
2.5V 2
X6S
4UF
20%
0201 2.5V 2
X6S
0201
U0600
TMLR68A0-B09
BGA
102 9 PP1V25_S2
SYM 14 OF 23
1 C1213 1 C1210 1 C1211
2.2UF 2.2UF 0.1UF AR40 VDD06_GRP1_S2 VDD2_S2_SENSE1 B10 VSNS_VDD2_1 48
20% 20% 10%
2 4V 2 4V 2 6.3V AP40 VDD06_GRP2_S2 VDD2_S2_SENSE2 B37 VSNS_VDD2_2 48
X6S-CERM X6S-CERM X6S
0201 0201 0201
BB22 VDDDIO_HIB_S4 VDD_PCPU_SENSE AD36 VSNS_VDD_PCPU 45 48
102 PP1V25_S2 VDD_ECPU_ ENSE AN23 VSNS_VDD_ECPU 45 48

AY23 VDDIO12_ OP_S2 VDD_GPU_SENSE AC23 VSNS_VDD_GPU 45 48
C1234 1 AY25 VDDIO12_AOP_S2 VDD_SOC_S1_SENSE AH22 VSNS_VDD_SOC 45 48

2.2UF AY27 VDDIO12_AOP_S2 VDD_DISP_S1_SENSE Y17 VSNS_VDD_DISP 48
20%
4V BA24 VDDIO12_AOP_ 2 VDD_DCS_SENSE AN17 VSNS_VDD_DCS
X6S-CERM 2 48
0201 BA26 VDDIO12_AOP_S2 VDDQL_SENSE AN15 VSNS_VDDQL 48
AP39 VDDIO12_GRP1_S2 VSS_PCPU_SENSE AD37 VSNS_VSS_PCPU

XW1230
SM VOLTAGE=1.25V VSS_DDR_SENSE AN16 VSNS_VSS_DDR
45 48
48
102 8 6 5 4 PP1V25_AWAKE_IO 1 2 97 PP1V25_AWAKE_GRP3 AF41 VDDIO12_GRP3 VSS_SENSE1 B9 VSNS_VSS_1 48
CRITICAL AG42 VDDIO12_GRP3 VSS_S NSE2 B36 VSNS_VSS_2

C1233 1 XW1231
SM VOLTAGE=1.25V
C1230 1 AH40 VDDIO12_GRP3
48
2.2UF
10UF 1 297 PP1V25_AWAKE_GRP4 20%
4V
AL40 VDDIO12_GRP3
20%
6.3V X6S-CERM 2 AN40 VDDIO12_GRP3
CER-X6S 2 C1231 1 0201
0402
138S00073
XW1232
SM VOLTAGE=1.25V 2.2UF
20% AT40 VDDIO12_GRP4
1 2 97 PP1V25_AWAKE_GRP5 4V
X6S-CERM 2 AV40
0201 VDDIO12_GRP4
C1232 1
2.2UF AP16 VDDIO12_GRP5
20%
AR17
X6S-CERM 2 VDDIO12_GRP5
0201 AT16 VDDIO12_GRP5
AU17 VDDIO12_GRP5
AV16
VDDIO12_GRP5
AW17 VDDIO12_GRP5
AP41 VDDIO18_GRP1
102 97 PP1V8_AWAKE AR41 VDDIO18_GRP1
C1240 1
2.2UF
2 %
V
X6S-CERM 2
0201
SOC: POWER (IO)
BOM_COST_GROUP=SOC
2 1
4
**OK2INTEGRATE**
SOC: POWER (CPU, GPU)
0.575V @ 4400MA
U0600 U0600
PPVDD_GPU_AWAKE TMLR68A0-B09
TMLR68A0-B09 101 12
BGA
BGA
SYM 11 OF 23
1 C1340 1 C1341 SYM 12 OF 23
12PF 3.0PF
5% +/-0.1PF
2 25V 2 25V AA24 VDD_GPU VDD_GPU AE26
AE33 VDD_PCPU VDD_PCPU AP45 PPVDD_PCPU_AWAKE 12 101
NP0-C0G N 0-C0G PPVDD_GPU_AWAKE 12 101
0201 02 1 AA26 VDD_GPU VDD_GPU AE27
AE35 VDD_PCPU VDD_PCPU AP46 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN
AA28 AE29
AE36 VDD_PCPU VDD_PCPU AP47
AA31
VDD_GPU VDD_GPU
AE30
C1353 C1354 C1355 C1356 C1357
AE37 AP48 VDD_GPU VDD_GPU 11UF 11UF 11UF 11UF 11UF
VDD_PCPU VDD_PCPU AA33 AE31 20% 20% 20% 20% 20%
AF33 AP49 VDD_GPU VDD_GPU 2.5V 2 5V 2.5V 2 5V 2.5V
VDD_PCPU VDD_PCPU AA35 AE42 X6T X6T X6T X6T X6T
AF36 AP50 VDD_GPU VDD_GPU 0402 0402 0402 0402 0402
VDD_PCPU VDD_PCPU AA37 AE43 1 3 1 3 1 3 1 3 1 3
AF39 AP51 VDD_GPU VDD_GPU
VDD_PCPU VDD_PCPU AB25 AE44
AG34 AP52 VDD_GPU VDD_GPU
VDD_PCPU VDD_PCPU AB27 AE45 2 4 2 4 2 4 2 4 2 4
AG38 AR30 VDD_GPU VDD_GPU
AH34 AR32 VDD_GPU VDD_GPU
AH39 AR33 VDD_GPU VDD_GPU
VDD_PCPU VDD_ CPU AB32 AE48
AJ33 AR35 VDD_GPU VDD_GPU
VDD_PCPU VDD_PC U AB34 AE49
AJ34 AR36 VDD_GPU VDD_GPU
AK29 AR37 VDD_GPU VDD_GPU
VDD_PCPU VDD_PCPU
101 12 PPVDD_PCPU_AWAKE AK33 AR39
AC24 VDD_GPU VDD_GPU AE 1
VDD_PCPU VDD_PCPU
AK35
PPVDD_ECPU_AWAKE 101
AC26 VDD_GPU VDD_GPU AE52
VDD_PCPU
C1300 1 C1301 1
AK36 AK25 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN AC31 VDD_GPU VDD_GPU AE53
3.0PF
+/-0.1PF
12PF
5% AK38
VDD_PCPU VDD_ECPU
AL26
C1320 C1321 C1322 C1323 C1324 C1325 AC35 VDD_GPU VDD_GPU AE54
25V 25V VDD_PCPU VDD_ECPU 11UF 11UF 11UF 11UF 11UF 11UF AC37 AE55
NP0-C0G 2 NP0-C0G 2 AK40 VDD_PCPU VDD_ECPU AL28 20%
2.5V
20%
2.5V
20%
2.5V
20%
2.5V
20%
2.5V
20%
2.5V
VDD_GPU VDD_GPU
0201 0201 X6T X6T X6T X6T X6T X6T AD25 VDD_GPU VDD_GPU AF24
AK41 VDD_PCPU VDD_ECPU AL29 0402 0402 0402 0402 0402 0402 AD27 VDD_GPU VDD_GPU AF32
AK42 VDD_PCPU VDD_ CPU AN24 1 3 1 3 1 3 1 3 1 3 1 3
AD32 VDD_GPU VDD_GPU AG25
AK43 VDD_PCPU VDD_EC U AN29
2 4 2 4 2 4 2 4 2 4 2 4 AD34 VDD_GPU VDD_GPU AG27
AK44 VDD_PCPU VDD_ECPU AP25
AK45 VDD_PCPU VDD_ECPU AR26
AK46 VDD_PCPU VDD_ECPU AR28
AD43 VDD_GPU
AL30 VDD_PCPU PPVDD_DISP_S1 101
AD44 VDD_GPU VDD_DISP_S1 AA19
AL32 VDD_PCPU VDD_SOC_S1 AB23
AD45 VDD_GPU VDD_DISP_S1 AA21 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN
AL37 VDD_PCPU VDD_SOC_S1 AC33
AD46 VDD_GPU VDD_DISP_S1 AA23
1 C1370 C1361 C1362 C1363 C1364
AL41 VDD_PCPU VDD_SOC_S1 AC38 12PF 11UF 11UF 11UF 11UF
AD47 VDD_GPU VDD_DISP_S1 AB22 5% 20% 20% 20% 20%
AL42 VDD_PCPU VDD_SOC_S1 AE23 2 25V 2.5V 2.5V 2.5V 2.5V
AD48 VDD_GPU VDD_DISP_S1 AC19 NP0-C0G X6T X6T X6T X6T
AL43 VDD_PCPU VDD_SO _S1 AE32 0201 0402 0402 0402 0402
AD49 VDD_GPU VDD_DISP_S1 AD22
AL44 VDD_PCPU VDD_SOC_ 1 AE38 1 3 1 3 1 3 1 3
AD50 VDD_GPU VDD_DISP_S1 AE19
AL45 VDD_PCPU VDD_SOC_S1 AF28
AD51 VDD_GPU VDD_DISP_S1 AE21 2 4 2 4 2 4 2 4
AL46 VDD_PCPU VDD_SOC_S1 AG23
AD52 VDD_GPU VDD_DISP_S1 AG21
AM29 VDD_PCPU VDD_SOC_S1 AG39
AD53 VDD_GPU
AM34 VDD_PCPU VDD_SOC_S1 AJ20
AD54 VDD_GPU
AD55 VDD_GPU
AE24 VDD_GPU 80UM_STEN 80UM_STEN
AM42 AJ26
AM43
VDD_PCPU VDD_SOC_S1
AJ28
80UM_STEN
C1350 C1351 C1352
80UM_STEN 80UM_STEN C1365 C1366
VDD_PCPU VDD_SOC_S1 11UF 11UF
AM44 AJ30 11UF 11UF 11UF 20% 20%
VDD_PCPU VDD_SO _S1 20% 2 % 20% 2.5V 2.5V
AM45 AJ32 2.5V 2.5V 2.5V X6T X6T
VDD_PCPU VDD_SOC_ 1 X6T X6T X6T 0402 0402
AM46 AL20 0402 0402 0402 1 3 1 3
VDD_PCPU VDD_SOC_S1 1 3 1 3 1 3
AM47 VDD_PCPU VDD_SOC_S1 AL22
AM48 AL24 2 4 4
VDD_PCPU VDD_SOC_S1 2 4 2 4 2 4
AM49 VDD_PCPU VDD_SOC_S1 AM39
AM50 VDD_PCPU VDD_SOC_S1 AN18
AM53 VDD_PCPU VDD_SOC_S1 AR18
AM54 VDD_PCPU VDD_SO _S1 AR22
AM55 VDD_PCPU VDD_SOC_ 1 AR24
AN33 VDD_PCPU VDD_SOC_S1 AT33
AN42 VDD_PCPU VDD_SOC_S1 AU18
AN47 VDD_PCPU VDD_SO _S1 AU28
80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN AN48 AU30
C1310 C1311 C1312 C1313 C1314 C1315 C1316 C1317 AN49
VDD_PCPU VDD_SOC_ 1
AU38
11UF 11UF 11UF 11UF 11UF 11UF 11UF 11UF VDD_PCPU VDD_SOC_S1
PPVDD_SOC_S1
20% 20% 20% 20% 20% 20% 20% 20% AN50 Y21 101
2.5V 2 5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V VDD_PCPU VDD_SOC_S1
X6T X T X6T X6T X6T X6T X6T X6T AN51
0402 0402 0402 0402 0402 0402 0402 0402 VDD_PCPU VDD_SOC_S1 Y26 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN
1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 AN52 VDD_PCPU VDD_SOC_S1 Y36 C1330 C1331 C1332 C1333
AN53 11UF 11UF 11UF 11UF
VDD_PCPU 20% 20% 20% 20%
2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 AN54 2.5V 2.5V 2.5V 2.5V
VDD_PCPU X6T X6T X6T X6T
AN55 0402 0402 0402 0402
VDD_PCPU 1 3 1 3 1 3 1 3
AP29 VDD_PCPU
AP33 VDD_PCPU 4 2 4 2 2 4
AP38 VDD_PCPU
AP43 VDD_PCPU
80UM_STEN 80UM_STEN AP44
C1318 C1319 VDD_PCPU
11UF 11UF 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN
20%
2.5V
20%
2.5V C1334 C1335 C1336 C1337
X6T X6T 11UF 11UF 11UF 11UF
0402 0402 20% 20% 20% 20%
1 3 1 3 2.5V 2.5V 2.5V 2.5V
X6T X6T X6T X6T
0402 0402 0402 0402
2 2 4 1 3 1 3 1 3 1 3
2 4 2 4 2 4 2 4
PAGE TITLE
SOC: POWER (SOC, CPU, GPU)
BOM_COST_GROUP=SOC
**OK2INTEGRATE**
SOC: POWER (SRAM, SOC)
U0600
TMLR68A0-B09
BGA
SYM 10 OF 23
AE34 VDD CPU_SRAM VDD_SRAM_S1 AA18

AE39 VDD CPU_SRAM VDD_SRAM_S1 AA32
AG36 VDD_CPU_SRAM VDD_SRAM_S1 AB20
AH35 VDD_CPU_SRAM VDD_SRAM_S1 AB24
AH37 VDD_CPU_SRAM VDD_SRAM_S1 AB31
AJ36 VDD_CPU_SRAM VDD_SRAM_S1 AB35
AJ38 VDD_CPU_SRAM VDD_SRAM_S1 AC21
AK27 VDD_CPU_SRAM VDD_SRAM_S1 AC28
AK31 VDD_CPU_SRAM VDD_SRAM_ 1 AC30
AK37 VDD_CPU_SRAM VDD_SRAM_S1 AD20
AL33 VDD CPU_SRAM VDD_SRAM_S1 AD21
AL35 VDD CPU_SRAM VDD_SRAM_S1 AD24
101 PVDD_CPU_SRAM_AWAKE AL38 AD28
VDD_CPU_SRAM VDD_SRAM_S1
80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN AM25 AD30
VDD_CPU_SRAM VDD_SRAM_S1
C1400 C1401 C1402 C1403 C1404 C1405 1 C1406 1 C1407 AM26 VDD_CPU_SRAM VDD_SRAM_S1 AD35
11UF 11UF 11UF 11UF 11UF 11UF 12PF 3.0PF
20% 20% 20% 20% 20% 20% 5% +/-0.1PF AM31 VDD_CPU_SRAM VDD_SRAM_S1 AF20
2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2 25V
NP0-C0G 2 25V
NP0-C0G AM36 AF22
PP0V764_S1_SRAM 48 101
X6T X6T X6T X6T X6T X6T 0201 0201 VDD_CPU_SRAM VDD_SRAM_S1
0402 0402 0402 0402 0402 0402 AN26 AF26 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN
1 3 1 3 1 3 1 3 1 3 1 3 VDD_CPU_SRAM VDD_SRAM_S1
AN27 VDD_CPU_SRAM VDD_SRAM_ 1 AF30 C1420 C1421 C1422 C1423 C1424 C1425
AN30 AG28 11UF 11UF 11UF 11UF 11UF 11UF
2 4 2 4 2 4 2 4 2 4 2 4 VDD_CPU_SRAM VDD_SRAM_S1 20% 20% 20% 20% 20% 20%
AN32 AH19 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
VDD CPU_SRAM VDD_SRAM_S1 X6T X6T X6T X6T X6T X6T
AN35 AH21 0402 0402 0402 0402 0402 0402
VDD CPU_SRAM VDD_SRAM_S1 1 3 1 3 1 3 1 3 1 3 1 3
AN37 VDD_CPU_SRAM VDD_SRAM_S1 AH23
AP27 VDD_CPU_SRAM VDD_SRAM_S1 AH25 2 4 2 4 2 4 2 4 2 4 2 4
AP36 VDD_CPU_SRAM VDD_SRAM_S1 AH27
AR31 VDD_CPU_SRAM VDD_SRAM_S1 AH29
AR34 VDD_CPU_SRAM VDD_SRAM_S1 AH31
AR38 VDD_CPU_SRAM VDD_SRAM_S1 AK19
VDD_SRAM_ 1 AK21
VDD_SRAM_S1 AK23
AA39 AM19
VDD DCS_S1 VDD_SRAM_S1
AB17 VDD DCS_S1 VDD_SRAM_S1 AM21
AB38 VDD_DCS_S1 VDD_SRAM_S1 AM23
AC18 VDD_DCS_S1 VDD_SRAM_S1 AP21
AC39 VDD_DCS_S1 VDD_SRAM_S1 AP23
AD17 VDD_DCS_S1 VDD_SRAM_S1 AT19
AE18 VDD_DCS_S1 VDD_SRAM_S1 AT21
AF17 VDD_DCS_S1 VDD_SRAM_S1 AT23
AG18 VDD_DCS_S1 VDD_SRAM_ 1 AT25
AJ18 VDD_DCS_S1 VDD_SRAM_S1 AT27
AK17 VDD DCS_S1 VDD_SRAM_S1 AT29
AL18 VDD DCS_S1 VDD_SRAM_S1 AT31
101 PPVDD_DCS_S1 W17 AT39
VDD_DCS_S1 VDD_SRAM_S1
W22 VDD_DCS_S1 VDD_SRAM_S1 AU36
80UM_STEN 80UM_STEN 80UM_STEN 80UM_STEN W24 AV37
VDD_DCS_S1 VDD_SRAM_S1
C1410 C1411 C1412 C1413 W26 VDD_DCS_S1
11UF 11UF 11UF 11UF W31
20% 20% 20% 20% VDD_DCS_S1
2.5V 2.5V 2.5V 2.5V W33
X6T X6T X6T X6T VDD_DCS_S1
0402 0402 0402 0402 W35
1 3 1 3 1 3 1 3 VDD_DCS_S1
W39 VDD_DCS_S1
2 4 2 4 2 4 2 4 Y18 VDD DCS_S1
Y20 VDD DCS_S1
Y23 VDD_DCS_S1
Y25 VDD_DCS_S1
Y27 VDD_DCS_S1
Y29 VDD_DCS_S1
Y32 VDD_DCS_S1
Y34 VDD_DCS_S1
Y38 VDD_DCS_S1
PAGE TITLE
SOC: POWER (SRAM)
BOM_COST_GROUP=SOC
**OK2INTEGRATE**
PP0V855_S2SW_CIO 102
U0600 80UM_STEN 80UM_STEN
TMLR68A0-B09
BGA C1542 C1543
4.3UF 4.3UF
SYM 13 OF 23 C1540 1 C1541 1 20%
2.5V
20%
2.5V
0.1UF 0.1UF X6T X6T
10% 10% 0402 0402
103 PP0V805_S1_VDD_FIXED AM28 VDD_FIXED_ECPU_S1 VDD_CIO AV34 6.3V 2
X6S
6.3V 2
X6S 1 3 1 3
VDD_CIO AV36 0201 0201
103 PP0V805_S1_VDD_FIXED AW19 VDD_FIXED_LPDP_RX_S1 VDD_CIO AW35 2 4 2 4

AW20 VDD_FIXED_LPDP_RX_S1
AW21 VDD_FIXED_LPDP_RX_S1 VDD12_CIO_S2 AU42
VDD12_CIO_S2 AU43
103 PP0V805_S1_VDD_FIXED BA37 AV42
PP1V2_S2_CIO 103
VDD_FIXED_LPDP_TX_S1 VDD12_CIO_S2 80UM_STEN 80UM_STEN
BA38 AV43
C1505 1 C1506 1 VDD_FIXED_LPDP_TX_S1 VDD12_CIO_S2 C1546 C1547
103 PP0V805_S1_VDD_FIXED 0.1UF 2.2UF
BA39 VDD_FIXED_LPDP_TX_S1 VDD12_CIO_S2 AY34 4.3UF 4.3UF
10% 20% VDD12_CIO_S2 AY36 C1544 1 C1545 1 20%
2.5V
20%
2.5V
6.3V 2 4V
X6S-CERM 2
0.1UF 0.1UF X6T X6T
C1507 1 C1508 1 X6S
0201 0201
R11 VDD_FIXED_MIPIC_S1 VDD12_CIO_S2 BA35 10%
6.3V 2
10%
6.3V 2 0402 0402
2.2UF 0.1UF R12 VDD_FIXED_MIPIC_S1 X6S
020
X6S
0201
1 3 1 3
2 % 10%
V 6.3V 2 R13 VDD_FIXED_MIPIC_S1 VDD_CIO_USB AU34
X6S-CERM 2 X6S
0201 0201 2 4 2 4
R10 VDD_FIXED_MIPID_PLL_S1 VDD12_CIO_USB_S2 AU35
R1500 103 PP0V805_S1_VDD_FIXED

VOLTAGE=0.805V P9 AT42
PP0V805_S1_VDD_FIXED 1
0 2 PP0V805_S1_SOC_VDDFIXEDPCIE_R VDD_FIXED_MIPID_S1 VDD12_AMUX_S2
PP0V855_S2SW_CIO
103 14 102
R9 VDD_FIXED_MIPID_S1
5%
AV11
PP1V2_S2_CIO 103
1/20W VDD12_LPDP_RX
MF
0201
C1500 1 C1501 1
AY18 VDD_FIXED_MTR_S1 VDD12_LPDP_RX AV20
PP1V25_S2 102 LPDP_RX POWER MAY BE GROUNDED
103 14 PP0V805_S1_VDD_FIXED 2.2UF 0.1UF PP1V25_AWAKE_IO 102 BUT J293 IS NOT DOING THIS PER
80UM_STEN 20% 10% VDD12_LPDP_RX AW11
4V 6.3V 2 <RDAR://61722166>
C1514 1 C1515 1 X6S-CERM 2 X6S AV33 AW13
C1513 0.1UF 0.1UF
0201 0201 VDD_FIXED_PCIE_REFBUF_S1 VDD12_LPDP_RX
AY13
PP1V2_AWAKE_PLL 102
4.3UF 10% 10% VDD12_LPDP_RX
20%
2.5V
X6T
6.3V 2
X6S
6.3V 2
X6S
AV29 VDD_FIXED_PCIE_S1 VDD12_LPDP_RX AY19 C1550 1 C1551 1
0402 0201 0201 AV30 VDD_FIXED_PCIE_S1 VDD12_LPDP_RX AY20 2.2UF 0.1UF
20% 10%
3 AV31 VDD_FIXED_PCIE_S1 VDD12_LPDP_RX AY21 4V 6.3V 2
X6S-CERM X6S
AV32 VDD_FIXED_PCIE_S1 0201 0201
2 4 AW37
VDD12_LPDP_TX
103 14 PP0V805_S1_VDD_FIXED AL34 VDD_FIXED_PCPU_S1 VDD12_LPDP_TX AW38
AW39
PP1V25_AWAKE_IO 102
VDD12_LPDP_TX
C1502 1 C1503 1 C1504 1 AT32 VDD_FIXED_PLL_ANE_S1 C1560 1 C1561 1 102
0.1UF 0.1UF 2.2UF VDD12_MIPIC P11 2.2UF 0.1UF
10% 10 20% 2 % 10%
6.3V 2
X6S
6.3V 2
X6S
4V
X6S-CERM 2
AF29 VDD_FIXED_PLL_GPU_S1 VDD12_MIPIC P12 V
X6S-CERM 2
6.3V 2
X6S C1562 1
0201 0201 0201 VDD12_MIPIC P13 0201 0201 2.2UF
20%
AR20 VDD_FIXED_PLL_SOC_S1 4V
X6S-CERM 2
VDD12_MIPID P8 201
FL1510 AH13 VDD12_MIPID R8
120OHM-25%-0.25A-0.5OHM VOLTAGE=0.805V
VDD_FIXED_PLL_DDR0_S1
AG13 VDD_FIXED_PLL_DDR1_S1
103 14 PP0V805_S1_VDD_FIXED 1 2 PP0V805_S1_SOC_VDDFIXEDPLL_F AC13 AW18
0201 VDD_FIXED_PLL_DDR2_S1 VDD12_MTR PP1V25_AWAKE_IO
T24 VDD_FIXED_PLL_DDR3_S1
1 C1510 C1511 1 C1512 1 C1516 1 C1517 1
R28 VDD_FIXED_PLL_DDR4_S1 VDD12_PCIE AY29 PP1V2_AWAKE_PLL
2.2UF 2.2UF 0.1UF 0.1UF 0.22UF 80UM_STEN 80UM_STEN
102
20% 20% 10 10% 20% R29 VDD_FIXED_PLL_DDR5_S1 VDD12_PCIE AY30
2 4V 4V
X6S-CERM 2
6.3V 6.3V 2 6.3V
X6S-CERM 2 C1555 C1556
X6S-CERM
0201 0201
X6S
0201
X6S
0201 0201
T34 VDD_FIXED_PLL_DDR6_S1 VDD12_PCIE AY31 C1553 1 C1554 1
4.3UF 4.3UF
AC42 VDD_FIXED_PLL_DDR7_S1 VDD12_PCIE AY32 0.1UF 0.1UF 20% 20%
10% 10% 2.5V 2.5V
VDD12_PCIE AY43 6 3V 2 6.3V 2 X6T X T
X6S X6S 0402 0402
A32 B 42 020 0201
R1590 VOLTAGE=0 805V
VDD_FIXED_XTAL_S1 VDD12_PCIE
BA43
1 3 1 3
10 2 PP0V805_S1_SOC_VDDFIXEDXTAL_R VDD12_PCIE
103
AD40 VDD_FIXED_S1 2 4 2 4
5%
1/20W AG40 VDD_FIXED_S1 VDD12_PCIE_REFBUF AW33
MF
201
1 C1590 AJ39 VDD_FIXED_S1 VOLTAGE=1.2V R1574
4UF 0
117S0004 20% AP17 VDD_FIXED_S1 VDD12_PLL_ANE AP31 PP1V2_AWAKE_PLL_PCIE_R 1 2
2 2.5V
X6S AU32
0201 VDD_FIXED_S1 5%
1/20W
138S00329 AV39 VDD_FIXED_S1 VDD12_PLL_CPU AK34 C1573 1 C1574 1 MF
0 01
AY16 VDD_FIXED_S1 0.1UF 2.2UF
103 97 PP0V805_S1_VDD_FIXED V17 AG29
10%
6.3V 2
20%
4V
VDD_FIXED_S1 VDD12_PLL_GPU X6S X6S-CERM 2
0201 0201
C1520 1 C1521 1
AV23 VDD_LOW_S2 VDD12_PLL_SOC AP19
3.0PF 2.2UF PP1V2_AWAKE_PLL 102
+/-0.1PF 20% AV25 VDD_LOW_S2
25V 4V
NP0-C0G 2 X6S-CERM 2 AV27 VDD_LOW_S2 VDD12_TSADC_CPU AK32 C1570 1 C1571 1 C1572 1
0201 0201
AW26 VDD_LOW_S2 0.1UF 0.1UF 2.2UF
10% 10% 20%
AY26 VDD_LOW_S2 VDD12_TSADC_SOC0 U20 6.3V 2 6.3V 2 4V
PP1V25_AWAKE_IO 102
X6S X6S X6S-CERM 2
102 48 PP0V72_S2_VDD_LOW BA23 VDD_LOW_S2 VDD12_TSADC_SOC1 Y33 0201 0201 0201
80UM_STEN 80UM_STEN AH32
C1530 C1531 AW24
VDD12_TSADC_SOC2
AY15 VOLTAGE=1.25V R1584
VDD_LOW_FLPPLL_S2 VDD12_TSADC_SOC3
PP1V25_S2_ULPPLL_R 49.9 2 PP1V25_S2
4.3UF 4.3UF AE40
1 102
20% 20% VDD12_TSADC_SOC4
2.5V 2.5V 1%
X6T
0402
X6T
0402
AW22 VDD_LOW_ULPPLL_S2 1 C1584 / 0W
MF
VDD12_ULPPLL_S2 AW23 PP1V25_S2 102
4.7UF 201
1 3 1 3 20%
AW28 VDD_LOW_USB_DEBUG_S2 2 6.3V
2 4 2 4 VDD12_USB_DEBUG_S2 AY28
1 C1582 CER
0402
0.1UF
BA22 VDD_HIB_S4 10%
BA33 2 6.3V
X6S
R1535 VOLTAGE=0.72V
VDD12_XTAL 0201
PP0V72_S2_VDD_LOW 2
10 1 PP0V72_S2_VDD_LOWFLPLL_R FL1580
102
VDD12_EFUSE1 AU40 VOLTAGE=1.25V
240-OHM-0.2A-0.9-OHM
5%
1/20W
MF
C1535 1 VDD12_EFUSE2 AT20 PP1V25_AWAKE_XTAL_F 2 1 PP1V25_AWAKE_IO 1 2
201 0.22UF VDD12_EFUSE3 AB43 0201

20%
6.3V 2
X6S-CERM
1 C1580 1 C1581
0201 VDD12_FMON AU19 0 1UF 2.2UF
10% 20%
R1536 2 6.3V
X6S 2 4V
X6S-CERM
VOLTAGE=0.72V 0201 0201
PP0V72_S2_VDD_LOW 1
49.9 2 PP0V72_S2_VDD_LOWULPPLL_R
102
1%
1/20W 1 C1536 VOLTAGE=1.25V R1583
MF
201 4UF PP1V25_AWAKE_FMON_R 1
49.9 2 PP1V25_AWAKE_IO 102
20%
2 2.5V
X6S 1%
1/20W
0201 1 C1583 MF
201
2.2UF
20%
2 4V
X6S-CERM
PAGE TITLE
0201 SOC: POWER (Fixed, PLL's, Filtered)
102 PP0V72_S2_VDD_LOW
C1537 1
0.1UF
10%
6.3V 2
X6S
0201
102 PP0V72_S2_VDD_LOW
BOM_COST_GROUP=SOC
2 1
**OK2INTEGRATE**
SOC: GND (1)

U0600 U0600 U0600 U0600 U0600
TMLR68A0-B09 TMLR68A0-B09 TMLR68A0-B09 TMLR68A0-B09 TMLR68A0-B09
BGA BGA BGA BGA
SYM 15 OF 23 SYM 16 OF 23 SYM 17 OF 23 SYM 18 OF 23 SYM 19 OF 23
A10 VSS VSS VSS AB42 AF40 VSS VSS VSS AK12 AN9 VSS VSS VSS AT52 AW45 V S VSS VS BA28 BD25 VSS VS VSS C21
A11 VSS VSS AB44 AF42 VSS VSS AK13 AP10 VSS VSS AT53 AW46 VSS VSS BA29 BD26 VSS VSS C23
A14 VSS VSS AB47 AF45 VSS VSS AK18 AP13 VSS VSS AU10 AW49 VSS VSS BA31 BD32 VSS VSS C27
A19 VSS VSS AB8 AG10 VSS VSS AK28 AP22 VSS VSS AU15 AW6 VSS VSS BA41 BD39 VSS VSS C33
A2 VSS V S AB9 AG11 VSS VSS AK30 AP24 VSS VSS AU16 AW9 V S VS BA44 BD40 VSS VSS C35
A20 VSS VSS AC10 AG12 VSS VSS AK39 AP26 VSS VSS AU21 AY10 VSS VSS BA45 BD41 VSS VSS C36
A28 VSS VSS AC25 AG32 VSS VSS AL10 AP37 VSS VSS AU33 AY3 VSS VSS BA53 BD52 VSS VSS C42
A3 VSS V S AC29 AG37 VSS VSS AL12 AP53 VSS VSS AU39 AY35 V S VS BA55 BD54 VSS VSS C44
A37 VSS VSS AC34 AG43 VSS VSS AL15 AP55 VSS VSS AU44 AY38 VSS VSS BA7 BE1 VSS VSS C46
A4 VSS VSS AC44 AG46 VSS VSS AL2 AR10 VSS VSS AU47 AY41 VSS VSS BB11 BE17 VSS VSS C50
A44 VSS V S AC9 AG8 VSS VSS AL31 AR15 VSS VSS AU6 AY47 VSS VS BB26 BE27 VSS VSS C8
A45 VSS VSS AD10 AG9 VSS VSS AL36 AR16 VSS VSS AU7 AY48 VSS VSS BB27 BE29 VSS VSS C9
A46 VSS VSS AD11 AH10 VSS VSS AL39 AR19 VSS VSS AU8 AY49 VSS VSS BB28 BE3 VSS VSS D1
A47 VSS VSS AD12 AH11 VSS VSS AL47 AR21 VSS VSS AU9 AY50 VSS VSS BB29 BE31 VSS VSS D10
A48 VSS VSS AD13 AH12 VSS VSS AL5 AR23 VSS VSS AV10 AY53 VSS VSS BB30 BE33 VSS VSS D11
A51 VSS VSS AD18 AH20 VSS VSS AL9 AR29 VSS VSS AV14 B1 VSS VSS BB33 BE41 VSS VSS D14
A52 VSS VSS AD19 AH24 VSS VSS AM10 AR3 VSS VSS AV15 B11 VSS VSS BB34 BE43 VSS VSS D15
A53
A54
VSS
VSS
VSS
V S
AD23
AD26
AH26
AH28
VSS
VSS
VSS
VSS
AM11
AM12
AR42
AR43
VSS
VSS
VSS
VSS
AV17
AV18
B12
B13
VSS
VSS
VSS
VS
BB35
BB36
BE45
BE47
VSS
VSS
VSS
VSS
D16
D17
A9 VSS VSS AD29 AH30 VSS VSS AM13 AR44 VSS VSS AV19 B14 VSS VSS BB39 BE49 VSS VSS D18
AA10 VSS VSS AD31 AH33 VSS VSS AM14 AR45 VSS VSS AV21 B15 VSS VSS BB40 BE5 VSS VSS D19
AA20 VSS VSS AE10 AH44 VSS VSS AM27 AR51 VSS VSS AV35 B20 VSS VSS BB46 BF2 VSS VSS D28
AA25 VSS V S AE12 AH46 VSS VSS AM32 AR53 VSS VSS AV41 B24 VSS VS BB48 BF23 VSS VSS D3
AA34 VSS VSS AE17 AH8 VSS VSS AM37 AT10 VSS VSS AV46 B29 VSS VSS BB51 BF29 VSS VSS D36
AA36 VSS VSS AE2 AH9 VSS VSS AM40 AT11 VSS VSS AV47 B32 VSS VSS BB52 BF3 VSS VSS D37
AA38 VSS VSS AE20 AJ10 VSS VSS AM6 AT12 VSS VSS AV48 B34 VSS VSS BB6 BF31 VSS VSS D38
AA41 VSS VSS AE22 AJ11 VSS VSS AM7 AT13 VSS VSS AV49 B38 VSS VSS BB8 BF33 VSS VSS D39
AA43 VSS VSS AE25 AJ12 VSS VSS AM8 AT14 VSS VSS AV50 B39 VSS VSS BC22 BF35 VSS VSS D40
AA44 VSS VSS AE28 AJ13 VSS VSS AM9 AT15 VSS VSS AV53 B40 VSS VSS BC23 BF37 VSS VSS D41
AA45 VSS VSS AE41 AJ15 VSS VSS AN1 AT17 VSS VSS AV6 B41 VSS VSS BC26 BF41 VSS VSS D42
AA46 VSS V S AE5 AJ21 VSS VSS AN10 AT18 VSS VSS AV9 B42 VSS VS BC28 BF43 VSS VSS D43
AA47 VSS VSS AE8 AJ23 VSS VSS AN11 AT22 VSS VSS AW10 B43 VSS VSS BC30 BF45 VSS VSS D44
AA8 VSS VSS AE9 AJ25 VSS VSS AN12 AT24 VSS VSS AW12 B44 VSS VSS BC32 BF47 VSS VSS D45
AA9 VSS VSS AF10 AJ27 VSS VSS AN13 AT26 VSS VSS AW14 B45 VSS VSS BC34 BF49 VSS VSS D46
AB10 VSS VSS AF11 AJ29 VSS VSS AN14 AT28 VSS VSS AW15 B46 VSS VSS BC36 BF51 VSS VSS D47
AB13 VSS VSS AF14 AJ37 VSS VSS AN21 AT34 VSS VSS AW27 B5 VSS VSS BC40 C1 VSS VSS D53
AB18 VSS V S AF19 AJ42 VSS VSS AN3 AT41 VSS VSS AW30 B55 VSS VS BC 4 C12 VSS VSS D9
AB19 VSS VSS AF21 AJ43 VSS VSS AN31 AT43 VSS VSS AW31 B7 VSS VSS BC46 C13 VSS VSS E1
AB2 VSS VSS AF23 AJ44 VSS VSS AN36 AT44 VSS VSS AW32 BA1 VSS VSS BC48 C14 VSS VSS E10
AB33 VSS VSS AF34 AJ8 VSS VSS AN5 AT48 VSS VSS AW41 BA20 VSS VSS BD1 C18 VSS VSS E14
AB37 VSS VSS AF35 AJ9 VSS VSS AN6 AT49 VSS VSS AW42 BA21 VSS VSS BD2 C19 VSS VSS E15
AB39 VSS VSS AF37 AK10 VSS VSS AN7 AT50 VSS VSS AW43 BA25 VSS VSS BD23 C2 VSS VSS E16
AB40 VSS VSS AF38 AK11 VSS VSS AN8 AT51 VSS VSS AW44 BA27 VSS VSS BD24 C20 VSS VSS E17
PAGE TITLE
SOC: GND
BOM_COST_GROUP=SOC
**OK2INTEGRATE**
SOC: GND (2)
U0600 U0600 U0600 U0600

TMLR68A0-B09 TMLR68A0-B09 TMLR68A0-B09 TMLR68A0-B09
BGA BGA BGA BGA
SYM 20 O 23 SYM 21 OF 23 SYM 22 OF 23 SYM 23 OF 23
E18 VSS VSS VSS F8 H45 VSS VSS VSS K3 M38 VSS VSS VSS P21 T3 VSS VSS VSS V6
E19 VSS VSS F9 H46 VSS VSS K4 M39 VSS VSS P22 T31 VSS VSS V7
E2 VSS VSS G10 H47 VSS VSS K40 M4 VSS VSS P25 T35 VSS VSS V8
E20 VSS VSS G11 H48 VSS VSS K41 M40 VSS VSS P26 T37 VSS VSS V9
E22 VSS VSS G12 H49 VSS VSS K42 M41 VSS VSS P27 T39 VSS VSS W10
E25 VSS VSS G14 H51 VSS SS K44 M43 VSS VSS P29 T41 VSS VSS W12
E34 VSS VSS G2 J10 VSS VSS K50 M49 VSS VSS P36 T47 VSS VSS W23
E39 VSS VSS G23 J14 VSS SS K6 M55 VSS VSS P4 T54 VSS VSS W34
E40 VSS VSS G27 J16 VSS VSS L1 M7 VSS VSS P41 T7 VSS VSS W42
E41 VSS VSS G28 J17 VSS VSS L10 M8 VSS VSS P42 T8 VSS VSS W43
E42 VSS VSS G29 J18 VSS VSS L13 N1 VSS VSS P43 T9 VSS VSS W44
E43 VSS VSS G31 J19 VSS VSS L16 N10 VSS VSS P44 U1 VSS VSS W45
E54 VSS VSS G40 J29 VSS VSS L27 N19 VSS VSS R1 U24 VSS VSS Y10
F1 VSS VSS G45 J36 VSS VSS L32 N23 VSS VSS R18 U32 VSS VSS Y16
F12 G48 J39 L36 N27 R21 U38 Y24
VSS VSS VSS VSS VSS VSS VSS VSS
F20 VSS VSS H10 J47 VSS VSS L45 N36 VSS VSS R32 U47 VSS VSS Y43
F29 VSS VSS H17 J6 VSS VSS L53 N43 VSS VSS R39 V1 VSS VSS Y9
F3 VSS VSS H18 J7 VSS VSS L54 N44 VSS VSS R4 V10 VSS VSS B48
F30 VSS VSS H19 J8 VSS VSS L55 N45 VSS VSS R40 V11 VSS
F32 VSS VSS H2 J9 VSS VSS L7 N46 VSS VSS R41 V12 VSS
F34 VSS VSS H20 K1 VSS VSS M1 N47 VSS VSS R42 V13 VSS
F43 VSS VSS H30 K22 VSS VSS M21 N7 VSS VSS T1 V31 VSS
F46 VSS VSS H35 K27 VSS VSS M25 P1 VSS VSS T12 V39 VSS
F53 VSS VSS H41 K35 VSS SS M34 P18 VSS VSS T2 V45 VSS
F7 VSS VSS H44 K38 VSS VSS M37 P20 VSS VSS T27 V5 VSS PAGE TITLE
SOC: GND-2
BOM_COST_GROUP=SOC
**OK2INTEGRATE**
SPI NOR (1.8V 64 M-BIT)
102 PP1V8_AWAKE
102 17 PP1V25_AWAKE_IO PP1V8_AWAKE 17 102
1 C1970
0.1UF
10%
1 C1974 1 C1975 2 6.3V
X6S
0.1UF 0 1UF 0201
R1971 1 R1970
10% 10
2 6.3V
X6S 2 6
X6S
3V
R1976 10K 100K PACK_OPTION=SMALL_NOR
R1974 0201 0201 33 5%
1/20W
5%
1/20W VCC
33 VCCA VCCB 1 2 SPI_SOCROM_1V8_MOSI 17 MF MF
SPI_SOCROM_MOSI_R 1 2 201 2 201 2
6 IN
5% U1974 5%
1/20W
U1970
1/20W 74AVC2T45 MF W25Q64JWUUIQ
MF SPI_SOCROM_MOSI 2 1A VSSOP 1B 7 SPI_SOCROM_1V8_MOSI_R 201 64MB-1.8V
201
SPI_SOCROM_CLK 3 2A 2B 6 SPI_SOCROM_1V8_CLK_R R1977 17 SPI_SOCROM_1V8_CLK 6 CLK USON DI(IO0) 5 SPI_SOCROM_1V8_MOSI 17
R1975 5 DIR 33
33 1 2 SPI_SOCROM_1V8_CLK 17 335S00494
6 IN SPI_SOCROM_CLK_R 1 2
SPI_SOCROM_1V8_CS_L
GND 5% 17 1 CS*
5% 1/20W DO(IO1) 2 SPI_SOCROM_1V8_MISO_R 17
1/20W MF SPI_SOCROM_WP_L 3 WP*/IO2
MF 201
1 1 7
R1972 R1973 201 HOLD*/RESET*/(IO3)
47K 47K GND EPAD
5% 5%
1/20W 1/20W
MF MF
2 201 2 201
102 17 PP1V8_AWAKE PP1V25_AWAKE_IO 17 102
1 C1983 1 C1984
0.1UF 0.1UF
10% 10%
2 6.3V
X6S U1983 2 6.3V
X6S
0201 SN74AXC1T45 0201
SOT- X3
VCCA VCCB
5
R1983 DIR R1984
SPI_SOCROM_1V8_MISO_R 1
33 2 SPI_SOCROM_1V8_MISO 3 4 SPI_SOCROM_MISO_R 1
33 2 SPI_SOCROM_MISO
17 A B OUT 6
5% 5%
1/20W 1/20W
MF GND MF
1
R1980 201 201
100K
5%
1/20W
MF
2 201
102 17 PP1V25_AWAKE_IO PP1V8_AWAKE 17 102
1 C1992 1 U1992 1 C1993

0.1UF
10%
R1992 SN74AXC1T45 0.1UF
10%
47K SOT-5X3
2 6.3V
X6S 5% 2 6.3V
X6S
0201 1/20W VCCA VCCB 0201
MF
2 201 5 DIR
SYNC_MASTER=REF_SOC_H13G SYNC_DATE=01/27/2020
6 IN SPI_SOCROM_CS_L 3 A B 4 SPI_SOCROM_1V8_CS_L 17
PAGE TITLE
SPI NOR
GND
BOM_COST_GROUP=SOC
2 1
TGA SPMI SE SOURCE TERMINATIONS TGA SPI SENSOR SOURCE TERMINATIONS TGA 1V2 TDM SOURCE TERMINATIONS
SENSOR_IMU
R2103 R2104 R2110
SPMI_SE_CLK_R 1
20 2 SPMI_SE_CLK SPI_AOP_GYRO_R1_MOSI_R 1
20 2 SPI_AOP_SENSOR_MOSI TDM_SPKRAMP_L_BCLK_R 1
20 2 TDM_SPKRAMP_L_BCLK
9 IN OUT 20 9 IN OUT 51 6 IN
MAKE_BASE=TRUE
5% PLACE_NEAR=U0600.BF20:10MM 5% 5%
1/20W 1/20W 1/20W TDM_SPKRAMP_L_BCLK 75
MF 201 MF PLACE_NEAR=U0600.BF14:10MM MF
201 201
R2102 SENSOR_IMU PLACE_NEAR=U0600.AK4:10MM

20 R2105
9 BI SPMI_SE_DATA_R 1 2 SPMI_SE_DATA BI 20 20
9 IN SPI_AOP_GYRO_R1_CLK_R 1 2 SPI_AOP_SENSOR_CLK OUT 51
R2111
5% PLACE_NEAR=U0600.BF21:10MM
1/20W
MF
%
1/20W TDM_SPKRAMP_L_R2D_R 1
20 2 TDM_SPKRAMP_L_R2D
201 6 IN
MF PLACE_NEAR=U0600.BF17:10MM MAKE_BASE=TRUE
201 5%
1/20W TDM_SPKRAMP_L_R2D 75
MF
201
TGA SPMI MPMU SOURCE TERMINATIONS TGA SPI IPD SOURCE TERMINATIONS
PLACE_NEAR=U0600.AJ5:10MM
R2107 R2100 R2112

SPMI_NUB_MPMU_CLK_R 20 SPMI_NUB_MPMU_CLK
9 IN 1 2 OUT 33
SPI_IPD_MOSI_R 1
20 2 SPI_IPD_MOSI TDM_SPKRAMP_L_FSYNC_R 1
20 2 TDM_SPKRAMP_L_FSYNC
6 IN OUT 84 6 IN
5% PLACE_NEAR=U0600.BB15:10MM MAKE_BASE=TRUE
1/20W 5% PLACE_NEAR=U0600 W1:10MM 5%
MF 201 1/20W 1/20W TDM_SPKRAMP_L_FSYNC 75
F MF
201 201
R2106 PLACE_NEAR=U0600.AJ4:10MM
SPMI_NUB_MPMU_DATA_R 1
20 2 SPMI_NUB_MPMU_DATA R2101
9 BI BI 33
5% SPI_IPD_CLK_R 1
20 2 SPI_IPD_CLK
PLACE_NEAR=U0600.BC14:10MM 6 IN OUT 84
1/20W
MF 201 5% PLACE_NEAR=U0600.AB1:10MM
1/20W
MF
201 6 OUT TDM_SPKRAMP_L_D2R TDM_SPKRAMP L_D2R 75
MA E_BASE=TRUE
TGA SPMI SPMU SOURCE TERMINATIONS

R2109
20 TGA SPI DFR SOURCE TERMINATIONS R2120
9 IN SPMI_NUB_SPMU_CLK_R 1 2 SPMI_NUB_SPMU_CLK OUT 29 20
R2113 6 IN TDM_SPKRAMP_R_BCLK_R 1 2 TDM_SPKRAMP_R_BCLK
5% PLACE_NEAR=U0600.BA12:10MM MAKE_BASE=TRUE
1/20W
MF 201 SPI_DFR_MOSI_R 1
20 2 SPI_DFR_MOSI
5%
1/20W TDM_SPKRAMP_R_BCLK
6 4 IN OUT 88 75
MF
5% PLACE_NEAR=U0600.AK2:10MM 201
1/20W
R2108 MF
201
PLACE_NEAR=U0600.AG3:10MM
SPMI_NUB_SPMU_DATA_R 1
20 2 SPMI_NUB_SPMU_DATA
9 BI BI 29
5% PLACE_NEAR=U0600.BC11:10MM R2114 R2121

1/20W
SPI_DFR_CLK_R 20 SPI_DFR_CLK
MF 201 4 IN 1 2 OUT 88
TDM_SPKRAMP_R_R2D_R 1
20 2 TDM_SPKRAMP_R_R2D
6 IN
5% PLACE_NEAR=U0600.AK1:10MM MAKE_BASE=TRUE
1 20 5%
MF 1/20W TDM_SPKRAMP_R_R2D 75
201 MF
201
TGA MISC DEBUG TEST-POINTS PLACE_NEAR=U0600.AG4:10MM
33 9 BI PMU_CLK32K_SOC
TP2126
1
A
TGA SPI TOUCHID SOURCE TERMINATIONS R2122
TP-P5
PLACE_SIDE=BOTTOM 20
R2115 6 IN TDM_SPKRAMP_R_FSYNC_R 1 2 TDM_SPKRAMP_R_FSYNC
TP2127 SPI_TOUCHID_MOSI_R 1
20 2 SPI_TOUCHID_MOSI 5%
MAKE_BASE=TRUE
6 IN OUT 80 9
106 9 BI TP_SOC_DOCK_ATTENTION 1
A 1/20W TDM_SPKRAMP_R_FSYNC 75
TP-P5
PLACE_SIDE=TOP 5%
1/20
MF
201
PLACE_NEAR=U0600.AF54:10MM
MF
01 LA E_NEAR=U0600.AF2:10MM
TP2128
9 BI TP_AON_SLEEP1_RESET_L 1
A
TP-P5
PLACE_SIDE=BOTTOM R2116
SPI_TOUCHID_CLK_R 1
20 2 SPI_TOUCHID_CLK
TP2129 6 IN OUT 80 89
89 9 BI SMC_FIXTURE_MODE_L 1
A PLACE_SIDE=BOTTOM 5% 6 OUT TDM_SPKRAMP_R_D2R TDM_SPKRAMP_R_D2R 75
1/20W PLACE_NEAR=U0600.AF55:10MM MAKE_BASE=TRUE
TP-P5 MF
201
TGA JTAG TEST-POINTS

TP2110
EUSB SERIES RESISTORS AND TEST POINTS R2130
SOC_JTAG_SEL 1 TDM_CODEC_BCLK_R 1
20 2 TDM_CODEC_BCLK
9 4 BI A R2150 6 IN OUT 76
TP-P5
EUSB_ATC0_P 1
0 2 EUSB_ATC0_R_P
5%
1/20W
5 BI BI 89
MAKE_BASE=TRUE MF
TP2111 5% (TP ON FCT PAGE) 201
89 56 9 BI SWD_SOC_SWCLK 1
A PP2190 1
1/20W
MF
EUSB_ATC0_R_P 60
PLACE_NEAR=U0600.AK5:10MM
TP-P5 PP
P4MM 0201
SM
PLACE_NEAR=U0600.BB54:10MM
TP2112 R2151 R2131
9 BI TP_JTAG_SOC_TDI 1
A
TP-P5 EUSB_ATC0_N 1
0 2 EUSB_ATC0_R_N TDM_CODEC_R2D_R 1
20 2 TDM_CODEC_R2D
5 BI BI 89 6 IN OUT 76
MAKE_BASE=TRUE
5% (TP ON FCT PAGE) 5%
TP2113 PP2191 1/20W EUSB_ATC0_R_N 60 1/20W
9 BI TP_JTAG_SOC_TDO 1
A PP MF MF
TP-P5
P4MM 0201 201
SM
PLACE_NEAR=U0600.BB55:10MM PLACE_NEAR=U0600.AJ7:10MM
TP2114 R2152
89 56 9 BI SWD_SOC_SWDIO 1
A 0
TP-P5
5 BI EUSB_ATC1_P 1 2 EUSB_ATC1_R_P R2132
MAKE_BASE=TRUE
5% 20
TP2115 PP2192 1/20W
MF
PP2196 EUSB_ATC1_R_P 60 6 IN TDM_CODEC_FSYNC_R 1 2 TDM_CODEC_FSYNC OUT 76
TP_JTAG_SOC_TRST_L 1 PP PP
9 BI A P4MM 0201 P4MM 5%
1/20W
SM S
TP-P5 PLACE_NEAR=U0600.BC54:10MM PLACE_NEAR=UF750.A1:10MM MF
R2153 201
EUSB_ATC1_N 1
0 2 EUSB_ATC1_R_N PLACE_NEAR=U0600.AM4:10MM
5 BI
TGA DEBUG TEST-POINTS PP2193 5%
1/20W PP2197
MAKE_BASE=TRUE
EUSB_ATC1_R_N 60
PP MF PP
TP2120 P4MM 0201 P4MM
SM SM
5 BI TP_TST_CLKOUT 1
A PLACE_NEAR=U0600.BC55:10MM PLACE_NEAR=UF750.B1:10MM
TP-P5
PLACE_SIDE=TOP
TP2121 60 9 BI EUSB_DBG_P
1 PLACE_SIDE=BOTTOM
A
TP-P5 PP21A0 PP21A
PP PP
TP2122 P4MM P4MM
SM SM
106 5 BI TP_SOC_AMUX_OUT 1
A PLACE_NEAR=U0600.BF24:10MM PLACE_NEAR UF 00.A1:10MM
TP-P5
PLACE_SIDE=BOTTOM SYNC_MASTER=AITKEN_T668_MLB SYNC_DATE=09/18/2019
PAGE TITLE
TP2123 EUSB_DBG_N
1
60 9 BI
PROJECT SUPPORT (1/2)
A PLACE_SIDE=TOP PP21A2 PP21A3
TP-P5 PP PP
P4MM P4MM
SM SM
PLACE_NEAR=U0600.BE24:10MM PLACE_NEAR=UF700.B1:10MM
TP2124
89 56 6 BI UART_DEBUGPRT_D2R 1
A
TP-P5
PLACE_SIDE=BOTTOM
TP2125
89 56 6 BI UART_DEBUGPRT_R2D 1
A
TP-P5
PLACE_SIDE=BOTTOM
BOM_COST_GROUP=SOC
2 1
94 89 56 5 IN SOC_DFU_STATUS
NOSTUFF
1
R2200
47K
5%
1/20W
MF
2 201
NOSTUFF
R2205
MPMU_BUTTONO1 1
0 SOC_REQUEST_DFU1
33 N OUT 5
5%
1/20W
MF
0201
OPTION FOR SW TO READ POWER BUTTON, NOT USED
7 IN LPDPRX0_RCAL_POS
LPDPRX0_RCAL_NEG
7 IN
7 IN LPDPRX1_RCAL_POS
7 IN LPDPRX1_RCAL_NEG
NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1 1 1 1
R2201 R2202 R2203 R2204
47K 47K 47K 47K
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
2 201 2 01 2 201 2 201
SOC_THROTTLE2
R2299
RSVD_GPU_TRIGGER1_L 1
0 2 SOC_THROTTLE_TRIGGER2
34 33 IN OUT 6
5%
1/ 0W
MF
0201
<RDAR://59954844>
SYNC_MASTER=AITKEN_T668_MLB SYNC_DATE=11/11/2019
PAGE TITLE
PROJECT SUPPORT (2/2)
BOM_COST_GROUP=SOC
Timing Requirements:
- VBAT supply ramp time: 20ms
Ceres - Secure Element

*** OK2INTEGRATE ***
101 PP1V8_S2 PP1V25_S2 102

Per TGA Power Block Diagram v0.3 IccMax SE only: 125mA IccMax SE only: 10mA Based on SPMI only use case
U5000.F9:3mm U5000.F8:3mm U5000.E7:3mm
C5014 1 C5002 1 C5003 1

1.0UF 0.22UF 0.22UF
20% 20% 20%
6.3V 2 6.3V 2 6.3V 2
X5R X5R X5R
0201-1 0201 0201
R5030
0
VDDBOOST_SE 1 2 VUP_SE
1/20W MF 0201 5%
VDDPLL_SE
VDDNV_SE
VDDC_SE PP3V8_AON 20 101
IccMax: 100mA As per NXP preliminary stimate, final pending
C5051 1
U5000.B5:3mm U5000.E8:3mm U5000.E9:3mm
2.2UF
20%
C5008 1 C5009 1 C5010 1 10V 2
X5R
0.22UF 0.22UF 0.22UF 0201
20% 20% 20%
6.3V 2 6.3V 2 6.3V 2
X5R X5R X5R
0201 0201 0201
NCNC NC NC NC
D4 NFC_CLK_32K U5000 SE_GPIO0 H3

NC
H6 NFC_CLK_REQ SE_GPIO1 F3 Pulls to be added in system, can be NC'd if unused
NC SN210VUK/B101V7 NC
A6 NFC_CLK_XTAL1 WLCSP SE_I2C_SCL G1 NC_I2C_SE_SCL 107
IN
20 SE_CTLR_FW_DWLD G4 NFC_DWL_REQ OMIT_TABLE SE_I2C_SDA H1 NC_I2C_SE_SDA BI 107
TP_SE_GPIO0 F6 NFC_GPIO0 SE_ISO_CLK F2

NC
J7 50K internal pull-down F1
NC NFC_GPIO1 SE_ISO_IO NC
J5 NFC_GPIO2_AO SE_ISO_RST G3
NC NC
NC NFC_GPIO3_AO G2
SE_SPI_CLK NC
R5042 47K
1 2 UART_SE_R2D_RTS_L E6 NFC_HSU_CTS SE_SPI_CS J2
NC
1/20W MF 201 5%
NO_TEST NC_UART_SE_D2R_CTS_L F5 NFC_HSU_RTS SE_SPI_MISO H2
NC
R5041 47K
1 2 UART_SE_R2D G5 NFC_HSU_RX SE_SPI_MOSI E2
NC
1/20W MF 201 5% E5
NC_UART_SE_D2R NO TEST NFC_HSU_TX D2
TXVCASCP NC
E4 NFC_I2C_SCL TXVCASCN D1
NC NC
F4 NFC_I2C_SDA
NC RXVCM B3
NC
J6 NFC_IRQ TXVCM C2
NC NC
NFC_SIM_SWIO1 TX1 A1
NC NC
J8 NFC_SIM_SWIO2 TX2 C1
NC NC
18 IN SPMI_SE_CLK H7 NFC_SPMI_SCLK VCASCHI D7
NC
18 BI SPMI_SE_DATA G7 NFC_SPMI_SDATA VCASCLO C7
NC
1 1 2 SE_DEV_WAKE H5 NFC_WKUP_REQ BOOST_LX B8 PP3V8_AON 20 101
R5050 R5051 B6 BOOST_LX B9
1M 1M NC NFC_XTAL2
5% 5% B7
1/20W 1/20W VHV VHV_SE
MF MF
2 201 2 201 G6 TM VTUNE D3
NC
A3 RXP VEN D5 SE_PWR_EN 33
IN
A4 RXN
VREF C5 VREF_SE
1 C5004 1 C5017
0.1UF 0.22UF
10% 20%
2 6.3V
CERM-X5R 2 6.3V
X5R
0201 0201
SYNC_MASTER=REF_SE_CERES SYNC_DATE=02/26/2020
PAGE TITLE
Secure Element
R5000 47K 1 2
5% 1/20W MF 201
SE_CTLR_FW_DWLD 20
R5006 47K 1 2
5% 1/20W MF 201
SE_DEV_WAKE 20
<rdar://problem/52067756> [SN200V] Wired Mode SE Only Reference Design Material

<rdar://problem/45108950> Mac - Venus Reference guide and De-coupling requirements BOM_COST_GROUP=SECURE ELEMENT
BATTERY (BMU) LOGIC CONNECTOR BATTERY (BMU) FLEX SOLDER PADS
BMU POWER FLEX IS SOLDERED TO MLB.
518S00014 998-03828
CRITICAL CRITICAL
J5151 J5150
FF18-10A-R11AD-B-3H
F-RT-SM-A PWR-MLB-X520
11 TP5103 HB-SM
1
A
TP-P5
1 PLACE_SIDE=BOTTOM 11 10
2 I2C_SMC_PWR_3V3_SCL 43
IN
3 I2C_SMC_PWR_3V3_SDA 43
BI 12
4 9
5
TP5104
CRITICAL 1
NC A
6
NC U5150 TP-P5
PLACE_SIDE=BOTTOM
1 8
7 RCLAMP3552T
8 SLP1006N3T TP5105
1
NC A
9 2 7 TP- 5
NC PLACE_SIDE=BOTTOM
10
12 3
6 PPVBAT_AON 101
C5150 1 C5160 1 C5161 1 C5162 1

0.1UF 1UF 3PF 3PF
TP5100 89 SYS_DETECT_L PP3V8_AON 101
4 5 10%
25V 2
10%
25V 2
+/-0.1PF
25V 2
+/-0.1PF
25V 2
1 376S00282 X5R X5R C0G C0G
A NOSTUFF 402 603-1 201 0201
TP P5
1
3 D Q5155 1
R5156
PLACE_SIDE=TOP R5155 NTNS4CS69N
XDFN 10K
10K SYM_VER_2
5%
5% 1/16W
1/16W MF-LF
MF-LF 2 402
TP5101 2 402
1 2 S G 1 TP5102
A 89 SYS_DETECT 1
TP-P5 A PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
PLACE_SIDE=TOP TP-P5
PLACE_SIDE=TOP
632-00731 1 PCBA,FLEX,BMU PWR,X502 J5150 CRITICAL
PLACE_SIDE=TOP PLACE_SIDE=BOTTOM
SYS_DET_BTN SYS_DET_BTN
S5190 S5191
STO-060A16AE STO-060A16AE
SM SM
705S00069 705S00069
SYNC_MASTER=AITKEN_T668_MLB SYNC_DATE=09/18/2019
PAGE TITLE
BATTERY CONNECTORS
BOM_COST_GROUP=BATTERY
*** OK2INTEGRATE *** CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE
CKPLUS_WAIVE CAPDERATE CKPLUS_WAIVE=CAPDERATE
98 89 PPDCIN_AON_CHGR_R
MIN_LINE_WIDTH=0.6000 CRITICAL CRITICAL CRITICAL CRITICAL
MIN_NECK_WIDTH=0.1800 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 1 1 1 1
VOLTAGE=20V 1
C5201 1
C5202 1
C5203 1 C520A 1 C520B 1 C520C 1 C520D C5250 C5251 C5252 C5253
2.2UF 2.2UF 2.2UF 2.2UF 68UF 68UF 68UF 68UF
6.8UF 6.8UF 6.8UF 20% 20% 20% 20%
20% 20% 20% 20%
20% 20% 20% 2 16V 2 16V 2 16V 2 16V
2 35V-0.09OHM 2 35V-0.09OHM 2 35V-0.09OHM 2 35V
X5R-CERM 2 35V
X5R-CERM 2 35V
X5R-CERM 2 35V
X5R-CERM
POLY-TANT POLY-TANT POLY-TANT POLY-TANT
POLY-TANT POLY-TANT POLY-TANT CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM
CASE-B1-2-SM CASE-B1-2-SM CASE-B1-2-SM 0402 0402 0402 0402 CAPMAT=POLY-TANT CAPMAT=POLY-TANT CAPMAT=POLY-TANT CAPMAT=POLY-TANT
CAPMAT=POLY-TANT CAPMAT=POLY-TANT CAPMAT=POLY-TANT
PACK_IGNORE=TRUE
PACK_OPTION=CHGR_60W PACK_OPTION CHGR_75W
PACK_IGNORE=TRUE
PACK_O TION=CHGR_60W PACK_OPTION=CHGR_75W
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

1 1 1 1 1 1
C520 C5205 C5206 C5205 C5206 C5207
6.8UF 6.8UF 6.8UF 6.8UF 6.8UF 6.8UF CRITICAL CRITICAL CRITICAL CRITICAL
20% 20% 20% 20% 20% 20%
2 35V-0.09OHM
POLY-TANT
2 35V-0.09OHM
POLY-TANT
2 35V-0.09OHM
POLY-TANT
2 35V-0.09OHM
POLY-TANT
2 35V-0.09OHM
POLY-TANT
2 35V-0.09OHM
POLY-TANT
1
C5254 1
C5255 1 C5256 1 C5257 1 C5258
CASE-B1-2-SM CASE-B1-2-SM CASE-B1-2-SM CASE-B1-2-SM CASE-B1-2-SM CASE-B1-2-SM 33UF 33UF 2.2UF 2.2UF 1000PF
CAPMAT=POLY-TANT CAPMAT=POLY-TANT CAPMAT=POLY-TANT CAPMAT=POLY-TANT CAPMAT=POLY-TANT CAPMAT=POLY-TANT 20% 20% 20% 20% 10%
CRITICAL 2 16V 2 16V 2 25V
X5R 2 25V
X5R 2 25V
X7R
PACK_IGNORE=TRUE TANT TANT
PACK_OPTION=CHGR_60W
PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W
PACK_IGNORE=TRUE
L5230 CASED12-SM CASED12-SM 0402-1 0402-1 0201
PACK_OPTION=CHGR_60W PACK_OPTION=CHGR_75W PACK_OPTION=CHGR_75W

2.7UH-20%-12.5A-0.0196OHM CAPMAT=POLY-TANT CAPMAT=POLY-TANT
PACK_IGNORE=TRUE
22 CHGR_PHASE1 1 2 CHGR_PHASE2 22 PACK_OPTION=CHGR_40W
CRITICAL DIDT=TRUE IHLP4040BD-PIMA102D-COMBO DIDT=TRUE PACK_IGNORE=TRUE
SWITCH_NODE=TRUE SWITCH_NODE=TRUE PACK_OPTION=CHGR_40W
R5220 NO_XNET_CONNECTION=1
(AMON)
152S00198
CRITICAL
0.01 2-CELL: 0.02 OHM
FROM USB-C SOURCE 0 5%
0. W 3-CELL: 0.01 OHM F5200 TO SYSTEM
MF
0306 107S00053 12A-32V-0.0045OHM
101 22 PPDCIN_USBC_AON 1 2 97 89 22 PPVBAT_AON_CHGR_REG 1 2 PPBUS_AON 101
3 4 MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=13.05V 1206
PP5201
P2MM
PP5211
P2MM
SM
1 22 CHGR_GATE_Q1 1
SM CRITICAL CRITICAL
PP PP ALLOW_APPLE_PREFIX=Q ALLOW_APPLE_PREF X=Q
PACK_OPTION=CHGR_TP_TOP PACK_OP ION=CHGR_TP_BOT
PP5202
P2MM
PP5212
P2MM
SM
PP
1 22 CHGR_GATE_Q2 1
M
PP
Q5230 Q5240
PACK_OPTION=CHGR_TP_TOP PACK_OPTION=CHGR_TP_BOT PPVBAT_AON_CHGR_R
MIN_LINE_WIDTH=0.6000
PP5203 PP5213 MIN_NECK_WIDTH=0.1500 CRITICAL CRITICAL CRITICAL CRITICAL
VOLTAGE=13.05V
P2MM
SM
P2MM SM CHGR_GATE_Q1 CHGR_GATE_Q2 CHGR_GATE_Q3 22 CHGR_GATE_Q4
1 C5265 1 C5266 1 C5267 1 C5268
PP
1 22 CHGR_GATE_Q3 1
PP 48 CHGR_CSI_P CHGR_CSI_N 48
22
DIDT=TRUE
22
DIDT=TRUE DIDT=TRUE DIDT=TRUE
22
2.2UF 2.2UF 0.1UF 0.01UF
SWITCH_NODE=TRUE GATE_NODE=TRUE GATE_NODE=TRUE SWITCH_NODE=TRUE 20% 20% 10% 10%
PLACE_SIDE=TOP PLACE_SIDE=BOTTOM 2 25V
X5R 2 25
X5R 2 25V
X5R 2 25V
X5R-CERM
PACK_OPTION=CH R_TP_TOP PACK_ PTION=CHGR_TP_BOT PLACE_NEAR=U5200.D5:2M PLACE_NEAR=U5200.C5:2MM 0402-1 0402 0201 0201
1 1 2 2
PP5204 PP5214 R5221 R5222 XW5230 XW5240
P2MM P2MM 1.00 1.00 CHGR_LX1 SM SM
CHGR_LX2
SM M 1% 1% DIDT=TRUE DIDT=TRUE
PP
1 22 CHGR_GATE_Q4 1
P 1/20W 1/20W SWITCH_NODE=TRUE SWITCH_NODE=TRUE
MF-LF MF-LF 1 1
PLACE_SIDE=TOP PLACE_SIDE=BOTTOM 0201 2 2 0201 CRITICAL CRITICAL NO_XNET_CONNECTION=1
PACK_OPTION=CHGR_TP_TOP PACK_OPTION=CHGR_TP_BOT
CHGR_CSI_FILT_P CHGR_CSI_FILT_N
1 C5230 C5240 1 CRITICAL CRITICAL
PP5205 PP5215 0.1UF 0.1UF R5260(BMON) Q5265
P2MM P2MM 10% 10%
SM SM CRITICAL CRITICAL 2 25V 25V 0.005 SI7655DN-COMBO
1 22 CHGR_PHASE1 1 X7R-CERM-1 X7R-CERM-1 2 1% 2-CELL: 0.010 OHM
3-CELL: 0.005 OHM PWRPK-1212-8
PP
PLACE_SIDE=TOP
PP
PLACE_SIDE=BOTTOM
C5221 1 1 C5222 0402 0402 1W
MF 107S00087
SYM-VER-2
TO/FROM BATTERY
PACK_OPTION=CHGR_TP_TOP PACK_OPTION=CHGR_TP_BOT 0.047UF 0.047UF CHGR_BOOT1_RC CHGR_BOOT2_RC 0612-8
10% 10% DIDT=TRUE DIDT=TRUE 1 2 3 S
50V 2 50V
PP5206 PP5216 CER-X7R 2 CER-X7R SWITCH_NODE=TRUE SWITCH_NODE=TRUE 3 4 2 D 5 PPVBAT_AON 101
P2MM P2MM 0402 0402 1 1
SM SM R5230 R5240 1
CHGR_PHASE2
1 22 1 0 0 VOLTAGE=13.05V
PP
PLACE_SIDE=TOP
PP
PLACE SIDE=BOTTOM
5%
1/16W
5%
1/16W G
1 C5269
PACK_OPTION=CHGR_T _ O PACK_OPT ON C GR_TP_BOT MF-LF MF-LF 0.1UF
CRIT CAL 4 10%
2 402 402 2
2 25V
PP5207 C5220 C5264 X5R
P2MM CHGR_BOOT1 CHGR_BOOT2 1000PF 0201
SM
1 CHGR_EN_MVR 0.47UF DIDT=TRUE DIDT=TRUE 1 2
PP 22 23
1 2 SWITCH_NODE=TRUE SWITCH_NODE=TRUE
PACK_OPTION=CHGR_TP 10%
20% R5275 25V
PP5208 97 89 22 PPVBAT_AON_CHGR_REG
4V
CERM-X5R-1 1
4.7 2
XW5260
SM
X7R
0201 1 C5263
P2MM 201
SM NO_XNET_CONNECTION=1 5% 1 2 4700PF
1 CHGR_INT_1V8_L 22 23 1/20W 10%
PP
PACK_OPTION=CHGR_TP
C5278 1 VOLTAGE=5V MF
201
VOLTAGE=5V PLACE_NEAR=Q5240.3:2MM 2 25V
CER X5R
2.2UF 23 PPCHGR_VDDA PPCHGR_VDDP 48 CHGR_CSO_P CHGR_CSO_N 48
0201
20%
35V CRITICAL CRITICAL 1
X5R-C RM 2 PLACE_NEAR=U5200. 4:2MM PLACE_NEAR=U5200.B4:2MM
0402 1 C5275 C5277 1 1
2.2UF
20%
10UF
20%
R5261 R5262
1.00 1.00 MIN_LINE_WIDTH=0.2000
2 25V 10V 2 1% 1% MIN_NECK_WIDTH=0.1000
X5R-CERM
0402-1
X5R
0603-1 1/20W 2 1/20W
MF-LF MF-LF
0201 2 0201
101 22 PPDCIN_USBC_AON
3
CHGR_CSO_FILT_P CHGR_CSO_FILT_N CRITICAL <rdar://37259372&39763505>
1
R5215 CRITICAL CRITICAL
Q5270 D
750K PPDCIN_USBC_AON 22 101
1% C5261 1 1 C5262
/20W
MF U5200 0.047UF
1 %
0.047UF
10%
NTNS4CS69N G 1
1
1 B5 P_IN ISL9240 IGATE_Q1 H1 50
CER-X7R 2 2 50
CER-X7R
XDFN S R5271
CHGR_AUX_DET C5 WCSP F1 0402 0402
SYM_VER_1 200K
CSIN BOOT1 1%
D5 G1 1/20W
NOSTUFF CSIP CRITICAL LX1 2 MF
C5216 1 1 A5 E1 2 201
0.01UF
R5216 D3
PBUS_PWR GATE_Q2
D1 CRITICAL SAVE_BAT_S SAVE_BAT_G
10% 255K AUX_DET GATE_Q3
25V
X5R-CERM 2
1%
1/20W LX2 B1 C5260
020 MF C1 0.47UF
2 201 SCH SYMBOL BOOT2 1 2
A1 CRITICAL
353S01525 GATE_Q4
PBUS A3 CHGR_PBUS_SNS
20% 4V
CERM-X5R-1
1
R5263 R5270 1 D5270
DFN0201
MIN_LINE_WIDTH=0.2000 201 1K 24K
CSOP A4 MIN_NECK_WIDTH=0.1000 NO_XNET_CONNECTION=1 5% 5% ALLOW APPLE_PREFIX=D
101 PP1V8_S2 F5 VDDIO1P8 B4 1/20W /2 W
I2C_SMC_PWR_1V8_SDA G5 CSON MF MF GDZ5V6LP3-55
43 BI SDA 2 201 201 2
BGATE B3 CHGR_BGATE
C5280 1 43 IN I2C_SMC_PWR_1V8_SCL H5 SCL
VBAT C3 CHGR_VBAT
1.0UF 34 IN CHGR_RST_IN G2 SMC_RST_IN
20%
6.3V 2 G3 EN_VR1 F2 NC_CHGR_EN_VR1 107
HPWR_EN*
X5R SMC_RST* H4 TP_CHGR_SMC_RST_L
0201-1 CHGR_COMP E5 COMP H3 CHGR_INT_1V8_L
IRQ* OUT 22 23
H:3-C LL G4 CELL CBC_ON H2 TP_CHGR_CBC_ON

L:2 CELL
(5V) EN_MVR F4 CHGR_EN_MVR OUT 22 23
B2 NC0 (OD) AUX_OK F3 CHGR_AUX_OK 23
OUT
SYNC_MASTER=REF_CHARGER_SUONA SYNC_DATE=02/25/2020
C2 NC1 AMON D4 CHGR_AMON 44 48
O T PAGE TITLE
NOSTUFF E4 NC2 BMON C4 CHGR_BMON
CRITICAL CRITICAL
OUT 4 48
PBUS SUPPLY & BATTERY CHARGER
C5270 1 C5271 1
0.12UF 0.12UF
10% 10%
10V 2 10V 2
X5R X5R
0402 0402
CHGR I2C Level Translation

SMBUS_CHGR_1V8_[SCL/SDA]: Level translation circuit to be placed in project specific I2C page.
CHGR_INT_L Level Translation

Stuff R5320 in case, glitch during power sequencing is a concern.
101 22 PP1V8_S2 PP1V25_S2 102
NOSTUFF PLACE_NEAR=U5320.6:5MM
1
R5320 1 C5320
47K 0.1UF
5% 10%
1/20W 2 6.3V
CERM-X5R
MF 0201
2 201
U5320
SN74AUP1G17
VCC SON >> SOC NUB_GPIO_5
22 IN CHGR_INT_1V8_L 2 A Y
4 CHGR_INT_L OUT 106
GND
NC
NC
CHGR_AUX_OK Pull Up
Pull up to MPMU LDO9, or rely on MPMU internal pull up.
OK, to compl te y remove pull up , but co sult PMU architecture and check OTP before that.
104 PP1V8_AON
NOSTUFF
1
R5330
47K
5%
1/20W
MF
2 201
>> MPMU GPIO2

22 IN CHGR_AUX_OK CHGR_AUX_OK OUT 33
MAKE_BASE=TRUE
Delay for 3.8V VR Enable

RDAR://59315467
NOSTUFF
R5340 and C5340 might need tweaking afer charz.
R5341
1
0 2
D5340
R5342
1
2 2K 2 CHGR_EN_MVR_A
X3DFN2
A K
5%
1/20W
MF
0201
5%
1/20W NSR01L30MXT5G-COMBO 22 PPCHGR_VDDA
MF
201 PLACE_NEAR=U5340.5:2MM
1 C5341
0.1UF
10%
2 6.3V
CERM-X5R
0201
5 U5340
R5340 74LVC1G17
X2SON5
CHGR_EN_MVR 1
200K 2 CHGR_EN_MVR_DLY 2 4 P3V8AON_PWR_EN
22 IN OUT 24
1
1/20W NC
MF
201
1 C5340 1 3
1UF
20%
2 10V
X5R PLACE_NEAR=U5200:5MM
0201
SYNC_MASTER=REF_CHARGER_SUONA SYNC_DATE=04/01/2020
PAGE TITLE
BATTERY CHARGER SUPPORT
*** OK2RELEASE ***
3V8 AON CONTROLLER

105 25 PPBUS_VMAIN_VIN_ISNS
5.5 < VIN < 13.5 V 1 C5704 U5700 F_SW IS REGISTER CONTROLLED
RAA225501A-BOM1 ICCMAX 30A DESIGN: 1 MHZ
2.2UF QFN
20%
2 25V
X6S-CERM OMIT_TABLE
0402 8 VIN BOOT1 4 P3V8AON_BST1 IN 25
138S00042
BYPASS=U5700.8::15MM
UGATE1 3 P3V8AON_DRVH1 OUT 25
"BOM1" SCH SYMBOL
FOR 30A OTP PHASE1 2 P3V8AON_SW1 IN 25
26 PP5V_S2_P3V8AON_VDRV 6 VDRV
LGATE1 1 P3V8AON_DRVL1 OUT 25
4.75 < VDRV < 5.5 V 1 C5700 APN OF SYMBOL

VDRV IS EXTERNAL OPTION TO 10UF 353S02326
20%
POWER IC INSTEAD OF VIN 2 16V
X6S
0603-1 BOOT2 29 P3V8AON_BST2 IN 2
TO SAVE POWER
138S00248
BYPASS=U5700.6::15MM UGATE2 30 P3V8AON_DRVH2 OUT 25
0603 SIZE REQUESTED BY DCDC
PHASE2 31 P3V8AON_SW2 IN 25 99
101 PP5V_AON 7 LDO5 LGATE2 32 P3V8AON_DRVL2 OUT 25
4.75 < LDO5 < 5.25 V 1 C5702

MAX I_OUT TYP 160 MA 10UF
20%
LDO5 NOT TO BE USED BY 2 16V
X6S BOOT3 28 P3V8AON_BST3 IN 25
SYSTEM IN 30A DESIGNS 0603-1

138S00248 UGATE3 27 P3V8AON_DRVH3 OUT 25
PHASE3 26 P3V8AON_SW3 IN 25 99
LGATE3 25 P3V8AON_DRVL3 OUT 25

25 P3V8AON_PVCC 5 PVCC
ONLY FOR USE BY GATE 1 C5701

DRIVE CIRCUITRY 10UF
20%
2 16V
X6S
0603-1
138S00248
R5710 VSEN 15 P3V8AON_VSENSE IN 25
P3V8AON_PWR_EN 1
0 2 P3V8AON_PWR_EN_R 12 ENABLE
23 IN (9M PD)
5% VIH_MAX 1.07 V VRTN 16 P3V8AON_VRTN IN 25
1/20W
MF VIL_MIN 0.63 V
0201
R5711
P3V8AON_LPM 1
0 2 P3V8AON_LPM_R 13 LPM
33 IN (9M PD)
5% VIH_MAX 1.1 V
1/20W
MF VIL_MIN 0.5 V
0201
P3V8AON_LPM
CSP1 19 P3V8AON_ISEN1_P IN 2
101 PP5V_AON CSN1 20 P3V8AON_ISEN1_N IN 25

117 24 I2C_P3V8AON_SCL 10 SCL
1
R5712 117 24 I2C_P3V8AON_SDA 9 SDA
47K VIH_MAX 1.1 V
5%
1/20W VIL_MIN 0.5 V
MF CSP2 21 P3V8AON_ISEN2_P IN 25
2 201 GND'ED FOR POR (DATASHEET TABLE 1.5)
PU TO INT LDO5 OR OTHER RAIL
CSN2 22 P3V8AON_ISEN2_N IN 25
P3V8AON_FAULT_L 14 FAULT* (OD)

FAULT PULL DOWN CURRENT 1-2 MA TYPICAL
R5750
P3V8AON_IMON 1M P3V8AON_IMON_P3V8AON 18 IMON
1 2 (0-4.5V) CSP3 23 P3V8AON_ISEN3_P IN 25
IMON NOT TO BE USED SYSTEM SIDE 5%

1/20W
<RDAR://58648650> NOSTUFF MF CSN3 24 P3V8AON_ISEN3_N IN 25
201
IMON IS 2.52 V @ 30 A 1 C5751 1
R5751 117S0009
P3V8AON_GPIO 11 GPIO
VENDOR REQUIRES R > 1M, C < 50 PF 10PF 2.21K
5% 1% OPEN FOR PRODUCTION APPLICATION
2 25V
C0G 1/20W
0201 MF PER DATASHEET REV 1.0
131S00003 2 201
118S0199
P3V8AON_SS 17 SOFTSTART
LONG STARTUP TIME SO INRUSH
NOSTUFF BELOW 0.5A USB LIMIT
1
R5700 1 C5703 EPAD
100K 0.22UF
5% 10%
1/20W
MF 2 25V
X5R
2 201 0201-1
132S00202
TPT_P3V8AON_PU_RAIL
TP5700
1 TP
3V8_AON_I2C-DEV 3V8_AON_I2C-DEV TP-P5
3V8_AON_I2C-DEV
NOSTUFF NOSTUFF
1 1
R5760 R5761
1K 1K
5% 5%
1/20W 1/20W
MF MF
2 201 2 201 SYNC_MASTE =REF_VR_ICEMAN SYNC_DATE=04/09/2020
CKPLUS_WAIVE=I2C_PULLUP PAGE TITLE
I2C_P3V8AON_SCL
CKPLUS_WAIVE=I2C_PULLUP
I2C_P3V8AON_SDA
24 117
24 117
POWER: 3V8 AON (1/2)
3V8_AON_I2C-DEV 3V8_AON_I2C-DEV 3V8_AON_I2C-POR 3V8_AON_I2C-POR
1 1
R5762 R5763
0 0
5% 5%
TA LE_5_ EAD
1/20W 1/20W
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION MF MF
TA LE_5_ TEM 2 0201 2 0201 GND GND
353S02326 1 IC,RAA225501,3-PH VOLT REG,TQFN32 U5700 CRITICAL P3V8AON_IC:A0 MAKE_BASE=TRUE MAKE_BASE=TRUE
TA LE_5_ TEM
353S02472 1 IC AA 5501B,ICE,BOM1,A1,OTP-R0B0,QFN32 U5700 CRITICAL P3V8AON_IC:A1_R0B0

BOM_COST_GROUP=PLATFORM POWER
8 2
*** OK2RELEASE ***
105 25 24 PPBUS_VMAIN_VIN_ISNS
CRITICAL C ITICAL CRITIC L CRITICAL CRITICAL CRITICAL MIRROR_WITH=C5804
R5804 1
C5800 1
C5801 1
C5800 1
C5801 1
C5800 1
C5801 1 C5804 1 C5805
P3V8AON_DRVH1 1
2.2 2 P3V8AON_DRVH1_R 33UF 33UF 33UF 33UF 68UF 68UF 2.2UF 2.2UF
24 IN
MIN_LINE_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000 CRITICAL 20% 20% 20% 20% 20% 20% 20% 20%
MIN_NECK_WIDTH=0.1000 5% MIN_NECK_WIDTH=0.1000 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 25V 2 25V
GATE_NODE=TRUE
DIDT=TRUE
1/20W
MF
GATE_NODE=TRUE
DIDT=TRUE
Q5800 TANT
CASE-T
TANT
CASE-T
TANT
CASED12-SM
TANT
CASED12-SM
POLY-TANT
CASE-D2E-SM
POLY-TANT
CASE-D2E-SM
X6S-CERM
0402
X6S-CERM
0402
201 CSD58889Q3D 128S00009 128S00009 128S0436 128S0436 128S0264 128S0264 138S00042 138S00042
117S0056 Q3D CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE
<RDAR://59524111> PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_ GNORE=TRUE PACK_IGNORE=TRUE
R5803 C5811 376S00012 3V8_AON_PBUS-B12 3V8_AON_PBUS-B12 3V8_AON PBUS-D12 3V8_AON_PBUS-D12 3V8_AON_PBUS-D2 3V8_AON_PBUS-D2
0 0.1UF VIN 1
24 OUT P3V8AON_BST1 1 2 P3V8AON_BST1_RC 1 2 P3V8AON_SW1
MIN_LINE_WIDTH=0.2000 MIN_LINE_WIDTH=0 2000 MIN_ INE_WIDTH=0.2000 107S00373
MIN_NECK_WIDTH=0.1000 5% MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000 3
DIDT=TRUE
SWITCH_NODE=TRUE
1/20W
F
DIDT=TRUE
SWITCH_NODE=T UE
10%
25V SWITCH NODE=TRUE
DIDT TRUE
TG
CRIT C L R5800
0201 X7R-CERM-1 6 0 004
117S0201 0402
132S0438 4 TGR VSW 7 L5800 1%
1/3W ICCMAX = 30 A
OUT 24 1UH-20%-11A-0.0127OHM LF
NOSTUFF 8 0306
99 P3V8AON_VSW1 1 2 PP3V8AON_PH1 1 2 PP3V8_AON 101
D5800 MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 PIHA052D-SM MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 3 4 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
25 24 P3V8AON_PVCC A K SWITCH_NODE=TRUE 152S00265 VOLTAGE=5V NO_XNET_CONNECT ON=1
1 1 1 1 1 1
5 BG DIDT=TRUE C5890 C5891 C5892 C5893 C5894 C5895
SBR1A30T5 150UF 150UF 150UF 150UF 150UF 150UF
SOD523 20% 20% 20% 20% 20% 20%
371S00245
3V8_EXT_DIODE
R5805 1
116S0007 R5801 2 6.3V
TANT-POLY
2 6.3V
TANT-POLY
2 6.3V
TANT-POLY
2 6.3V
TANT-POLY
2 6 3V
TANT-POLY
2 6.3V
TANT-POLY
P3V8AON_DRVL1 1
1 2 P3V8AON_DRVL1_R R5809 2
1.00 1 P3V8AON_ISNS1_P
CASE-B1S-1 CASE-B1S-1 CASE-B1S-1 CASE-B1S-1 CASE-B1S-1 CASE-B1S-1
24 IN 95 128 00067 128S00067 128S00067 128S00067 128S00067 128S00067
MIN_LINE_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000 1.5 CKPLUS_WAI =CAPDERATE CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE CKPL _WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERAT CKPLUS_WAIVE=CAPDERATE
MIN NECK_WIDTH=0.1000 5%
1 16
MIN_NECK WIDTH=0.1000 5% NOSTUFF NO_XNET_CONNECTION=1 1%
1/20W
AT _ ODE=TRUE GATE_N DE=TRUE 1/16W
DID =TRUE MF-LF
402
DIDT=TRUE MF-LF 1 C5814 1 C5810 MF-LF
0201
116S0006 2 402 220PF 5600PF 118S0744
P3V8AON_SNUB1 5% 10% MIRROR_WITH=C5887 MIRROR_WITH=C5889
SWITCH_NODE=TRUE 2 50V 2 10V
DIDT=TRUE C0G
0201-1
CERM-X7R
0201
1 C5886 1 C5887 1 C5888 1 C5889
2.2UF 2.2UF 2.2UF 2.2UF
132S0370 R5802 20% 20% 20% 20%
131S0514 1.00 2 2 25V 2 25V 2 25V 2 25V
1 P3V8AON_ISNS1_N 95
X6S-CERM X6S-CERM X6S-CERM X6S-CERM
1 C5809 NOSTUFF 1%
0402
138S00042
0402
138S0 042
0402
138S00042
0402
138S00042
150PF 1/20W
5%
2 50V
1 C5815 MF-LF
0201
C0G-CERM
0402
220PF 118S0744
5%
<RDAR://59524111> 2 50V
C0
0201-1
24 OUT P3V8AON_ISEN1_P
24 OUT P3V8AON_ISEN1_N
CRITICAL CRITICAL CRITICAL CRITICAL MIRROR_WITH=C5824
1
C5820 1
C5821 1
C5820 1
C5820 1 C5824 1 C5825
ALLOW_APPLE_PREFIX=Q 33UF 33UF 33UF 68UF 2.2UF 2.2UF
20% 20%
R5824 CRITICAL
20%
2 16V
20%
2 16V
20%
2 16V
20%
2 16V 2 25V
X6S CERM 2 25V
X6S-CERM
1 5 TANT TANT TANT POLY-TANT
24 IN P3V8AON_DRVH2
1 P3V8AON_DRVH2_R
Q5820 CASE-T
128S00009
CAS -T
128S00009
CASED12-SM
128S0436
CASE-D2E-SM
128S0264
0402
138S00042
0402
138S00042
MIN_NECK_WIDTH=0.1000 5% MIN_NECK_WIDTH=0.1000 AONE36196 CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE
GATE_NODE=TRUE 1/8W GATE_NODE=TRUE DFN PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE
DIDT=TRUE TK DIDT=TRUE 376S00281 3V8_AON_PBUS-B12 3V8_AON_PBUS-B12 3V8_AON_PBUS-D12 3V8_AON_PBUS-D2
0402
107S00371
D1 8
R5823 C5831 D1 9 107S00090
0 0.22UF
CRITICAL R5820
P3V8AON_BST2 1 2 P3V8AON_BST2_RC 1 2 P3V8AON_SW2 0.001
24 OUT
MIN_NECK_WIDTH=0.1000 0%
MIN_NECK_WIDTH 0.1000
1 G1
SAME SW NET
L5820 1%
1/3W
0.56UH-20%-22.0A-0.0067OHM
www.teknisi-indonesia.comPP3V8AON_PH2
DIDT=TRUE 1/16W DIDT=TRUE 10% SWITCH_NODE=TRUE ON BOTH SIDES MF
SWITCH_NODE=TRUE MTL-FILM SWITCH_NODE=TRUE 25V DIDT= RUE 2 030
0402 X7R
0402 3 D2/S1 99 25 24 IN P3V8AON_SW2 1 2 1 2
116 0 0 MIN_LINE_WIDTH=0.2000
PILA062D-SM- OMBO MIN_LINE_WIDTH=0.2000
3 4
132S0401 OUT 24 25 99
4 MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000
SWITCH_NODE=TRUE 152S01248 VOLTAGE=5V NO_XNET_CONNECT ON=1
NOSTUFF DIDT=TRUE
D5820 1
R5829NOSTUFF
25 24 P3V8AON_PVCC A K
G2 7 2.2 R5821
5%
2
1/16W 95
SBR1A30T5 MF-LF DIDT=TRUE
SOD523
2 402 SWITCH_NODE=TRUE NOSTUFF NO_XNET_CONNECTION=1 1%
1/20W
371S00245
8_EXT_DIODE P3V8AON_SNUB2 1 C5834 1 C5830 MF-LF
0201
220PF 5600PF 118S0744
R5825 R5826 1 C5829NOSTUFF 5%
2 50V
10%
2 10V
0.1002 0.1002 100PF C0G CERM-X7R
24 IN P3V8AON_DRVL2 1 P3V8AON_DRVL2_R 1 P3V8AON_DRVL2_RR VER-1
5% 0201-1 0201
M N_ ECK_WIDTH=0.2000 MIN_NECK_WIDTH=0. 00 MIN_ IN _WIDTH=0.2000 2 50V
C0G 132 3 0 R5822
MIN LINE_WIDTH=0.1000 1% MIN_LINE_WIDTH=0.1000 1% MIN_NECK_WIDTH=0.1000 0402
GATE_NODE=TRUE 1/4W
MF
GATE_NODE=TRUE 1/4W
MF
GATE_NODE=TRUE
1
1.00 2 P3V8AON_ISNS2_N
DIDT=TRUE DIDT=TRUE DIDT=TRUE 95
0402 0402
104S0050 104S0050 NOSTUFF 1%
1/20W
1 C5835 MF-LF
0201
24 OUT P3V8AON_ISEN2_P 220PF 118S0744
5%
2 50V
24 OUT P3V8AON_ISEN2_N C0G
0201-1
NO_XNET_CONNEC ON
CRITICAL CRITICAL CRITICAL CRITICAL MIRROR_WITH=C5844 NO_XNET_CONNECTION=1
ALLOW_APPLE_PREFIX=Q 1
C5840 1
C5841 1
C5840 1
C5840 1 C5844 1 C5845 XW5870 R5870
R5844 33UF 33UF 33UF 68UF 2.2UF 2.2UF 2 1 P3V8AON_VSNS_XW_P 0 P3V8AON_VSENSE
1.5 CRITICAL 20% 20% 20% 20% 20% 20%
1 2 OUT 24
24 IN P3V8AON_DRVH3
1 2 P3V8AON_DRVH3_R
Q5840 2 16V
TANT
2 16V
TANT
2 16V
TANT
2 16V
POLY-TANT
2 25V
X6S-CERM 2 25V
X6S-CERM
SM 5%
1/20W
NOSTUFF
GATE_NODE=TRUE
5%
1/8W
GATE_NODE=TRUE
AONE36196
DFN
CASE-T
128S00009
CASE-T
128S00009
CASED12-SM
128S0436
CASE-D2E-SM
128S0264
0402
138S00042
0402
138S00042
MF
0201
1 C5870
DIDT=TRUE TK DIDT=TRUE 376S00281 CKPLUS_WAIVE=CAPDERA CKPLUS_WAIVE=CAPDERATE CKPLUS_W VE=CAPDERATE CKPLUS_WAIVE=CAPDERATE 117S0201 1UF
0402 PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE
20%
107S00371 3V8_AON_PBUS-B12 3V8_AON_PBUS-B12 3V8_AON_PBUS-D12 3V8_AON_PBUS-D2 2 10V
X6S-CERM
NO_XNET_CONNECTION=1
D1 8 NO_XNET_CONNECTION=1
0201
R5843 C5851 D1 9 107S00090

XW5871 R5871 138S00044
0 0.22UF
CRITICAL R5840 2 1 P3V8AON_VSNS_XW_N 1
0 2 P3V8AON_VRTN
P3V8AON_BST3 1 P3V8AON_BS 3_RC 1 2 P3V8AON_SW3 0 001 OU 24
24 OUT
MIN LINE_WIDTH=0.2000
MIN_L NE_WIDTH=0.2000
1 G1
SAME SW NET
L5840 1%
1/3W
S 5%
1/20W
DIDT=TRUE 1/16W DIDT=TRUE 10% SWITCH_NODE=TRUE ON BOTH SIDES
0.56UH-20%-22.0A-0.0067OHM MF MF
SWITCH_NODE=TRUE MTL-FILM SWITCH_NODE=TRUE 25V DIDT=TRUE 2 0306 0201
0402 X7R
0402 3 D2/S1 99 25 24 IN P3V8AON_SW3 1 2 PP3V8AON_PH3 1 2 117S0201
116S00006 MIN_LINE_WIDTH=0.2000
PILA062D-SM-COMBO MIN_LINE_WIDTH=0.2000
3 4
132S0401 OUT 24 25 99
4 MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000
SWITCH_NODE=TRUE 152S01248 VOLTAGE=5V
NOSTUFF DIDT=TRUE NO_XNET_CONNECT ON=1
D5840 1
R5849NOSTUFF
25 24 P3V8AON_PVCC A K
G2 7 2. R5841
5%
2
1/16W 95
SBR1A30T5 MF-LF DIDT=TRUE
SOD5 3
2 402 SWITCH_NODE=TRUE NOSTUFF NO_XNET_CONNECTION=1 1%
1/20W
371S00245 SYNC_MASTER=REF_VR_ICEMAN
3V8_EXT_DIODE P3V8AON_SNUB3 1 C5854 1 C5850 MF-LF
0201 PAGE TITLE
220PF 5600PF
R5845 R5846 1 C5849NOSTUFF
100PF
5%
2 50V
C0G
10%
2 10V
CERM-X7R
118S0744
POWER: 3V8 AON (2/2)
P3V8AON_DRVL3 1
0.1002 P3V8AON_DRVL3_R 1
0.1002 P3V8AON_DRVL3_RR 5% 0201-1 0201
24 IN VER-1 2 50V
MIN_LINE_WIDTH=0.1000 1%
MIN_LINE_WIDTH=0.1000 1%
C0G
0402
132S0370 R5842
GATE_NODE=TRUE 1/4W
MF
GATE_NODE=TRUE 1/4W
MF
GATE_NODE=TRUE
1
1.00 2 P3V8AON_ISNS3_N
DIDT=TRUE DIDT=TRUE DIDT=TRUE 95
0402 0402
104S0050 104S0050 NOSTUFF 1%
1/20W
1 C5855 MF-LF
0201
24 OUT P3V8AON_ISEN3_P 220PF 118S0744
5%
2 50V
24 OUT P3V8AON_ISEN3_N C0G
0201-1
2 1
ZERO OHM RESISTOR TO ALLOW ACCESS TO VDRV
R5900
PP5V_S2 1
0 2 PP5V_S2_P3V8AON_VDRV PP5V_S2_P3V8AON_VDRV
104 24
MAKE_BASE=TRUE
5% VOLTAGE=5V
1/16W MIN_NECK_WIDTH=0.1000
MF-LF MIN_LINE_WIDTH=0.2000
402
116S0004
PAGE TITLE
POWER: 3V8 AON SUPPORT
2 1
SLAVE PMU INPUT POWER & BUCKS
998-22526
OMIT_TABLE PP1V06_S2SW_DRAM 101
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
U7700 1 C7740 1 C7741 1 C7742 1 C7743 1 C7744 1 C7745 1 C7746 1 C7747
PP3V8_AON_SPMU_ISNS_VIN TMLT47A1-JPE L7740 15UF 15UF 15UF 15UF 15U 15UF 15UF 15UF
105 28 27
WLCSP 20% 20% 20% 20% 20% 20% 20% 20%
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL SYM 1 OF 4
OUT 30 1.0UH-20%-4A-0.038OHM 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V
X6S X6S X6S X6S X6S X6S X6S X6S
1 C7700 1 C7701 1 C7702 1 C7703 1 C7704 1 C7705 1 C7706 1 C7707 C13 VDD_BUCK5_4_10 BUCK4_LX0 F14 BUCK4_LX0 1 2 CRITICAL 0402 0402 0402 0402 0402 0402 0402 0402
10UF 10UF 10UF 10UF 10UF 10UF 1UF 1UF C14 DIDT=TRUE PIKA20161B-COMBO
20% 20% 20% 20% 20% 20% 20% 20% VDD_BUCK5_4_10 SWITCH_NODE=TRUE
2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 10V
X6S-CERM 2 10V
X6S-CERM
G13 VDD_BUCK5_4_10 L7741 CRITICAL CRITICAL CRITICAL CRITICAL
0402 0402 0402 0402 0402 0402 0201 0201 G14 VDD_BUCK5_4_10
OUT 30 0.22UH-20%-6.7A-0.023OHM 1 C7710 1 C7711 1 C7712 1 C7713 1 C777M 1 C777N
BUCK4_LX1 D13 BUCK4_LX1 1 2 CRITICAL 15UF 15UF 15UF 15UF 12PF 3.0PF
DIDT=TRUE 20% 20% 20% 20% 5% +/-0.1PF
BUCK4_LX1 D14 SWITCH_NODE=TRUE PINA20121T-SM 2 2V 2 2V 2 2V 2 2V 5V
2 NP0-C0G 2 25V
M2 VDD_BUCK6 R770A XW7700
SHORT-14L-0.1MM-SM
X6S
0402
X6S
0402
X6S
0402
X6S
0402 0201
NP0-C0G
0201
0 PLACE_NEAR=L7740.2:5MM
1 C7708 1 C7709 1 C770A 1 C770B 1 C770C 1 C770D 1 C770E 1 C770F N2 VDD_BUCK6 BUCK4_FB 1 2 BUCK4_FB_R 1 2 P CE N AR=L7741.2:5MM
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF P2 VDD_BUCK6 BUCK4_FB F11 5 1/20W MF 0201 NO_XNET_CONNECTION=1
20% 20% 20% 20% 20% 20% 20% 20% PLACE_NEAR=U7700.F11:15MM
2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V F12 PP0V764_S1_SRAM 101
X6S-CERM
0201
X6S-CERM
0201
X6S-CERM
0201
X6S-CERM
0201
X6S-CERM
0201
X6S-CERM
0201
X6S-CERM
0201
X6S-CERM
0201 BUCK4_VSS_FB VSS_ANA_SPMU 27 29 30
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
N6 VDD_BUCK12
L7750
1 C7750 1 C7751 1 C7752 1 C7753 1 C7754 1 C7755 1 C7756 1 C7757
P6 VDD_BUCK12 OUT 30 0.47UH-20%-4A-0.027OHM 15UF 15UF 15UF 15UF 15UF 15UF 15UF 15UF
20% 20% 20% 20% 20% 20% 20% 20%
H13 2 CRITICAL 2 2V 2V
2 X6S 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V
BUCK5_LX_0 BUCK5_LX0 1 X6S X6S X6S X6S X6S X6S X6S
1 C770G 1 C770H 1 C770I 1 C770J 1 C770K 1 C770L 1 C770M 1 C770N BUCK5_LX_1 H14 DIDT=TRUE
SWITCH_NODE=TRUE 2012
0402 0402 04 0402 0402 0402 0402 04
1UF 1UF 1UF 1UF 1UF 1UF 12PF 3.0PF L13 XW7701
20% 20% 20% 20% 20% 20% 5% +/-0.1PF
L14
VDD_BUCK13 R770B SHORT-14L-0.1MM-SM
2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 25V 2 25V VDD_BUCK13 0
X6S-CERM X6S-CERM X6S-CERM X6S- ERM X6S-CERM X6S-CERM NP0-C0G NP0-C0G BUCK5_FB 1 2 BUCK5_FB_R 1 2
0201 0201 0201 0201 0201 0201 0201
PLACE_NEAR=U7700 L1 0MM
0201
BUCK5_FB H11 5% 1/20W MF 0201
1 C778M 1 C778N 1 C779M 1 C779N
PLACE_N AR=U7700.L1:10MM PLAC _NEAR=U7700.H12:15MM
12PF 3.0PF 12PF 3.0PF
5% +/-0.1PF 5% +/-0.1PF
L1 VDD_MAIN_BUCK6 BUCK5_VSS_FB H12 VSS_ANA_SPMU 27 29 30 2 25V 2 25V 2 25V 2 25V
NP0-C0G NP0-C0G NP0-C0G NP0-C0G
0201 0201 0201 0201
PLACE_NEAR=L7750.2:5MM PLACE_NEAR=L7760.2:5MM
1 C771M 1 C771N 1 C772M 1 C772N 1 C773M 1 C773N 1 C774M 1 C774N L9 VDD_MAIN_SOUTH L7760 PLACE_NEAR=L7750.2:5MM PLACE_NEAR=L7760.2:5MM
12PF 3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 3.0PF OUT 30 0.47UH-20%-6.9A-0.022OHM
5% +/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5% +/-0.1PF
2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V E8 VDD_MAIN BUCK6_LX_0 M3 BUCK6_LX0 1 2 CRITICAL PP2V5_AWAKE_NAND 27 101
NP0-C0G NP0-C0G NP0-C0G NP0-C0G NP0-C0G NP0-C0G NP0-C0G NP0-C0G DIDT= RUE
0201 02 0201 0201 0201 0201 02 0201 BUCK6_LX_1 N3 SWITCH_NODE=TRUE IUA25201B-SM CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
PLACE_NEAR=U7700.C13:10MM PLACE_NEAR=U7700.G13:10MM PLACE_NEAR=U7700.M2:10MM PLACE_NEAR=U7700.N6:10MM
PLACE_NEAR=U7700 C13:10MM PLACE_NEAR=U7700.G13:10MM PLACE_NEAR=U7700.M2:10MM PLACE_NEAR=U7700.N6:10MM BUCK6_LX_2 P3 R770C XW7760 1 C7760 1 C7761 1 C7762 1 C7763 1 C7764 1 C7765 1 C776C 1 C776D
D2 VDD_MAIN_LDO 0 SHORT-14L-0.1MM-SM 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
E2 BUCK6_FB 1 2 BUCK6_FB_R 1 2 20% 20% 20% 20% 20% 20% 20% 20%
VDD_MAIN_LDO 2 6.3V
CER-X6S 2 6 3V
C R-X6S 2 6.3V
CER-X6 2 6.3V
CER-X6S 2 6 3V
C R- 6S 2 6.3V
CER-X6S 2 6 3V
C R-X6S 2 6.3V
CER-X6S
5% 1/20W MF 0201 NO_XNET_CONNECTION=1
1 C775M 1 C775N 1 C776M 1 C776N BUCK6_FB L3 PLACE_NEAR=U7700.L3:15MM
0402 0402 0402 0402 0402 0402 0402 0402
12PF 3.0PF 12PF 3.0PF K2
5% +/-0.1PF 5% +/-0.1PF
D8 BUCK6_VSS_FB VSS_ANA_SPMU 27 29 30
2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G VDD_MAIN_SNS CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
0201
PLACE_NEAR=U7700.L13:10MM
0201 0201
PLACE_NEAR=U7700.D9:10MM
0201
PP2V5_AWAKE_NAND
1 C7766 1 C7767 1 C7768 1 C7769 1 C776A 1 C776B 1 C776E 1 C776F
PLACE_NEAR=U7700.L13:10MM PLACE_NEAR=U7700.D9:10MM
E10 VDD_SNS_SPARE M1
27 101
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
BUCK6_VOUT_0 20% 20% 20% 20% 20% 20% 20% 20%
N1 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6 3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6 3V
CER-X6S
BUCK6_VOUT_1 0402 0402 04 0402 0402 0402 0402 04
BUCK6_VOUT_2 P1
28 PP1V5_VLDOINT_SPMU C12 VDD_ANA
www.teknisi-indonesia.com 0.47UH-20%-4A-0.027OHM
D3 VDD_ANA
E7 VDD_ANA
L77A0
30
OUT
G12 VDD_ANA CRITICAL
BUCK10_LX_0 B13 BUCK10_LX0 1 2 PP0V6_S1_VDDQL 101
K3 VDD_ANA DIDT=TRUE
BUCK10_LX_1 B14 SWITCH_NODE=TRUE 2012 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
L8 VDD_ANA R770D XW77A0
SHORT-14L-0.1MM-SM
1 C77A0 1 C77A1 1 C77A2 1 C77A3 1 C7722 1 C7723 1 C7790 1 C7791
L12 VDD_ANA 0
M6 BUCK10_FB 1 2 BUCK10_FB_R 1 2 15UF 15UF 15UF 15UF 15UF 15UF 12PF 3.0PF
VDD_ANA 20% 20% 20% 20% 20% 20% 5% +/-0.1PF
BUCK10_FB B11 5% 1/20W MF 0201 NO_XNET_CONNECTION=1 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 25V 2 25V
PLACE_NEAR=U7700.B11:15MM
X6S X6S X6S X6S X6S X6S NP0-C0G NP0-C0G
0402 0402 0402 0402 0402 0402 0201 0201
D5 VDD_DIG BUCK10_VSS_FB B12 VSS_ANA_SPMU 27 29 30 PLACE_NEAR=L77A0.2:5MM
PLACE_NEAR=L77A0.2:5MM
D10 VDD_DIG L77C0
J3 VDD_DIG
OUT 30 0.47UH-20%-4A-0.027OHM
J10 VDD_DIG BUCK12_LX0 1 2 CRITICAL NOSTUFF NOSTUFF PP0V88_S1 1 1
N5 DIDT=TRUE
BUCK12_LX_0 SWITCH_NODE=TRUE 2012 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
105 28 27 PP3V8_AON_SPMU_ISNS_VIN D9 VDD_BOOST BUCK12_LX_1 P5
R770E XW77C0 1 C77C0 1 C77C1 1 C77C2 1 C77C3 1 C7718 1 C7719 1 C7720 1 C7721
B2 0 SHORT-14L-0.1MM-SM 15UF 15UF 15UF 15UF 15UF 15UF 15UF 15UF
VDD_BOOST_LDO BUCK12_FB 1 2 BUCK12_FB_R 1 2 20% 20% 20% 20% 20% 20% 20% 20%
C2 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S
VDD_BOOST_LDO L5 5% 1/20W MF 0201 NO_XNET_CONNECTION=1 0402 0402 0402 0402 0402 0402 0402 0402
BUCK12_FB PLACE_NEAR=U7700.L5:15MM
E9 VDD_BOOST_SNS
BUCK12_VSS_FB M5 VSS_ANA_SPMU 27 29
28 PP5V_BSTLQ_SPMU
VOLTAGE=5V CRITICAL CRITICAL CRITICAL D4 VDD_HI_INT1
L77D0
1 C7792 1 C7793
1 C7717 1 C7714 1 C7715 L4 VDD_HI_INT2 0.47UH-20%-4A-0.027OHM 12PF 3.0PF
5% +/-0.1PF
0.1UF 0.1UF 0.1UF L7 2 25V 25V
10% 10% 1 % VDD_HI_INT3
BUCK13_LX_0 K13 30 BUCK13_LX0 1 2 CRITICAL NP0-C0G 2 N 0-C0G
2 10V 2 10V 2 10V M10 VDD_HI_INT4 DIDT=TRUE 0201 0201
X6S-CERM X6S-CERM X6S-CERM BUCK13_LX_1 K14 SWITCH_NODE=TRUE 2012 PLACE_NEAR=L77C0.2:5MM
0201 0201 0201 J11 VDD_HI_INT5 PLACE_NEAR=L77C0.2:5MM
PLACE_NEAR=U7700.D4:5MM PLACE_NEAR=U7700.C9:5MM
PLACE_NEAR=U7700.L7:5MM
A11 VDD_HI_INT6 R770F XW77D0
SHORT-14L-0.1MM-SM
C9 BUCK13_FB 1
0 2 BUCK13_FB_R 1 2 PP1V25_S2
VDD_HI_INT7 K11 102
BUCK13_FB
5% 1/20W MF 0201 NO_XNET_CONNECTION=1 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
PLACE_NEAR=U7700.K11:15MM
FED BY SPMU BUCK13 (1.2V)POWER ALIAS=>

102 PP1V25_S2 G10 VDDIO_1V2 BUCK13_VSS_FB K12 1 C77D3 1 C77D4 1 C77D5 1 C77D6 1 C77D7 1 C77D8 1 C7794 1 C7795
H10 VSS_ANA_SPMU 27 29 30
20% 20% 20% 20% 20% 20% 5% +/-0 1PF
FED BY MPMU BUCK3 (1.8V)POWER ALIAS=> 101 PP1V8_S2 VDDIO_BUCK3 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S
V
2 X6S 2 2V
X6S 2 25V
NP0-C0G 2 25V
NP0-C0G
0402 0402 0402 0402 0402 0402 0201 0201
CRITICAL CRITICAL VSS_ANA_SPMU K6 PLACE_NEAR=L77D0.2:5MM
30 29 27 VPP PLACE_NEAR=L77D0.2:5MM
1 C7716 1 C771A
0.1UF 0.1UF
10% 10%
2 10V
X6S-CERM 2 10V
X6S-CERM
0201 0201
PLACE_NEAR=U7700.G10:5MM
PLACE_NEAR=U7700.H10:5MM
C M TE E T M C TE
PAGE TITLE
PMU: SLAVE INPUT PWR & BUCKS
BOM COST GROUP=PLATFORM POWER

SLAVE PMU LDO, SWITCHES & BOOST
LDO/SW INPUTS 998-22526

LDO/SW OUTPUTS
OMIT_TABLE
U7700
TMLT47A1-JPE
WLCSP
SYM 2 OF 4
FROM BUCK13 => M7 M8
102 PP1V25_S2 VDD_LDO4 VLDO4 PP0V72_S2_VDD_LOW 28 102
VLDO6 D1 NC_SPMU_VLDO6 102
FROM BUCK13 OR =>

POST EVT: BUCK14 C4 C3 PP1V2_AWAKE_PLL
34 28 PPVDD_PMU_LDO_PREREG VDD_LDO8 VLDO8 28 102
VLDO9 E3 PP1V8_AON_SPMU 28 102
FROM BUCK4 => N7 N8

101 PP1V06_S2SW_DRAM VDD_LDO11 VLDO11 PP0V855_S2SW_CIO 28 102
FROM BUCK12 => P7 P8

101 28 PP0V88_S1 VDD_LDO12 VLDO12 PP0V805_S1_VDD_FIXED 28 103
105 28 27 PP3V8_AON_SPMU_ISNS_VIN A1 VDD_LDO15 VLDO15 A3 NC_SPMU_VLDO15 103

A2 VDD_LDO15
VLDO17 B1 NC_SPMU_VLDO17 103
VLDO18 C1 NC_SPMU_VLDO18 103

FROM BUCK13 OR =>
POST EVT: BUCK14
34 28 PPVDD_PMU_LDO_PREREG B4 VDD_LDO20 VLDO20 B3 PP1V2_S2_CIO 28 103
<= BUCK_SW4 USED FOR SPMU GPIO

PP1V8_AWAKE_SPMU_GPIO
M11 M12 VOLTAGE=1.8V
FROM BUCK3 POWER ALIAS => 101 PP1V8_S2 VDD_SW4 BUCK_SW4
PP1V25_S2 M13 VDD_SW5 BUCK_SW5 M14 PP1V25_AWAKESW_VCCQ 1 C7822 1 C7898
1 C7899
FROM BUCK13 POWER ALIAS =>
102 29 28 102
3.0PF
N13 VDD_SW5 BUCK_SW5 N14 1UF 12PF +/-0.1PF
P13 P14
20% 5% 2 25V
VDD_SW5 SWITCHED RAILS BUCK_SW5 2 10
X6S-CERM 2 25V
NP0-C0G
NP0-C0G
0201
101 28 PP0V88_S1 N11 VDD_SW6 BUCK_SW6 N12 PP0V88_AWAKESW_NAND 28 102
0201 0201
P11 P12 PLACE_NEAR=U7700.M12:5MM
CRITICAL CRITICAL CRITICAL VDD_SW6 BUCK_SW6 CRITICAL PLACE_NEAR=U7700.M12:5MM
1 C7810 1 C7811 1 C7812 N9 VDD_SW7 BUCK_SW7 N10 L7800
FROM BUCK12 POWER ALIAS => 10UF 10UF 10UF P9 VDD_SW7 BUCK_SW7 P10 0.47UH-20%-1.7A-0.175OHM
20% 20% 20%
2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 30 SPMU_BSTLQ_LX 1 2 PP3V8_AON_SPMU_ISNS_VIN 27 28 105
0402 J2 G1 SWITCH_NODE=TRUE
0402 0402 105 28 27 PP3V8_AON_SPMU_ISNS_VIN VDD_MAIN_BSTLQ BSTLQ_LX DIDT=TRUE 0402-COMBO
BSTLQ_FB J1 27 PP5V_BSTLQ_SPMU XW78D0
SHORT-12L-0.25MM-SM
H1 VOLTAGE=5V 1 2
BSTLQ_VOUT
NO_TEST=1 PP5V_BSTLQ_VOUT_SPMU
THIS IS AN OUTPUT(1.5V) => E1 M9 VOLTAGE=5V
27 PP1V5_VLDOINT_SPMU VLDOINT VCP_OUT_SPARE NC_SPMU_VCP_OUT_SPARE CRITICAL CRITICAL CRITICAL
VOLTAGE=1.5V
VMBX_SPARE F10 NC_SPMU_VMBX_SPARE
1 C7800 1 C7801 1 C7892 1 C7893 1 C7831
20UF 20UF 12PF 3.0PF 0.1UF
NO_TEST=1 20% 20% 5% +/-0.1PF 1 %
2 10V
X5R 2 10V
X R 2 25V
NP0-C0 2 25V
NP0-C0G 2 10V
X S ERM PLACE_NEAR=U7700 H :5MM
0402 0402 0201 0201 02 1
PLACE_NEAR=U7700.H1:5MM
PLACE_NEAR=U7700.H1:5MM GND 29 30
CRITICAL
1 C7825
0.1UF
10%
Decoupling: VDD_LDO8 Decoupling: LDO11 Decoupling: SW5 Decoupling: LDO.INT 2 10V
X6S-CERM
0201
PPVDD_PMU_LDO_PREREG 28 34 PP0V855_S2SW_CIO 28 102 PP1V25_AWAKESW_VCCQ 28 102 PP1V5_VLDOINT_SPMU 27 28 PLACE_NEAR=U7700.J1:5MM
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C7813 1 C7809 1 C780C 1 C7802 1 C7803 1 C7896 1 C7897 1 C7807 1 C7808 1 C7823 1 C7834
10UF 10UF 10UF 10UF 10UF 12PF 3.0PF 220PF 220PF 10UF 10UF
20% 20% 20% 20% 20% 5% +/-0.1PF 10% 10% 20% 20%
2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 25V
NP0-C0G 2 25V
NP0-C0G 2 16V
CER-X7R 2 16V
CER-X7R 2 6.3V
CER-X6S 2 6.3V
CER-X6S
0402 0402 0402 0402 0402 0201 0201 0201 0201 0402 0402
PLACE_NEAR=U7700.M14:5MM
NOSTUFF PLACE_NEAR=U7700.M14:5MM
Decoupling: LDO4
Decoupling: LDO12 Decoupling: SW6/7 Decoupling and Desense: BSTLQ
PP0V72_S2_VDD_LOW 28 102
CRITICAL CRITICAL PP0V805_S1_VDD_FIXED 28 103 PP0V88_AWAKESW_NAND 28 102 PP3V8_AON_SPMU_ISNS_VIN 27 28 105

1 C7820 1 C780D CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
10UF 10UF 1 C7821 1 C780B 1 C7830 1 C7829 1 C7828 1 C7894 1 C7895 1 C7815 1 C7816 1 C7890 1 C7891
20% 20%
2 6.3V
CER-X6S 2 6.3V
CER-X6S
10UF 10UF 10UF 10UF 10UF 12PF 3.0PF 1UF 1UF 12PF 3.0PF
20% 20% 20% 20% 20% 5% +/-0.1PF 20% 20% 5% +/-0.1PF
0402 0402 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 25V 2 25V 2 10V 2 10V 2 25V 2 25V
CER-X6S CER-X6S CER-X6S CER-X6S CER-X6S NP0-C0G NP0-C0G X6S-CERM X6S-CERM NP0-C0G NP0-C0G
0402 0402 0402 0402 0402 0201 0201 0201 0201 0201 0201
PLACE_NEAR=U 700.N12:5MM PLACE_NEAR= 7700.J2:5MM PLACE_NEAR=L7800.2:5MM
PLACE_NEAR=U7700.N12:5MM PLACE_NEAR=U7700.J2:5MM PLACE_NEAR=L7800.2:5MM
Decoupling: LDO8 Decoupling: VDD_LDO20

PP1V2_AWAKE_PLL 28 102 PPVDD_PMU_LDO_PREREG 28 34
CRITICAL CRITICAL CRITICAL

1 C7805 1 C7806 1 C7814
10UF 10UF 10UF
20% 20% 20%
2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S
0402 0402 0402
NOSTUFF
C M TE E T M
PAGE TITLE
Decoupling: LDO9 Decoupling: LDO20 PMU: SLAVE LDO
PP1V8_AON_SPMU 28 102 PP1V2_S2_CIO 28 103
CRITICAL CRITICAL CRITICAL CRITICAL

1 C7824 1 C7835 1 C7804 1 C780A
1UF 1UF 10UF 10UF
20% 20% 20% 20%
2 10V
X6S-CERM 2 10V
X6S-CERM 2 6.3V
CER-X6S 2 6.3V
CER-X6S
0201 0201 0402 0402
NOSTUFF

SLAVE PMU GND,ADC,& GPIO
998-22526
OMIT_TABLE
PLACEMENT NOTE: U7700

CONNECT VSS_REF THROUGH ALL GND PLANES PLACE XW AT VSS_REF PIN, ROUTE VSS_RTN TMLT47A1-JPE
BACK FROM THE VREF / IREF PASSIVES WLCSP
SYM 3 OF 4
SPMU_IREF D7 IREF GPIO1 NC_SPMU_GPIO1 30
OUT
GPIO2 K8 NC_SPMU_GPIO2 30
NOSTUFF SPMU_VREF D6 VREF
OUT
1 K7 SWD_NUB_PMU_SWDIO
R7903 1 C7906 GPIO3 BI 9 33
200K
0.1% 0.1UF
1 C7905 SPMU_VREF_ADC C7 VREF_ADC GPIO4 J7 NC_SPMU_GPIO4 OUT 30
1/20W 10% 1.5UF C6 GPIO5 G7 NC_SPMU_GPIO5 OUT 30

XW79D0 TF 2 6.3V 20% 49 30 29 VSS_ANA_SPMU VSS_REF F7
SHORT-14L-0.1MM-SM 2 0201
CERM-X5R
0201 2 6.3V
CER-X5R GPIO6 NC_SPMU_GPIO6 OUT 30
49 30 29 VSS_ANA_SPMU 2 1 SPMU_VREF_IREF_RTN 0201 GPIO7 F6 NC_SPMU_GPIO7 30

SPMU_TCAL A7 TCAL
OUT
GPIO8 H6 NC_SPMU_GPIO8 30
OUT
GPIO GPIO9 G6 NC_SPMU_GPIO9 30
49 SPMU_THMSNS A6 TDEV1
OUT
IN
GPIO10 J6 NC_SPMU_GPIO10 30
1 AMB_THMSNS A5 OUT
C7985 49 IN
NAND0_THMSNS B8
TDEV2 TDEV
GPIO11 F5 NC_SPMU_GPIO11 OUT 30
0.1UF 103S00511
49 IN TDEV3
GPIO12 H5 NC_SPMU_GPIO12
10% B7 OUT 30
6.3V 2 49 IN NAND1_THMSNS TDEV4 J5
CERM-X5R CRITICAL 2 B6 GPIO13 NC_SPMU_GPIO13 OUT 30
0201 R7940 49 FINSTACK_THMSNS TDEV5
3.92K
1 C7940 IN
GPIO14 G5 NC_SPMU_GPIO14 OUT 30
0.1% 100PF E6 GPIO15 F4 NC_SPMU_GPIO15 OUT 30

30 29 VSS_ANA_SPMU 0201-2 5% 30 IN SPMU_ADC_IN ADC_IN F3
1/20W 2 25V
C0G GPIO16 NC_SPMU_GPIO16 OUT 30
MF 1 0201
30 SOC_VDDPCPU_VSENSE B10 AMUX_A<0>
VSS_ANA_SPMU IN
30 A10
30 IN SOC_VSSPCPU_VSENSE AMUX_A<1> J9
A9 SPMI_SCLK SPMI_NUB_SPMU_CLK IN 18
3 IN SOC_VDDPGPU_VSENSE AMUX_A<2> H9
A8 SPMI_SDATA SPMI_NUB_SPMU_DATA BI 18
30 IN SOC_VDDSOC_VSENSE AMUX_A<3>
30 SPMU_AMUX_AY C8 AMUX_AY AMUX SGPIO_SCLK H3 SGPIO_SCLK 33

OUT IN
SPMI G3
D11 SGPIO_SDATA SGPIO_SDATA BI 33
30 IN SOC_VDDECPU_VSENSE AMUX_B<0>
30 SPMU_AMUX_B<1> E11 AMUX_B<1> PP1V8_AON_MPMU 33 34 35 <== FROM LDO9 POWER ALIAS
IN 102
30 WLANBT_3V3_ISENSE B9 AMUX_B<2>
IN
SPMU_HS_ISENSE C10 NOSTUFF
30 IN AMUX_B<3> 1
B5
R7900
30 OUT SPMU_AMUX_BY AMUX_BY 10K
5% <== IPU on Sera enabled.
1/20W
J4 G8 MF
30 IN SPMU_RESET_IN RESET_IN UVWARN* VDD_MAIN_PRE_UVLO_L 29
2 201
DFT_CTRL0=0 ==> DFT_CTRL1=SWDCLK
30 29 27 VSS_ANA_SPMU H8 DFT_CTRL_0 SCRASH* G4 PMU_SCRASH_R_L R7904 1 1K 2 PMU_SCRASH_L BI
33 9 SWD_NUB_SWCLK J8 DFT_CTRL_1 5% 1/20W MF 201
IN
SGPIO_READY_REQ H4 PMU_SGPIO_READY_REQ 33
IN
BI 33 91
SPMU_EXT32K_EN F9 EXT32K_EN
30 SPMU_EXT32K_IN K9 EXT32K_IN
IN
Pulls
FORCE_SYNC G9 FORCE_SYNC
1 1 www.teknisi-indonesia.com PP1V25_S2
R7 01 1 10K
28 102 <== FROM BUCK13 POWER ALIAS
R7920 R7902 2 VDD_MAIN_PRE_UVLO_L 29

10K 10K
1% 1% 5% 1/20W MF 201
1/20W 1/20W
MF MF
201 2 201 2
998-22526
OMIT_TABLE
U7700
TMLT47A1-JPE
WLCSP
SYM 4 OF 4
30 28 GND F1 VSS_BSTLQ VSS A4 VSS_ANA_SPMU 29 30
VSS A12 VSS_ANA_SPMU 27 29

E13 VSS_BUCK4 VSS C5 VSS_ANA_SPMU 29 30
30 GND E14 VSS_BUCK4 VSS C11 VSS_ANA_SPMU 27 29
VSS D12 VSS_ANA_SPMU 27 29

A13 VSS_BUCK10 VSS E4
30 GND A14 VSS_BUCK10 VSS E5 VSS_ANA_SPMU 29 30
VSS E12 VSS_ANA_SPMU 27 29
N4 VSS_BUCK12_6 VSS F2 VSS_ANA_SPMU 29 30
30 GND P4 VSS_BUCK12_6 VSS F13 VSS_ANA_SPMU 27 29
VSS G2 VSS_ANA_SPMU 29 30
J13 VSS_BUCK13_5 VSS G11 VSS_ANA_SPMU 27 29 30
30 GND J14 VSS_BUCK13_5 VSS H2 VSS_ANA_SPMU 29 30

VSS J12 VSS_ANA_SPMU 27 29 30
30 VSS_ANA_SPMU F8 VSS_DFT_2 VSS K1

VSS K4
VSS K5 VSS_ANA_SPMU 27 29 30
VSS K10 VSS_ANA_SPMU 27 29 30
VSS L2
VSS L6 VSS_ANA_SPMU 27 29 30
VSS L10
VSS L11 VSS_ANA_SPMU 27 29 30
VSS M4 VSS_ANA_SPMU 27 29 30
C M TE E T M NC TE
PAGE TITLE
PMU: SLAVE GPIO & GND

SLAVE PMU AMUX ALIAS SLAVE PMU GPIOS SLAVE PMU PROBE POINTS
PP8001
P4MM PP8040
45 IN SOC_VDDPCPU_VSENSE SOC_VDDPCPU_VSENSE OUT 29 29 NC_SPMU_GPIO1 NC_SPMU_GPIO1 SM P4MM
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 PP
1 SPMU_EXT32K_IN OUT 29 SM
NO_TEST=1 27 IN BUCK4_LX0 1
PP
NO_TEST=1
45 SOC_VSSPCPU_VSENSE SOC_VSSPCPU_VSENSE 9 29 NC_SPMU_GPIO2 NC_SPMU_GPIO2
IN
MAKE_BASE=TRUE NO_TEST=1
OUT
MAKE_BASE=TRUE NO_TEST=1 R8001
5%1/20W
1 2 100K
MF 201
45 SOC_VDDPGPU_VSENSE SOC_VDDPGPU_VSENSE 29 29 NC_SPMU_GPIO4 NC_SPMU_GPIO4 PP8041
P4MM
IN OUT SM
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1
27 IN BUCK4_LX1 1
PP
NO_TEST=1
45 IN SOC VDDSOC_VSENSE SOC_VDDSOC_VSENSE OUT 29 29 NC_SPMU_GPIO5 NC_SPMU_GPIO5
29 NC_SPMU_GPIO6 NC_SPMU_GPIO6 PP8002 PP8050

P4MM
SOC_VDDECPU_VSENSE SOC_VDDECPU_VSENSE MAKE_BASE=TRUE NO_TEST=1 P4MMSM BUCK5_LX0 1
SM
45 IN OUT 29 27 IN PP
MAKE_BASE=TRUE NO_TEST=1 PP
1 SPMU_ADC_IN OUT 29 NO_TEST=1
29 NC_SPMU_GPIO7 NC_SPMU_GPIO7 NO_TEST=1
R8004
5% 1/20W
1 2 1M
MF 201
SPMU_AMUX_B<1>
NO_TEST=1
OUT 29 R8002
5%1/20W
1 2
MF
1M
201 PP8060
29 NC_SPMU_GPIO8 NC_SPMU_GPIO8 P4MM
MAKE_BASE=TRUE NO_TEST=1 SM
27 IN BUCK6_LX0 1
PP
NO_TEST=1
29 NC_SPMU_GPIO9 NC_SPMU_GPIO9
WLANBT_3V3_ISENSE WLANBT_3V3_ISENSE
46 IN
OUT 29
29 NC_SPMU_GPIO10 NC_SPMU_GPIO10 PP80A0

P4MM
45 IN SPMU_HS_ISENSE
SPMU_HS_ISENSE OUT 29 PP8003
P4MM IN BUCK10_LX0
NO_TEST=1
1
PP
29 NC_SPMU_GPIO11 NC_SPMU_GPIO11 SM
MAKE_BASE=TRUE NO_TEST=1 PP
1 SPMU_RESET_IN OUT 29
29 NC_SPMU_GPIO12 NC_SPMU_GPIO12 R80031 2 100K

PP80C0
P4MM
MAKE_BASE=TRUE NO_TEST=1 5% 1/20W MF 201 SM
27 IN BUCK12_LX0 1
PP
NO_TEST=1
29 NC_SPMU_GPIO13 NC_SPMU_GPIO13
29 NC_SPMU_GPIO14 NC_SPMU_GPIO14 PP80D0

P4MM
PP8004
P4MM 27 IN BUCK13_LX0
NO_TEST=1
1
PP
VSS alias connection 29 NC_SPMU_GPIO15 NC_SPMU_GPIO15

MAKE_BASE=TRUE NO_TEST=1 2 IN SPMU_AMUX_AY
NO_TEST=1
1
SM
PP
PP80E0
29 NC_SPMU_GPIO16 NC_SPMU_GPIO16 P4MM
PP8005
P4MM 28 IN SPMU_BSTLQ_LX
NO_TEST=1
1
PP
29 GND SM
29 IN SPMU_AMUX_BY 1
PP
29 GND NO_TEST=1
29 GND
GND
29 28 GND
# & WIDTH XW IS LAYOUT DEPENDENT
29 VSS_ANA_SPMU VSS_ANA_SPMU
29 VSS_ANA_SPMU MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.1000 2 2
2 27 VSS_ANA_SPMU MIN_LINE_WIDTH=0.2000
29 VSS_ANA_SPMU VOLTAGE=0 XW8001 XW8002
29 27 VSS_ANA_SPMU
1 1
VSS_ANA_SPMU
29
49 29 VSS_ANA_SPMU SHORT-12L-0.25MM-SM
SH RT-12L-0.25MM-SM
29 VSS_ANA_SPMU
XW8000
SHORT-12L-0.25MM-SM
46 45 VSS_SPMU_AMUX 1 2
C M TE E T M
PAGE TITLE
PMU: SLAVE SUPPORT
MASTER PMU BUCKS
33 31
105 34
PP3V8_AON_MPMU_ISNS_VIN
1 C81C0 1 C81C1 1 C81C2 1 C81C3 1 C81C4 1 C81C6 1 C81C7
1UF 1UF 1UF 1UF 1UF 1UF 1UF OMIT_TABLE
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
L8100
X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM OUT 34 1.0UH-20%-4A-0.038OHM
0201 02 1 0201 0201 0201 02 1 0201 U8100 BUCK0_LX0 1 2 CRITICAL PPVDD_PCPU_AWAKE 101
TMLT46B0-JPE DIDT=TRUE
WLCSP SWITCH_NODE=TRUE PIKA20161B-COMBO CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
SYM 1 OF 6 1 C8100 1 C8101 1 C8102 1 C8103 1 C8104 1 C8105 1 C8109 1 C810A
L1 VDD_BUCK0_2_7_11 BUCK0_LX0 W6 L8101 15UF 15UF 15UF 15UF 15UF 15UF 15UF 15UF
1 C81C8 1 C81C9 1 C81CA 1 C81CB 1 C81CC 1 C81CD 1 C81E0 1 C81E1 L2 VDD_BUCK0_2_7_11 BUCK0_LX0 Y6 0.1UH-20%-10.3A-0.01OHM 20%
2 2V
20
2 2V
20%
2 2V
20%
2 2V
20%
2 2V
20%
2 2V
20
2 2V 2 2V
20%
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF PCCE20161B-SM CRITICAL X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
20% 20% 20% 20% 20% 20% 20% 20% L3 VDD_BUCK0_2_7_11
2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM L4 OUT 34
0201 0201 0201 0201 0201 0201 0201 0201 VDD_BUCK0_2_7_11
R1 VDD_BUCK0_2_7_11 BUCK0_LX1 V1 BUCK0_LX1 1 3
R2 V2 DIDT=TRUE
VDD_BUCK0_2_7_11 BUCK0_LX1 SWITCH_NODE=TRUE CRITICAL CRITICAL CRITICAL CRITICAL
CRITICAL CRITICAL CR TICAL CRITICAL
R3 VDD_BUCK0_2_7_11 BUCK0_LX1 V3
2 4
1 C810B 1 C810C 1 C810D 1 C810E 1 C81H0 1 C81H1 1 C81H2 1 C81H3
R4 VDD_BUCK0_2_7_11 BUCK0_LX1 V4 15UF 15UF 15UF 15UF 12PF 3.0PF 12PF 3.0PF
1 C81F6 1 C81F7 1 C81F8 1 C81F9 1 C81D0 1 C81D1 1 C81D2 1 C81D3 W1 VDD_BUCK0_2_7_11
20%
2 2V
20%
2 2V
20%
2 2V
20%
2 2V
5%
2 25V
+/-0.1PF
2 25V
5%
2 25V
+/-0.1PF
2 25V
1UF 1UF 1UF 1UF 10UF 10UF 10UF 10UF OUT 34 152S01268 X6S
0402
X6S
0402
X6S
0402
X6S
0402
NP0-C0G
0201
NP0-C0G
0201
NP0-C0G
0201
NP0-C0G
0201
20% 20% 20% 20% 20% 20% 20% 20% W2 VDD_BUCK0_2_7_11
2 10V 2 10V 2 10V 2 10V 6.3V
2 CER-X6S 2 6.3V 2 6.3V 2 6.3V
X S-CERM
0201
X6S-CERM
0201
X6S-CERM
0201
X S-CE M
0201 0402
C R-X6S
0402
CER-X6
0402
CER-X6S
0402
W3 VDD_BUCK0_2_7_11 BUCK0_LX2 P1 BUCK0_LX2 PLAC _NEAR=L8100.2:5MM PLA E_NEAR=L8101.4:5MM
W4 P2 DIDT=TRUE PLACE_NEAR=L81 0.2:5MM PLACE_NEAR=L8101.3:5MM
VDD_BUCK0_2_7_11 BUCK0_LX2 SWITCH_NODE=TRUE
W7 VDD_BUCK0_2_7_11 BUCK0_LX2 P3
W11 P4 CRITICAL CRITICAL
VDD_BUCK0_2_7_11 BUCK0_LX2
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL W15 VDD_BUCK0_2_7_11
L8102 1 C810F 1 C810G
1 C81D4 1 C81D5 1 C81D6 1 C81D7 1 C81D8 1 C81D9 1 C81DA 1 C81DB OUT 34
0.1UH-20%-10.3A-0.01OHM 2.2UF 2.2UF
W19 VDD_BUCK0_2_7_11 PCCE20161B-SM CRITICAL 20% 20%
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 2 4V 2 4V
20% 2 % 20% 20% 20% 20% 2 % 20% Y7 VDD_BUCK0_2_7_11 BUCK0_LX3 T1 BUCK0_LX3 X6S-CERM X6S-CERM
2 6.3V
CER-X6S 2 6. V
CER X6S 2 6.3V
CER-X6S
6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S
6. V
2 CER X6S 2 6.3V
CER-X6S Y11 T2 DIDT=TRUE 0201 0201
0402 0402 0402 0402 0402 0402 0402 0402 VDD_BUCK0_2_7_11 BUCK0_LX3 SWITCH_NODE=TRUE 1 3
Y15 T3 PLACE_SIDE=TOP
VDD_BUCK0_2_7_11 BUCK0_LX3 PLACE_NEAR=U8100 5MM
Y19 T4 PLACE_SIDE=TOP
VDD_BUCK0_2_7_11 BUCK0_LX3 PLACE_NEAR=U8100:5MM
2 4
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL A7 VDD_BUCK1_8_9 34
OUT
1 C81DC 1 C81DD 1 C81F2 1 C81F3 1 C81F4 1 C81F5 1 C81F0 1 C81F1 A11 VDD_BUCK1_8_9
BUCK0_LX4 M1 BUCK0_LX4 152S01268
10UF 10UF 10UF 10UF 10UF 10UF 12PF 3.0PF B1 VDD_BUCK1_8_9 DIDT=TRUE
20% 20% 20% 20% 20% 20% 5% +/-0.1PF BUCK0_LX4 M2 SWITCH_NODE=TRUE
2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S
6.3V
2 CER-X6S 2 25V
NP0-C0G 2 25V
NP0-C0G
B2 VDD_BUCK1_8_9 M3
0402 0402 0402 0402 0402 0402 0201 0201 B3 BUCK0_LX4
VDD_BUCK1_8_9
PLACE_NEAR=U8100.B15:10MM B4 VDD_BUCK1_8_9
BUCK0_LX4 M4
R810A XW8100
SHORT-14L-0.1MM-SM
B7 BUCK0_FB 1
0 2 BUCK0_FB_R 1 2
VDD_BUCK1_8_9
B11 5% 1/20W MF 0201
VDD_BUCK1_8_9 U6 NO_XNET_CONNECTION=1
BUCK0_FB PLACE_NEAR=U8100.U6:15MM
1 C81FA 1 C81FB 1 C81FC 1 C81FD 1 C81FE 1 C81FF 1 C81FG 1 C81FH F1 VDD_BUCK1_8_9
12PF 3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 3.0PF F2 VDD_BUCK1_8_9 BUCK0_VSS_FB T6 VSS_ANA_MPMU 31 32 34
5 +/-0.1 F 5% + -0 1 F 5% + -0.1PF 5% +/-0.1PF
2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0 C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G
F3 VDD_BUCK1_8_9
0201
0201
PLACE_NEAR=U8100.F1:10MM
0201 0201
PLACE_NEAR=U8100.K1:10MM
0201
PLACE_NEAR=U8100.A15:10MM
0201 0201 0201 F4 VDD_BUCK1_8_9 L8110
PLACE_NEAR=U8100.B1:10MM PLACE_NEAR=U8100.F1:10MM PLACE_NEAR=U8100.K1:10MM PLACE_NEAR=U8100.A15:10MM K1 VDD_BUCK1_8_9
OUT 34 1.0UH-20%-4A-0.038OHM
K2 VDD_BUCK1_8_9 BUCK1_LX0 A6 BUCK1_LX0 1 2 CRITICAL PPVDD_GPU_AWAKE 34 101
K3 B6 DIDT=TRUE
VDD_BUCK1_8_9 BUCK1_LX0 SWITCH_NODE=TRUE PIKA20161B-COMBO CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C81FJ 1 C81FK 1 C81FL 1 C81FM 1 C81FN 1 C81FP 1 C81FQ 1 C81FR K4 VDD_BUCK1_8_9 L8111 1 C8110 1 C8111 1 C8112 1 C8113 1 C8114 1 C8115 1 C8116 1 C8117
12PF 3 0PF 12PF 3.0PF 12PF 3.0PF 12PF 3.0PF OUT 34 0.1UH-20%-10.3A-0.01OHM 15UF 15UF 15UF 15UF 15UF 15UF 15UF 15UF
5% +/-0 1PF 5% +/-0.1PF 5% +/-0.1PF 5% +/-0.1PF A15 VDD_BUCK3_14 PCCE20161B-SM CRITICAL 20% 20% 20% 20% 20% 20% 20% 20%
2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G B15 BUCK1_LX1 C1 BUCK1_LX1 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S
0201 0201 0201 0201 0201 0201 0201 0201 VDD_BUCK3_14 DIDT=TRUE
BUCK1_LX1 C2 SWITCH_NODE=TRUE 0402 0402 0402 0402 0402 0402 0402 0402
PLACE_NEAR=U8100.L1:10MM PLAC _NEAR=U8100.R1:10MM PLACE_NEAR=U8100.W1:10MM PLACE_NEAR=U8100.Y7:10MM K19 C3 1 3
PLACE_NEAR=U8100.L1:10MM PLACE_NEAR=U8100.R1:10MM PLACE_NEAR=U8100.W1:10MM PLACE_NEAR=U8100.Y7:10MM VDD_LDO2 BUCK1_LX1 MIRROR_WITH=C8111 MIRROR_WITH=C8113 MIRROR WITH=C8115 MIRROR WITH=C8117
L20 VDD_LDO3_14 BUCK1_LX1 C4
K21 VDD_LDO5 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
34
2 4
J19 VDD_LDO19
OUT 1 C8119 1 C811A 1 C811B 1 C811C 1 C811D 1 C811E 1 C81H4 1 C81H5
BUCK1_LX2 G1 BUCK1_LX2 152S01268 15UF 15UF 15UF 15UF 15UF 15UF 12PF 3.0PF
C18 VDD_MAIN_WBOOST DIDT=TRUE 20% 20% 20% 20% 20% 20% 5% +/-0.1PF
F20 BUCK1_LX2 G2 SWITCH_NODE=TRUE 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 25V
NP0-C0G 2 25V
NP0-C0G
VDD_MAIN_WBOOST G3 0402 0402 0402 0402 0402 0402 0201 0201
BUCK1_LX2
FROM BUCK13 OR => PLACE_NEAR=L8110.2:5MM
OPTIONAL BUCK14
34 PPVDD_P U_LDO_PREREG F15 VDD_MAIN_WIDAC BUC 1_LX2 G4 MIRROR_WITH=C811A MIRROR_ ITH=C811C MIRROR_WITH=C811E PLACE_NEAR=L811 .2:5MM
34 33 32 PP1V5_VLDOINT_MPMU K11 VDD_MAIN 34
CRITICAL V17 VDD_MAIN1

OUT
L8112 CRITICAL CRITICAL
0.1UH-20%-10.3A-0.01OHM
1 C8 30 BUCK1_LX3 E1 BUCK1_LX3
DIDT=TRUE PCCE20161B-SM CRITICAL
1 C81H6 1 C81H7 1 C811F 1 C811G
E19 VDD_MAIN_DRV BUCK1_LX3 E2 SWITCH_NODE=TRUE 12PF 3 0PF 2.2UF 2.2UF
10UF 5% +/-0 1PF 20% 20%
20% BUCK1_LX3 E3 2 25V 2 25V 2 4V 2 4V
2 6.3V
CER-X6S
K10 VDD_MAIN_SNS E4 1 3
NP0-C0G
0201
NP0-C0G
0201
X6S-CERM
0201
X6S-CERM
0201
0402 BUCK1_LX3
F19 PLACE_NEAR=L8111.3:5MM
VDD_MAIN_SNS_WLED PLACE_NEAR=L8111.4:5MM PLACE_SIDE=TOP
OUT 34 PLACE_NEAR=U8100:5MM
PLACE_SIDE=TOP
44 31 PMU_VDD_HI H8 VDD_BOOST_SNS 2 4 PLACE_NEAR=U8100:5MM
BUCK1_LX4 J1 BUCK1_LX4
DIDT=TRUE
FED BY SPMU BUCK13 (1.2V) 102
=> PP1V25_ 2 R16 VDDIO_1V2 BUC 1_LX4 J2 SWITCH_NODE=TRUE 152S01268
BUCK1_LX4 J3
101 PP1V8_S2 N16 VDDIO_BUCK3
FED BY MPMU BUCK3 (1.8V) =>
CRITICAL CRITICAL
BUCK1_LX4 J4
R810B XW8110
SHORT-14L-0.1MM-SM
COINCELL BATTERY 105
=> PP3V8_AON_MPMU_ISNS_VIN N20 VDD_RTC_ALT 0
1 C8131 1 C8 32 BUCK1_FB 1
5% 1/20W
2 BUCK1_FB_R
MF 0201
1 2
0.1UF 0.1UF 34 32 31 VSS_ANA_MPMU K6 VPP PLACE_NEAR=U8100.D6:15MM NO_XNET_CONNECTION=1
10% 10% BUCK1_FB D6
2 10V 2 10V
X6S-CERM X6S-CERM NOSTUFF PPVDD_SOC_S1 101
0201 0201 BUCK1_VSS_FB E6 VSS_ANA_MPMU 32 34
L8120 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1.0UH-20%-4A-0.038OHM 1 C8120 1 C8121 1 C8122 1 C8123 1 C8124 1 C8125 1 C8126 1 C8127
PP3V8_AON_MPMU_ISNS_VIN 15UF 15UF 15UF 15UF 15UF 15UF 15UF 15UF
105 34 33 31
PLACE_NEAR=U8110.5:5MM 34 BUCK2_LX0 1 2 CRITICAL 20% 20% 20% 20% 20% 20% 20% 20%
DIDT=TRUE 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V
1 C8128 BUCK2_LX0 Y20 SWITCH_NODE=TRUE PIKA20161B-COMBO X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
0 1UF L8121
OMIT_TABLE 10%
0.1UH-20%-10.3A-0.01OHM
U8110 2 6.3V
CERM-X5R PCCE20161B-SM
R8100 0201 18 BUCK2_LX1 CRITICAL CRITICAL CRITICAL
NCS333ASQ3 BUCK2_LX1 34
PPBUS_AON 1
887K 2 MPMU_SNS_DIV 1 SC70-5-COMBO BUCK2_LX1 Y18 DIDT=TRUE
SWITCH_NODE=TRUE
1 C81H8 1 C81H9 1 C812A 1 C812B
101
12PF 3.0PF 2.2UF 2.2UF
0.1% 4 PMU_VDD_HI 31 44
1 3 5% +/-0.1PF 20% 20%
OUT
1/20W
1 2 25V
NP0-C0G 2 25V
NP0-C0G 2 4V
X6S-CERM 2 4V
X6S-CERM
3
TK
0201 R8101 0201 0201 0201 0201
453K BUCK2_LX2 W16 34 BUCK2_LX2 2 4 PLACE_NEAR=L8120.2:5MM
1% Y16 DIDT=TRUE PLACE_NEAR=L8120.2:5MM PLACE_SIDE=TOP
1/20W BUCK2_LX2 SWITCH_NODE=TRUE PLACE_NEAR=U8100:5MM
MF PLACE_SIDE=TOP
2 201 152S01268 PLACE_NEAR=U8100:5MM
OMIT_TABLE R810C XW8120
SHORT-14L-0.1MM-SM
V20 BUCK2_FB 1
0 2 BUCK2_FB_R 2 1
BUCK2_FB
5% 1/20W MF 0201
U20 PLACE_N AR=U8100.V20:15MM NO_XNET_CONNECTION=1 C M TE E T M NC TE
BUCK2_VSS FB PAGE TITLE

VSS_ANA_MPMU
PMU: MASTER INPUT PWR & BUCKS
T BLE_5_HE D
32 33 34
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
T BLE_5_IT M
103S00385 1 RES,TK,887KOHM,0.1%,1/20W,0201 R8100 CRITICAL PBUS_3S <== FOR 3S BATTERY

T BLE_5_IT M
103S00480 1 RES,MF,453KOHM,0.1%,1/20W,0201 R8101 CRITICAL PBUS_3S

T BLE_5_IT M
103S00481 1 RES,MF,910KOHM,0.1% 1/20W,0201 R8100 CRITICAL PBUS_12VDCIN <== FOR 12V DCIN
T BLE_5_IT M
103S00482 1 RES,MF,348KOHM,0.1%,1/ 0W,0201 R8101 CRITICAL PBUS_12VDCIN

T BLE_5_IT M
103S00385 1 RES,TK,887KOHM,0.1%,1/20W,0201 R8100 CRITICAL PBUS_15P8VDCIN <== FOR 15.8V DCIN

T BLE_5_IT M
103S0413 1 RES,MF,180KOHM,0.1%,1/20 0 1 R8101 CRITICAL PBUS_ 5 8VDCIN

PP1V8_S2
MASTER PMU BUCKS & GND 1
CRITICAL
C8230 1
CRITICAL
C8231 1
CRITICAL
C8232 1
CRITICAL
C8233 1
CRITICAL
C8234 1
CRITICAL
C8235 1 C82D0 1 C82D1
01

OMIT_TABLE 20% 20% 20% 20% 20% 20% 5% +/-0.1PF
2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 25V
NP0-C0G 2 25V
NP0-C0G
0402 0402 0402 0402 0402 0402 0201 0201
U8100 L8230
OMIT_TABLE TMLT46B0-JPE OUT 34 0.47UH-20%-4A-0.027OHM
WLCSP
SYM 2 OF 6 BUCK3_LX0 2 1 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CR TICAL CRITICAL PLACE_NEAR=L8230.1:5MM
U8100 3 MPMU_ADC_IN K9 ADC_IN BUCK3_LX A16 DIDT=TRUE
SWITCH_NODE=TRUE 2012 1 C8236 1 C8237 1 C8238 1 C8239 1 C823A 1 C823B PLACE_NEAR=L8230.1:5MM
TMLT46B0-JPE B16 10UF 10UF 10UF 10UF 10UF 10UF
BUCK3_LX
WLCSP 34 33 31 PP1V5_VLDOINT_MPMU C7 VDD_ANA R820A XW8230 20% 20% 20% 20% 20% 20%
N1 VSS_BUCK0
SYM 6 OF 6
VSS A18 VSS_ANA_MPMU 32 34
C11
C15
VDD_ANA
BUCK3_FB 1
0 2 BUCK3_FB_
SHORT-14L-0.1MM-SM
2 1
2 6.3V
CER-X6S
0402
2 6.3V
C R-X6
0402
2 6.3V
CER-X6S
0402
2 6.3V
C R-X6S
0402
2 6.3V
CER-X6
0402
2 6.3V
CER-X6S
0402 D
VDD_ANA
N2 VSS_BUCK0 VSS B8 VSS_ANA_MPMU 32 33 34 PLACE_NEAR=U8100.C15:5MM
F5 BUCK3_FB D16 5% 1/20W MF 0201 NO_XNET_CONNECTION=1
VDD_ANA PLACE_NEAR=U8100.D16:15MM
N3 VSS_BUCK0 VSS B18 VSS_ANA_MPMU 32 34
1 C8206 F18 VDD_ANA BUCK3_VSS_FB C16 VSS_ANA_MPMU
N4 VSS_BUCK0 VSS C5 0.1UF 32 34
L8270 NOSTUFF NOSTUFF PPVDD_CPU_SRAM_AWAKE 101
10% J15 VDD_ANA
U1 VSS_BUCK0 VSS C6 VSS_ANA_MPMU 31 32 34 2 10V
X6S-CERM K5 OUT 34 1.0UH-20%-4A-0.038OHM CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
VDD_ANA
U2 VSS_BUCK0 VSS C9 0201
K8 VDD_ANA BUCK7_LX0 2 1 CRITICAL
1 C8270 1 C8271 1 C8272 1 C8273 1 C8274 1 C8275 1 C8276 1 C8277
U3 VS _BUCK0 VSS C10 DIDT=TRUE 15UF 15UF 15UF 15UF 15UF 15UF 15UF 15UF
L5 VDD_ANA BUCK7_LX0 Y12 SWITCH_NODE=TRUE PIKA20161B-COMBO 20% 20% 20% 20% 20% 20% 20% 20%
U4 VSS_BUCK0 VSS C13 VSS_ANA_MPMU 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V
W5 VSS_BUCK0 VSS C17 VSS_ANA_MPMU
32 33 34
P18 VDD_ANA L8271 X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
X6S
0402
32 34
R5 VDD_ANA
OUT 34 0.22UH-20% 6.7A-0.023OHM
Y1 VSS_BUCK0 VSS D5 CRITICAL
V7 VDD_ANA BUCK7_LX1 W14 BUCK7_LX 2
Y2 VSS_BUCK0 VSS D7 VSS_ANA_MPMU 31 32 34
V11 Y14 DIDT=TRUE PINA20121T-SM
Y3 D10 VDD_ANA BUCK7_LX1 SWITCH_NODE=TRUE
VSS_BUCK0 VSS V15 CRITICAL CRITICAL
VDD_ANA
Y4 VSS_BUCK0 VSS D11
V19 VDD_ANA R820B XW8270 1 C82D2 1 C82D3 1 C8278 1 C8279
34 GND Y5 VSS_BUCK0 VSS D15 VSS_ANA_MPMU 32 33 34 0 SHORT-14L-0.1MM-SM 12PF 3.0PF 2.2UF 2.2UF
BUCK7_FB U12 BUCK7_FB 1 2 BUCK7_FB_R 2 1 5% +/-0.1PF 20% 20%
VSS D18 D9 VDD_DIG 2 25V
NP0-C0G 2 25V
NP0-C0G 2 4V
X6S-CERM 2 4V
X6S-CERM
A1 D19 E16 V12 5% 1/20W MF 0201 NO_XNET_CONNECTION=1 0201 0201 0201 0201
VSS_BUCK1 VSS VDD_DIG BUCK7_VSS_FB PLACE_NEAR=U8100.U12:15MM
PLACE_NEAR=L8270.1:5MM PLACE_SIDE=TOP
A2 VSS_BUCK1 VSS D20 VSS_ANA_MPMU 32 34 J7 VDD_DIG VSS_ANA_MPMU 32 34 PLACE_NEAR=L82 .1:5MM PLACE_NEAR U8100:5MM
A3 VSS_BUCK1 VSS E5 M18 VDD_DIG L8280 PLACE_SIDE=TOP
A4 VSS_BUCK1 VSS E7 VSS_ANA_MPMU 31 32 34 P9 VDD_DIG
OUT 34 1.0UH-20%-4A-0.038OHM PLACE_NEAR=U8100:5MM
A5 VSS_BUCK1 VSS E15 VSS_ANA_MPMU 32 33 34 R17 VDD_DIG BUCK8_LX0 A8 BUCK8_LX0 2 1 CRITICAL PPVDD_DISP_S1 101
B5 E17 DIDT=TRUE
VSS_BUCK1 VSS SWITCH_NODE=TRUE PIKA20161B CO BO CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
D1 VSS_BUCK1 VSS E20 VSS_ANA_MPMU 32 34 32 MPMU_VREF K12 VREF L8281 1 C8280 1 C8281 1 C8282 1 C8283 1 C8284 1 C8285 1 C82D4 1 C82D5
D2 VSS_BUCK1 VSS F6 VSS_ANA_MPMU 31 32 34 BUCK8_LX1 A10 OUT 34 0.22UH-20%-6.7A-0.023OHM 15UF 15UF 15UF 15UF 15UF 15UF 12PF 3.0PF
34 IN MPMU_VBAT J10 VBAT 1 CRITICAL
20% 20% 20% 20% 20% 20% 5% +/-0.1PF
D3 VSS_BUCK1 VSS F16 BUCK8_LX1 B10 BUCK8_LX1 2 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 25V
NP0-C0G 2 25V
NP0-C0G
DIDT=TRUE
D4 VSS_BUCK1 VSS F17 34 MPMU_IBAT J9 IBAT SWITCH_NODE=TRUE PINA20121T-SM 0402 0402 0402 0402 0402 0402 0201 0201
H1 VSS_BUCK1 VSS F21
IN
R820C XW8280
SHORT-14L-0.1MM-SM
PLACE_NEAR=L8280.1:5MM
MPMU_IREF J8 0
H2
H3
VSS_BUCK1
VSS_BUCK1
VSS
VSS
F22
G5
VSS_ANA_MPMU 32 34
32 IREF
BUCK8_FB D8 BUCK8_FB 1
5% 1/20W MF 0201
2 BUCK8_FB_R 2 1
NO_XNET_CONNECTION=1 1
CRITICAL
C8286 1
CRITICAL
C8287
C
BUCK8_VSS_FB C8 PLACE_NEAR=U8100.D8:15MM
34 GND H4 VSS_BUCK1 VSS G6 VSS_ANA_MPMU 31 32 34
2.2UF 2.2UF
VSS_ANA_MPMU 32 33 34
20% 20%
VSS G15 2 4V 2 4V
W17 VSS_BUCK2 VSS G18 VSS_ANA_MPMU L8290 X6S-CERM
0201
X S-CE M
0201
32 33 34 OUT 34 0.47UH-20%-4A-0.027OHM PLACE_SIDE=TOP PLACE_SIDE=TOP
W21 H5
VSS_BUCK2 VSS
BUCK9_LX A12 BUCK9_LX0 2 1 CRITICAL PLACE_NEAR=U8100:5MM PLACE_NEAR=U8100:5MM
W22 VSS_BUCK2 VSS H6 VSS_ANA_MPMU 31 32 34
B12 DIDT=TRUE 2012
PPVDD_DCS_S1 101
Y17 H15 BUCK9_LX SWITCH_NODE=TRUE
VSS_BUCK2 VSS CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
Y21 VSS_BUCK2 VSS H18 VSS_ANA_MPMU 32 33 34
R820D XW8290 1 C8290 1 C8291 1 C8292 1 C8293 1 C8294 1 C8295 1 C82D6 1 C82D7
34 GND Y22 VSS_BUCK2 VSS J5 0 SHORT-14L-0.1MM-SM 15UF 15UF 15UF 15UF 15UF 15UF 12PF 3.0PF
BUCK9_FB D12 BUCK9_FB 1 2 BUCK9_FB_R 2 1 20% 20% 20% 20% 2 % 20% 5% +/-0.1PF
VSS J6 VSS_ANA_MPMU 31 32 34 2 2V
X6S
2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S
25V
NP0-C0G 2 25V
NP0-C0G
5% 1/20W MF 0201 NO_XNET_CONNECTION=1
A17 VSS_BUCK3 VSS J13 VSS_ANA_MPMU 32 34 BUCK9_VSS_FB C12 PLACE_NEAR=U8100.D12:15MM
0402 0402 0402 0402 0402 0402 0201 0201
PLACE_NEAR L8290.1:5MM
GND VSS_ANA_MPMU
www.teknisi-indonesia.com1.0UH-20%-4A
34 B17 VSS_BUCK3 VSS J17 32 33 34 P ACE_NEAR=L8290.1:5MM
VSS J18 L82B0
W13 VSS_BUCK7 VSS K15 OUT0 34 038OHM
34 GND Y13 VSS_BUCK7 VSS K18 VSS_ANA_MPMU 32 33 34 BUCK11_LX0 Y8 BUCK11_LX0 2 1 CRITICAL NOSTUFF NOSTUFF PPVDD_ECPU_AWAKE 101
L6 DIDT=TRUE
VSS SWITCH_NODE=TRUE PIKA20161B-COMBO CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
A9 VSS_BUCK8 VSS L7 VSS_ANA_MPMU 31 32 34 L82B1 1 C82B1 1 C82B2 1 C82B3 1 C82B4 1 C82B6 1 C82B7 1 C82B8 1 C82B9
34 GND B9 VSS_BUCK8 VSS L8 BUCK11_LX1 W10 OUT 34 0.22UH-20%-6.7A-0.023OHM 15UF 15UF 15UF 15UF 15UF 15UF 15UF 15UF
20% 20% 20% 20% 20% 20% 20% 20%
VSS L9 BUCK11_LX1 Y10 BUCK11_LX1 2 1 CRITICAL 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V
DIDT=TRUE X6S X6S X6S X6S X6S X6S X6S X6S
A13 VSS_BUCK9_14 VSS L10 SWITCH_N DE=TRUE PINA20121T-SM 0402 0402 0402 0402 04 2 0402 0402 0402
34 GND B13 VSS_BUCK9_14 VSS L11 R820E XW82B0

SHORT-14L-0.1MM-SM
L12 VSS_ANA_MPMU U8 BUCK11_FB 0 BUCK11_FB_R
VSS 32 34 BUCK11_FB 1 2 2 1 CRITICAL CRITICAL
W9 VSS_BUCK11 VSS L15 VSS_ANA_MPMU 32 33 34
BUCK11_VSS_FB V8 5% 1/20W
PLACE_NE R=U8100.U8:15MM
MF 0201 NO_XNET_CONNECTION=1 1 C82D8 1 C82D9 1 C82BA 1 C82BB
34 GND Y9 VSS_BUCK11 VSS M5 12PF 3.0 F 2.2UF 2.2UF
VSS_ANA_MPMU 32 34
5% +/-0 1PF 20% 2 %
VSS N5 VSS_ANA_MPMU 31 32 34 2 25V
NP0-C0G 2 25V
NP0-C0G 2 4V
X6S-CERM 2 4V
X6S-CERM
33 GND V22 VSS_BSTLQ VSS N18 VSS_ANA_MPMU 31 32 33
0201 0201 0201 0201
34 PLACE_NEAR=L82B0.1:5MM PLACE_SIDE=TOP PLACE_SIDE=TOP
VSS N22 VSS_ANA_MPMU 34 PLACE_NEAR=L82B1.1:5MM PLACE_NEAR=U8100:5MM PLACE_NEAR=U8100:5MM
A21 P5 BUCK14_LX A14 BUCK14_LX 34
VSS_WLED_LP VSS B14
BUCK14_LX
A22 VSS_WLED_LP VSS P7 VSS_ANA_MPMU 31 32 34
B21 VSS_WLED_LP VSS R18 VSS_ANA_MPMU 31 32 33 34
B22 VSS_WLED_LP VSS T5 VSS_ANA_MPMU 31 32 34
BUCK14_FB D14 BUCK14_FB_MPMU 34
VSS T18 VSS_ANA_MPMU 31 32 33 34
A20 VSS_WLED_HP1 VSS U5 VSS_ANA_MPMU 31 32 34 BUCK14_VSS FB C14 VSS_ANA_MPMU 32 33 34
B20 VSS_WLED_HP1 VSS U19 VSS_ANA_M MU 31 32 33 34 VIN FROM BUCK13 IS POR FOR LDO3, 8, 20. IF PDN (VMIN VIOLATION, WHEN LDO8 IN DROPOUT MODE)
SWITCHED RAILS
C20 VSS_WLED_HP1 VSS V5 VSS_ANA_MPMU 31 32 34 101 PP1V8_S2 R21 VDD_SW1 BUCK_SW1 P21 PP1V8_AWAKE 32
102
IS AN ISSUE THEN BUCK14 WILL BE THE BACKUP OPTION. THIS WOULD THEN REQUIRE ADDING BEAD AND CAPS
VSS V6 FROM BUCVK3 => R22 VDD_SW1 BUCK_SW1 P22
D21 VSS_WLED_HP2 VSS V9 VSS_ANA_MPMU 32 34 T20 VDD_SW2 BUCK_SW2 T19 NC_MPMU_BUCK_SW2 NO_TEST=1
D22 VSS_WLED_HP2 VSS V10 R19 VDD_SW3 BUCK_SW3 P19
VSS V13 102 32 PP1V25_S2 R20 VDD_SW3 BUCK_SW3 P20 PP1V25_AWAKE_IO 32 102
34
32
33
VSS_ANA_MPMU J11 VS _REF VSS V14 FROM BUCK13 =>
49
VSS V16
34 VSS_ANA_MPMU K7 VSS_DFT_2 VSS V18 VSS_ANA_MPMU 31 32 33 34
VSS V21 VSS_ANA_MPMU 32 34
VSS W8 Decoupling: VDD_SW3 Decoupling:BUCK_SW1

VSS W12 VSS_ANA_MPMU 32 34
VSS W20 VSS_ANA_MPMU 32 34 PP1V25_S2 32 102 PP1V8_AWAKE 32 102

1 C8201 1 C8202 1 C8203
10UF 10UF 10UF
20% 20% 20%
MPMU_VREF 32 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S
0402 0402 0402
MPMU_IREF
NOSTUFF
32
C M TE
PAGE TITLE
E T M NC TE
A
1 C8204 1
R8201 1 C8205 Decoupling: BUCK_SW3 PMU: MASTER BUCKS & GND
1.5UF 200K 0.1UF PP1V25_AWAKE_IO 32 102
20% 0.1% 10%
2 6.3V 1/20W 2 6.3V CRITICAL CRITICAL
XW82B2 CER-X5R
0201 TF CERM-X5R
0201 1 C8240 1 C8241
SHORT-14L-0.1MM-SM 2 0201
49 34 33 32 VSS_ANA_MPMU 2 1 MPMU_VREF_IREF_RTN 15UF 15UF
20% 20%
2 2V
X6S 2 2V
X6S
0402 0402
PLACEMENT NOTE:
CONNECT VSS_REF THROUGH ALL GND PLANES PLACE XW AT VSS_REF PIN, ROUTE VSS_RTN
BACK FROM THE VREF / IREF PASSIVES
2 1
OMIT_TABLE
MASTER PMU LDO,ADC, & GPIO OMIT_TABLE
U8100
TMLT46B0-JPE
U8100 WLCSP
TMLT46B0-JPE SYM 4 OF 6
WLCSP 49 P3V8AONVR_THMSNS E8 TDEV1 GPIO1 P16 IPD_LID_OPEN_1V8 73 85 87 89
IN IN
SYM 5 OF 6
NO_TEST=1 49 IN SOC_THMSNS1 F9 TDEV2 GPIO2 T9 CHGR_AUX_OK IN 23
NC_MPMU_IDAC_OUT<0> G17 IDAC_OUT<0> WLED_LP_LX C21 NC_MPMU_WLED_LP_LX_0 NO_TEST=1
NO_TEST=1 49 IN SOC_THMSNS3 F8 TDEV3 GPIO3 T7 SWD_NUB_PMU_SWDIO BI 9 29
NC_MPMU_IDAC_OUT<1> G16 IDAC_OUT<1> WLED_LP_LX C22 NC_MPMU_WLED_LP_LX_1 NO_TEST=1
NO_TEST=1 9 IN NC_MPMU_TDEV4 F7 TDEV4 GPIO4 R11 CODEC_WAKE_L IN 76
NC_MPMU_IDAC_OUT<2> G14 IDAC_OUT<2>
NO_TEST=1 49 IN NC_MPMU_TDEV5 G9 TDEV5 GPIO5 T8 WLBT_WAKE IN 62 63
NC_MPMU_IDAC_OUT<3> G13 IDAC_OUT<3>
NO_TEST=1 49 IN WLANBT_THMSNS G10 TDEV6 GPIO6 U7 MPMU_GPIO6 IN 34
NC_MPMU_IDAC_OUT<4> H17 IDAC_OUT<4> WLED_HP1_LX A19 NC_MPMU_WLED_HP1_LX_0 NO_TEST=1
NO_TEST=1 49 IN MPMU_THMSNS G8 TDEV7 GPIO7 T11 NC_HDMI_CEC_IRQ OUT 34 <= FOR J274 ONLY
NC_MPMU_IDAC_OUT<5> H16 IDAC_OUT<5> WLED_HP1_LX B19 NC_MPMU_WLED_HP1_LX_1 NO_TEST=1
NO_TEST=1 49 IN CHGR_THMSNS G7 TDEV8 GPIO8 U10 NC_USB3_WAKE IN 34 <= FOR J274 ONLY
NC_MPMU_IDAC_OUT<6> H14 IDAC_OUT<6> WLED_HP1_LX C19 NC_MPMU_WLED_HP1_LX_2 NO_TEST=1
NO_TEST=1 GPIO9 R12 NC_HDMI_RESET_L OUT 34 <= FOR J274 ONLY
NC_MPMU_IDAC_OUT<7> H13 IDAC_OUT<7> 103S00511 MPMU_TCAL F10 TCAL
NO_TEST=1 GPIO10 U9 MPMU_GPIO10 OUT 34
NC_MPMU_IDAC_OUT<8> J16 IDAC_OUT<8> CRITICAL 2
NO_TEST=1 R8320 GPIO11 T12 P3V3S2_PWR_EN 33 38
NO_TEST=1
NC_MPMU_IDAC_OUT<9> J14 IDAC_OUT<9> WLED_HP2_LX E21 NC_MPMU_WLED_HP2_LX_0
NO_TEST=1 3.92K
1 C8320 TDEV GPIO GPIO12 U11 PVDD1_PWR_EN
OUT
NC_MPMU_IDAC_OUT<10> K17 IDAC_OUT<10> WLED_HP2_LX E22 NC_MPMU_WLED_HP2_LX_1 NO_TEST=1 0.1% 100PF OUT 33 39
NO_TEST=1 0201-2 5% GPIO13 T13 WLBT_PWR_EN OUT 33 62 63 94

NC_MPMU_IDAC_OUT<11> K16 IDAC_OUT<11> 1/20W 2 25V
NO_TEST=1 MF 1 C0G GPIO14 U13 MPMU_GPIO14 OUT 34
NC_MPMU_IDAC_OUT<12> K14 IDAC_OUT<12> 0201
NO_TEST=1 GPIO15 M13 SE_PWR_EN OUT 20 33
NC_MPMU_IDAC_OUT<13> K13 IDAC_OUT<13> WLED_VOUT_FB E18 NC_MPMU_WLED_VOUT_FB NO_TEST=1 34 VSS_ANA_MPMU
NO_TEST=1 GPIO16 M14 SENSOR_PWR_EN OUT 33 39 44
NC_MPMU_IDAC_OUT<14> L17 IDAC_OUT<14>
NO_TEST=1 GPIO17 N14 NAND0_LPB_L OUT 64 65 67 HDMI_PWR_EN==> FOR J274 ONLY
NC_MPMU_IDAC_OUT<15> L16 IDA _O T 15>
NO_TEST=1 GPIO18 R13 BL_PWR_EN OUT 71 94 HDMI_CECFET_EN==> FOR J274 ONLY
CRITICAL NC_MPMU_IDAC_OUT<16> L14 IDAC_OUT<16> VCP_OUT_SPARE U21 NC_MPMU_VCP_OUT_SPARE NO_TEST=1
NO_TEST=1 GPIO19 U14 P3V8AON_LPM
L8300 NC_MPMU_IDAC_OUT<17> L13 IDAC_OUT<17>
VMBX_SPARE J12 NC_MPMU_VMBX_SPARE NO_TEST=1 GPIO20 U15 MPMU_GPIO20
OUT 24 33
0.47UH-20%-1.7A-0.175OHM OUT 34
GPIO21 T14 TPT_MPMU_NAND0_RESET_L OUT 34 NAND RESET NOT POR

34
31 PP3V8_AON_MPMU_ISNS_VIN 1 2 34 MPMU_BSTLQ_LX U22 BSTLQ_LX
33
105 0402-COMBO SWITCH_NODE=TRUE T22 GPIO22 U16 NC_MPMU_GPIO22 OUT 34
DIDT=TRUE BSTLQ_VOUT
GPIO23 U17 NC_USB3_PWR_EN 34
1 C83A0 1 C83A1 VOLTAGE=5V PP5V_BSTLQ_VOUT_MPMU H9 VDD_BOOST GPIO24 R14 NC_UWB_PWR_EN
OUT FOR DESKTOP ONLY (5V USB3 SWITCH ENABLE
12PF 3.0PF OUT 34 FOR J456 ONLY (ENABLE UWB LDO)

5% +/-0.1PF 34 33 31 PP3V8_AON_MPMU_ISNS_VIN H10 VDD_SNS_SPARE GPIO25 N10 P2V5_NAND0_DISCHARGE_EN OUT 66
2 25V 2 25V 105 XW83D0
NP0-C0G
0201
NP0-C0G
0201 SHORT-12L-0 25MM SM GPIO26 P8 NC_MPMU_GPIO26 OUT 34
PLACE_NEAR=L8300.1:5MM 1 2 PP5V_BSTLQ_MPMU T21 VDD_HI_INT1 GPIO27 P17 NC_MPMU_GPIO27 OUT 34

CRITICAL CRITICAL H11 VDD_HI_INT2
VOLTAGE=5V 1 C8310 1 C8311 D13 VDD_HI_INT3 90 89 80 34 33 IN PMU_ONOFF_L P10 BUTTON1 BUTTONO1 N7 MPMU_BUTTONO1 OUT 19 <= NOT USED
10%
0.1UF
10%
0.1UF D17 VDD_HI_INT4 90 89 82 34 33 IN PMU_RSLOC_RST_L M6 BUTTON2 BUTTONS BUTTONO2 N9 NC_MPMU_BUTTONO2 NO_TEST=1 OUT 34 <= NOT USED
2 10V
X6S-CERM 2 10V
X6S-CERM
H12 VDD_HI_INT5 34 IN NC_MPMU_BUTTON3 N8 BUTTON3 BUTTONO3 M7 NC_MPMU_BUTTONO3 OUT 34 <= NOT USED
0201 0201 L18 VDD_HI_INT6 34 IN NC_MPMU_BUTTON4 P11 BUTTON4
CRITICAL CRITICAL PLACE_NEAR=U8100.T21:5MM PLACE_NEAR=U8100.L18:5MM DBLCLICK_DET N6 DBL_CLICK_DET OUT 6
CRITICAL
1 C8300 1 C8301 1 C8302 CRITICAL CRITICAL
20UF 20UF 1 C8316 1 C8317 SOC_WDOG N11 RESET_IN1 RESET* N13 PMU_RESET_L
20% 20% 0.1UF 100 9 IN OUT 5 9 74 89 90 100 << VDDIO_1V2 OD
2 10V
X5R 2 10V
X5R
10% 0.1UF 0.1UF 3 IN UPC_PMU_RESET_1V8 M10 RESET_IN2
2 10V 10% 10% RESET
0402 0402 X6S-CERM
0201 2 10V
X6S-CERM 2 10V
X6S-CERM R8321 100 96 91 89 6 IN SOC_SOCHOT_L M9 RESET_IN3
0201 0201 1K FORCE_DFU T10 SOC_FORCE_DFU T 5 56 89 90
102 35 34 33 29 PP1V8_AON_MPMU 1 2 MPMU_VBUS_DET R7 VBUS_DET << PMOS_OD
PLACE_NEAR=U8100.T22:5MM PLACE_NEAR=U8100.D17:5MM PLACE_NEAR=U8100.H12:5MM
1 C83A2 1 C83A3 OMIT_TABLE
FEED BY PP1V8_AON (LDO9) ==> 1%
1/20W VSS_ANA_MPMU E9 BRICK_ID1
FAULT_OUT* M12 MPMU_FAULT_OUT_L 33 91
12PF 3.0PF MF
34 32
5% +/-0.1PF 201 E10 BRICK_ID2 SCRASH* N12 PMU_SCRASH_L BI 29 91
2 25V 25V
2 NP0-C0G
NP0-C0G
0201 0201 GND
32 34
U8100 IPD >>
90 89 PMU_SHDN M8 SHDN SGPIO_READY_REQ M15 PMU_SGPIO_READY_REQ 29
OUT
TMLT46B0-JPE
WLCSP R8322
SYM 3 OF 6
1
10K 2
SGPIO_SCLK N15 SGPIO_SCLK_R 33
105 34 33 31 PP3V8_AON_MPMU_ISNS_VIN G19 VDD_BOOST_LDO VLDO1 J22 NC_MPMU_VLDO1 102 NOSTUFF SGPIO_SDATA P15 SGPIO_SDATA_R 33
1% SPMI
CRITICAL CRITICAL G21 VDD_BOOST_LDO 1/20W
MF SPMI_SCLK R15 SPMI_NUB_MPMU_CLK 18
1 C8314 1 C8315 H19 VDD_BOOST_LDO VLDO2 K20 NC_MPMU_VLDO2
NO_TEST=1
201
SPMI_SDATA T15 SPMI_NUB_MPMU_DATA
IN
10UF 10UF H21 VDD_BOOST_LDO
BI 18
20% 20%
2 6.3V 6.3V
2 CER-X6S J21 VDD_BOOST_LDO VLDO3 L21 PP1V2_S2 33 102
R83312 33
CER-X6S
0402 0402 NXTAL_MEMS=0 ==> XTAL 34 32 31 VSS_ANA_MPMU N19 NXTAL_MEMS SLEEP_32K U18 PMU_CLK32K_SOC_R 1 PMU_CLK32K_SOC OUT 9 18
M20 VDD_MAIN_LDO CLOCKS PLACE_NEAR=U8100.U18:5MM 5% 1/20W MF 201
VLDO5 K22 NC_MPMU_VLDO5 102 33 MPMU_XIN L22 XIN OUT_32K T16
LDO1 NOT USED ==> 33 MPMU_XOUT M22 XOUT R83302 33
34 NC_MPMU_LDO1_EN N17 LDO1_EN PMU_CLK32K_WLBT_R 1 PMU_CLK32K_WLBT OUT 62 63
VLDO7 H22 PP3V3_S2_UPC 33 102 PLACE_NEAR=U8100.T16:5MM
THIS IS AN OUTPUT ==> 5% 1/20W MF 201
34 33 32 31 PP1V5_VLDOINT_MPMU M21 VLDOINT CRASH* P12 PMU_CRASH_L 33 91
VOLTAGE=1.5V 3 IN DCIN_VSENSE E13 AMUX_A<0>
THIS IS AN OUTPUT ==> VLDO9 M19 PP1V8_AON_MPMU 33 102 DFT_CTRL0 M16 VSS_ANA_MPMU 32 34
34 33 PP1V5_VLDOINT_MPMU N21 VLDORTC 3 IN DCIN_ISENSE F11 AMUX_A<1>
DFT_CTRL1 M17 SWD_NUB_SWCLK IN 9 29
34 IN PBUS_VSENSE E12 AMUX_A<2>
VLDO10 G20 NC_MPMU_VLDO10 102
34 N BMON_ISENSE E11 AMUX_A<3> SYS_ALI E M11 PMU_SYS_ALIVE OUT 33 67 89 100 107
34 OUT MPMU_AMUX_AY G12 AMUX_AY

DECOUPLING: LDORTC KEEP AS NOSTUFF FOR P1 VLDO13 H20 NC_MPMU_VLDO13 103 ACTIVE_READY P13 PMU_ACTIVE_READY OUT 5 55 89 94
PP1V5_VLDOINT_MPMU 33 34 34 IN P3V8AON_HS_ISENSE E14 AMUX_B<0>

REQUEST_DFU R6 MPMU_REQUEST_DFU 33
CRITICAL CRITICAL VLDO14 L19 NC_MPMU_VLDO14 103 34 IN P3V3S2_HS_ISENSE F14 AMUX_B<1>
1 C8326 1 C8327 34 IN P5VS2_HS_ISENSE F12 AMUX_B<2> CPU_TRIGGER0* P6 BUCK0_THERMAL_THROTTLE_L OUT 6 34
1.0UF 1.0UF VLDO16 G22 NC_MPMU_VLDO16 103 34 IN MPMU_HS_ISENSE F13 AMUX_B<3> CPU_TRIGGER1* R9 PMU_VDDHI_UVWARN_L OUT 34 106
20% 20%
2 6.3V
X5R 2 6.3V
X5R 34 OUT MPMU_AMUX_BY G11 A UX_BY GPU_TRIGGER0* R8 BUCK1_THERMAL_THROTTLE_L OUT 6 34
0201-1 0201-1 VLDO19 J20 NC_MPMU_VLDO19 GPU_TRIGGER1* R10 RSVD_GPU_TRIGGER1_L 19 34
BOMOPTION=DESKTOP_COINCELL
NO_TEST=1 R8326 1 100K 2 WLBT_PWR_EN 33 62 63 94
AMUX
UVWARN* P14 PMU_VDDMAIN_UVWARN_L
OUT
6 34
OUT
BOMOPTION=DESKTOP_COINCELL VREF_ADC H7 MPMU_VREF_ADC 5% 1/20W MF 201 NOSTUFF VDD_BOOST_UVLO* T17 TPT_MPMU_BOOST_UVLO_L OUT 34
DECOUPLING: LDOINT 1 C8321 R8327 1 100K 2 SE_PWR_EN 20 33
PP1V5_VLDOINT_MPMU 0.1UF R8313

31 32 33 34 10% 5% 1/20W MF 201 NOSTUFF
2 6.3V MPMU_XTAL1_R 0 MPMU_XOUT
CRITICAL CRITICAL CERM-X5R 1 2 33
1 C8322 1 C830D 1 C830G 1 C830H 49 34 32 VSS_ANA_MPMU 0201 R8328 1 100K 2 P5VS2_PWR_EN_RC 34 37 84 CRITICAL 1/20W 5% MF 0201 NOSTUFF MPMU_XIN 33
10UF 10UF 220PF 220PF 5% 1/20W MF 201 Y8301 1
R8318
20% 20% 10% 10%
2 6.3V 2 6.3V 16V 2 16V 32.768KHZ 20PPM-12.5PF 1M
CER-X6S
0402
CER-X6S
0402
CER-X7R
0201
CER-X7R
0201 R8329 1 100K 2 P3V3S2_PWR_EN 33 38
1 2 5%
1/20W
1.60X1.00-SM MF
5% 1/ 0W MF 201 NOSTUFF 2 201
INTEGRATOR ALIAS TO: PP1V25_S2 102 CRITICAL CRITICAL
DECOUPLING: LDO3 DECOUPLING: LDO7 1V8 OCARINA=Y
R8343 1 10K R8335 1 100K 2
1 C8312 1 C8313
1V2 OCARINA=N 2 PMU_SYS_ALIVE 33 67 89 100 107 SENSOR_PWR_EN 33 39 44
18PF 18PF
PP1V2_S2 33 102 PP3V3_S2_UPC 33 102
5% 5%
5% 1/20W MF 201 NOSTUFF 5% 1/20W MF 201 NOSTUFF 2 25V
C0G-CERM 2 25V
C0G-CERM
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL VSS_ANA_MPMU 0201 0201
NOSTUFF SINCE PMU_SYS_ALIVE IS PUSH PULL PER OTP 34
1 C8307 1 C830A 1 C8309 1 C8303 1 C830E R8336 1 100K 2 IPD_PWR_EN
10UF 10UF 10UF 10UF 10UF 34 84 92
20% 20% 20% 20% 20% 5% 1/20W MF 201
2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S 2 6.3V
CER-X6S
0402 0402 0402 0402 04 2 PP1V8_AON_MPMU 29<== LDO9 POWER ALIAS
33 34 35 102
R8334 1 10K 2 MPMU_REQUEST_DFU 33
NOSTUFF R8324 1 10K 2 PMU_ONOFF_L 33 34 80 89 90

5% 1/20W MF 201 R8341
SGPIO_SCLK_R 20 SGPIO_SCLK
DECOUPLING: LDO9 5% 1/20W MF 201
R8337 1 100K 2 33 1 2 OU 29
C M TE
PAGE TITLE
E T M NC TE
PP1V8_AON_ PMU P3V8AON_LPM

CRITICAL CRITICAL
33 102
R8325 1 100K 2 PMU_RSLOC_RST_L 33 34 82 89 90 5% 1/20W MF 201 NOSTUFF
24 33 PL CE_NEAR=U8100.N15:5MM 5%
1/20W
MF
PMU: MASTER LDO & GPIO
201
1 C8304 1 C830C 5% 1/20W MF 201
R8344 1 100K 2
1UF 1UF R8338 1 100K 2 PVDD1_PWR_EN
20% 20% MPMU_FAULT_OUT_L 33 91
33 39
R8342
2 10V 2 10V 5% 1/20W MF 201 NOSTUFF 20
X6S-CERM
0201
X6S-CERM
0201 5% 1/20W MF 201 33 SGPIO_SDATA_R 1 2 SGPIO_SDATA OUT 29
PLACE_NEAR=U8100.P15:5MM 5%
R8339 1 10K 2 PMU_CRASH_L 33 91
1/20W
MF
201
5% 1/20W MF 201 NOSTUFF
2 1
PP1V2 LDO VDD IN option (LDO3, 8, 20) MASTER PMU AMUX ALIAS ADDITIONAL VDD_MAIN DECOUPLING CAPS
14X 1.0UF X6S
Stuff R8422 for BUCK14 pre-regulator (Proto2 and later) 44 IN DCIN_VSENSE DCIN_VSENSE OUT 33
MAKE_BASE=TRUE 105 34 33 31 PP3V8_AON_MPMU_ISNS_VIN
44 IN DCIN_ISENSE
MAKE_BASE=TRUE
DCIN_ISENSE OUT 33
1 C84C0 1 C84C1 1 C84C2 1 C84C3 1 C84C4 1 C84C5 1 C84C6 1 C84C7
P1V2_PREREG:BUCK13 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 2 %
R8411 44 IN PBUS_VSENSE PBUS_VSENSE OUT 3 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM
10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S CERM
PP1V25_S2 1
0 2 PPVDD_PMU_LDO_PREREG MAKE_BASE=TRUE 0201 0201 0201 0201 0201 0201 0201 0201
102
MAKE_BASE=TRUE
1/16W 5% MF 0402 MIN_NECK_WIDTH=0.1000 44 IN BMON_ISENSE BMON_ISENSE OUT 33
116S00014 MIN_LINE_WIDTH=0.2000 MAKE_BASE=TRUE
VOLTAGE=1.4
105 34 33 31 PP3V8_AON_MPMU_ISNS_VIN
P1V2_PREREG:BUCK14
R8422 PPVDD_PMU_LDO_PREREG 31 44 IN P3V8AON_HS_ISENSE
P3V8AON_HS_ISENSE OUT 33
1 C84C8 1 C84C9 1 C84CA 1 C84CB 1 C84CC 1 C84CD 1 C84CE
0 PPVDD_PMU_LDO_PREREG 28
1UF 1UF 1UF 1UF 1UF 1UF 1UF
102 PP1V4_LDO_PREREG 1 2 20% 20% 20% 20% 20% 20% 20%
PPVDD_PMU_LDO_PREREG 28 44 IN P3V3S2_HS_ISENSE P3V3S2_HS_ISENSE OUT 33 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM 2 10V
X6S-CERM
1/16W 5% MF 0402 MAKE_BASE=TRUE NO_TEST=1 0201 0201 0201 0201 0201 0201 0201
116S00014 P5VS2_HS_ISENSE P5VS2_HS_ISENSE
44 IN OUT 33
BUCK 14 L84E0
45 IN MPMU_HS_ISENSE
MPMU_HS_ISENSE OUT 33
GPU RAIL N&V DOE CAPS

0.47UH-20%-4A-0.027OHM
32 IN BUCK14_LX 34 BUCK14_LX 1 2 PP1V4_LDO_PREREG 102 101 31 PPVDD_GPU_AWAKE
MAKE_BASE=TRUE 2012
DIDT=TRUE MIRROR_WITH=C84E0 MIRROR_WITH=C84E2 MIRROR_WITH=C84E4
SWITCH_NODE=TRUE
PLACE_NEAR=U8100.D14:15MM 1 C84E0 1 C84E1 1 C84E2 1 C84E3 1 C84E4 1 C84E5 1 C84EA 1 C84EB 1 C8410 1 C8411 1 C8412 1 C8413 1 C8414 1 C8415
R84E0 XW84E0 20%
15UF
20%
15UF 15UF
20%
15UF
20%
15UF
20%
15UF
20% 5%
12PF 3.0PF
+/-0.1PF 20%
15UF 15UF
20%
15UF
20%
15UF
20%
15UF
20%
15UF
20%
BUCK14_FB_MPMU BUCK14_FB_MPMU 0 BUCK14_FB_R
32 OUT 1 2 1 2 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 25V
NP0-C0G 2 25V
NP0-C0G 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S 2 2V
X6S
MAKE_BASE=TRUE 5% 1/20W MF 0201 SM 0402 0402 0402 0402 0402 0402 0201 0201 0402 0402 0402 0402 0402 0402
PLACE_SIDE=TOP PLACE_SIDE=TOP PLACE_SIDE=TOP PLACE_SIDE=TOP PLACE_SIDE=TOP PLACE_SIDE=TOP
BOMOPTION=NV_DOE
BOMOPTION=NV_DOE BOMOPTION=NV_DOE
MASTER PMU SIGNALS EVT GPIO changes <rdar://59851797>
BOMOPTION=NV_DOE BOMOPTION=NV_DOE BOMOPTION=NV_DOE
NC_MPMU_LDO1_EN NC_MPMU_LDO1_EN
33
33 NC_MPMU_BUTTON3
MAKE_BASE=TRUE
NC_MPMU_BUTTON3
MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
34 33 IN MPMU_GPIO6
IPD_PMU_GPIO:EVT
R84311
1/20W
0
5%
2
MF 0201
IPD_PWR_EN OUT 33 84 92 MASTER PMU PROBE POINTS
33 NC_MPMU_BUTTON4 NC_MPMU_BUTTON4
MAKE_BASE=TRUE NO_TEST=1 0 PP8403
SM P4MM
PP
1 MPMU_ADC_IN
NO_TEST=1
OUT 32 31 IN BUCK0_LX0
NO_TEST=1
1
PP PP8406
P4MM SM
33 NC_MPMU_BUTTONO2 NC_MPMU_BUTTONO2 34 33 IN MPMU_GPIO14 R8432 1 2
MAKE_BASE=TRUE NO_TEST=1 IPD_PMU_GPIO:PROTO 1/20W 5 MF 0201 PP1V8_AON_MPMU 29 33 34 35 102 R8402
5% 1/20W
2 1M
MF 201
31 IN BUCK0_LX1
NO_TEST=1
1
PP PP8407
P4MM SM
33 NC_MPMU_BUTTONO3 NC_MPMU_BUTTONO3 1
MAKE_BASE=TRUE NO_TEST=1 R8420 PP8404 PP
1 MPMU_AMUX_AY OUT 33 31 IN BUCK0_LX2 1
PP PP8408
GPIO7 33 NC_HDMI_CEC_IRQ NC_HDMI_CEC_IRQ 100K P4MM NO_TEST=1 NO_TEST=1 P4MM SM
MAKE_BASE=TRUE NO_TEST=1 5%
1/20W
GPIO8 33 NC_USB3_WAKE NC_USB3_WAKE
MF PP8405
P4MM PP
1 MPMU_AMUX_BY
NO_TEST=1
NO_TEST=1
1
PP PP8409
P4MM SM
2 201
NC_HDMI_RESET_L NC_HDMI_RESET_L
GPIO9 33
PP8401 34 33 MPMU_GPIO14 R84331 0 2 TPAD_KBD_WAKE_L OUT 85 89 MPMU_VBAT
NO_TEST=1
NO_TEST=1
1
PP PP840A
P4MM SM
GPIO21 33 TPT_MPMU_NAND0_RESET_L TPT_MPMU_NAND0_RESET_L 1
PP P4MM SM IPD_PMU_GPIO:EVT 1/20W 5% MF 0201
33 NC_MPMU_GPIO22 NC_MPMU_GPIO22 0 R8403
5% 1/20W
1 2 1M
MF 201
31 IN BUCK1_LX0
NO_TEST=1
1
PP PP8410
P4MM SM
MAKE_BASE=TRUE NO_TEST=1 34 3 MPMU_GPIO6 R8434 1 2
GPIO23 33 NC_USB3_PWR_EN NC_USB3_PWR_EN
IPD_PMU_GPIO:PROTO 1/20W 5 MF 0201 MPMU_IBAT
NO_TEST=1
NO_TEST=1
1
PP PP8411
P4MM SM
NC_UWB_PWR_EN NC_UWB_PWR_EN
GPIO24 33
MPMU_GPIO20 R84351 0 P5VS2_PWR_EN_RC R8404 BUCK1_LX2 PP8412
MAKE_BASE=TRUE NO_TEST=1 34 33 2 33 37 4 1 2 1M 31 1
IN OUT IN PP
NC_MPMU_GPIO26 NC_MPMU_GPIO26 5% 1/20W MF 201 NO_TEST=1 P4MM SM
33 IPD_PMU_GPIO:EVT 1/20W 5% MF 0201
MAKE_BA E= R E NO_TEST=1
33 NC_MPMU_GPIO27 NC_MPMU_GPIO27 0 31 IN BUCK1_LX3
NO_TEST=1
1
PP PP8413
P4MM SM
MAKE_BASE=TRUE NO_TEST=1 34 33 IN MPMU_GPIO10 R84361 2
102 35 34 33 29 PP1V8_AON_MPMU
IPD_PMU_GPIO:PROTO 1/20W 5% MF 0201 31 IN BUCK1_LX4
NO_TEST=1
1
PP PP8414
P4MM SM
EXTERNAL PULL UPS FOR THROTTLE SIGNALS: SOC HAS IPU R8410 1 2 100K
34 33 MPMU_GPIO10 R84371 0 2 LCD_PWR_EN OUT 70 94
5% 1/20W MF 201
PP8402 31 IN BUCK2_LX0
NO_TEST=1
1
PP PP8420
P4MM SM
PP1V25_AWAKE_IO 102 IPD_PMU_GPIO:EVT 1/20W 5% MF 0201 33 IN TPT_MPMU_BOOST_UVLO_L 1
PP P4MM
NO_TEST=1
0 31 IN BUCK2_LX1
NO_TEST=1
1
PP PP8421
P4MM SM
10K NOSTUFF 34 33 MPMU_GPIO20 R84381 2
R8450
5% 1/20W
1 2
MF 201
BUCK0_THERMAL_THROTTLE_L IN 6 33 IPD_PMU_GPIO:PROTO 1/20W 5% MF 0201 31 IN BUCK2_LX2
NO_TEST=1
1
PP PP8422
P4MM SM
10K NOSTUFF
R8451
5% 1/20W
1 2
MF 201
PMU_VDDHI_UVWARN_L IN 33 106 32 IN BUCK3_LX0
NO_TEST=1
1
PP PP8430
P4MM SM
10K NOSTUFF
R8452
5% 1/20W
1 2
MF 201
BUCK1_THERMAL_THROTTLE_L IN 6 33 32 IN BUCK7_LX0
NO_TEST=1
1
PP PP8470
P4MM SM
10K
R8453
5% 1/20W
1 2
MF 201
RSVD_GPU_TRIGGER1_L IN 19 33 32 IN BUCK7_LX1
NO_TEST=1
1
PP PP8471
P4MM SM
10K NOSTUFF
R8454
5%1/20W
1
MF 201
PMU_VDDMAIN_UVWARN_L IN 6 33 32 IN BUCK8_LX0
NO_TEST=1
1
PP PP8480
P4MM SM
32 IN BUCK8_LX1
NO_TEST=1
1
PP PP8481
P4MM SM
VLDORTC SHORTED TO VDD_ANA FOR PORTABLES RDAR://57024711 32 IN BUCK9_LX0
NO_TEST=1
1
PP PP8490
P4MM SM
33 PP1V5_VLDOINT_MPMU PP1V5_VLDOINT_MPMU
MAKE_BASE=TRUE
31 32 33 32 IN BUCK11_LX0
NO_TEST=1
1
PP PP84B0
P4MM SM
32 IN BUCK11_LX1 1
PP PP84B1
CHARGER RESET CIRCUIT VSS alias connection NO_TEST=1 P4MM SM
RIGHT SHIFT & LEFT OPTION CONTROL (RSLOC) # & WIDTH OF XW IS LAYOUT DEPENDENT
34 BUCK14_LX
NO_TEST=1
1
PP PP84E0
P4MM SM
FOLLOWED BY ON-OFF BUTTON PRESS.
NEW APN 343S00387 can take 1.8V as BTN1/2 inputs. 32 3 VSS_ANA_MPMU VSS_ANA_MPMU 33 IN MPMU_BSTLQ_LX
NO_TEST=1
1
PP PP84F0
P4MM SM
32 31 VSS_ANA_MPMU MAKE_BASE=TRUE
MIN_ E K_WIDTH=0.1000 2 2 2 2
3 VSS_ANA_MPMU MIN_LINE_WIDTH=0.2000
32 VSS_ANA_MPMU VOLTAGE=0 XW8401 XW8402 XW8403 XW8404
104 PP3V3_AON
33 32 VSS_ANA_MPMU
PLACE_NEAR=U8440.1:5MM 1 1 1 1
32 VSS_ANA_MPMU
C8440 1 Isolation for CHGR_RST_IN not to assert when ACE drives UPC_PMU_RESET VSS_ANA_MPMU SHORT-12L-0.25MM-SM SHORT-12L-0.25MM-SM
0.1UF VDD SAK output should hold it below charger VIL
33 32
SHORT-12L-0.25MM-SM SHORT-12L-0.25MM-SM
10%
25V 2 33 32 31 VSS_ANA_MPMU
X5R
0201 U8440 32 VSS_ANA_MPMU
SLG4AP43601 VSS_ANA_MPMU
STQFN R8440 32
3.3K 2 3 VSS_ANA_MPMU 32 GND

90 89 80 33 IN PMU_ONOFF_L 3 BTN1 RE ET 10 CHGR_RST_IN_R 1 CHGR_RST_IN OUT 22 PP1V8_AON 104
49 33 32 VSS_ANA_MPMU 32 GND C M TE E T M NC TE
90 89 82 33 PMU_RSLOC_RST_L 4 BTN2 5% PAGE TITLE

IN
CRITICAL 2
1/20W
MF
1 C8445 3 VSS_ANA_MPMU 32 GND
PMU: MASTER SUPPORT
NC 201 0.1UF 33 VSS_ANA_MPMU 32 GND
343S00387 5 10%
NC 2 6.3V GND
6
NC
R8441 311S00246 CERM-X5R 32
NC 8 1
3.3K 2 U8445
0201
XW8400
SHORT-8L-0.25MM-SM
32 GND
NC SN74AUP1G17 32 GND
9 5% VCC VSS_MPMU_AMUX 1 2
NC 1/20W SON 45 44
32 GND
11 MF 2 4 UPC_PMU_RESET_1V8
NC 201 NC
OUT 33
33 32 GND
12 NC
NC GND
GND
100 90 58 57 IN UPC_PMU_RESET_3V3
NC
NC
101 PP3V8_AON
3.3V AON LDO
CC100 1 353S3698 250MA MAX
1.0UF IQ_ON < 12 UA
20%
6.3V 2 UC100
X5R
0201-1
LP5907UVX-3.3V
USMD
A1 VIN VOUT A2 PP3V3_AON 104
RC100
0
102 35 34 33 29 PP1V8_AON_MPMU 1 2 P3V3_AON_EN B1 VEN 1 CC101
5% GND 1.0UF
1/20W 20%
MF 2 6.3V
X5R
0201 0201-1
101 PP3V8_AON 1.8V AON LDO

CC120 1 353S4262
1.0UF 250MA MAX
20%
6.3V 2 UC120 IQ_ON < 12 UA
X5R
0201-1
LP5907UVX-1.8
DSBGA
A1 VIN VOUT A2 PP1V8_AON 104
102 35 34 33 29 PP1V8_AON_MPMU
RC120
1
0 2 P1V8_AON_EN www.teknisi-indonesia.com
B1 VEN CC121 1
5% GND 1.0UF
1/20W 20%
MF 2 6.3V
X5R
0201 0201-1
SYNC_MASTER=KEI_T668_MLB SYNC_DATE=09/23/2019
PAGE TITLE
POWER: EXTERNAL LDO
* OK2INTEGRATE * 5V_S2 Voltage Regulator
SET ONE OPTION FOR PBUS CAPS
PACK_OPTION=5V_S2_PBUS-B12
PACK_OPTION=5V_S2_PBUS-D2
105 PPBUS_AON_5VS2_VIN_ISNS
CAPDERATE CAPDERATE CAPDERATE
POLY-TANT POLY-TANT POLY-TANT
1 CC320 1
CC321 1
CC322
33UF 33UF 33UF
20% 20% 20%
2 16V
TANT
CASE-T
128S00009
2 16V
TANT
CASE-T
128S00009
2 16V
TANT
CASE-T
128S00009
START UP TIME < 15 MS
PAC _IGNORE=TRUE
PACK_OPTION=5V_S2_PBUS-B12
CAPDERATE CAPDERATE
POLY T N POLY-TANT
CRITICAL CRITICAL
1 1
CC340 CC341
68UF 68UF
20% 20%
2 16V 2 16V
POLY-TANT POLY-TANT
CASE-D2E-SM CASE-D2E-SM
128S0264 128S0264
RC328
PAC _OPTION=5V_S2_PBUS-D2
P5VS2_PGOOD 1
100K 2 PP5V_S2
36 104
5%
CAPDERATE CAPDERATE 1/20W
POLY-T NT POLY-TANT MF
CRITICAL CRITICAL 201
1 1 117S 008
CC350 CC351
33UF 33UF
20% 20%
2 16V 2 16V
TANT TANT
CASED12-SM CASED12-SM
128S0436 128S0436
PACK_IGNORE=TRUE
1 CC323 1 CC324 1 CC325 1 CC326 1 CC330 1 CC331
1
RC327
2.2UF 2.2UF 2.2UF 2.2UF 0
20% 20% 20% 20% 2.2UF 2.2UF 5%
2 25V 2 25V 2 25V 2 25V 20% 20% 1/20W
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402 UC300 2 25V
X6S-CERM 2 25V
X6S-CERM MF
138S00042 138S00042 138S00042 138S00042 LT8642EV-2#PBF 0402 0402 2 0201
117S0201
LQFN 138S00042 138S00042
4 353S02219 1
VIN BIAS P5VS2_BIAS
CRITICAL
5 VIN 2 P5VS2_INTVCC CC332 Vout=5.15V
6 VIN
INTVCC RC332 47NF
13 7 P5VS2_BST 1
1.5 2 P5VS2_BST_R 1 2 EDC=6.6A
RC333 VIN BST
SWITCH_NODE=TRUE SWITCH_NODE=TRUE
37 IN P5VS2_PWR_EN 1
0 2
14 VIN
SW 8 DIDT=TRUE 5%
1/20W
DIDT=TRUE % CRITICAL
F=1.5MHz
15 VIN MF 10V
5% SW 9 201 X6S-CERM
1/20W
MF P5VS2_EN 17 EN/UV SW 10 117S0029 0201
132S00028
LC320
1UH-20%-11A-0.0127OHM
0201
11 PP5V_S2 104
117S0201 SW
P5VS2_VC 22 VC
12
P5VS2_SW 1 2
SW SWITCH_NODE=TRUE PIHA052D-SM
DIDT=TRUE CAPDERATE CAPDERATE
36 OUT P5VS2_PGOOD 23 PG
19 MIN_NECK_WIDTH=0.1000 152S00265 2 POLY-TANT POLY-TANT
1 CLKOUT NC MIN_LINE_WIDTH=0.2000 CRITICAL CRITICAL CRITICAL CRITICAL
RC321 36 P5VS2_FB 24 FB XWC321
SM
1
CC334 1
CC335 1 CC337 1 CC338
20.5K 150UF 150UF 2.2UF 2.2UF
1%
1/20W P5VS2_SS 21 SS 1 20% 20% 20% 20%
MF 2 6.3V 2 6.3V 2 25V 2 25V
2 201
P5VS2_FB_XW TANT TANT X6S-CERM X6S-CERM
118S0 8 P5VS2_RT 18 RT CASE-B-S CASE-B-SM 04 2 0402
128S00038 128S00038 138S00042 138S00042
P5VS2_VC_R 20 SYNC/MODE
1
GND NC
RC322
10
5%
1 CC328 1 CC329 1 CC327 1
RC320 1/20W
MF
1000PF 100PF 0.01UF 25.5K
10% 5% 10% 1% XWC320 2 201
117S0004
2 16V 2 25V 2 16V 1/20W SM
X R-1
02 1
C0G
0201
X7R-CERM
0402 MF
1 2
P5VS2_FB_RC
132S0651 131S0805 132S0374 2 201
118S0235
RC326 1 1
RC323
47K 9.31K
1% 1%
1/20W 1/20W
MF MF
201 2 201
118S0395 2 118S0569
P5VS2_FB_C P5VS2_FB_RC2
CRITICAL
CC333 1
1
470PF
10%
RC324
16 200K
X5R-X7R-CERM 2 0.1%
1/20W
www.teknisi-indonesia.com 0201 TF
132S0361 2 0201
118S0738
SYNC_MASTER=REF_VR_5V_TPS62135 SYNC_DATE=04/16/2020
36 P5VS2_FB PAGE TITLE
1
CRITICAL
RC325
POWER: 5V S2
27.4K
0.1%
1/20W
MF
2 0201
103S00009
P5VS2_AGND
2 1
5VS2_EN TURN OFF DELAY 13-16MS
DC401
X3DFN2
RC401
P5VS2_PWR_EN_RC A K P5VS2_PWR_EN_RC_D 1
1K 2 P5VS2_PWR_EN
84 34 33 IN OUT 36
5%
NSR01L30MXT5G-COMBO 1/20W
MF
371S00062 201
RC402
2
255K 1
1%
1/20W
MF
201
CC401 1
0.1UF
10%
6.3V 2
X6S
0201
SYNC_MASTER=T668_MLB
PAGE TITLE
POWER: 5V S2 SUPPORT
* OK2INTEGRATE * 3V3_S2 VR
SET ONE OPTION FOR PBUS CAPS
PACK_OPTION=3V3_S2_PBUS-B12
105 PPBUS_AON_3V3S2_VIN_ISNS
PACK_OPTION=3V3_S2_PBUS-D2
CAPDERATE CAPDERATE
1
POLY-TANT
CRITICAL
1
POLY-TANT
CRITICAL PACK_OPTION=3V3_S2_PBUS-D12
CC710 CC711
33UF
20%
33UF
20%
PACK_OPTION=3V3_S2_PBUS-25V_D2
2 16V 2 16V
TANT TANT
CASE-T CASE-T
128S00009 128S00009
PACK_IGNORE=TRUE
PACK_O TION=3V3_S2_PBUS-B12
START UP TIME <5 MS

CAPDERATE
POLY-TANT
CRITICAL
1
CC721
68UF
20%
2 16V
POLY-TANT
CASE-D2E-SM
128S0264
PACK_O TION=3V3_S2_PBUS-D2
CAPDERATE
POLY-TANT
CRITICAL CRITICAL
1 1
CC722 CC723
33UF 22UF
20% 20%
2 16V 2 25V
TANT POLY-TANT
CASED12-SM CASE-D2-SM RC715
128 0436 128S0217
P3V3S2_PGOOD 1
100K 2 PP3V3_S2
38 104
5%
PACK_IG ORE=TRUE PACK_IGNORE=TRUE 1/20W
PACK_OPTION=3V3_S2_PBUS-D12 PACK_OPTION=3V3_S2_PBUS-25V_D2 MF
201
117S0008
CRITICAL CRITICAL
1 CC712 1 CC713
2.2UF 2.2UF
20% 20%
2 25V
X6S-CERM 2 25V
X6S-CERM
0402 0402
138S00042 138S00042
www.teknisi-indonesia.com VOUT=3.3V
EDC=2.5A
CRITICAL TDC=2.0A
LC710 F=1.5MHz
UC710 MIN_NECK_WIDTH=0.1000
1.5UH-20%-3.9A-0.048OHM
1210
SN621371 DIDT=TRUE 152S00476
VQFN SWITCH_NODE=TRUE PP3V3_S2 104
1 2 P3V3S2_SW 1 2
RC714 VIN
353S02228
SW
P3V3S2_PWR_EN 1
0 2 P3V3S2_EN 8 6 P3V3S2_VOS POLY-TANT
33 IN EN CRITICAL VOS CRITICAL CRITICAL CRITICAL
2
5%
P3V3S2_SS 9 5 P3V3S2_FB
1
CC715 1 CC717 1 CC718
1/20W
MF
SS/TR FB XWC711
SM
150UF 10UF
20%
10UF
20%
0201 20%
117S0201 11 VSEL PG 7 P3V3S2_PGOOD 38 2 6.3V 2 6 3V 2 6.3V
O T TANT CE -X6S CER-X6S
1 02 0402
CASE-B-SM
10 MODE FB2 4 P3V3S2_FB_XW 128S00038 138S00073 138S00073
GND
1
RC709
1 CC714 XWC710 5%
15
0.01UF SM 1/20W
10% MF
2 10V
X7R-CERM
1 2
2 201
0201 117S0030 CC719
132S0411 0.1UF
P3V3S2_FB_LPF 1 2
10%
1 16V
RC710 CER
0201
0
5% 132S00048
1/20W
MF
2 0201
117S0201
1
RC711
2.26K
1%
1/20W
MF
2 201
118S0204
P3V3S2_FB_R
CRITICAL
1 CC720 1
5%
150PF RC712
127K
2 50V
CER-C0G 0.1%
0201 1/20W
MF
131S00142 2 0201
103S0442
CRITICAL
1
RC713 SYNC_MASTER=REF_VR_3V3_TPS62135
PAGE TITLE
34.8K
0.1%
1/20W
MF
POWER: 3V3 S2
2 0201-1
103S00058
P3V3S2_AGND
3.3V SENSOR SWITCH (WIP) 1V8_S2 SWITCH (FROM J213 1V8 G3S)
101 PP3V8_AON
VDD: 2.5 to 5.5V
104 PP3V3_S2
PLACE_NEAR=UC810.1:5MM
1 CC821 VDD: 2.5 to 5.5V
0.1UF
CC810 1 10%
2 35V
0.1UF CER-X5R
0201
10%
35V
CER-X5R 2
0201
VDD VDD
UC810 UC820
SLG5AP1445V SLG5AP1445V
TDFN8 TDFN8
UC810_SS 7 CAP D 3 UC820_SS 7 CAP D 3 PP1V8_S2 101
CRITICAL CRITICAL
44 33 SENSOR_PWR_EN 2 ON 353S00764 S 5 PP3V3_S2SW_SNS 104 33 PVDD1_PWR_EN 2 ON 353S00764 S 5 PP1V8_S2SW_VDD1 104
CC811 1 IN
VIH_MIN
IN
NOSTUFF
VIH_MIN
4700PF 0.85 V
GND
0.85 V
GND
10% 1
10V 2
X7R
1 CC820 RC820
20 4700PF 47K
10% 5%
1/20W
2 10V
X7R MF
201 2 201
PAGE TITLE
POWER: FETS
PAGE TITLE
POWER: SUPPORT
PP1V25_S2
SIO I2C0 102
1 1
DIAGS BUS: 0 RD000 RD001
1.5K 1.5K
DEVICE 7-BIT 5% 5%
------ ----- 1/20W 1/20W
ACE 0 0X38 MF MF
2 201 2 201
ACE 1 0X3F
I2C_UPC_SCL OUT 55 57
6 IN I2C_UPC_SCL I2C_UPC_SCL OUT 58

MAKE_BASE=TRUE
6 BI I2C_UPC_SDA I2C_UPC_SDA I 55 57
MAKE_BASE=TRUE
I2C_UPC_SDA BI 58
SIO I2C1 PP1V25_AWAKE_IO PP1V8_AWAKE

102 102
DIAGS BUS: 1
DEVICE 7-BIT
1 CD010 1
RD010 1
RD011 1
RD012 1
RD013
------ ----- 0.1UF 1.5K 1.5K 2.2K 2.2K
SPKRAMP L (A) 0X31 20% 5% 5% UD010 5% 5%
SPKRAMP L (B) 0X32 2 16V
X6S-CERM 1/20W 1/20W LSF0101DRY 1/20W 1/20W
0201 MF MF SON MF MF
2 201 2 201 2 201 2 201
6 EN VER-2
I2C_1V8_SPKRAMP_L_SCL OUT 77 80
IN I2C_SPKRAMP_L_SCL 5 VREF_B VREF_A 2 I2C_1V8_SPKRAMP_L_SCL I2C_1V8_SPKRAMP_L_SCL OUT 77

MAKE_BASE=TRUE
I2C_SPKRAMP_L_SDA 4 INB 311S00244 INA 3 I2C_1V8_SPKRAMP_L_SDA I2C_1V8_SPKRAMP_L_SDA 77 80
BI BI
MAKE_BASE=TRUE
I2C_1V8_SPKRAMP_L_SDA BI 77
GND
PP1V25_AWAKE_IO
SIO I2C2 102
1 1
1.5K 1.5K
DEVICE 7-BIT 5% 5%
------ ----- 1/20W 1/20W
CS42L83A 0X48 MF
2 201 2 201
6 IN I2C_CODEC_SCL I2C_CODEC_SCL O T 76
MAKE_BASE=TRUE
6 BI I2C_CODEC_SDA I2C_CODEC_SDA BI 76
MAKE_BASE=TRUE
PP1V25_AWAKE_IO PP1V8_AWAKE
SIO I2C3 102 102
DIAGS BUS: 3 1 CD030 1

RD030 1
RD031 1
RD032 1
RD033
0.1UF
20% 1.5K 1.5K UD030 2.2K 2.2K
DEVICE 7-BIT 5% 5% 5% 5%
------ ----- 2 16V
SPKRAMP R (D) 0X34 0201 MF MF SON MF MF
SPKRAMP R (E) 0X35 2 201 2 201 2 201 2 201
6 EN VER-2
I2C_1V8_SPKRAMP_R_SCL OUT 78 80
6 IN I2C_SPKRAMP_R_SCL 5 VREF_B VREF_A 2 I2C_1V8_SPKRAMP_R_SCL I2C_1V8_SPKRAMP_R_SCL OUT 78

MAKE_BASE=TRUE
6 I2C_SPKRAMP_R_SDA 4 INB 311S00244 INA 3 I2C_1V8_SPKRAMP_R_SDA I2C_1V8_SPKRAMP_R_SDA 78 80
BI BI
MAKE_BASE=TRUE
I2C_1V8_SPKRAMP_R_SDA BI 78
GND
PP1V8_AWAKE_DFR
SIO I2C4 89 88 87
1 1
2.2K 2.2K
DEVICE 7-BIT 5% 5%
------ ----- 1/20W 1/20W
DFR DISPLAY 0X-- MF
DFR TOUCH 0X-- 2 201 2 201
CKPLUS_WAIVE=I2C_PULLUP I2C_DFR_RES_SCL 87
6 I2C_DFR_SCL RD042 1
15 2 89 I2C_DFR_RES_SCL I2C_DFR_RES_SCL
OUT
87
IN UT
5% 1/2 W M 201 MAKE_B SE T UE
6 I2C_DFR_SDA RD043 1
15 2 89 I2C_DFR_RES_SDA I2C_DFR_RES_SDA 87
BI BI
5% 1/20W MF 201 MAKE_BASE=TRUE
CKPLUS_WAIVE=I2C_PULLUP I2C_DFR_RES_SDA BI 87
RD055
PP1V25_AWAKE_IO 1
0 2
102
5%
1/20W
MF
DISP I2C 0201
DIAGS BUS: 12 NOSTUFF

VOLTAGE=1.2
DEVICE 7-BIT RD056 MIN_LINE_WIDTH=0.2000
------ -----
PP1V25_S2 1
0 2 PP1V2_DISPI2C_PU PP3V3_SW_LCD
102 69 89 104
JERRY 0X--
5%
1/20W 1 CD050 1
RD050 1
RD051 1 1 1
MF
0201 0.1UF
20% 1.5K 1.5K RD054 RD052 RD053
5% 200K 1.8K 1.8K
2 16V
X6S-CERM 1/20W 1/20W VREF_A VREF_B 5% 5% 5%
0201 MF MF 1/20W /20W 1/20W
2 201 2 201 UD050 MF MF MF
EN 8 2 201 2 201 2 201 SYNC_MASTER=T668_MLB SYNC_DATE=06/20/2019
LSF0102 UD050_EN
X2SON-COMBO PAGE TITLE
I2C_DISP_BKLT_SCL 3 6 I2C_MLB2JERRY_3V3_SCL
1 6 7 IN A1
311S00234
B1 OUT 69 89
I2C: SIO, DISP
106 7 BI I2C_DISP_BKLT_SDA 4 A2 B2 5 I2C_MLB2JERRY_3V3_SDA BI 69 89
GND
1 CD051
0.1UF
20%
2 16V
X6S-CERM
0201
BOM_COST_GROUP=SMC
2
ISP I2C0
UNUSED
ISP I2C1
UNUSED
ISP I2C2 102 PP1V25_S2 PP1V8_S2 101
DIAGS BUS: TBD

1 CD120 1
RD120 1
RD121 1
RD122 1
RD123
DEVICE 7-BIT 0.1UF 1.5K 1.5K 2.2K 2.2K
------ ----- 20% 5% 5% UD120 5% 5%
CAMERA PMU 0X-- 2 16V
CAMERA SENSOR 0X-- 2 201 2 201 201 2 201
6 EN VER-2
7 IN I2C_CAM_SCL 5 VREF_B VREF_A 2 I2C_CAM_1V8_SCL I2C_CAM_1V8_SCL OUT 68

MAKE_BASE=TRUE
7 I2C_CAM_SDA 4 INB 311S00244 INA 3 I2C_CAM_1V8_SDA I2C_CAM_1V8_SDA 68
BI BI
MAKE_BASE=TRUE
GND
ISP I2C3
UNUSED
AOP I2C0 1 2 PP1V25_S2 PP1V8_S2 101
DIAGS BUS: 5
1 CD140 1
RD140 1
RD141 1
RD142 1
RD143
DEVICE 7-BIT 0.1UF 1.5K 1.5K 2.2K 2.2K
------ ----- 20% 5% 5% UD140 5% 5%
ALS CT720SW 0X29 2 16V
2 201 2 201 2 201 2 201
6 EN VER-2
106 IN I2C_AOP_ALS_SCL 5 VREF_B VREF_A 2 I2C_ALS_1V8_SCL OUT 69 89

MAKE_BASE=TRUE
106 I2C_AOP_ALS_SDA 4 INB 311S00244 INA 3 I2C_ALS_1V8_SDA 69 89
BI BI
MAKE_BASE=TRUE
GND
AOP I2C1
UNUSED SYNC_MASTER=T668_MLB
PAGE TITLE
I2C: ISP, AOP

BOM_COST_GROUP=SMC
PP1V25_S2 PP1V8_S2
SMC I2C0 102 43 101
DIAGS BUS: 7 1 CD200 1

RD200 1
RD201 1
RD202 1
RD203
0.1UF 2.2K 2.2K 2.2K 2.2K
DEVICE 7-BIT 20% 5% 5% UD200 5% 5%
------ ----- 2 16V
CHGR ISL9240HI 0X9 0201 MF MF SON MF MF
2 201 2 201 2 201 2 201
BMU BQ40Z651 0XB 6 EN VER-2
106 91 IN I2C_SMC_PWR_SCL 5 VREF_B VREF_A 2 I2C_SMC_PWR_1V8_SCL I2C_SMC_PWR_1V8_SCL OUT 22

MAKE_BASE=TRUE
106 91 I2C_SMC_PWR_SDA 4 INB 311S00244 INA 3 I2C_SMC_PWR_1V8_SDA I2C_SMC_PWR_1V8_SDA 22
BI BI
MAKE_BASE=TRUE
GND
PP3V3_S2 104
1 43 PP1V25_S2 UD201_EN PP3V3_AON 104
NOSTUFF
1 1 1 1
RD206 RD209 RD207 RD208
VREF_A VREF_B
200K 200K 4.7K 4.7K
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
UD201 EN 8 2 201 2 201 2 201 2 201
LSF0102
3 X2SON-COMBO
A1 B1 6 89 I2C_SMC_PWR_3V3_SCL I2C_SMC_PWR_3V3_SCL OUT 21
311S00234 MAKE_BASE=TRUE
4 A2 B2 5 89 I2C_SMC_PWR_3V3_SDA I2C_SMC_PWR_3V3_SDA 21
BI
MAKE_BASE=TRUE
GND
1 CD201
0.1UF
20%
2 16V
X6S-CERM
0201
102 PP1V25_S2
SMC I2C1
1 1
1.5K 1.5K
5% 5%
DEVICE 7-BIT 1/20W 1/20W
------ ----- MF MF
ACE 0 0X38 2 201 2 201
ACE 1 0X3F I2C_SMC_UPC_SCL 55 57
BI
89 9 IN I2C_SMC_UPC_SCL I2C_SMC_UPC_SCL BI 58
MAKE_BASE=TRUE
89 9 BI I2C_SMC_UPC_SDA I2C_SMC_UPC_SDA OUT 55 57
MAKE_BASE=TRUE
I2C_SMC_UPC_SDA OUT 58
102 PP1V25_S2
PP3V3_S2SW_SNS
SMC I2C2 50 104
DIAGS BUS: 9
1 CD220
0.1UF
20%
1
RD220
1.5K
1
RD221
1.5K www.teknisi-indonesia.com
RD224 1
RD222 RD223 1 1
5% 5% 200K 2.2K 2.2K
DEVICE 7-BIT 2 16V
------ ----- 0201 MF MF 1/20W 1/20W 1/20W
TMP464 0X48 2 201 2 201 UD220 MF MF MF
EN 8 2 201 2 201 2 201
LSF0102 UD220_EN
X2SON-COMBO
9 IN I2C_SMC_SNS1_SCL 3 A1 B1 6 I2C_THMSNS_3V3_SCL I2C_THMSNS_3V3_SCL OUT 50
311S00234 MAKE_BASE=TRUE
9 BI I2C_SMC_SNS1_SDA 4 A2 B2 5 I2C_THMSNS_3V3_SDA I2C_THMSNS_3V3_SDA BI 50
MAKE_BASE=TRUE
GND
1 CD221
0.1UF
20%
2 16V
X6S-CERM
0201
PP1V8_S2 101
SMC I2C3
102 PP1V25_S
DIAGS BUS: 10
DEVICE
------
7-BIT
-----
1 CD230 1
RD230 1
RD231 1
RD233 1
RD234
0.1UF 1.5K 1.5K 4.7K 4.7K
PALM TMP461 0X4C 20% 5% 5% UD230 5% 5%
2 16V
2 201 2 201 2 201 2 201
6 EN VER-2
106 BI I2C_SMC_IPD_SCL 5 VREF_B VREF_A 2 89 I2C_SMC_IPD_1V8_SCL I2C_SMC_IPD_1V8_SCL OUT 85

MAKE_BASE=TRUE
106 I2C_SMC_IPD_SDA 4 INB 311S00244 INA 3 89 I2C_SMC_IPD_1V8_SDA I2C_SMC_IPD_1V8_SDA 85
IN BI
MAKE_BASE=TRUE
GND
102 PP1V25_S2
PP3V3_S2SW_SNS
SMC I2C4 SNSRES_DEV
SNSRES_DEV SNSRES_DEV SNSRES_DEV
43 50 104
1 CD240 1
RD240 1
RD241 1 1 1
DIAGS BUS: 11
20%
0.1UF 1 5K 1.5K RD244 RD242 RD243
5% 5% 200K 2.2K 2.2K
DEVICE 7-BIT 2 16V
------ ----- 0201 MF MF 1/20W 1/20W 1/20W
TLA2528 EADC1 0X17 2 201 2 201 UD240 MF MF MF
TLA2528 EADC2 0X10 EN 8 2 201 2 201 2 201 SYNC_MASTER=KEI_T668_MLB SYNC_DATE=12/20/2019
LSF0102 UD240_EN I2C_EADC_3V3_SCL OUT 48
PAGE TITLE
9 IN I2C_SMC_SNS0_SCL A1
X2SON-COMBO
311S00234
B1 6 I2C_EADC_3V3_SCL
MAKE_BASE=TRUE
I2C_EADC_3V3_SCL OUT 48 I2C: SMC
9 BI I2C_SMC_SNS0_SDA 4 A2 SNSRES_DEV B2 5 I2C_EADC_3V3_SDA I2C_EADC_3V3_SDA BI 48
MAKE_BASE=TRUE
GND SNSRES_DEV I2C_EADC_3V3_SDA BI 48
1 CD241
0.1UF
20%
2 16V
X6S-CERM
0201
BOM_COST_GROUP=SMC
P3V8 AON HIGH SIDE CURRENT SENSE (IMVR) DCIN VOLTAGE SENSE (VD0R)
GAIN: 50X, TDP: 3.55 A PMU AMUX inputs are not fail safe but RD501 limits the current rdar://60591705
RSENSE: 0.01 OR SHORT 104 47 46 45 44 PP3V3_S2SW_SNS
VSENSE: 35.6 MV, RANGE: 6.6 A SNSRES_DEV 101 48 PPDCIN_USBC_AON
SHORT APN: 998-01924? 1 CD540 PLACE_NEAR=U8100.E13:15MM
0.1UF 1
RD501
10% PLACE_NEAR=U8100.E14:15MM
PLACE_NEAR=UD540.3:5MM VS 2 6.3V 255K
101 PPBUS_AON CERM-X5R
0201 SNSRES_DEV 1%
UD540 RD548
1/20W
MF
OUT 48 INA190A2RSW 2 201
SNSRES_DEV UQFN 10 INA_3V8AONHS_IOUT 1
36.5K2 P3V8AON_HS_ISENSE DCIN_VSENSE
1 3 OUT OUT 34 OUT 34
RD540 ISNS_3V8AONHS_P 3 IN+ 1
0 01 REF 8 1/20W RD502 1
0 5%
1W
CRITICAL MF
201 54.9K
1 CD501
MF ISNS_3V8AONHS_N 4 IN- NC 1 1% 0.022UF
0612-COMBO 2 4 SNSRES_DEV NC NOSTUFF 1/20W 10%
107S00076 NC 2 SNSRES_DEV MF 2 6.3V
PPBUS_VMAIN_VIN_ISNS
OUT 48
50X NC 5
NC
RD549 1 1 CD549 201 2 X5R-CERM
0201
105
7 ENABLE NC 100K
PLACE_NEAR=UD540.4:5MM 1% 0.22UF VSS_MPMU_AMUX 34 44 45
1/20W 10%
104 47 46 45 44 PP3V3_S2SW_SNS GND MF 2 6.3V
X5R-CERM
201 2 0201
VSS_MPMU_AMUX 34 44 45 DCIN CURRENT SENSE [AMON] (ID0R)
PLACE_NEAR=U8100.F11:15MM
RD518
45.3K2
5V S2 VR HIGH SIDE CURRENT SENSE (IO5R) 48 22 IN CHGR_AMON 1 DCIN_ISENSE OUT 34
GAIN: 100X, EDP: 2.52 A 1%

1/20W
NOSTUFF
BYPASS=UD550.6::5MM
SNSRES_DEV
MF
201 RD519 1 1 CD519
VSENSE: 25.2 MV, RANGE: 5.0 A 45.3K 0.022UF
SHORT APN: 998-07031
1 CD550 1%
1/20W
10%
2 6.3V
0.1UF MF X5R-CERM
0201
10% 201 2
2 6.3V
CERM-X5R PLACE_NEAR=U8100.F12:15MM
PLACE_NEAR=UD550.3:5MM VS
101 PPBUS_AON 0201 SNSRES_DEV
UD550 VSS_MPMU_AMUX 34 44 45
OUT 48 INA19 A3RSW RD558
SNSRES_DEV UQFN 10 INA_5VS2HS_IOUT 1
36.5K2 P5VS2_HS_ISENSE
1 3 OUT OUT 34
RD550 ISNS_5VS2HS_P
0.01
3 IN+
REF 8
1%
1/20W
BATTERY CHARGER CURRENT SENSE [BMON] (IPBR)
1%
1/3W
CRITICAL MF
201 PLACE_NEAR=U8100.E11:15MM
MF ISNS_5VS2HS_N 4 IN- NC 1 NC
0306 2 4 SNSRES_DEV NOSTUFF RD528
107S00020 NC 2 SNSRES_DEV
PPBUS_AON_5VS2_VIN_ISNS
OUT 48
100X NC 5
NC
RD559 1
1 CD559 CHGR_BMON 1
45.3K2 BMON_ISENSE
105
7 E ABLE NC 100K 48 22 IN OUT 34
PLACE_NEAR=UD550.4:5MM 1% 0.22UF 1% NOSTUFF

1/20W 10% 1/20W
104 47 46 45 44 PP3V3_S2SW_SNS GND MF
201 2
2 6.3V
X5R-CERM MF
201 RD529 1 1 CD529
0201 45.3K 0.022UF
1% 10%
VSS_MPMU_AMUX 4 44 45 1/20W 6. V
X R CERM
MF 0201
201 2
VSS_MPMU_AMUX 34 44 45
3V3 S2 VR HIGH SIDE CURRENT SENSE (IO3R)

GAIN: 100X, EDP: 0.69 A
RSENSE: 0.05 OR SHORT 104 47 46 45 4 PP3V3_S2SW_SNS BYPASS=UD560.6::5MM
SNSRES_DEV
PBUS VOLTAGE SENSE (VP0R)
VSENSE: 34.5 MV, RANGE: 1.0 A RD531/RD532 updated per rdar://60591705
1 CD560
0.1UF
PPBUS_AON PLACE_NEAR=UD560.3:5MM VS
10%
2 6.3V
CERM-X5R
0201
PLACE_NEAR=U8100.F14:15MM www.teknisi-indonesia.com QD530
101 SNSRES_DEV NTUD3169CZ
UD560 RD568 SOT-963
OUT 48 INA190A3RSW N-CHANNEL
SNSRES_DEV UQFN 10 INA_3V3S2HS_IOUT 1
36.5K2 P3V3S2_HS_ISENSE
6
1 3 OUT OUT 34
RD560 ISNS_3V3S2HS_P 3 IN+ D
1%
0.05 REF 8 1/20W
1%
1/3W
CRITICAL MF
201
MF ISNS_3V3S2HS_N 4 IN- NC 1 NC 39 33 IN SENSOR_PWR_EN 2 G
0306 2 4 SNSRES_DEV NOSTUFF S
107S00017 NC 2 SNSRES_DEV
PPBUS_AON_3V3S2_VIN_ISNS
OUT 48
100X NC 5
NC
RD569 1
1 CD569 1
105
PLACE_NEAR=UD560 4:5MM 7 ENABLE NC 100K
1% 0.22UF XWD530
SM 3 48 PBUS_VSNS_OUT
1/20W 10% PLACE_NEAR=U8100.E12:15MM
4 7 6 45 44 PP3V3_S2SW_SNS GND MF 2 6. V
X R CERM 101 PPBUS_AON 1
D 1
201 2 0201 RD538
VSS_MPMU_AMUX 200K
34 44 45 1%
5 G 1/20W
S MF
2 201
PBUS_VSNS_IN 4
P-CHANNEL
PBUS_VSENSE OUT 34
1
RD531
75K
1%
1/20W NOSTUFF RD539 1
MF
201 2 RD530 59K
1%
1 CD539
0 1/20W 0.022UF
PBUS_VSNS_EN_L_DIV 2 MF 10%
NO_TEST=1 201 2 2 6.3V
X5R-CERM
5%
RD532 1 1/20W
MF
0201
124K 0201
VSS_MPMU_AMUX
1% 34 44 45
1/20W
MF
201 2
PBUS_VSNS_EN_L
NO_TEST=1
NOSTUFF
RD535
PMU_VDD_HI 1
45.3K2
3 N
1%
1/20W
MF
201
C M TE E T M C TE
PAGE TITLE
SENSORS: POWER HIGH SIDE (1/2)
BOM_COST_GROUP=SENSORS
MASTER PMU HIGH SIDE CURRENT SENSE (IPMR) SOC VDD PCPU VSENSE (VCDP) SOC VSS PCPU VSENSE (VCSP)
GAIN: 100X, EDP: 24.5 A
BYPASS=UD610.6::5MM PLACE_NEAR=U7700.B10:5MM PLACE_NEAR=U7700.A10:5MM
VSENSE: 61.25 MV, RANGE: 13.2 A RD638 RD648
SHORT APN: 998-01924?
1 CD610 VSNS_VDD_PCPU 1
36.5K2 SOC_VDDPCPU_VSENSE VSNS_VSS_PCPU 1
36.5K2 SOC_VSSPCPU_VSENSE
0.1UF 48 11 IN OUT 30 48 11 IN OUT 30
10% 1% 1%
6.3V
2 CERM-X5R PLACE_NEAR=U8100.F13:15MM 1/20W 1/20W
PLACE_NEAR=UD610.3:5MM VS MF MF
101 PP3V8_AON 0201 201 NOSTUFF 201 NOSTUFF
UD610 RD618 RD639 1
RD649 1
OUT 48 INA190A3RSW
36.5K2 100K
1 CD639 100K
1 CD649
UQFN
OUT 10 INA_MPMUHS_IOUT 1 MPMU_HS_ISENSE 34 1% 0.22UF 1% 0.22UF
RD610 1 3 ISNS_MPMUHS_P 3 IN+ 1%
OUT
1/20W
MF
10%
2 6.3V
1/20W
MF
10%
2 6.3V
0.0025 REF 8 1/20W 201 2 X5R-CERM
0201 201 2 X5R-CERM
0201
1%
1.5W
CRITICAL MF
201
MF ISNS_MPMUHS_N 4 IN- NC 1 NC VSS_SPMU_AMUX 30 45 46 VSS_SPMU_AMUX 30 45 46
0612 2 4 NOSTUFF
107S00094 NC 2
PP3V8_AON_MPMU_ISNS_VIN
OUT 48
100X NC 5
NC
RD619 1 1 CD619 SOC VDD GPU VSENSE (VGDR) SOC VDD SOC VSENSE (VSDR)
105
7 ENABLE NC 100K
47 46 45 44 PP3V3_S2SW_SNS 1% 0.22UF
1/20W 10% PLACE_NEAR=U7700.A9:5MM PLACE_NEAR=U7700.A8:5MM
PLACE_NEAR=UD610.4:5MM GND MF 2 6.3V
X5R-CERM
201 2 0201 RD658 RD668
VSS_MPMU_AMUX VSNS_VDD_GPU 1
36.5K2 SOC_VDDPGPU_VSENSE VSNS_VDD_SOC 1
36.5K2 SOC_VDDSOC_VSENSE
34 44 48 11 IN OUT 30 48 11 IN OUT 30
1% 1%
1/20W 1/20W
MF MF
201 NOSTUFF 201 NOSTUFF
1
SLAVE PMU HIGH SIDE CURRENT SENSE (IPSR) RD659 1 CD659 RD669 1 1 CD669
100K 0.22UF 100K 0.22UF
GAIN: 100X, EDP: 9.92 A 1% 10% 1% 10%
BYPASS=UD620.6::5MM 1/20W 1/20W
RSENSE: 0.005 OR SHORT 104 47 46 45 44 PP3V3_S2SW_SNS MF 2 6.3V
X5R-CERM MF 2 6.3V
X5R-CERM
201 2 0201 201 2 0201
VSENSE: 49.6 MV, RANGE: 6.6 A
1 CD620 VSS_SPMU_AMUX VSS_SPMU_AMUX
0.1UF 30 45 46 30 45 46
10%
2 6.3V
101 PP3V8_AON PLACE_NEAR=UD620.3:5MM VS
CERM-X5R
0201
PLACE_NEAR=U7700.C10:5MM
SOC VDD ECPU VSENSE (VCDE)
UD620 RD628 PLACE_NEAR=U7700.D11:5MM
OUT 48 INA19 A3RSW
UQFN 10 INA_SPMUHS_IOUT 1
36.5K2 SPMU_HS_ISENSE RD678
1 3 OUT OUT 30
RD620 ISNS_SPMUHS_P NO_TEST=1 36.5K2
0.005
3 IN+ 1% 48 11 IN VSNS_VDD_ECPU 1 SOC_VDDECPU_VSENSE OUT 30
REF 8 1/20W
1%
1/3W
CRITICAL MF
201
1%
1/20W
MF ISNS_SPMUHS_N 4 IN- NC 1 NC MF
0306 2 4 NOSTUFF 201 NOSTUFF
107S00005 NC 2
PP3V8_AON_SPMU_ISNS_VIN
OUT 48
100X NC 5
NC
RD629 1
1 CD629 RD679 1 1 CD679
105
7 E ABLE NC 100K 100K
104 47 46 45 44 PP3V3_S2SW_SNS 1% 0.22UF 1% 0.22UF
1/20W 10% 1/20W 10%
PLACE_NEAR=UD620.4:5MM GND MF 2 6.3V
X5R-CERM MF 2 6.3V
X5R-CERM
201 2 0201 201 2 0201
VSS_SPMU_AMUX 0 45 46 VSS_SPMU_AMUX 30 45 46
ATC 3V3 LDO HIGH SIDE CURRENT SENSE (IULR) MESA 1.8/3.3/16V HIGH SIDE CURRENT SENSE (IIDR)
GAIN: 100X, EDP: 0.68 A GAIN: 100X, EDP: 0.176 A BYPASS=UD6B0.6::5MM
BYPASS=UD690.6::5MM
RSENSE: 0.025 OR SHORT 104 47 46 45 44 PP3V3_S2SW_SNS RSENSE: 0.1 OR SHORT 104 47 46 45 44 PP3V3_S2SW_SNS SNSRES_DEV
SNSRES_DEV
VSENSE: 17 MV, RANGE: 1.32 A VSENSE: 17.6 MV, RANGE: 0.33 A
1 CD690 SHORT APN: 998-07031
1 CD6B0
0.1UF 0.1UF
PP3V8_AON
PLACE_NEAR=UD690.2:5MM
VS
10%
2 6.3V
CERM-X5R
0201
PLACE_NEAR=UE000.15:5MM www.teknisi-indonesia.com
PP3V8_AON PLACE_NEAR=UD6B0.2:5MM VS
10%
2 6.3V
CERM-X5R
0201
PLACE_NEAR=UE000.3:5MM
101 SNSRES_DEV 101 SNSRES_DEV
UD690 UD6B0
OUT 48 INA190A3RSW RD698 NO_XNET_CONNECTION=1
OUT 48 INA190A3RSW RD6B8
SNSRES_DEV UQFN 10 INA_ATCHS_IOUT 1
45.3K2 ATC3V3_HS_ISENSE SNSRES_DEV UQFN 10 INA_MESAHS_IOUT 1
45.3K2 MESA_HS_ISENSE
1 3 OUT OUT 48 1 3 OUT OUT 48
RD690 ISNS_ATCHS_P 3 IN+ RD6B0 ISNS_MESAHS_P 3 IN+
1% 1%
0.025 REF 8 1/20W 0.1 REF 8 1/20W
1%
1/3W
CRITICAL MF
201
1%
0.5W
CRITICAL MF
201
MF ISNS_ATCHS_N 4 IN- NC 1 NC MF ISNS_MESAHS_N 4 IN- NC 1 NC
0306 2 4 SNSRES_DEV NOSTUFF 0306 2 4 SNSRES_DEV NOSTUFF
107S00058 NC 2 SNSRES_DEV 107S00116 NC 2 SNSRES_DEV
PP3V8_AON_ATC_ISNS
OUT 48
100X NC 5
NC
RD699 1
1 CD699 PP3V8_MESA_ISNS
OUT 48
100X NC 5
NC
RD6B9 1 1 CD6B9
105
PLACE_NEAR=UD690 4:5MM 7 ENABLE NC 100K 105
PLACE_NEAR=UD6B0.4:5MM 7 ENABLE NC 100K
1% 2.2UF 1% 2.2UF
1/20W 20% 1/20W 20%
4 7 6 45 44 PP3V3_S2SW_SNS GND MF 6. V
X R CERM 4 47 46 45 44 PP3V3_S2SW_SNS GND MF 6.3V
X5R-CERM
201 2 0201 201 2 0201
GND_EADC1_COM 45 46 48 GND_EADC1_COM 45 46 48
DFR 1.8/3.3V HIGH SIDE CURRENT SENSE (IFDC) LCD BACKLIGHT HIGH SIDE CURRENT SENSE (IBLR)
GAIN: 100X, EDP: 0.75 A GAIN: 100X, EDP: 0.9 A BYPASS=UD6C0.6::5MM
BYPASS=UD6A0.6::5MM
RSENSE: 0.025 OR SHORT 104 47 46 45 44 PP3V3_S2SW_SNS RSENSE: 0.025 (RP800) OR SHORT 104 47 6 45 44 PP3V3_S2SW_SNS SNSRES_DEV
SNSRES_DEV
VSENSE: 18.75 MV, RANGE: 1.32 A VSENSE: 22.6 MV, RANGE: 1.32 A
1 CD6A0 1 CD6C0
0.1UF 0.1UF
10% 10%
PLACE_NEAR=UD6A0.2:5MM 2 6.3V
CERM-X5R PLACE_NEAR=UE000.2:5MM 2 6.3V
CERM-X5R PLACE_NEAR=UE020.15:5MM
PP3V8_AON VS 0201 VS 0201
101 SNSRES_DEV SNSRES_DEV
UD6A0 UD6C0
OUT 48 INA190A3RSW RD6A8 INA190A3RSW RD6C8
SNSRES_DEV UQFN 10 INA_DFRHS_IOUT 1
45.3K2 DFR_HS_ISENSE UQFN 10 INA_LCDBKLT_IOUT 1
45.3K2 LCDBKLT_HS_ISENSE
1 3 OUT OUT 48 OUT OUT 48
RD6A0 ISNS_DFRHS_P NO_TEST=1
0.025
3 IN+ 1% 71 48 IN ISNS_LCDBKLT_P 3 IN+ 1%
REF 8 1/20W REF 8 1/20W
1%
1/3W
CRITICAL MF
201
CRITICAL MF
201
MF ISNS_DFRHS_N 4 IN- NC 1 NC 71 48 IN ISNS_LCDBKLT_N 4 IN- NC 1 NC
0306 2 4 SNSRES_DEV NOSTUFF SNSRES_DEV NOSTUFF
107S00058 NC 2 SNSRES_DEV NC 2 SNSRES_DEV
PP3V8_AON_DFR_ISNS
OUT 48
100X NC 5
NC
RD6A9 1
1 CD6A9 100X NC 5
NC
RD6C9 1 1 CD6C9
105
PLACE_NEAR=UD6A0.4:5MM 7 ENABLE NC 100K 7 ENABLE NC 100K
1% 2 2UF 1% 2.2UF
1/20W 20% 1/20W 20%
X5R-CERM 104 47 46 45 44 PP3V3_S2SW_SNS GND MF 2 6.3V
X5R-CERM
201 2 0201 201 2 0201
C M TE E T M C TE
PAGE TITLE
SENSORS: POWER HIGH SIDE (2/2)
2 1
WLAN BT 3V3 S2 CURRENT SENSE (IW3C) WLAN BT 1V8 S2 CURRENT SENSE (IW2C)
GAIN: 100X, EDP: 1.5 A GAIN: 200X, EDP: 0.008 A
BYPASS=UD810.6::5MM BYPASS=UD850.6::5MM
RSENSE: 0.01 OR SHORT 104 47 46 45 44 PP3V3_S2SW_SNS RSENSE: 0.005 OR SHORT 104 47 46 45 44 PP3V3_S2SW_SNS
SNSRES_DEV SNSRES_DEV
VSENSE: 15 MV, RANGE: TBA A VSENSE: 8 MV, RANGE: 0.0165 A
APN: 107S00020
1 CD810 1 CD850
0.1UF 0.1UF
SHORT APN: 998-07031 10% SHORT APN: 998-07031 10%
2 6.3V
CERM-X5R PLACE_NEAR=U7700.B9:5MM PLACE_NEAR=UD850.2:5MM 2 6.3V
PLACE_NEAR=UD810.2:5MM VS VS
104 PP3V3_S2 0201 SNSRES_DEV 101 PP1V8_S2 0201 SNSRES_DEV
UD810 UD850
OUT 48 INA190A4IRSW RD858
SNSRES_DEV UQFN 10 INA_WLBT3V3_IOUT 1
36.5K2 WLANBT_3V3_ISENSE SNSRES_DEV UQFN 10 INA_WLBT1V8_IOUT 1
45.3K2 WLANBT_1V8_ISENSE
RD810 ISNS_WLBT3V3_P 3 IN+ RD850 ISNS_WLBT1V8_P 3 IN
1 1
0 01 REF 8 1/2 W 1.0 REF 8 1/20W
1%
1/3W
CRITICAL MF
201
1%
1/3W
CRITICAL MF
201
MF ISNS_WLBT3V3_N 4 IN- NC 1 NC MF ISNS_WLBT1V8_N 4 IN- NC 1 NC
PP3V3_S2_WLBT_ISNS
OUT 48
100X NC 5
NC
RD819 1
1 CD819 PP1V8_S2_WLBT_ISNS
OUT 48
200X NC 5
NC
RD859 1 1 CD859
105
PLACE_NEAR=UD810.4:5MM 7 ENABLE NC 100K 105
PLACE_NEAR=UD850.4:5MM 7 ENABLE NC 100K
1% 0.22UF 1% 2.2UF
1/20W 10% 1/20W 20%
X5R-CERM
201 2 0201 201 2 0201
VSS_SPMU_AMUX 30 45 GND_EADC1_COM 45 46 48
LEFT AMP CURRENT SENSE (IALR) USB2 LEVEL SHIFTER 3.3V (UF750) CURRENT SENSE (IU3C)
VSENSE: 20 MV, RANGE: 6.6 A VSENSE: 29 MV, RANGE: 0.033 A
1 CD820 SHORT APN: 998-07031
1 CD860
0.1UF 0.1UF
10% 10%
PLACE_NEAR=UD820.2:5MM 2 6.3V
CERM-X5R PLACE_NEAR=UE000.6:5MM PLACE_NEAR=UD860.2:8MM 2 6.3V
PPBUS_AON VS 0201 PP3V3_S2SW_USB1 VS 0201
UD820 UD860
OUT 48 INA19 A3RSW RD828 NO_XNET_CONNECTION=1
OUT 48 IN 190A3RSW RD868
SNSRES_DEV UQFN 10 SPKRAMPL_IOUT 1
45 3K2 SPKRAMPL_ISENSE SNSRES_DEV UQFN 10 INA_USBLS3V3_IOUT 1
4 3K2 USBLS_3V3_ISENSE
RD820 ISNS_SPKRAMPL_P 3 IN+ RD860 ISNS_USBLS3V3_P 3 IN+
1% 1%
0.005 REF 8 1/20W 1.0 REF 8 1/20W
1%
1/3W
CRITICAL MF
201
1%
1/3W
CRITICAL MF
201
MF ISNS_SPKRAMPL_N 4 IN- NC 1 NC MF ISNS_USBLS3V3_N 4 IN- NC 1 NC
PPBUS_SPKRAMP_LEFT_ISNS
OUT 48
100X NC 5
NC
RD829 1
1 CD829 PP3V3_S2SW_USBLS1_ISNS
OUT 48
100X NC 5
NC
RD869 1 1 CD869
105
PLACE_NEAR=UD860.4:8MM ENABLE NC 100K
1% 2.2UF 1% 2.2UF
1/20W 20% 1/20W 20%
X5R-CERM
201 2 0201 201 2 0201
RIGHT AMP CURRENT SENSE (IARR) USB2 LEVEL SHIFTER 1.8V (UF750) CURRENT SENSE (N/A)
VSENSE 20 MV, RANGE: 6.6 A VSENSE: 15.8 MV, RANGE: 0.33 A
1 CD830 SHORT APN: 998-07031
1 CD870
0.1UF 0.1UF
PPBUS_AON
VS
10%
2 6.3V
CERM-X5R
0201
PP1V8_S2
VS
10%
2 6.3V
CERM-X5R
0201
PLACE_NEAR=RE052.1:5MM
UD830 UD870
OUT 48 INA190A3RSW RD878
SNSRES_DEV UQFN 10 SPKRAMPR_IOUT 1
45.3K2 SPKRAMPR_ISENSE SNSRES_DEV UQFN 10 INA_USBLS1V8_IOUT 1
45.3K2 USBLS_1V8_ISENSE
RD830 ISNS_SPKRAMPR_P 3 IN+ NO_TEST=1 RD870 ISNS_USBLS1V8_P 3 IN+
1% 1%
0.005 REF 8 1/20W 0.1 REF 8 1/20W
1%
1/3W
CRITICAL MF
201
1%
0.5W
CRITICAL MF
201
MF ISNS_SPKRAMPR_N 4 IN- NC 1 NC MF ISNS_USBLS1V8_N 4 IN- NC 1 NC
PPBUS_SPKRAMP_RIGHT_ISNS
OUT 48
100X NC 5
NC
RD839 1
1 CD839 PP1V8_S2_USBLS1_ISNS
OUT 48
100X NC 5
NC
RD879 1 1 CD879
105
PLACE_NEAR=UD830 4:5MM 7 ENABLE NC 100K 105
PLACE_NEAR=UD870.4:8MM 7 ENABLE NC 100K
1% 2.2UF 1% 2.2UF
1/20W 20% 1/20W 20%
X R CERM 4 47 46 45 44 PP3V3_S2SW_SNS GND MF 6.3V
X5R-CERM
201 2 0201 201 2 0201
KEYBOARD BACKLIGHT 5V CURRENT SENSE (IKBC) KEYBOARD 1.85V CURRENT SENSE (IK2C)
VSENSE: 11.5 MV, RANGE: 0.33 A VSENSE: 8 MV, RANGE: 0.165 A
SHORT AP : 9 8-07031
1 CD880 SHORT APN: 998-07031
1 CD890
0.1UF 0.1UF
10% 10%
2 6.3V
CERM-X5R PLACE_NEAR=UE000.5:5MM 2 6.3V
PLACE_NEAR=UD880.2:5MM VS PLACE_NEAR=UD890.2:5MM VS
104 PP5V_S2 0201 SNSRES_DEV 104 PP1V85_S2_IPD 0201 SNSRES_DEV
UD880 UD890
OUT 48 INA190A4IRSW RD888 NO_XNET_CONNECTION=1
SNSRES_DEV UQFN 10 INA_KBDLED_IOUT 1
45.3K2 KBDLED_5V_ISENSE SNSRES_DEV UQFN 10 INA_KBD1V85_IOUT 1
45.3K2 KBD_1V85_ISENSE
RD880 ISNS_KBDLED_P 3 IN+ NO_TEST=1 RD890 ISNS_KBD1V85_P 3 IN+
1% 1%
0.05 REF 8 1/20W 0.1 REF 8 1/20W
1%
1/3W
CRITICAL MF
201
1%
0.5W
CRITICAL MF
201
MF ISNS_KBDLED_N 4 IN- NC 1 NC MF ISNS_KBD1V85_N 4 IN- NC 1 NC
PP5V_S2_KB LED_ISNS
OUT 48
200X NC 5
NC
RD889 1
1 CD889 PP1V85_S2_KBD_ISNS
OUT 48
200X NC 5
NC
RD899 1 1 CD899
105
7 ENABLE NC 100K
1% 2 2UF PLACE_NEAR=UD890.4:5MM 1% 2.2UF
1/20W 20% 1/20W 20%
104 47 46 45 44 PP3V3_S2SW_SNS GND MF 2 6.3V GND MF 2 6.3V
201 2 X5R-CERM
0201 104 47 46 45 44 PP3V3_S2SW_SNS 201 2 X5R-CERM
0201
C M TE E T M
PAGE TITLE
SENSORS: POWER LOW SIDE (1/2)
2 1
4
TODO: UPDATE PLACE NEAR
LCD PANEL 5V CURRENT SENSE (IL5C) TPAD 5V CURRENT SENSE (IT5C)

RSENSE: 0.1 (RP621) OR SHORT 104 47 46 45 44 PP3V3_S2SW_SNS RSENSE: 0.1 OR SHORT 104 47 46 45 44 PP3V3_S2SW_SNS
1 CD910 SHORT APN: 998-07031
1 CD940
0.1UF 0.1UF
10% 10%
2 6.3V
VS 0201 PP5V_S2 VS 0201
SNSRES_DEV 104 SNSRES_DEV
UD910 UD940
INA190A4IRSW RD918 NO_XNET_CONNECTION=1
UQFN 10 INA_LCD5V_IOUT 1
45.3K2 LCD_5V_ISENSE SNSRES_DEV UQFN 10 INA_TPAD5V_IOUT 1
45.3K2 TPAD_5V_ISENSE
OUT OUT 48 1 3 OUT OUT 48
RD940 ISNS_TPAD5V_P NO_TEST=1
69 48 IN ISNS_PP5V_SW_LCD_P 3 IN+ 1% 3 IN 1
REF 8 1/20W 0.1 REF 8 1/20W
CRITICAL MF
201
1%
0.5W
CRITICAL MF
201
69 48 IN ISNS_PP5V_SW_LCD_N 4 IN- NC 1 NC MF ISNS_TPAD5V_N 4 IN- NC 1 NC
SNSRES_DEV NOSTUFF SNSRES_DEV 0306 2 4 SNSRES_DEV NOSTUFF SNSRES_DEV
NC 2 107S00116 NC 2
200X NC 5
NC
RD919 1 1 CD919 PP5V_S2_TPAD_ISNS
OUT 48
200X NC 5
NC
RD949 1 1 CD949
7 ENABLE NC 100K 2.2UF 105
PLACE_NEAR=UD940.4:5MM 7 ENABLE NC 100K 2.2UF
1% 20% 1% 20%
1/20W 2 6.3V 1/20W 2 6.3V
104 47 46 45 44 PP3V3_S2SW_SNS GND MF X5R-CERM
0201 104 47 46 45 44 PP3V3_S2SW_SNS GND MF X5R-CERM
0201
201 2 201 2
GND_EADC2_COM 45 46 47 48 GND_EADC2_COM 45 46 47 48
LCD PANEL 3.3/3.8V CURRENT SENSE (IL3C) TPAD 3.3V S2 CURRENT SENSE (IT3C)
RSENSE: 0.01 (RP620) OR SHORT 104 47 46 45 44 PP3V3_S2SW_SNS RSENSE: 0.1 OR SHORT 104 47 46 45 44 PP3V3_S2SW_SNS
1 CD920 SHORT APN: 998-07031
1 CD950
0.1UF 0.1UF
10% 10%
2 6.3V
VS 0201 PP3V3_S2_TPAD VS 0201
SNSRES_DEV 104 SNSRES_DEV
UD920 UD950
IN 1 0 4IRSW RD928 NO_XNET_CONNECTION=1
UQFN 10 INA_PPPANEL_IOUT 1
45.3K2 LCD_3V3_ISENSE SNSRES_DEV UQFN 10 INA_TPAD3V3_IOUT 1
4 3K2 TPAD_3V3_ISENSE
OUT OUT 48 1 3 OUT OUT 48
RD950 ISNS_TPAD3V3_P NO_TEST=1
69 48 IN ISNS_PPPANEL_SW_LCD_P 3 IN+ 1%
0.1
3 IN+ 1%
REF 8 1/20W REF 8 1/20W
CRITICAL MF
201
1%
0.5W
CRITICAL MF
201
69 48 IN ISNS_PPPANEL_SW_LCD_N 4 IN- NC 1 NC MF ISNS_TPAD3V3_N 4 IN- NC 1 NC
SNSRES_DEV NOSTUFF 0306 2 4 SNSRES_DEV NOSTUFF SNSRES_DEV
NC 2 SNSRES_DEV 107S00116 NC 2
200X NC 5
NC
RD929 1
1 CD929 PP3V3_S2_TPAD_ISNS
OUT 48
200X NC 5
NC
RD959 1 1 CD959
7 E ABLE NC 100K 105
PLACE_NEAR=UD950.4:5MM 7 ENABLE NC 100K 2.2UF
1% 2.2UF 1% 20%
1/20W 20% 1/20W 2 6.3V
X5R-CERM 104 47 46 45 44 PP3V3_S2SW_SNS GND MF X5R-CERM
0201
201 2 0201 201 2
ALSCAM 5V CURRENT SENSE (ICMC) TPAD 1.85V S2 CURRENT SENSE (IT2C)

BYPASS=UD930.6 :5MM BYPASS=UD960.6::5MM
VSENSE: 10MV, RANGE: 0.165 A VSENSE: 18.6 MV, RANGE: 0.66 A
1 CD930 SHORT APN: 998-07031
1 CD960
0.1UF 0.1UF
PP5V_S2 PLACE_NEAR=UD930.3:8MM VS
10%
2 6.3V
CERM-X5R
0201
PP1V85_S2_IPD
VS
10%
2 6.3V
CERM-X5R
0201
UD930 UD960
OUT 48 INA190A4IRSW RD938 NO_XNET_CONNECTION=1
OUT 48 INA190A3RSW RD968
SNSRES_DEV UQFN 10 INA_ALSCAM_IOUT 1
45.3K2 ALSCAM_5V_ISENSE SNSRES_DEV UQFN 10 INA_TPAD1V85_IOUT 1
45.3K2 TPAD_1V85_ISENSE
RD930 ISNS_ALSCAM_P 3 IN+ RD960 ISNS_TPAD1V85_P 3 IN+ NO_TEST=1
1% 1%
0.1 REF 8 1/20W 0.05 REF 8 1/20W
1%
0.5W
CRITICAL MF
201
1%
1/3W
CRITICAL MF
MF ISNS_ALSCAM_N 4 IN- NC 1 NC MF ISNS_TPAD1V85_N 4 IN- NC 1
0306 2 4 SNSRES_DEV NOSTUFF 0306 2 4 SNSRES_DEV NOSTUFF SNSRES_DEV
107S00116 NC 2 SNSRES_DEV 107S00017 NC 2
PP5V_S2_ALSCAM_ISNS
OUT 48
200X NC 5
NC
RD939 1
1 CD939 PP1V85_S2_TPAD_ISNS
OUT 48
100X NC 5 RD969 1 1 CD969
105
PLACE_NEAR=UD960.4:5MM 7 ENABLE 100K 2.2UF
1% 2.2UF 1% 20%
1/20W 20% 1/20W 2 6.3V
X R CERM 47 46 45 44 PP3V3_S2SW_SNS GND MF X5R-CERM
0201
201 2 0201 201 2
C M TE E T M
PAGE TITLE
SENSORS: POWER LOW SIDE (2/2)
2 1
EADC1 (ADDR WR:0X2E RD: 0X2F [7BIT: 0X17]) EADC2 (ADDR WR:0X20 RD: 0X21 [7BIT 0X10])
PPDECAP_EADC1 PPDECAP_EADC2
VOLTAGE=1.8 VOLTAGE=1.8
MIN_LINE_WIDTH=0.2000 PLACE_NEAR=UE000.8:5MM MIN_LINE_WIDTH=0.2000 PLACE_NEAR=UE020.8:5MM
MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000
1 CE002 1 CE022
UE010 1.0UF
20%
UE030 1.0UF
20%
REF3325AIRSE REF3325AIRSE
UQFN 2 6.3V
X5R UQFN 2 6.3V
X5R
SNSRES_DEV 0201-1 SNSRES_DEV 0201-1
PP3V3_S2SW_SNS 5 IN SNSRES_DEV SNSRES_DEV
104 48 OUT 8 PP2V5_S2SW_EADC1_AVREF 104 48 PP3V3_S2SW_SNS 5 IN OUT 8 PP2V5_S2SW_EADC2_AVREF
MIN_LINE_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000 PP3V3_S2SW_SNS 48 104 MIN_NECK_WIDTH=0.1000 PP3V3_S2SW_SNS 104
1 CE010 NC0 1 VOLTAGE=2.5V
LACE_NEAR=UE000.10:5MM
1 CE020 NC0 1 VOLTAGE=2.5V
1.0UF NC 1 CE001 1.0UF NC 1 CE021
20%
2 6.3V
NC1 2
NC 1.0UF
1 CE003 2 %
2 6.3V
NC1 2
NC 1.0UF
1 CE023 NOSTUFF
X5R NC2 3 20% 1 0UF 1
RE005 X5R NC2 3 20% 1.0UF 1
RE025
0201-1 NC 2 6.3V AVDD DECAP DVDD
20% 0201-1 NC 2 6.3V AVDD DECAP DVDD
20%
SNSRES_DEV NC3 6 X5R 2 6.3V 0 SNSRES_DEV NC3 6 X5R 2 6.3V 0
NC 0201-1 X5R 5% NC 0201-1 X5R 5%
7 SNSRES_DEV 0201-1 7 SNSRES_DEV 0201-1
NC4 NC UE000 SNSRES_DEV
1/20W
MF
NC4 NC UE020 SNSRES_DEV
1/20W
MF
TLA2528 2 0201 TLA2528 2 201
WQFN WQFN
ATC3V3_HS_ISENSE 15 SNSRES_DEV 11 EADC1_ADDR LCDBKLT_HS_ISENSE 15 SNSRES_DEV 11 EADC2_ADDR
48 AIN0/GPIO0 ADDR 48 AIN0/GPIO0 ADDR
48 USBLS_3V3_ISENSE 16 AIN1/GPIO1 14 NOSTUFF 48 LCD_5V_ISENSE 16 AIN1/GPIO1
SDA I2C_EADC_3V3_SDA BI 43 48 SDA 14 I2C_EADC_3V3_SDA BI 43
WLANBT_1V8_ISENSE 1 AIN2/GPIO2 1
RE006 LCD_3V3_ISENSE 1 AIN2/GPIO2 1
RE026
PPE001
P4MM
8
48 DFR_HS_ISENSE 2 AIN3/GPIO3 SCL 13 I2C_EADC_3V3_SCL 43 48 0

48
48 TPAD_5V_ISENSE 2 AIN3/GPIO3 SCL 13 I2C_EADC_3V3_SCL 43 0

SM IN IN
5% 5%
48 43 I2C_EADC_3V3_SDA 1
PP 48 MESA_HS_ISENSE 3 AIN4/GPIO4 1/20W 8 TPAD_3V3_ISENSE 3 AIN4/GPIO4 1/20W
MF MF
PLACE_NEAR=UE010:10MM EADC1_AIN5 4 AIN5/GPIO5 2 201
TPAD_1V85_ISENSE 4 AIN5/GPIO5 2 0201
PPE002
P4MM
48
48 KBDLED_5V_ISENSE 5 AIN6/GPIO6
48
48 ALSCAM_5V_ISENSE 5 AIN6/GPIO6
SM
48 43 I2C_EADC_3V3_SCL 1
PP 48 SPKRAMPL_ISENSE 6 AIN7/GPIO7 NC 12
NC 48 SPKRAMPR_ISENSE 6 AIN7/GPIO7 NC 12
NC
PLACE_NEAR=UE010:10MM
PPE003
P4MM PULL UP TO DECAP WITH 0 OHM: I2C ADDR = 0B0010_1110 PULL UP TO DECAP WITH 0 OHM: I2C ADDR = 0B0010_1110
SM
PP3V3_S2SW_SNS 1 EPAD GND PULL DOWN TO GND WITH 0 OHM: I2C ADDR = 0B0010_0000 EPAD GND PULL DOWN TO GND WITH 0 OHM: I2C ADDR = 0B0010_0000
104 48
PP
XWE000
SM
XWE020
SM
PPE004
P4MM 46 45 GND_EADC1_COM 1 2 47 46 45 GND_EADC2_COM 1 2
SM
1 PLACE_NEAR=UE000.9:5MM PLACE_NEAR UE020.9:5MM
PP
PLACE_N A =UE010:10MM
EADC1 AIN ALIAS POWER VALIDATION TEST POINTS (WIP) SOC SENSE LINES
PPE0A1
P4MM
ATC3V3_HS_ISENSE ATC3V3_HS_ISENSE ISNS_3V8AONHS_P
TPE001 ISNS_LCDBKLT_P
TPE025 ISNS_TPAD5V_P
TPE049 VSNS_VDD_PCPU 1
SM
45 IN 48 44 IN 1 TP PLACE_SIDE=TOP 71 45 IN 1 TP PLACE_SIDE=TOP 47 IN 1 TP PLACE_SIDE=TOP 45 11 IN PP PLACE_SIDE=TOP
MAKE_BASE=TRUE NO_TEST=1 TP-P5 PLACE_NEAR=RD540.3:5MM TP-P5 PLACE_NEAR=RP800.4:5MM TP-P5 PLACE_NEAR=RD940.3:5MM
46 USBLS_3V3_ISENSE USBLS_3V3_ISENSE 48 TPE002 TPE026 TPE050 PPE0A2

P4MM
IN ISNS_3V8AONHS_N 1 TP ISNS_LCDBKLT_N 1 TP ISNS_TPAD5V_N 1 TP SM
MAKE_BASE=TRUE 44 IN PLACE_SIDE=TOP 71 45 IN PLACE_SIDE=TOP 47 IN PLACE_SIDE=TOP
TP-P5 PLACE_NEAR=RD540.4:5MM TP-P5 PLACE_NEAR=RP800.3:5MM TP-P5 PLACE_NEAR=RD940.4:5MM 45 1 IN VSNS_VSS_PCPU 1
PP PLACE_SIDE=TOP
WLANBT_1V8_ISENSE WLANBT_1V8_ISENSE
46 IN
48
TPE003 TPE027 TPE051 PPE0A3
P4MM
44 IN ISNS_5VS2HS_P 1 TP PLACE_SIDE=TOP 46 IN ISNS_WLBT3V3_P 1 TP PLACE_SIDE=TOP 47 IN ISNS_TPAD3V3_P 1 TP PLACE_SIDE=TOP SM
45 IN DFR_HS_ISENSE DFR_HS_ISENSE 48 TP-P5 PLACE_NEAR=RD550.3:5MM TP-P5 PLACE_NEAR=RD810.3:5MM TP-P5 PLACE_NEAR=RD950.3:10MM 45 11 IN VSNS_VDD_GPU 1
PP PLACE_SIDE=TOP
MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1
MESA_HS_ISENSE MESA_HS_ISENSE ISNS_5VS2HS_N

TPE004 ISNS_WLBT3V3_N
TPE028 ISNS_TPAD3V3_N
TPE052 PPE0A4
45 IN 48 44 IN 1 TP PLACE_SIDE=TOP 46 IN 1 TP PLACE_SIDE=TOP 47 IN 1 TP PLACE_SIDE=TOP P4MM
MAKE_BASE=TRUE NO_TEST=1 TP-P5 PLACE_NEAR=RD550.4:5MM TP-P5 PLACE_NEAR=RD810.4:5MM TP-P5 PLACE_NEAR=RD950.4:10MM SM
45 11 IN VSNS_VDD_SOC 1
PP PLACE_SIDE=TOP
NO_TEST=1
KBDLED_5V_ISENSE KBDLED_5V_ISENSE TPE005 TPE029 TPE053
46 IN
48
44 ISNS_3V3S2HS_P 1 TP PLACE_SIDE=TOP 46 ISNS_SPKRAMPL_P 1 TP PLACE_SIDE=TOP 47 ISNS_TPAD1V85_P 1 TP PLACE_SIDE=TOP

PPE0A5
P4MM
IN IN IN SM
TP-P5 PLACE_NEAR=RD560.3:5MM TP-P5 PLACE_NEAR=RD820.3:5MM TP-P5 PLACE_NEAR=RD960.3:5MM
46 IN SPKRAMPL_ISENSE SPKRAMPL_ISENSE 48 45 1 IN VSNS_VDD_ECPU 1
PP PLACE_SIDE=TOP
MAKE_BASE=TRUE NO_TEST=1 TPE006 TPE030 TPE054
ISNS_3V3S2HS_N ISNS_SPKRAMPL_N ISNS_TPAD1V85_N PPE0A6
44 IN 1 TP PLACE_SIDE=TOP 46 IN 1 TP PLACE_SIDE=TOP 47 IN 1 TP PLACE_SIDE=TOP
TP-P5 PLACE_NEAR=RD560.4:5MM TP-P5 PLACE_NEAR=RD820.4:5MM TP-P5 PLACE_NEAR=RD960.4:5MM P4MM
PLACE_NEAR=UE000.4:5MM SM
11 N VSNS_VDD_DISP 1
PP PLACE_SIDE=TOP
RE051 TPE007 TPE031 TPE055 NO_TEST=1
46 KBD_1V85_ISENSE 1
0 2 EADC1_AIN5 48
101 44 IN PPDCIN_USBC_AON
TP-P5
1 TP PLACE_SIDE=TOP
PLACE_NEAR=RD501.1:5MM
46 IN ISNS_SPKRAMPR_P
TP-P5
1 TP PLACE_SIDE=TOP
22 IN CHGR_CSI_P
TP-P5
1 TP PLACE_SIDE=TOP
PLACE_NEAR=R5220.3:15MM
PPE0A7
P4MM
IN SM
NO_TEST=1 NO_TEST=1
1/20W 5% MF 0201
TPE008 TPE032 TPE056 11 IN VSNS_VDD2_1 1
PP PLACE_SIDE=TOP
NO_TEST=1
1 TP PLACE_SIDE=TOP ISNS_SPKRAMPR_N 1 TP PLACE_SIDE=TOP CHGR_CSI_N 1 TP PLACE_SIDE=TOP
PLACE_NEAR=UE000.4:5MM TP-P5 PLACE_NEAR=RD502.2:5MM
46 IN
TP-P5 PLACE_NEAR=RD830.4:5MM
22 IN
TP-P5 PLACE_NEAR=R5220.4:15MM PPE0A8
P4MM
RE052 TPE009 TPE033 TPE057 11 IN VSNS_VSS_1 1
SM
PP PLACE_SIDE=TOP
0 44 2 IN CHGR_AMON 1 TP PLACE_SIDE=TOP NO_TEST=1
USBLS_1V8_ISENSE 1 2 TP-P5 ISNS_KBDLED_P 1 TP PLACE_SIDE=TOP CHGR_CSO_P 1 TP PLACE_SIDE=TOP
46 IN
NO_TEST=1
1/20W 5% MF 0201
46 IN
22 IN
TP-P5 PPE0A9
P4MM
TPE010 TPE034 TPE058 VSNS_VDD2_2 1
SM
NOSTUFF 1 TP PLACE_SIDE=TOP
ISNS_KBDLED_N 1 CHGR_CSO_N 1
11 IN PP PLACE_SIDE=TOP
TP-P5 PLACE_NEAR=TPE009.1:5MM 46 IN P PLACE_SIDE=TOP 22 IN P PLACE_SIDE=TOP
TP-P5 PLACE_NEAR=RD880.4:5MM TP-P5 PLACE_NEAR=TPE057.1:5MM
TPE011 PPE0AA
P4MM
CHGR_BMON TPE035
EADC2 AIN ALIAS 44 22 IN
TP-P5
1 TP PLACE_SIDE=TOP
46 IN ISNS_WLBT1V8_P
TP-P5
1 TP PLACE_SIDE=TOP
11 IN VSNS_VSS_2 1
SM
PP PLACE_SIDE=TOP
LCDBKLT_HS_ISENSE LCDBKLT_HS_ISENSE
TPE012 TPE036 PPE0AB
45 IN 48 1 TP PLACE_SIDE=TOP P4MM
MAKE_BASE=TRUE NO_TEST=1 TP-P5 PLACE_NEAR=TPE011.1:5MM 46 IN ISNS_WLBT1V8_N 1 TP PLACE_SIDE=TOP SM
VSNS_VDD_DCS 1
LCD_5V_ISENSE LCD_5V_ISENSE TPE013
TP-P5
TPE037
PROBE POINTS 11 IN
NO_TEST=1
PP PLACE_SIDE=TOP
47 IN
AKE_BASE=TRUE NO_TEST=1
48
IN PBUS_VSNS_OUT
TP-P5
1 TP PLACE_SIDE=TOP
PLACE_NEAR=RD538.1:10MM 46 ISNS_USBLS3V3_P 1 TP PLACE_SIDE=TOP
PPE0B1
P4MM
PPE0AC
P4MM
IN SM SM
47 IN LCD_3V3_ISENSE LCD_3V3_ISENSE 48
TPE014 1 1 13 IN PPVDD_CPU_SRAM_AWAKE 1
PP PLACE_SIDE=TOP 1 IN VSNS_VSS_DDR 1
PP PLACE_SIDE=TOP
1 TP PLACE_SIDE=TOP TPE038 NO_TEST=1
47 TPAD_5V_ISENSE TPAD_5V_ISENSE 48
TP-P5 PLACE_NEAR=TPE013.1:5MM 46 IN ISNS_USBLS3V3_N
TP-P5
1 P PLACE_SIDE=TOP
PPE0B2
P4MM
PPE0AD
P4MM
IN
ISNS_MPMUHS_P
TPE015 TPE039 101 13 IN PP0V764_S1_SRAM 1
SM
PP PLACE_SIDE=TOP 11 IN VSNS_VDDQL 1
SM
PP PLACE_SIDE=TOP
45 IN 1 TP PLACE_SIDE=TOP NO_TEST=1
TPAD_3V3_ISENSE TPAD_3V3_ISENSE TP-P5 PLACE_NEAR=RD610.3:10MM ISNS_USBLS1V8_P 1 TP PLACE_SIDE=TOP
47 IN
48 46 IN
TP-P5 PLACE_NEAR=RD870.4:10MM PPE0B3
P4MM
TPAD_1V85_ISENSE TPAD_1V85_ISENSE ISNS_MPMUHS_N
TPE016 TPE040 PP0V72_S2_VDD_LOW 1
SM
1 TP PLACE_SIDE=TOP PLACE_SIDE=TOP
47 IN
48 45 IN
TP-P5 PLACE_NEAR=RD610.4:10MM 46 IN ISNS_USBLS1V8_N
TP-P5
1 TP PLACE_SIDE=TOP
102 14 IN PP
PPE0AE
P4MM
SM PLACE_NEAR=PPE0A3:2MM
47 IN ALSCAM_5V_ISENSE ALSCAM_5V_ISENSE 48
TPE017 TPE041 1
PP PLACE_SIDE=TOP
AKE_BASE=TRUE NO_TEST=1
45 IN ISNS_SPMUHS_P 1 TP PLACE_SIDE=TOP 46 IN ISNS_KBD1V85_P 1 TP PLACE_SIDE=TOP
TP-P5 PLACE_NEAR=RD620.3:5MM TP-P5 PLACE_NEAR=RD890.3:10MM
46 IN SPKRAMPR_ISENSE SPKRAMPR_ISENSE 48
ISNS_SPMUHS_N
TPE018 ISNS_KBD1V85_N
TPE042
45 N 1 TP PLACE_SIDE=TOP 46 IN 1 TP PLACE_SIDE=TOP
P P5 PLACE_NEAR=RD620.4:5MM TP-P5 PLACE_NEAR=RD890.4:10MM
PPE0AF
P4MM
ISNS_ATCHS_P
TPE019 ISNS_PP5V_SW_LCD_P
TPE043 1
SM
PP PLACE_SIDE=TOP
45 IN 1 TP PLACE_SIDE=TOP 69 47 IN 1 TP PLACE_SIDE=TOP
TP-P5 PLACE_NEAR=RD690.3:5MM TP-P5 PLACE_NEAR=RP621.3:5MM
ISNS_ATCHS_N
TPE020 ISNS_PP5V_SW_LCD_N
TPE044
TP-P5 PLACE_NEAR=RD690.4:5MM TP-P5 PLACE_NEAR=RP621.4:5MM
ISNS_DFRHS_P
TPE021 ISNS_PPPANEL_SW_LCD_P
TPE045
TP-P5 PLACE_NEAR=RD6A0.3:10MM TP-P5 PLACE_NEAR=RP620.3:5MM
C M TE E T M
ISNS_DFRHS_N
TPE022 ISNS_PPPANEL_SW_LCD_N
TPE046 PAGE TITLE
45 IN
TP-P5
1 TP PLACE_SIDE=TOP
PLACE_NEAR=RD6A0.4:10MM
69 47 IN
TP-P5
1 TP PLACE_SIDE=TOP
PLACE_NEAR=RP620.4:5MM SENSORS: POWER SUPPORT
ISNS_MESAHS_P
TPE023 ISNS_ALSCAM_P
TPE047
45 IN 1 TP PLACE_SIDE=TOP 47 IN 1 TP PLACE_SIDE=TOP
TP-P5 PLACE_NEAR=RD6B0.3:5MM TP-P5 PLACE_NEAR=RD930.3:5MM
ISNS_MESAHS_N
TPE024 ISNS_ALSCAM_N
TPE048 PLACE_SIDE=TOP
5 IN 1 TP PLACE_SIDE=TOP 47 IN 1 TP PLACE_NEAR=RD930.4:5MM
TP-P5 PLACE_NEAR=RD6B0.4:5MM TP-P5
8 7 2 1
MASTER PMU TDEV1 [TMVR] MASTER PMU TDEV6 [TW0P] SLAVE PMU TDEV1 [TPSP]
LOCATION: 3.8V AON VR BETWEEN PHASE 2 AND PHASE3 MOSFETS LOCATION: WLANBT, BACKSIDE LOCATION: SLAVE PMU, BUCK10 INDUCTOR PROXIMITY
XWE111
SM
XWE161
SM
XWE1B1
SM
THMSNS_MPMU1_P 1 2 P3V8AONVR_THMSNS 49 THMSNS_MPMU6_P 1 2 WLANBT_THMSNS 49 THMSNS_SPMU1_P 1 2 SPMU_THMSNS 49
NO_TEST=1 NO_TEST=1
NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 NO_XNET_C NNEC ION=1
1 1 1
CRITICAL PLACE_NEAR=U8100.E8:15MM CRITICAL PLACE_NEAR=U8100.G10:15MM CRITICAL PLACE_NEAR=U7700.A6:5MM
RE111 1 CE111 RE161 1 CE161 RE1B1 1 CE1B1
100PF 100PF 100PF
10KOHM-1%-0.31MA 5% 10KOHM-1%-0.31MA 5% 10KOHM-1%-0.31MA 5%
0201 2 25V
C0G 0201 2 25V
C0G 0201 2 25V
C0G
0201 0201 0201
2 XWE112
SM
2 XWE162
M
2 XWE1B2
SM
THMSNS_MPMU1_N 1 2 THMSNS_MPMU_VSS 49 THMSNS_MPMU6_N 1 2 THMSNS_MPMU_VSS 49 THMSNS_SPMU1_N 1 2 THMSNS_SPMU_VSS 49
NO_TEST=1 NO_TEST=1
NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1
MASTER PMU TDEV2 [TSDD] MASTER PMU TDEV7 [TPMP] SLAVE PMU TDEV2 [TaMP]
LOCATION: SOC DRAM AREA, BACKSIDE (TOP) LOCATION: MASTER PMU, BETWEEN BUCK0 AND BUCK1 INDUCTORS LOCATION: MLB AIR INTAKE PROXIMITY
XWE121
SM
XWE171
SM
XWE1C1
SM
THMSNS_MPMU2_P 1 2 SOC_THMSNS1 49 THMSNS_MPMU7_P 1 2 MPMU_THMSNS 49 THMSNS_SPMU2_P 1 2 AMB_THMSNS 49
NO_TEST=1 NO_TEST=1
1 1 1
CRITICAL PLACE_NEAR=U8100.F9:15MM CRITICAL PLACE_NEAR=U8100.G8:15MM CRITICAL PLACE_NEAR=U7700.A5:5MM
RE121 1 CE121 RE171 1 CE171 RE1C1 1 CE1C1
100PF 100PF 100PF
0201 2 25V
C0G 0201 2 25V
C0G 0201 2 25V
C0G
0201 0201 0201
2 XWE122
SM
2 XWE172
SM
2 XWE1C2
SM
NO_TEST=1 NO_TEST=1
MASTER PMU TDEV3 [TSCD] MASTER PMU TDEV8 [TCHP] SLAVE PMU TDEV3 [TH0T]
LOCATION: SOC CORE AREA BACKSIDE (TOP) LOCATION: CHARGER, BETWEEN INDUCTOR AND MOSFETS LOCATION: LOWER LEFT CORNER OF NAND DEVICES
XWE131
SM
XWE181
SM
XWE1D1
SM
THMSNS_MPMU3_P 1 2 SOC_THMSNS3 49 THMSNS_MPMU8_P 1 2 CHGR_THMSNS 49 THMSNS_SPMU3_P 1 2 NAND0_THMSNS 49
NO_TEST=1 NO_TEST=1
1 1 1
CRITICAL PLACE_NEAR=U8100.F8:15MM CRITICAL PLACE_NEAR=U8100.G7:15MM CRITICAL PLACE_NEAR=U7700.B8:5MM
RE131 1 CE131 RE181 1 CE181 RE1D1 1 CE1D1
100PF 100PF 100PF
2 25V
0201 C0G 0201 2 25V
C0G 0201 2 25V
C0G
0201 0201 0201
2 XWE132
SM
2 XWE182 SM
2 XWE1D2
SM
NO_TEST=1 NO_TEST=1
MASTER PMU TDEV4 & TDEV5 SLAVE PMU TDEV4 [TH0B]

LOCATION: DOES NOT EXIST LOCATION: UPPER RIGHT CORNER OF NAND DEVICES
XWE1E1
SM
THMSNS_SPMU4_P 1 2 NAND1_THMSNS 49
NO_TEST=1
1
CRITICAL
PMU TDEV MAPPING RE1E1 1
CE1E1
100PF
49 P3V8AONVR_THMSNS P3V8AONVR_THMSNS OUT 33 49 SPMU_THMSNS SPMU_THMSNS OUT 29 10KOHM-1%-0.31MA 5%
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 0201 2 25V
C0G
0201
49 SOC_THMSNS1
SOC_THMSNS1 OUT 33 49 AMB_THMSNS
AMB_THMSNS OUT 29
2 XWE1E2
SM
THMSNS_SPMU4_N 1 2 THMSNS_SPMU_VSS 49
49 SOC_THMSNS3 SOC_THMSNS3 OUT 33 49 NAND0_THMSNS NAND0_THMSNS OUT 29 NO_TEST=1
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 NO_XNET_CONNECTION=1
NC_MPMU_TDEV4 NC_MPMU_TDEV4 OUT 33 49 NAND1_THMSNS NAND1_THMSNS OUT 29

SLAVE PMU TDEV5 [Th1H]
NC_MPMU_TDEV5 NC_MPMU_TDEV5 OUT 33 49 FINSTACK_THMSNS FINSTACK_THMSNS OUT 29
LOCATION: FINSTACK PROXIMITY
WLANBT_THMSNS WLANBT_THMSNS
49
OUT 33
XWE1F1
SM
49 MPMU_THMSNS MPMU_THMSNS OUT 33 THMSNS_SPMU5_P 1 2 FINSTACK_THMSNS 49
MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1
49 CHGR_THMSNS CHGR_THMSNS OUT 33
1
MAKE_BASE=TRUE NO_TEST=1 CRITICAL PLACE NEAR=U7700.B6:5MM
RE1F1 1 CE1F1
100PF
10KOHM-1%-0.31MA 5%
2 25V
TAP NEGATIVE CLOSE TO VSS_REF 0201 C0G
0201
ADDED OPTION PER RDAR://60203428 2 XWE1F2
SM
THMSNS_SPMU5_N 1 2 THMSNS_SPMU_VSS 49
PLACE_NEAR=U8100.J11:5MM NO_TEST=1
NOSTUFF NOSTUFF NO_XNET_CONNECTION=1
PLACE_NEAR=U7700.C6:5MM
RE100 RE1A0
THMSNS_MPMU_VSS 1
0 2 THMSNS_SPMU_VSS 1
0 2
49 49 C M TE E T M C TE
1 20 5% MF 0201 1/20W 5% MF 0201 PAGE TITLE
SENSORS: THERMAL (1/2)

RE101 RE1A1
1
0 2 VSS_ANA_MPMU 1
0 2 VSS_ANA_SPMU
32 33 34 29 30
1/20W 5% MF 0201 1/20W 5% MF 0201
2 1
RETIMER ATC0 [TT0D] I/O PROXIMITY [TIOP]
LOCATION: ON CHIP I2C ADDR WR:0X90 RD: 0X91
XWE211 LOCATION: TBD
SM RE201
ATCRTMR0_THERM_D_P 1 2 THMSNS_D1 PP3V3_S2SW_SNS 1
0 2 PP3V3_S2SW_THMSNS_R
53 IN 50 104 43
NO_XNET_CONNECTION=1 5% MIN_NECK_WIDTH=0.1000
PLACE_NEAR=UE200.6:5MM 1/20W VOLTAGE=3.3V
MF
1 CE211 0201
1 CE201
2200PF
10% 0.1UF
2 10V
X7R-CERM
10%
2 6.3V
0201 XWE212
SM
CERM-X5R
0201 V+
53 IN ATCRTMR0_THERM_D_N 1 2 THMSNS_COM 50
UE200
TMP464
NO_XNET_CONNECTION=1 VQFN
50 THMSNS_D1 6 D1+ CRITICAL SCL
13 I2C_THMSNS_3V3_SCL 43
50 THMSNS_D2 5 D2+
SDA
12 I2C_THMSNS_3V3_SDA 43
50 THMSNS_COM 4 D3+
RETIMER ATC1 [TT1D] UNUSED CHANNELS CONNECT TO D- 50 THMSNS_COM 3 D4+ THERM2* 11
NC
THERM* 10
LOCATION: ON CHIP NC
XWE221
SM NC1 2
NC
54 IN ATCRTMR1_THERM_D_P 1 2 THMSNS_D2 50 NC0 1
NC
50 THMSNS_COM 7 D- 16
NO_XNET_CONNECTION=1 NC3 NC
THMSNS_ADDR_SEL 9 ADD NC2 15
NC
1 CE221
2200PF 1
RE202 GND EPAD
10%
2 10V
X7R-CERM 100K
5%
0201 XWE222
SM
1/20W
MF
54 ATCRTMR1_THERM_D_N 1 2 THMSNS_COM 50
2 201
IN
C M TE E T M C TE
PAGE TITLE
SENSORS: THERMAL (2/2)
2 1
KOBOL: ACCEL & GYRO
VOLTAGE=1.8V SENSOR_IMU
MIN_NECK_WIDTH=0.1000 FLE400
120OHM-25%-0.25A-0.5OHM
PP1V8_S2 51 PP1V8_S2_IMU_FILT 1 2 PP1V8_S2 51 101
SENSOR_IMU SENSOR_IMU SENSOR_IMU 0201
SENSOR_IMU SENSOR_IMU SENSOR_IMU

1 CE400 1 CE401 1 CE402
0.1UF 0.1UF 2.2UF
1 1 10% 10% 20%
RE403 RE404 RE400 2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R
100K 100K 100K 0201 0201 0201
5% 5% 5%
1/20W 1/20W 1/20W
MF MF MF
201 2 201 2 2 201
VDD VDDIO
SENSOR_IMU
UE400
BMI282AA
LGA
51 SPI_GYRO_CS_1V8_L 5 CS* SCLK 2 SPI_AOP_SENSOR_CLK_1V8 51 SENSOR_IMU
15 SM
MOSI 3 SPI_AOP_SENSOR_MOSI_1V8 51
RE401
GYRO_INT_1V8 6 20
51 INT MISO 4 SPI_AOP_SENSOR_MISO_1V8_R 1 2 SPI_AOP_SENSOR_MISO_1V8 51
51 GYRO_MOTION_INT_1V8 7 MOTION_INT 5%
1/20W
MF
201
GND
SENSOR_IMU
RE4051
47K
5%
1/20W
MF
201 2
102 51 PP1V25_S2
1
SENSOR_IMU
CE411
0.1UF
SPI LEVEL TRANSLATION
10%
2 10V
X5R-CERM
0201 102 51 PP1V25_S2 PP1V8_S2_IMU_FILT 51
SENSOR_IMU SENSOR_IMU
SENSOR_IMU
UE411 1 CE421 1 CE422
SN74AUP1G17 0.1UF SENSOR_IMU 0.1UF
VCC SENSOR_IMU 10% 10%
SPI_AOP_SENSOR_MISO_1V8 2
SON
4 SPI_AOP_GYRO_R1_MISO 2 10V
X5R-CERM UE420 2 10V
X5R-CERM
51
NC
OUT 9 RE4201 0201 SN74AXC1T45 0201
GND
NC 47K SOT-5X3
5%
1/20W VCCA VCCB
MF
201 2
5 DIR
106 9 IN SPI_GYRO_CS_L 3 A B 4 SPI_GYRO_CS_1V8_L 51
GND
102 51 PP1V25_S2
SENSOR_IMU
1 CE412
0.1UF
10%
2 10V
X5R-CERM
0201 SENSOR_IMU
SENSOR_IMU RE435
UE412 SPI_AOP_SENSOR_CLK_1V8_R 1
20 2 SPI_AOP_SENSOR_CLK_1V8
51 51
VCC
SN74AUP1G17 5%
SON 1/20W
51 GYRO_INT_1V8 2 4 GYRO_INT OUT 9 106 MF
NC 201
GND
NC PLACE_NEAR=UE430:10MM
SENSOR_IMU
RE436
SPI_AOP_SENSOR_MOSI_1V8_R 1
20 2 SPI_AOP_SENSOR_MOSI_1V8
51 51
5%
1/20W
MF
102 51 PP1V25_S2 201
SENSOR_IMU
1 CE413 PP1V25_S2 PP1V8_S2_IMU_FILT
0.1UF 102 51 51
10% SENSOR_IMU SENSOR_IMU
2 10V
X5R-CERM
0201
1 CE431 1 CE432
0.1UF 0.1UF
SENSOR_IMU 10% 10%
UE413 2 10V
X R-CE M 2 10V
X5R-CERM
SN74AUP1G17 0201 0201
VCC SON
51 GYRO_MOTION_INT_1V8 2 4 GYRO_MOTION_INT OUT 9 106 VCCA VCCB
NC
NC
GND UE430
SPI_AOP_SENSOR_CLK 2 1A 74AVC2T45 1B 7 SPI_AOP_SENSOR_CLK_1V8_R
18 IN VSSOP 51
18 IN SPI_AOP_SENSOR_MOSI 3 2A 2B 6 SPI_AOP_SENSOR_MOSI_1V8_R 51
SENSOR_IMU
5 DIR
GND
SENSOR_IMU SENSOR_IMU SYNC_MASTER=WUDI_T668_MLB C TE
1 1 PAGE TITLE
RE430 RE431
47K
5%
47K
5%
SENSORS: MOTION
1/20W 1/20W
MF MF
201 2 201 2
FAN CONTROL
XWE598
SM
NOSTUFF
104 52 PP5V_S2 1 2
RE590
PP3V3_S2 1
0 2
104
0%
1/16W
1 CE503
MTL-FILM 0.1UF
0402 10%
116S00006 2 10V
X6S-CERM
0201
RE591
PP1V8_S2 1
0 2 PPVCC_FAN_PWM_LS
101
0% MIN_LINE_WIDTH=0.2000
1/16W VOLTAGE=3.3V
MTL-FILM
0402
116S00006
1 CE502
0.1UF
102 PP1V25_S2 10%
2 6.3V
CERM-X5R NOSTUFF
1 CE501 UE501 0201
RE501 1 QE500
0.1UF SN74AXC1T45 NTNS4CS69N
0%
2 6.3V
CERM-X5R
0201 VCCA VCCB
SOT-5X3 100K
5%
1/20W
MF
1 XDFN
376S00282
J223 FAN CONNECTOR
201 2
5 DIR
3
2
1V2 106 9 IN SMC_FAN_PWM 3 A B 4 SMC_FAN_LS_PWM NOSTUFF 518S0818
1
RE503 1 GND
RE502 1 RE580 JE501
1M
47K 100K 5% FF14A-6C-R11DL-B-3H
5% 5% 1/20W F-RT-SM
RE500 1 1/20W
MF
1/20W
MF
MF
201 2 MIN_LINE_WIDTH=0.2000 7
20K 201 2 201 2 MIN_NECK_WIDTH=0.1000
5% VOLTAGE=5
1/20W
MF 89 PP5V_S2_TO_FAN 1
201 2
RE505 89 FAN_RT_PWM 2
NOTE: 1.5 MOHM PU INSIDE IC 3
SMC_FAN_TACH 20K FAN_RT_TACH
1V2 9 OUT 1 2 89 4
5% 89 TP_FAN_RT_OTP1 5
1/20W 2
MF
201
DZE500 89 TP_FAN_RT_OTP2 6
5.5V-0.28PF
0201-THICKSTNCL 8
1
XWE599
SM
1 289 GND_FAN
5V POWER FOR A DEBUG FAN

518S0769
CRITICAL
PLACE_SIDE=BOTTOM
DBG_FAN
JE500
FF14A-5C-R11DL-B-3H
F-RT-SM
6
NC
104 52 PP5V_S2 1
NC
1 CE504 3
0.1UF 4
10% NC SYNC_MASTER=AITKEN_T668_MLB SYNC_DATE=09/18/2019
2 10V
X6S-CERM NC
5
PAGE TITLE
0201
7 FAN
NC
BOM_COST_GROUP=FAN
** OK2INTEGRATE **
Caps and connector must be aliased to BBR signals.
Lanes 1 and 2 can be swapped, both pairs, both sides; all or nothing.
USBC HIGH-SPEED AC COUPLING Inputs can be polarity inverted independently per pair.
GND_VOID=TRUE All swaps and inversions must be communicated to TBT Firmware team.
5 IN USBC_ATC0_R2D_C_P<1> CF020 1 2
20%
USBC_ATC0_R2D_P<1>
6.3V 0201
107
GND_VOID=TRUE 0.22UF X5R

5 IN USBC_ATC0_R2D_C_N<1> CF021 1 2
20%
USBC_ATC0_R2D_N<1>
6.3V 0201
107
338S00561
0.22UF X5R
GND_VOID=TRUE UF000
20%
USBC_ATC0_R2D_P<2>
6.3V 0201
107
GND_VOID=TRUE
9999HH
GND_VOID=TRUE
GND_VOID=TRUE 0.22UF X5R GND_VOID=TRUE BGA
J12 GND_VOID=TRUE
USBC_ATC0_R2D_P<1> J1 ASSRXP1 SYM 1 OF 2 BSSRXP1 USBC0_D2R_P<1>
20%
USBC_ATC0_R2D_N<2>
6.3V 0201
107
107
107 USBC_ATC0_R2D_N<1> J2 ASSRXN1 BSSRXN1 J11 USBC0_D2R_N<1>

BI 107
07
0.22UF BI
GND_VOID=T U X5R
GND_VOID=TRUE CRITICAL GND_VOID=TRUE
GND_VOID=TRUE C12 GND_VOID=TRUE
5 BI USBC_ATC0_D2R_P<1> CF022 1 2
20%
USBC_ATC0_D2R_C_P<1>
6.3V 0201
107 107 USBC_ATC0_R2D_P<2> C1 ASSRXP2 OMIT_TABLE BSSRXP2 USBC0_D2R_P<2> BI 107
GND_VOID=TRUE 0.22UF X5R 107 USBC_ATC0_R2D_N<2> C2 ASSRXN2 BSSRXN2 C11 USBC0_D2R_N<2> BI 107
5 BI USBC_ATC0_D2R_N<1> CF023 1 2 USBC_ATC0_D2R_C_N<1> 107 GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE 0.22UF
20%
X5R
6.3V 0201
107 USBC_ATC0_D2R_C_P<1> G1 ASSTXP1 BSSTXP1 G12 GND_VOID=TRUE USBC0_R2D_CR_P<1> 107
OUT
USBC_ATC0_D2R_C_N<1> G2 ASSTXN1 BSSTXN1 G11 USBC0_R2D_CR_N<1>
%
6.3V 0201
107
107
OUT 107
GND_VOID=TRUE 0.22UF X5 GND_VOID=TRUE E12 GND_VOID=TRUE

USBC_ATC0_D2R_C_P<2> E1 ASSTXP2 BSSTXP2 USBC0_R2D_CR_P<2>
5 BI USBC_ATC0_D2R_N<2> CF027 1 2
20%
USBC_ATC0_D2R_C_N<2>
6 3V 0201
107
107
107 USBC_ATC0_D2R_C_N<2> E2 ASSTXN2 BSSTXN2 E11 USBC0_R2D_CR_N<2>

OUT 107
107
0.22UF OUT
X5R
5 BI USBC_ATC0_AUX_P CF028 1 2
10% 6.3V 0201
USBC_ATC0_AUX_C_P L8 PA_AUX_P INTERNAL CAPS,
PU, PD
BSBU1 M10 USBC0_AUXLSX_P BI 57
0.1UF CERM-X5R USBC_ATC0_AUX_C_N M8 PA_AUX_N BSBU2 L10 USBC0_AUXLSX_N BI 57
5 BI USBC_ATC0_AUX_N CF029 1 2
10% 6.3V 0201
60 IN CIO_ATC0_LSTX_3V3 M7 PA_LSTX_SBU1 PERST* B8 ATCRTMR01_ACTIVE_READY_3V3 IN 53 54 55
0.1UF CERM-X5R 60 OUT CIO_ATC0_LSRX_3V3 L7 PA_LSRX_SBU2 RESET* L11 ATCRTMR0_RESET_L IN 55 57 60
NOSTUFF INT_I2C_ATCRTMR0_L A10 A3 JTAG_ATCRTMR01_TDI

55 OUT I2C_INT TDI IN 55
RF0281 1
RF029 RF0081 RF0091 60 57 55 BI I2C_UPC0_ATCRTMR0_SCL C9 I2C_SCL TMS C3 JTAG_ATCRTMR0_TMS IN 55
33K 33K 100K 100K I2C_UPC0_ATCRTMR0_SDA E7 B5 JTAG_ATCRTMR01_TCK
5% 5% 5% 5% 60 57 55 BI I2C_SDA TCK IN 55
1/20W 1/20W 1/20W 1/20W C5
MF MF MF MF TDO JTAG_ATCRTMR01_TDO OUT 55
201 2 2 201 201 2 201 2 53 ATCRTMR0_GPIO_5 B9 POC_GPIO_5
53 ATCRTMR0_GPIO_6 A8 POC_GPIO_6 To SPI Flash EE_DI C4 SPI_ATCRTMR0_R_MOSI UT 55
53 ATCRTMR0_FLASH_SHARE_EN A4 POC_GPIO_10 IPU ~ 65K EE_DO B4 SPI_ATCRTMR0_R_MISO IN 55
55 IN ATCRTMR01_FLASH_MSTR A5 POC_GPIO_11 IPU ~ 65K EE_CS* B6 SPI_ATCRTMR0_R_CS_L OUT 55
53 ATCRTMR0_GPIO_12 A6 POC_GPIO_12 IPU ~ 65K EE_CLK C7 SPI_ATCRTMR0_R_CLK OUT 55
50 OUT ATCRTMR0_THERM_D_P M11 THERMDA TEST_EN B11

TEST_PWR_GOOD B3 ATCRTMR0_TEST_PWR_GOOD
53 ATCRTMR0_XTAL25M_IN L9 XTAL_25_IN RBIAS L4 ATCRTMR0_RBIAS RF0061

ATCRTMR0_XTAL25M_OUT M9 L5 ATCRTMR0_RSENSE 2 1
100
53 XTAL_25_OUT RSENSE 5%
1/20W
4.75K 1/20W TF MF
0.5% 201 2
PP3V3_S2SW_USB0 53 55 104
L12 MONDC_SVR ATEST_P A1
NC 0201 RF007
PP3V3_S2SW_USB0 53 55 104
A11 MONDC ATEST_N A2
NC
PLACE_NEAR=UF000.L5:2MM
100K 2 RF050 RF002 M12 TEST_EDM FORCE_PWR B10 ATCRTMR0_FORCE_PWR IN 55 57

1 ATCRTMR0_GPIO_5 53 0
5% 1/20W MF 201 ATCRTMR0_XTAL25M_OUT_R 2 1 ATCRTMR0_XTAL25M_OUT 53
100K 2 A12 A9 FLASH_BUSY_USBC01_L

NOSTUFF 1 RF041 ATCRTMR0_GPIO_6 53 CF002 1 0201
MF
5%
1/20W NC
J6
NC_A12 FLASH_BUSY*
B2
BI 55
5% 1/20W MF 201 NC_J6 FUSE_VQPS_64

20PF NC
L3
0 5% CRITICAL
55 54 53 ATCRTMR01_ACTIVE_READY_3V3 1 2 RF040 25V 2 NC NC_L3
IN 5% 1/20W MF 0201 C0G
0201 YF000 NC
J5 NC_J5 SMBUS_SCL A7 TP_SMBUS_ATCRTMR0_SCL
100K 2 25MHZ-25PPM-20PF-50OHM B7 TP_SMBUS_ATCRTMR0_SDA
NOSTUFF 1 RF051 0201
C0G 2
SMBUS_SDA
5% 1/20W MF 201 2.00X1.60-SM
25V
100K 2 5%
NOSTUFF 1 RF043 ATCRTMR0_FLASH_SHARE_EN 53 20PF RF003
5% 1/20W MF 201
CF003 1 0 ATCRTMR0_XTAL25M_IN
100K 2 RF045 ATCRTMR0_GPIO_12
2 1 53 FROM USB-C PORT
NOSTUFF 1
5% 1/20W MF
53
ATCRTMR0_XTAL25M_IN_R0201 5%
CONTROLLER (UPC)
MF 1/20W PP3V3_S2SW_USB0 53 55 104
RF000 NOSTUFF
VOLTAGE=3.3V
338S00561
PP3V3_ATCRTMR0_VCCA 1
0 2
1 CF036 1 CF037 1 CF042
UF000 2.2UF 2.2UF 47UF
5% 4 2 20% 20% 20
PP0V9_ATCRTMR0_SVR 9999HH 1 CF043 1 CF030 1 CF031 1/16W MF-LF 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
CER-X5R
53
CRITICAL CRITICAL CRITICAL CRITICAL BGA 12PF 2.2UF 10UF 0201 0201 0603
F6 E6 5% 20% 20%
G6 VCC0P9_SVR_ANA
SYM 2 OF 2 VCC3P3_SX
2 25V
NP0-C0G 2 6.3V
X5R-CERM 2 6.3V
CERM
RF001
0201 0201 0402 1
0 2
1 CF065 1 CF064 1 CF063 1 CF062 1 CF061 1 CF060 1 CF050 1 CF051 1 CF052 1 CF053 E9
VCC0P9_SVR_PB_ANA
VCC3P3A J7
5% 402 XWF001
20UF 20UF 20UF 20UF 4UF 4UF 4UF 4UF 4UF 4UF G9 VOLTAGE=3.3V 1/16W MF-LF SM
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-C RM 2 6.3V
CER-X5R 2 6 3V
CE -X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R CRITICAL PP3V3_ATCRTMR0_SVR 1 2 PP3V3_S2SW_USB0 53 55 104
0402 0402 0402 0402 0201 020 0201 201 0201 0201 OMIT_TABLE M4 NO_XNET_CONNECTION=1
VCC3P3_SVR M5
1 CF032 1 CF033 1 CF034 1 CF035
10UF 10UF 10UF 10UF
20% 20% 20% 20%
2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM
0402
CERM
0402
CERM
0402
CERM
0402 XWF000
SM
PP0V9_ATCRTMR0_LVR L6 VCC0P9_LVR E3 BYPASS=UF000.M4:M3:3MM
VOLTAGE=0.9V M6 VCC0P9_SVR G3
P0V9_ATCRTMR0_SVR_PGND 1 2
VCC0P9_LVR_SENSE VOLTAGE=0V
CF054 1 CF055 1 PLACE_NEAR=CF032.2:2MM
10UF 2.2UF PP0V9_ATCRTMR0_SVR 53
20% 20% E5 VCC3P3_LC VOLTAGE=0.9V
6.3V 2 6.3V L1
CERM X5R-CERM 2 VOLTAGE=3 3V PP3V3_ATCRTMR0_ANA L2 VCC3P3_ANA SVR_IND
0402 0201
55 PP0V9_ATCRTMR0_LC J3 VCC0P9_LC
M1 1 CF038 1 CF039 1 CF041
VOLTAGE=0.9V 12PF 4UF 4UF
5% 20% 20%
2 25V
NP0-C0G 2 6.3V
CER-X5R 2 6.3V
CER-X5R
PP3V3_ATCRTMR0_LC F3
M2 0201 0201 0201
VOLTAGE=3.3V SVR_VSS M3
MIN_NECK_WIDTH=0.0750 1 CF056 1 CF057 1 CF058
F5 VSS CRITICAL 1 CF040
2 2UF G5 F7 LF000
20% 2.2UF 2.2UF 0.68UH-20%-4.3A-0.043OHM 47UF
2 6.3V 20% 20% F9 20%
X5R-CERM 2 6.3V 2 6.3V 2 6.3V
3.3V LDO PACK_OPTION=PKGS:SMALL_PITCH
0201 X5R-CERM
0201
X5R-CERM
0201
B1
B12
D1
G7
H1
H11
PP0V9_ATCRTMR0_SVR_IND 1
_
VOLTAGE=0.9V
DIDT=TRUE
2
0805
CER-X5R
0603
ALLOW_APPLE_PREFIX=U
D11 H12
UF015 D12 H2
TLV75533 VSS_ANA VSS_ANA
105 PP3V8_AON_ATC_ISNS 4 IN
X2SON
OUT 1 PP3V3_S2SW_USB0 104
D2 J9 XWF030
SM
PACK_IGNORE=TRUE F1 K1 SYNC_MASTER=REF_USBC_ACE2 SYNC_DATE=02/14/2020
PACK_OPTION=PKGS:LARGER_PITCH 1 2 ATCRTMR0_THERM_D_N OU 50
107 USBC0_3V3LDO_EN_MUX 3 EN F11 K11 PAGE TITLE
IN
THRM
1 CF015 F12 K12 PLACE_NEAR=UF000.K11:2MM USB-C: High Speed ATC0
GND PAD 1.0UF UF015
RF012 1 CF010 1 20%
2 6.3V TLV75533
F2 K2 NO_XNET_CONNECTION=1
100K 1.0UF X5R
0201-1 WSON CONNECT TO GND PIN
5% 20% 6 IN OUT 1
1/20W 6.3V 2 CLOSEST TO THERMDA PIN
MF X5R
201 2 0201-1 4 EN 2
NC
NC 5
NC
GND EPAD
BOM_COST_GROUP=TBT
** OK2INTEGRATE **
Caps and connector must be aliased to BBR signals.
Lanes 1 and 2 can be swapped, both pairs, both sides; all or nothing.
USBC HIGH-SPEED AC COUPLING Inputs can be polarity inverted independently per pair.
GND_VOID=TRUE All swaps and inversions must be communicated to TBT Firmware team.
20%
USBC_ATC1_R2D_P<1>
6.3V 0201
107
GND_VOID=TRUE 0.22UF X5R

20%
USBC_ATC1_R2D_N<1>
6.3V 0201
107
338S00561
0.22UF X5R
GND_VOID=TRUE UF100
20%
USBC_ATC1_R2D_P<2>
6.3V 0201
107
GND_VOID=TRUE
9999HH
GND_VOID=TRUE
GND_VOID=TRUE 0.22UF X5R GND_VOID=TRUE BGA
J12 GND_VOID=TRUE
USBC_ATC1_R2D_P<1> J1 ASSRXP1 SYM 1 OF 2 BSSRXP1 USBC1_D2R_P<1>
20%
USBC_ATC1_R2D_N<2>
6.3V 0201
107
107
107 USBC_ATC1_R2D_N<1> J2 ASSRXN1 BSSRXN1 J11 USBC1_D2R_N<1>

BI 107
07
0.22UF BI
GND_VOID=TRUE X5R
GND_VOID=TRUE CRITICAL GND_VOID=TRUE
GND_VOID=TRUE C12 GND_VOID=TRUE
20%
6.3V 0201
107 107 USBC_ATC1_R2D_P<2> C1 ASSRXP2 OMIT_TABLE BSSRXP2 USBC1_D2R_P<2> BI 107
GND_VOID=TRUE 0.22UF X5R 107 USBC_ATC1_R2D_N<2> C2 ASSRXN2 BSSRXN2 C11 USBC1_D2R_N<2> BI 107
5 BI USBC_ATC1_D2R_N<1> CF123 1 2 USBC_ATC1_D2R_C_N<1> 107 GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE 0.22UF
20%
X5R
6.3V 0201
107 USBC_ATC1_D2R_C_P<1> G1 ASSTXP1 BSSTXP1 G12 GND_VOID=TRUE USBC1_R2D_CR_P<1> 107
OUT
USBC_ATC1_D2R_C_N<1> G2 ASSTXN1 BSSTXN1 G11 USBC1_R2D_CR_N<1>
%
6.3V 0201
107
107
GND_VOID=TRU GND_VOID=TRUE
OUT 107
GND_VOID=TRUE 0.22UF X5 GND_VOID=TRUE E12 GND_VOID=TRUE

USBC_ATC1_D2R_C_P<2> E1 ASSTXP2 BSSTXP2 USBC1_R2D_CR_P<2>
5 BI USBC_ATC1_D2R_N<2> CF127 1 2
20%
USBC_ATC1_D2R_C_N<2>
6 3V 0201
107
107
107 USBC_ATC1_D2R_C_N<2> E2 ASSTXN2 BSSTXN2 E11 USBC1_R2D_CR_N<2>

OUT 107
107
0.22UF OUT
X5R
5 BI USBC_ATC1_AUX_P CF128 1 2
10% 6.3V 0201
USBC_ATC1_AUX_C_P L PA_AUX_P INTERNAL CAPS,
PU, PD
BSBU1 M10 USBC1_AUXLSX_P BI 58
0.1UF CERM-X5R USBC_ATC1_AUX_C_N M8 PA_AUX_N BSBU2 L10 USBC1_AUXLSX_N BI 58
5 BI USBC_ATC1_AUX_N CF129 1 2
10% 6.3V 0201
60 IN CIO_ATC1_LSTX_3V3 M7 PA_LSTX_SBU1 PERST* B8 ATCRTMR01_ACTIVE_READY_3V3 IN 53 54 55
0.1UF CERM-X5R 60 OUT CIO_ATC1_LSRX_3V3 L7 PA_LSRX_SBU2 RESET* L11 ATCRTMR1_RESET_L IN 58 60
NOSTUFF INT_I2C_ATCRTMR1_L A10 A3 JTAG_ATCRTMR01_TDI

55 OUT I2C_INT TDI IN 55
RF1281 1
RF129 RF1081 RF1091 60 58 55 BI I2C_UPC1_ATCRTMR1_SCL C9 I2C_SCL TMS C3 JTAG_ATCRTMR1_TMS IN 55
33K 33K 100K 100K I2C_UPC1_ATCRTMR1_SDA E7 B5 JTAG_ATCRTMR01_TCK
5% 5% 5% 5% 6 58 55 BI I2C_SDA TCK IN 55
1/20W 1/20W 1/20W 1/20W C5
MF MF MF MF TDO JTAG_ATCRTMR01_TDO OUT 55
201 2 2 201 201 2 201 2 54 ATCRTMR1_GPIO_5 B9 POC_GPIO_5
54 ATCRTMR1_GPIO A8 POC_GPIO_6 To SPI Flash EE_DI C4 SPI_ATCRTMR1_R_MOSI UT 55
54 ATCRTMR1_FLASH_SHARE_EN A4 POC_GPIO_10 IPU ~ 65K EE_DO B4 SPI_ATCRTMR1_R_MISO IN 55
55 IN ATCRTMR01_FLASH_SLV_L A5 POC_GPIO_11 IPU ~ 65K EE_CS* B6 SPI_ATCRTMR1_R_CS_L OUT 55
54 ATCRTMR1_GPIO_12 A6 POC_GPIO_12 IPU ~ 65K EE_CLK C7 SPI_ATCRTMR1_R_CLK OUT 55
50 OUT ATCRTMR1_THERM_D_P M11 THERMDA TEST_EN B11

TEST_PWR_GOOD B3 ATCRTMR1_TEST_PWR_GOOD
54 ATCRTMR1_XTAL25M_IN L9 XTAL_25_IN RBIAS L4 ATCRTMR1_RBIAS RF1061

ATCRTMR1_XTAL25M_OUT M9 L5 ATCRTMR1_RSENSE 1
100
54 XTAL_25_OUT RSENSE 5%
1/20W
4.75K 1/20W TF MF
0.5% 201 2
PP3V3_S2SW_USB1 54 104
L12 MONDC_SVR ATEST_P A1
NC 0201 RF107
PP3V3_S2SW_USB1 54 55 104
A11 MONDC ATEST_N A2
NC
100K 2 RF150 RF102 M12 TEST_EDM FORCE_PWR B10 ATCRTMR1_FORCE_PWR IN 55 58

1 ATCRTMR1_GPIO_5 54 0
5% 1/20W MF 201 ATCRTMR1_XTAL25M_OUT_R 2 1 ATCRTMR1_XTAL25M_OUT 54
100K 2 A12 A9 FLASH_BUSY_USBC01_L

NOSTUFF 1 RF141 ATCRTMR1_GPIO_6 54 CF102 1 0201
MF
5%
1/20W NC
J6
NC_A12 FLASH_BUSY*
B2
BI 5 55
5% 1/20W MF 201 NC_J6 FUSE_VQPS_64

20PF NC
L3
0 5% CRITICAL
55 54 53 ATCRTMR01_ACTIVE_READY_3V3 1 2 RF140 25V 2 NC NC_L3
IN 5% 1/20W MF 0201 C0G
02 1 YF100 NC
J5 NC_J5 SMBUS_SCL A7 TP_SMBUS_ATCRTMR1_SCL
100K 2 25MHZ-25PPM-20PF-50OHM B7 TP_SMBUS_ATCRTMR1_SDA
NOSTUFF 1 RF151 0201
C0G 2
SMBUS_SDA
5% 1/20W MF 201 2.00X1.60-SM
25V
100K 2 5%
NOSTUFF 1 RF143 ATCRTMR1_FLASH_SHARE_EN 54 20PF RF103
5% 1/20W MF 201
CF103 1 0 ATCRTMR1_XTAL25M_IN
100K 2 RF145 ATCRTMR1_GPIO_12
2 1 54 FROM USB-C PORT
NOSTUFF 1
5% 1/20W MF 201
54
ATCRTMR1_XTAL25M_IN_R0201 5%
CONTROLLER (UPC)
MF 1/20W PP3V3_S2SW_USB1 54 104
RF100 NOSTUFF
VOLTAGE=3.3V
338S00561
PP3V3_ATCRTMR1_VCCA 1
0 2
1 CF136 1 CF137 1 CF142
UF100 2.2UF 2.2UF 47UF
5% 402 20% 20% 20%
PP0V9_ATCRTMR1_SVR 9999HH 1 CF143 1 CF130 1 CF131 1/16W MF-LF 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
CER-X5R
54
CRITICAL CRITICAL CRITICAL CRITICAL BGA 12PF 2.2UF 10UF 0201 0201 0603
F6 E6 5% 20% 20%
G6 VCC0P9_SVR_ANA
SYM 2 OF 2 VCC3P3_SX
2 25V
NP0-C0G 2 6.3V
X5R-CERM 2 6.3V
CERM
RF101
0201 0201 0402 1
0 2
1 CF165 1 CF164 1 CF163 1 CF162 1 CF161 1 CF160 1 CF150 1 CF151 1 CF152 1 CF153 E9
VCC0P9_SVR_PB_ANA
VCC3P3A J7
5% 402 XWF101
20UF 20UF 20UF 20UF 4UF 4UF 4UF 4UF 4UF 4UF G9 VOLTAGE=3.3V 1/16W MF-LF SM
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-C RM 2 6.3V
CER-X5R 2 6 3V
CE -X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R CRITICAL PP3V3_ATCRTMR1_SVR 1 2 PP3V3_S2SW_USB1 54 55 104
0402 0402 0402 0402 0201 020 0201 201 0201 0201 OMIT_TABLE M4 NO_XNET_CONNECTION=1
VCC3P3_SVR M5
1 CF132 1 CF133 1 CF134 1 CF135
10UF 10UF 10UF 10UF
20% 20% 20% 20%
2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM
0402
CERM
0402
CERM
04 2
CERM
0402 XWF100
SM
PP0V9_ATCRTMR1_LVR L6 VCC0P9_LVR E3 BYPASS=UF100.M4:M3:3MM
VOLTAGE=0.9V M6 VCC0P9_SVR G3
P0V9_ATCRTMR1_SVR_PGND 1 2
VCC0P9_LVR_SENSE VOLTAGE=0V
CF154 1 CF155 1 PLACE_NEAR=CF132.2:2MM
10UF 2.2UF PP0V9_ATCRTMR1_SVR 54
20% 20% E5 VCC3P3_LC VOLTAGE=0.9V
6.3V 2 6.3V L1
CERM X5R-CERM 2 VOLTAGE=3 3V PP3V3_ATCRTMR1_ANA L2 VCC3P3_ANA SVR_IND
0402 0201
PP0V9_ATCRTMR1_LC J3 VCC0P9_LC
M1 1 CF138 1 CF139 1 CF141
VOLTAGE=0.9V 12PF 4UF 4UF
5% 20% 20%
2 25V
NP0-C0G 2 6.3V
CER-X5R 2 6.3V
CER-X5R
PP3V3_ATCRTMR1_LC F3
M2 0201 0201 0201
VOLTAGE=3.3V SVR_VSS M3
MIN_NECK_WIDTH=0.0750 1 CF156 1 CF157 1 CF158
F5 VS CRITICAL
CF140
2 2UF G5 F7 LF100
20% 2.2UF 2.2UF 0.68UH-20%-4.3A-0.043OHM 47UF
2 6.3V 20% 20% F9 20%
X5R-CERM 2 6.3V 2 6.3V 2 6.3V
3.3V LDO PACK_OPTION=PKGS:SMALL_PITCH
0201 X5R-CERM
0201
X5R-CERM
0201
B1
B12
D1
G7
H1
H11
PP0V9_ATCRTMR1_SVR_IND 1
_
VOLTAGE=0.9V
DIDT=TRUE
2
0805
CER-X5R
0603
D11 H12
UF115 D12 H2
TLV75533 VSS_ANA VSS_ANA
105 PP3V8_AON_ATC_ISNS 4 IN
X2SON
OUT 1 PP3V3_S2SW_USB1 104
D2 J9 XWF130
SM
PACK_IGNORE=TRUE F1 K1 SYNC_MASTER=REF_USBC_ACE2 SYNC_DATE=02/14/2020
PACK_OPTION=PKGS:LARGER_PITCH 1 2 ATCRTMR1_THERM_D_N OU 50
107 USBC1_3V3LDO_EN 3 EN F11 K11 PAGE TITLE
IN
THRM
1 CF115 F12 K12 PLACE_NEAR=UF100.K11:2MM USB-C: High Speed ATC1
GND PAD 1.0UF UF115
RF112 1 CF110 1 20%
2 6.3V TLV75533
F2 K2 NO_XNET_CONNECTION=1
100K 1.0UF X5R
0201-1 WSON CONNECT TO GND PIN
5% 20% 6 IN OUT 1
1/20W 6.3V 2 CLOSEST TO THERMDA PIN
MF X5R
201 2 0201-1 4 EN 2
NC
NC 5
NC
GND EPAD
BOM_COST_GROUP=TBT
2 1
** OK2INTEGRATE ** NO_XNET_CONNECTION=1
PP3V3_UPC0_LDO 55 100 ATC0: I2C_ADDR=GND, I2CM_*_CNFG=1M\u03a9 3V3_LDO_X pull-ups
NOSTUFF
RF294 1 2
5% 1/20W
SPI_UPC01_CLK_DBG
MF 201
55
ATC1: I2C_ADDR=Float, I2CM_*_CNFG=1M\u03a9 3V3_LDO_X pull-ups
1
1
RF260 RF261 1 1
RF263 1
RF262 1 CF260 RF295 1
5% 1/20W MF 201
SPI_UPC01_R_CLK 55 ATC2: I2C_ADDR=GND, I2CM_*_CNFG=1M\u03a9 pull-downs
3.3K 3.3K 3.3K 3.3K 1UF 15 ATC3: I2C_ADDR=Float, I2CM_*_CNFG=1M\u03a9 pull-downs
5%
1/20W
5%
1/20W
5%
1/20W VCC 5%
1/20W 10% RF296 1 2
5% 1/20W MF 201
SPI_UPC01_R_CS_L 55 SPI Ace
MF MF MF MF 2 6.3V 15
2 201 201 2 2 201 UF260 2 201
CERM
402 RF297 1 2
5% 1/20W MF 201
SPI_UPC01_R_MOSI 55
8MBIT-3.0V 15 57 GND MAKE_BASE=TRUE
W25Q80DVUXIE RF298 1 2
5% 1/20W MF 201
SPI_UPC01_R_MISO 55
58
OUT
NC_UPC1_I2C_ADDR MAKE_BASE=TRUE NC_UPC1_I2C_ADDR
OUT
6 CLK DI(IO0) 5 55 SPI_UPC01_MOSI 15 NO_TEST=1
USON
DO(IO1) 2 55 SPI_UPC01_MISO
RF290 1 2
5% 1/20W MF 201
SPI_ATCRTMR0_R_CLK IN 53
1 CS* 15 Configure to enable VDDIO and use it for SWD.
OMIT_TABLE RF291 1 2
5% 1/20W MF 201
SPI_ATCRTMR0_R_CS_L IN 53 BB 57 GND
ROM_UPC01_WP_L 3 15 OUT
55 WP*(IO2) CRITICAL RF292 1 2
5% 1/20W MF 201
SPI_ATCRTMR0_R_MOSI IN 53 58 OUT GND
MAKE_BASE=TRUE
ROM_UPC01_HOLD_L 7 HOLD*(IO3) 15
RF293 1 2
5% 1/20W MF 201
SPI_ATCRTMR0_R_MISO OUT 53
15
RF264 1 GND EPAD 55 SPI_UPC01_CLK RF299 1 2
5% 1/20W MF 201
SPI_ATCRTMR1_R_CLK IN 54 PP3V3_UPC0_LDO 55
3.3K 15
5%
1/20W
55 SPI_UPC01_CS_L RF29A 1 2
5% 1/20W MF 201
SPI_ATCRTMR1_R_CS_L IN 54
1
10K 2 RF242 FLASH_BUSY_USBC01_L 53 54 55
OUT
MF
201 2 RF29B 1
15 2 SPI_ATCRTMR1_R_MOSI 54
BB 5% 1/20W MF 201 MAKE_BASE=TRUE
IN
5% 1/20W MF
15
RF29C 1 2
5% 1/20W MF
SPI_ATCRTMR1_R_MISO OUT 54 UPC_ATCRTMR_INT 0
53 IN INT_I2C_ATCRTMR0_L
5%
1RF210
1/20W
MF 0201
2
UPC_EUSBLS_INT 0 INT_I2C_UPC0_ATCRTMR0_L OUT 55 57
60 IN INT_I2C_EUSBLS0_L
5%
RF211
1
1/20W
MF 0201
2
ACE 0 IS SPI ACE UPC_ATCRTMR_INT 0

PACK_OPTION=USBC_SPI_UPC0 54 IN INT_I2C_ATCRTMR1_L
5%
1RF215
1/20W
MF 0201
2
UPC_EUSBLS_INT 0 INT_I2C_UPC1_ATCRTMR1_L OUT 55 58

55 SPI_UPC01_R_CLK MAKE_BASE=TRUE SPI_UPC01_R_CLK 57
IN
60 IN INT_I2C_EUSBLS1_L
5%
RF216
1
1/20W
MF 0201
2
55 SPI_UPC01_R_CS_L MAKE_BASE=TRUE SPI_UPC01_R_CS_L IN 57
55 SPI_UPC01_R_MOSI MAKE_BASE=TRUE SPI_UPC01_R_MOSI IN 57 Is UPCx_5V_EN being used?

55 SPI_UPC01_R_MISO MAKE_BASE=TRUE SPI_UPC01_R_MISO 57
OUT
57 UPC0_5V_EN RF234 1
100K 2
55 ROM_UPC01_WP_L MAKE_BASE=TRUE ROM_UPC01_WP_L IN 57 5% 1/20W MF 201
58 UPC1_5V_EN RF235 1
100K 2
5% 1/20W MF 201
55 6 OUT SWD_UPC_SWCLK MAKE_BASE=TRUE SWD_UPC_SWCLK IN 57
55 6 BI SWD_UPC_SWDIO0 MAKE_BASE=TRUE SWD_UPC_SWDIO0 BI 57 PACK_OPTION=USBC01_VR5V_LOCAL_NO
55 PP3V3_UPC0_LDO PP3V3_UPC0_LDO 56 57 89
MAKE_BASE=TRUE
OUT
57 55
102 58
PP3V3_S2_UPC RF220 1
10K 2 JTAG_ATCRTMR01_TCK JTAG_ATCRTMR01_TCK 53
OUT
JTAG_ATCRTMR0_TMS 53
(Internal pull-up) Master should be on SPI Ace2.

RF221 1
10K 2 JTAG_ATCRTMR0_TMS JTAG_ATCRTMR01_TDI
OUT
53
OUT
104 53 PP3V3_S2SW_USB0 100K 2 RF244 JTAG_ATCRTMR01_TDO 53
NOSTUFF 1
5% 1/20W
ATCRTMR01_FLASH_MSTR
MF 201 OUT 53 RF222 1
100K 2 JTAG_ATCRTMR1_TMS IN

ATCRTMR01_FLASH_MSTR JTAG_ATCRTMR01_TCK 54
MAKE_BASE=TRUE RF223 1
100K 2 JTAG_ATCRTMR01_TDI JTAG_ATCRTMR1_TMS
OUT
54
FLASH_BUSY_USBC01_L FLASH_BUSY_USBC01_L OUT
55 54 53 BI MAKE_BASE=TRUE BI 57 5% 1/20W MF 201 MAKE_BASE=TRUE
JTAG_ATCRTMR01_TDI 54
RF224 1
10K 2 JTAG_ATCRTMR01_TDO JTAG_ATCRTMR01_TDO
OUT
54
IN
PACK_OPTION=USBC_S
PACK_OPTION=USBC_SPI_UPC0
_UPC0
ACE 1 IS UART ACE 5% 1/20W MF 20 MAKE_B SE=TRUE
GND
GND
IN 58
www.teknisi-indonesia.com 102 5 57 55 PP1V25_S2 PP3V3_S2_UPC 55 57 58 102
58
MAKE_BASE=TRUE
IN
CF230 1 UF230
1 CF231
GND 0.1UF 0.1UF
IN 58
10%
6.3V 2
SN74AXC1T45 10%
SOT-5X3 2 6.3V
GND OUT 58
CERM-X5R
0201
CERM-X5R
0201
VCCA VCCB
55 OUT SWD_UPC01_UART_CLK MAKE_BASE=TRUE SWD_UPC01_UART_CLK IN 58
5 DIR
55 BI SWD_UPC01_UART_DATA MAKE_BASE=TRUE SWD_UPC01_UART_DATA BI 58
94 89 33 5 IN PMU_ACTIVE_READY 3 A B 4 ATCRTMR01_ACTIVE_READY_3V3 OUT 53 54 55
ATCRTMR01_FLASH_SLV_L MAKE_BASE=TRUE GND

RF247 1 2 201
2K ATCRTMR01_FLASH_SLV_L OUT 54
1/20W 5% MF
RF272 1 2 100K PD_UPC1_GPIO1 BI 58
1/20W 5% MF 201
RF273 1 2 100K OUT 58
1/20W 5% MF 201
HV POWER ALIASES
SPI Ace 55 UART Ace Fuses for laptop charging. Desktops only need connection
PACK_IGNORE=TRUE
57 IN UART_UPC01_TX UART_UPC01_TX UART_UPC01_TX OUT 58 PACK_OPTION=USBC_DESKTOP for programming OTP.
MAKE_BASE=TRUE PACK_OPTION=USBC_LAPTOP
55
57 OUT UART_UPC01_RX UART_UPC01_RX UART_UPC01_RX IN 5 CRITICAL RF200

MAKE_BASE=TRUE 0603-1 1
0 2
FF200 5%
USBC_DBG 1/20W
ACE ARKANOID CONN 6A-32V MF
JF200 RF280 101 PPDCIN_USBC_AON 1 2 PPHV_INT0_AONSW
0201
PPHV_INT0_AONSW 57
USBC_DBG 505070-1222 VREFB_ARDV01 1
200K 2 MF PP3V3_S2_UPC MAKE_BASE=TRUE
M-ST-SM 55 57 58 102 PLACE_NEAR=UF400:5MM VOLTAGE=20V
13 14
PPHV_INT0_AONSW 57
102 58 57 55 PP1V25_S2
201 5% 1/20W
USBC_DBG USBC_DBG USBC_DBG CRITICAL RF201
SMC SOC 1 1 0603-1 0
ATCRTMR0_RESET_L 1 2 UPC_I2C_INT_L USBC_DBG CF280 RF282 RF283 1 2
60 57 53
I2C_SMC_UPC_SCL 3 4 I2C_UPC_SDA
57 107
CF281 1 0.1UF 5.1K 5.1K FF201 5%
1/20W
57 43 41 55 57
0.1UF 1 2 5% 5%
I2C_SMC_UPC_SDA 5 6 I2C_UPC_SCL 10% VREF_A VREF_B
1/20W 1/20W 6A-32V MF
0201
57 43 41 55 57 MF MF 1 2
6.3V 2 20 2 2 201
PPHV_INT1_AONSW PPHV_INT1_AONSW 58
107 57 UPC_SMC_I2C_INT_L 7 8 UPC0_SER_DBG 57
CERM-X5R 10% MAKE_BASE=TRUE
SPI_UPC01_CLK_DBG 9 10 UPC1_SER_DBG
0201 UF280 EN 8
6.3V
CERM-X5R PLACE_NEAR=UF500:5MM VOLTAGE=20V
PPHV_INT1_AONSW
55 58
LSF0102 0201 58
55 UART_UPC01_TX 11 12 UART_UPC01_RX 55 X2SON-COMBO

SPI Ace SPI Ace 57 55 41 I2C_UPC_SCL 3 A1 B1 6 I2C_UPC01_3V3_SCL 55
311S00234
15 16 57 55 41 I2C_UPC_SDA 4 A2 USBC_DBG B2 5 I2C_UPC01_3V3_SDA 55 57 PPVBUS_USBC0 MAKE_BASE=TRUE PPVBUS_USBC0 57 59 89
PACK_OPTION=PKGS:SMALL_PITCH
GND 58 PPVBUS_USBC1 MAKE_BASE=TRUE PPVBUS_USBC1 58 59 89
BRIDGE ARKANOID CONN AARDVARKANOID CONN

JF201 PACK_IGNORE=TRUE JF202
USBC_DBG 505070-1222 PACK_OPTION=PKGS LARGER_PITCH USBC_DBG 505070-1222 SYNC_MASTER=REF_USBC_ACE2 SYNC_DATE=02/01/2020
M-ST-SM M-ST-SM PAGE TITLE
13 14 13 14
VREF_A VREF_B
SPI ACE USB-C: Support 1 ATC01
ATCRTMR0_FORCE_PWR 1 2 INT_I2C_UPC0_ATCRTMR0_L USBC_DBG PP1V25_S2 1 2 SPI_UPC01_CS_L
57 53 55 57 102 58 57 55 55
PP3V3_S2SW_USB0 3 4 I2C_UPC0_ATCRTMR0_SCL UF280 EN 8 SWD_UPC_SWDIO0 3 4 SPI_UPC01_CLK

104 53 53 57 60
LSF0102 55 6 55
53 PP0V9_ATCRTMR0_LC 5 6 I2C_UPC0_ATCRTMR0_SDA 53 57 60
3 VSSOP 6 55 6 SWD_UPC_SWCLK 5 6 SPI_UPC01_MOSI 55
A1 B1
55 54 53 ATCRTMR01_ACTIVE_READY_3V3 7 8 ATCRTMR1_FORCE_PWR 54 58 55 SPI_UPC01_MISO 7 8 SWD_UPC01_UART_CLK 55
104 54 PP3V3_S2SW_USB1 9 10 INT_I2C_UPC1_ATCRTMR1_L 5 58

4 A2 B 5 55 I2C_UPC01_3V3_SDA 9 10 SWD_UPC01_UART_DATA 55
60 58 54 I2C_UPC1_ATCRTMR1_SDA 11 12 I2C_UPC1_ATCRTMR1_SCL 54 5 60 GND 55 I2C_UPC01_3V3_SCL 11 12 PP1V25_S2 55 57 58 102
15 16 15 16 UART ACE
BOM_COST_GROUP=USB-C
7 3 2 1
** OK2INTEGRATE **
Ace 0 is Debug Port?
ATC0 / UPC0 / RTMR0
PACK_OPTION=USBC_DEBUG_UPC0
89 18 6 IN UART_DEBUGPRT_R2D UART_DEBUGPRT_R2D IN 57 96
MAKE_BASE=TRUE
89 18 6 OUT UART_DEBUGPRT_D2R UART_DEBUGPRT_D2R IN 57 96
MAKE_BASE=TRUE
89 18 9 BI SWD_SOC_SWCLK SWD_SOC_SWCLK OUT 57 96
MAKE_BASE RUE
89 18 9 BI SWD_SOC_SWDIO SWD_SOC_SWDIO OUT 57 96
MAKE_BASE=TRUE
89 9 IN UART_SMC_DEBUGPRT_R2D UART_SMC_DEBUGPRT_R2D OUT 57 96
MAKE_BASE=TRUE
89 9 OUT UART_SMC_DEBUGPRT_D2R UART_SMC_DEBUGPRT_D2R IN 57 96
MAKE_BASE=TRUE
Main Debug Port

96 89 BI USB_DBG_LS_P USB_DBG_LS_P BI 57
MAKE_BASE=TRUE
96 89 BI USB_DBG_LS_N USB_DBG_LS_N BI 57
MAKE_BASE=TRUE
PP1V8_S2 PP1V8_S2 BI 57 60 101
PP1V8_S2 PP1V8_S2 BI 60 101
107 OUT UPC0_GPIO7 UPC0_GPIO7 IN 57 96 107
94 89 19 5 IN SOC_DFU_STATUS SOC_DFU_STATUS OUT 57

MAKE_BASE=TRUE
90 89 33 5 OUT SOC_FORCE_DFU SOC_FORCE_DFU IN 57
MAKE_BASE=TRUE
Ace 1 is non-debug Port?

ATC1 / UPC1 / RTMR1
PACK_OPTION=USBC_DEBUG_UPC0
PP1V8_S2 PP1V8_S2 BI 58 60 101
PP1V8_S2_USBLS1_ISNS PP1V8_S2_USBLS1_ISNS BI 60 105
RF320 1 2 100K PD_UPC1_DBG0_R PD_UPC1_DBG0_R BI 58

1/20W 5% MF 201 MAKE_BASE=TRUE
RF325 PD_UPC1_DBG5_R PD_UPC1_DBG5_R
1 2 100K
BI 58
Non-debug Port
RF328 1 2 100K PD_UPC1_USBP2_RP PD_UPC1_USBP2_RP BI 58
RF329 1 2 100K PD_UPC1_USBP2_RN PD_UPC1_USBP2_RN BI 58
Ace2 GPIOs
RF373
1/20W
1
5%
2
MF
100K
201
PD_UPC1_GPIO7
MAKE_BASE=TRUE
PD_UPC1_GPIO7 OUT 58
RF374
1/20W
1
5%
2
MF
100K
201
PD_UPC1_GPIO9
MAKE_BASE=TRUE
RF375
1/20W
1
5%
2
M
100K
201
PD_UPC1_GPIO10
MAKE_BASE=TRUE
CKPLUS_WAIVE=SINGLE_NODENET
on all nets above.
Unused ports
RF316 1 2 100K201 PD_UPC0_DBG6_R PD_UPC0_DBG6_R BI 57
1/20W 5% MF MAKE_BASE=TRUE 1/20W 5% MF 201 MAKE_BASE=TRUE
1/20W 5% MF 201 MAKE_BASE=TRUE 1/20W 5% MF 201 MAKE_BASE=TRUE
RF31A 1 2 100K PD UPC0_USBP3_RP PD_UPC0_USBP3_RP BI 57

RF32A 1 2 100K PD_UPC1_USBP3_RP PD_UPC1_USBP3_RP B 58
1/20W 5% MF 201 MAKE_BASE=TRUE 1/20 5% MF 201 MAKE_BASE RUE
RF31B 1 2 100K PD_UPC0_USBP3_RN PD_UPC0_USBP3_RN BI 57
RF32B 1 2 100K PD_UPC1_USBP3_RN PD_UPC1_USBP3_RN BI 58
1/20W 5% MF 201 MAKE_BASE=TRUE 1/20W 5% MF 201 MAKE_BASE=TRUE
Connections for Laptops (USBC power in)

PACK_OPTION=USBC_LAPTOP
57 OUT PP3V3_UPC0_LDO MAKE_BASE=TRUE PP3V3_UPC0_LDO IN 55 57 89

SYNC_MASTER=REF_USBC_ACE2 SYNC_DATE=02/01/2020 A
5 BI USBC0_CC1 MAKE_BASE=TRUE USBC0_CC1 BI 57 59 89
PAGE TITLE

USB-C: Support 2 ATC01
58 OUT PP3V3_UPC1_LDO MAKE_BASE=TRUE PP3V3_UPC1_LDO IN 58
2 1
PPVBUS_USBC0 55 59 89
CF401 1
1UF
10%
35V 2
X5R
0402
PPHV_INT0_AONSW
PP3V3_S2_UPC 55 58 102
MAX 100uF TOTAL ON RAIL CF400 1

10UF
20%
104 58 PP5V_S2 6.3V 2
CERM
0402
104 58 PP5V_S2
CAP FOR PP_5V0 ON VR PAGE
PP1V25_S2 55 58 102
CF402 1 MIN_LINE_WIDTH=0.2800
1.0UF VOLTAGE=3.3V
353S02158 20%
6.3V 2
X5R PP3V3_UPC0_LDO 55 56 57 89
CRITICAL 0201-1
UF400 OMIT_TABLE 1 CF408
PP3V3_UPC0_LDO 55 56 57 89
B13 CD3217B12BCE C20 10UF
HRESET VIN_3V3
Internal Pull-ups FCBGA 20% PP1V8_S2 56 60 101
Enabled after reading straps 57 PD_UPC0_MRESET A14 MRESET A12 2 6 3V
CERM
VDDIO
1
1M 2 RF409 I2C_UPC0_ATCRTMR0_SCL 60 55 53 OUT ATCRTMR0_RESET_L B17 RESET*
VDDIO_CFG D11 GND
0402 1 CF403
5% /2 W MF 201 CKPLUS_WAIVE=I2C_PULLUP
53 55 5 60 55
0.1UF
55 OUT UPC0_SER_DBG A2 10%
1M RF408 C22 2 6.3V
1 2 I2C_UPC0_ATCRTMR0_SDA 53 55 57 60 B1 GPIO0
LDO_3V3 D21
CERM-X5R
0201
5% 1/20W MF 201 CKPLUS_WAIVE=I2C_PULLUP
10K RF407 55 OUT FLASH_BUSY_USBC01_L D1 GPIO1
1 2 INT_I2C_UPC0_ATCRTMR0_L 55 57 VIN_LV L20
5% 1/20W MF 201 57 55 IN INT_I2C_UPC0_ATCRTMR0_L F1 GPIO2
VOUT_LV L18 USBC0_3V3LDO_EN 96
55 OUT UPC0_5V_EN C2 GPIO3 (cap needed when used as power source)
55 53 OUT ATCRTMR0_FORCE_PWR E2 GPIO4 VRET C16
57 PD_UPC0_GPIO5 B3 GPIO5
1M SS L22 UPC0_SS
1 2 RF405 UART_UPC01_RX 55 57 61 58 6 IN UPC_FORCE_PWR C4 GPIO6 DIGITAL CORE I/O & CONTROL POWER
VOLTAGE=1.5V
5% 1/20W MF 201 UPC0_GPIO7 D3
107 96 56 GPIO7 MIN_LINE_WIDTH=0.2800
1
100K 2
RF406 PD_UPC0_MRESET
OUT
UPC_PMU_RESET_3V3 E4 GPIO8
LDO_CORE E22 PP1V5_UPC0_LDO_CORE MIN_NECK_WIDTH=0.0750 1 CF409
57 100 90 58 34 OUT 0.68UF
100K 2
5% 1/20W MF 201
56 IN SOC_DFU_STATUS F3 GPIO9 VBUS_OPT D5 PPVBUS_USBC0 55
1 CF405 5%
2 6.3V
1 RF402 PD_UPC0_GPIO5 57 56 OUT SOC_FORCE_DFU F7 GPIO10 10UF X6S
5% 1/20W MF 201 PP_HV_OPT F5 PPHV_INT0_AONSW 55
20% 0402
2 6.3V
56 PP3V3_UPC0_LDO A18 BUSPOWER CERM
0402
Either a Testpoint or Arkanoid connector GND I2C_ADDR 55 GND M19 I2C_ADDR IPU-BOOT MIN_LINE_WIDTH=0.4000
must be present for GPIO0 PRIMARY ONLY TYPE-C M15 USBC0_CC1 MIN_NECK_WIDTH=0 1500 BI 56 59 89
(EVEN IN PRODUCTION) UPC0_R_OSC M21 R_OSC C_CC1 N16
CRITICAL
RF403 1 60 57 55 53 BI I2C_UPC0_ATCRTMR0_SDA A16 I2CM_SDA_CNFG M17 USBC0_CC2 MIN_NECK_WIDTH=0.1500
BI 56 59 89
I2C_UPC0_ATCRTMR0_SCL
15K 60 57 55 53 B15 I2CM_SCL_CNFG
BI C_CC2 N18
0.1%
1/20W
TF-LF 55 41 BI I2C_UPC_SDA B5 I2C_SDA1
0201 2 RPD_G1 L14 USBC0_CC1 56
55 41 BI I2C_UPC_SCL A4 I2C_SCL1
RPD_G2 L16 USBC0_CC2
BI 1 CF414 1 CF413
107 55 OUT UPC_I2C_INT_L D7 I2C_IRQ1*
BI 56
220PF 220PF
10% 10%
C_USB_TP K19 USBC0_USB_TOP_P BI 59 2 25V 2 25V
55 43 BI I2C_SMC_UPC_SDA B7 I2C_SDA2 X7R-CERM X7R-CERM
C_USB_TN K21 USBC0_USB_TOP_N BI 59
201 201
55 43 BI I2C_SMC_UPC_SCL A6 I2C_SCL2 132S0212 132S0212
107 55 OUT UPC_SMC_I2C_INT_L C8 I2C_IRQ2* C_USB_BP J20 USBC0_USB_BOT_P BI 59
C_USB_BN J22 USBC0_USB_BOT_N BI 59

55 OUT SPI_UPC01_R_CLK B9 SPI_CLK
REAR PORT: 55 OUT SPI_UPC01_R_MOSI B11 SPI_MOSI C_SBU1 J16 USBC0_SBU1 BI 59 89
CONNECT UPC SPI TO ROM
FRONT PORT: 55 IN SPI_UPC01_R_MISO A10 SPI_MISO C_SBU2 H15 USBC0_SBU2 BI 59 89
GROUND UPC SPI
55 OUT SPI_UPC01_R_CS_L A8 SPI_SSZ
55 BI SWD_UPC_SWDIO0 E20 SWD_DATA IPU

55 BI SWD_UPC_SWCLK E16 SWD_CLK IPU
57 55 IN UART_UPC01_RX B19 UART_RX

55 OUT UART_UPC01_TX A20 UART_TX
GND_OPT C18
91 89 61 BI USB2_UPC0_P1_P H19 USB_RP1_P E18
GND_OPT
91 89 61 BI USB2_UPC0_P1_N H21 USB_RP1_N D17
GND_OPT
56 BI USB_DBG_LS_P G20 USB_RP2_P G18
PORT_MUX GND GND_OPT
56 BI USB_DBG_LS_N G22 USB_RP2_N
56 BI PD_UPC0_USBP3_RP F19 USB_RP3_P
56 BI PD_UPC0_USBP3_RN F21 USB_RP3_N
53 BI USBC0_AUXLSX_P J12 AUX_P

53 BI USBC0_AUXLSX_N H11 AUX_N
55 OUT ROM_UPC01_WP_L C12 HPD
96 56 BI UART_DEBUGPRT_R2D G12 DEBUG0

96 56 BI UART_DEBUGPRT_D2R F11 DEBUG1
96 56 BI SWD_SOC_SWCLK E8 DEBUG2
96 56 BI SWD_SOC_SWDIO E12 DEBUG3
96 56 OUT UART_SMC_DEBUGPRT_R2D G16 DEBUG4
96 56 BI UART_SMC_DEBUGPRT_D2R F15 DEBUG5
56 IN PD_UPC0_DBG6_R D15 DEBUG6
56 OUT PD_UPC0_DBG7_R D19 DEBUG7 GND
SYNC_MASTER=REF_USBC_ACE2
PAGE TITLE
USB-C: Port Controller ATC0
** OK2INTEGRATE **
CF501 1
1UF
10%
35V 2
X5R
0402
55 PPHV_INT1_AONSW
PP3V3_S2_UPC 55 57 102
MAX 100uF TOTAL ON RAIL CF500 1

10UF
20%
104 57 PP5V_S2 6.3V 2
CERM
0402
104 57 PP5V_S2
CAP FOR PP_5V0 ON VR PAGE
PP1V25_S2 55 57 102
CF502 1 MIN_LINE_WIDTH=0.2800
1.0UF VOLTAGE=3.3V
353S02158 20%
6.3V 2
X5R PP3V3_UPC1_LDO 56 58
CRITICAL 0201-1
UF500 OMIT_TABLE 1 CF508
PP3V3_UPC1_LDO 56 58
B13 CD3217B12BCE C20 10UF
HRESET VIN_3V3
FCBGA 20% PP1V8_S2 56 60 101
58 PD_UPC1_MRESET A14 MRESET A12 2 6 3V
CERM
VDDIO
1M RF509 60 54 ATCRTMR1_RESET_L B17 RESET* 0402
1 2 I2C_UPC1 ATCRTMR1_SCL
CKPLUS_ AI E I2C_PULLUP
54 55 58 6
OUT
VDDIO_CFG D11 GND 55
1 CF503
5% 1/2 W MF 201
55 OUT UPC1_SER_DBG A2 0.1UF
1M C22 10%
1 2 RF508 I2C_UPC1_ATCRTMR1_SDA 54 55 58 60 B1
LDO_3V3 D21 2 6.3V
CERM-X5R
5% 1/20W MF 201 CKPLUS_WAIVE=I2C_PULLUP 0201
10K RF507 55 OUT PD_UPC1_GPIO1 D1 GPIO1
1 2 INT_I2C_UPC1_ATCRTMR1_L 55 58 VIN_LV L20
5% 1/20W MF 201 58 55 IN INT_I2C_UPC1_ATCRTMR1_L F1 GPIO2
VOUT_LV L18 USBC1_3V3LDO_EN 107
55 OUT UPC1_5V_EN C2 GPIO3 (cap needed when used as power source)
55 54 OUT ATCRTMR1_FORCE_PWR E2 GPIO4 VRET C16
58 PD_UPC1_GPIO5 B3 GPIO5
1M SS L22 UPC1_SS
1 2 RF505 UART_UPC01_TX 55 58 61 57 6 IN UPC_FORCE_PWR C4 GPIO6 DIGITAL CORE I/O & CONTROL POWER
VOLTAGE=1.5V
5% 1/20W MF 201 PD_UPC1_GPIO7 D3
56 GPIO7 MIN_LINE_WIDTH=0.2800
1
100K 2
RF506 PD_UPC1_MRESET
OUT
UPC_PMU_RESET_3V3 E4 GPIO8
LDO_CORE E22 PP1V5_UPC1_LDO_CORE MIN_NECK_WIDTH=0 0750 1 CF509
58 100 90 57 34 OUT 0.68UF
100K 2
5% 1/20W MF 201
56 IN PD_UPC1_GPIO9 F3 GPIO9 VBUS_OPT D5 PPVBUS_USBC1 55
1 CF505 5%
2 6.3V
1 RF502 PD_UPC1_GPIO5 58 56 OUT PD_UPC1_GPIO10 F7 GPIO10 10UF X6S
5% 1/20W MF 201 PP_HV_OPT F5 PPHV_INT1_AONSW 55
20% 0402
2 6.3V
56 PP3V3_UPC1_LDO A18 BUSPOWER CERM
0402
Either a Testpoint or Arkanoid connector GND I2C_ADDR 55 NC_UPC1_I2C_ADDR M19 I2C_ADDR IPU-BOOT MIN_LINE_WIDTH=0.4000
must be present for GPIO0 PRIMARY ONLY TYPE-C M15 USBC1_CC1 MIN_NECK_WIDTH=0.1500 BI 56 59 89
(EVEN IN PRODUCTION) UPC1_R_OSC M21 R_OSC C_CC1 N16
CRITICAL
RF503 1 60 58 55 54 BI I2C_UPC1_ATCRTMR1_SDA A16 I2CM_SDA_CNFG M17 USBC1_CC2 MIN_NECK_WIDTH=0.1500
BI 56 59 89
15K 60 58 55 54 BI I2C_UPC1_ATCRTMR1_SCL B15 I2CM_SCL_CNFG C_CC2 N18
0.1%
1/20W
TF-LF 41 BI I2C_UPC_SDA B5 I2C_SDA1
0201 2 RPD_G1 L14 USBC1_CC1 56
41 BI I2C_UPC_SCL A4 I2C_SCL1
RPD_G2 L16 USBC1_CC2
BI 1 CF514 1 CF513
107 OUT UPC_I2C_INT_L D7 I2C_IRQ1*
BI 56
220PF 220PF
10% 10%
C_USB_TP K19 USBC1_USB_TOP_P BI 59 2 25V 2 25V
43 BI I2C_SMC_UPC_SDA B7 I2C_SDA2 X7R-CERM X7R-CERM
C_USB_TN K21 USBC1_USB_TOP_N BI 59
201 201
43 BI I2C_SMC_UPC_SCL A6 I2C_SCL2 132S0212 132S0212
107 OUT UPC_SMC_I2C_INT_L C8 I2C_IRQ2* C_USB_BP J20 USBC1_USB_BOT_P BI 59
C_USB_BN J22 USBC1_USB_BOT_N BI 59

55 OUT GND B9 SPI_CLK
REAR PORT: 55 OUT GND B11 SPI_MOSI C_SBU1 J16 USBC1_SBU1 BI 59 89
CONNECT UPC SPI TO ROM
FRONT PORT: 55 IN GND A10 SPI_MISO C_SBU2 H15 USBC1_SBU2 BI 59 89
GROUND UPC SPI
55 OUT GND A8 SPI_SSZ
55 BI SWD_UPC01_UART_DATA E20 SWD_DATA

55 BI SWD_UPC01_UART_CLK E16 SWD_CLK IPU
58 55 IN UART_UPC01_TX B19 UART_RX

55 OUT UART_UPC01_RX A20 UART_TX
GND_OPT C18
61 BI USB2_UPC1_P1_P H19 USB_RP1_P E18
GND_OPT
61 BI USB2_UPC1_P1_N H21 USB_RP1_N D17
GND_OPT
56 BI PD_UPC1_USBP2_RP G20 USB_RP2_P G18
PORT_MUX GND GND_OPT
56 BI PD_UPC1_USBP2_RN G22 USB_RP2_N
56 BI PD_UPC1_USBP3_RP F19 USB_RP3_P
56 BI PD_UPC1_USBP3_RN F21 USB_RP3_N
54 BI USBC1_AUXLSX_P J12 AUX_P

54 BI USBC1_AUXLSX_N H11 AUX_N
55 OUT PD_UPC1_HPD C12 HPD
56 BI PD_UPC1_DBG0_R G12 DEBUG0

56 BI PD_UPC1_DBG1_R F11 DEBUG1
56 BI PD_UPC1_DBG2_R E8 DEBUG2
56 BI PD_UPC1_DBG3_R E12 DEBUG3
56 OUT PD_UPC1_DBG4_R G16 DEBUG4
56 BI PD_UPC1_DBG5_R F15 DEBUG5
56 IN PD_UPC1_DBG6_R D15 DEBUG6
56 OUT PD_UPC1_DBG7_R D19 DEBUG7 GND
SYNC_MASTER=REF_USBC_ACE2 SYNC_DATE=02/01/2020
PAGE TITLE
USB-C: Port Controller ATC1
BOM COST GROUP=USB-C

2 1
---- Reference only ----
Left Rear Port FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK
PLACE VBUS CAP NEAR EACH VBUS PIN

BYPASS=JF600.57::10MM BYPASS=JF600.57::10MM
BYPASS=JF600.57::10MM BYPASS=JF600.5 ::10MM MIN_LINE_WIDTH=0.2000
CRITICAL CRITICAL CRITICAL CRITICAL PLACE_NEAR=JF600 58:5MM VOLTAGE=20V
K CRITICAL
1 CF620 1 CF621 1 CF622 1 CF623 DF622
0 01UF
10%
0.01UF
10%
0.01UF
10% 10%
0 01UF TVS2200 DF620
X3-WLB1608-1
WSON
2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM 4 IN SDM2U40CSP
0201 0201 0201 0201 A
5 IN
6 IN
516S00457
1 CF626 1 CF627 1 CF628 1 CF625
0.01UF 0.01UF 0.01UF 0.01UF
10% 10% 10% 10%
Mates with: 2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM
x on y 0 01 0201 0201 02 1 ALLOW_APPLE_PREFIX=D
(NO LANE REVERSALS ALLOWED)

89 57 56 USBC0_CC1 TP USBC0 PP20V 89
GND_VOID=TRUE GND_VOID=TRUE USBC0_CC2 56 57 89
USBC0_R2D_CR_N<1> RF661 1 2 2 USBC0_R2D_C_N<1> CF661 1 2 0.22UF USBC0_R2D_N<1> JF600

107 IN GND_VOID=TRUE GND_VOID=TRUE
5% 1/20W MF 201 20875-056E-01 0.22UF 1 CF691 RF691
X5R 10% 25V 0201 F-ST-SM USBC0_R2D_N<2> 2 USBC0_R2D_C_N<2> 2 1 2 USBC0_R2D_CR_N<2> IN 107
RF660 1 CF660 2 0.22UF
5% 1/20W MF 201
107 IN USBC0_R2D_CR_P<1> 2 2 USBC0_R2D_C_P<1> 1 USBC0_R2D_P<1> 57 PWR 58
X5R 10% 25V 0201
5% 1/20W MF 201
X5R 10% 25V 0201 USBC0_R2D_P<2> 0 22UF 1 2 CF690 USBC0_R2D_C_P<2> 2 1 2 RF690 USBC0_R2D_CR_P<2>
GND_VOID=TRUE GND_VOID=TRUE IN 107
5% 1/20W MF 201
X5R 10%
GND_VOID=TRUE
25V 0201 GND_VOID=TRUE
USBC0_D2R_N<1> RF663 1 2 2 USBC0_D2R_R_N<1> CF663 1 2 0.33UF USBC0_D2R_CR_N<1> SIGNAL

107 OUT 5% 1 20W MF 201 1 2 USBC0_USB_TOP_P 5
CER-X5R 10% 25V 0201
0.33UF 3 4 USBC0_USB_TOP_N
107 OUT USBC0_D2R_P<1> RF662 1 2 2 USBC0_D2R_R_P<1> CF662 1 2 USBC0_D2R_CR_P<1> 5 6
57
5% 1/20W MF 201
GND_VOID=TRUE
CER-X5R 10%
GND_VOID=TRUE
25V 0201 GND_VOID=TRUE GND_VOID=TRUE
7 8 0.33UF 1
89 57 USBC0_SBU2 GND_VOID=TRUE
9 10
USBC0_D2R_CR_N<2> 2 CF693 USBC0_D2R_R_N<2> 2 1 2 RF693 USBC0_D2R_N<2> OUT 107
GND_VOID=TRUE GND_VOID=TRUE 5% 1/20W MF 201
CER-X5R 10% 25V 0201
11 12 0.33UF 1
57 USBC0_USB_BOT_N 13 14
GND_VOID=TRUE
USBC0_D2R_CR_P<2> 2 CF692 USBC0_D2R_R_P<2> 2 1 2 RF692 USBC0_D2R_P<2> OUT 107
GND_VOID=TRUE 5% 1/20W MF 201
57 USBC0_USB_BOT_P 15 16
CER-X5R 10%
GND_VOID=TRUE
25V 0201 GND_VOID=TRUE
GND_VOID=TRUE
17 18
USBC0_SBU1 57 89
19 20
1 22 GND_VOID=TRUE
2 2 2 2 2 2 2 2 23 24 GND_VOID=TRUE
1 1 1 1
25 26 1 1 1 1 2 2 2 2 2 2 2 2
27 28
29 30
1 1 1 1 1 1 1 1 2 2 2 2 31 32
2 2 2 2 1 1 1 1 1 1 1 1
33 34 GND_VOID=TRUE
35 36 GND_VOID=TRUE
37 38
USBC1_USB_BOT_N
GND_VOID=TRUE
39
1
40
42
USBC1_SBU2 58 89
58 GND_VOID=TRUE GND_VOID=TRUE
43 44 0.22UF 1
58 USBC1_USB_BOT_P GND_VOID=TRUE
45 46
USBC1_R2D_P<1> 2 CF670 USBC1_R2D_C_P<1> 21 2 RF670 USBC1_R2D_CR_P<1> IN 107
X5R 10% 25V 0201
47 48 0.22UF 1
89 58 USBC1_SBU1 GND_VOID=TRUE
49 50
GND_VOID=TRUE
USBC1_R2D_N<1> 2 CF671 USBC1_R2D_C_N<1> 2 1 2 RF671 USBC1_R2D_CR_N<1> IN 107
X5R 10% 25V
GND_VOID=TRUE
0201 GND_VOID=TRUE
0.22UF 51 52
107 IN USBC1_R2D_CR_P<2> RF680 1 2 2 USBC1_R2D_C_P<2> CF680 1 2 USBC1_R2D_P<2> 53 54
5% 1/20W MF 201
X5R 10% 25V 201
USBC1_USB_TOP_P 58
55 56 USBC1_USB_TOP_N
107 USBC1_R2D_CR_N<2> RF681 1 2 2 USBC1_R2D_C_N<2> CF681 1 2 0.22UF USBC1_R2D_N<2> 58
IN 5% 1/20W MF 201
GND_VOID=TRUE
X5R 10%
GND_VOID=TRUE
25V 0201 GND_VOID=TRUE GND_VOID=TRUE
PWR 0 33UF 1
59 60 USBC1_D2R_CR_P<1> 2 CF672 USBC1_D2R_R_P<1> 21 2 RF672 USBC1_D2R_P<1> UT 107
RF682 1 CF682 2 0.33UF
5% 1 20 MF 201
107 OUT USBC1_D2R_P<2> 2 2 USBC1_D2R_R_P<2> 1 USBC1_D2R_CR_P<2> CER-X5R 1 % 25V 0201
5% 1/20W MF 201
CER-X5R 10% 25V 0201 GND USBC1_D2R_CR_N<1> 0.33UF 1 2 CF673 USBC1_D2R_R_N<1> 2 1 2 RF673 USBC1_D2R_N<1> OUT 107
61 62
RF683 1 CF683 2 0.33UF
5% 1/20W MF 201
107 OUT USBC1_D2R_N<2> 2 2 USBC1_D2R_R_N<2> 1 USBC1_D2R_CR_N<2> 63 64
CER-X5R 10% 25V
GND_VOID=TRUE
0201 GND_VOID=TRUE
5% 1/20W MF 201
GND_VOID=TRUE
CER-X5R 10%
GND_VOID=TRUE
25V 0201
65 66
USBC1_CC1 56 58 89
89 58 56 USBC1_CC2 67 68
TP_USBC1_PP20V 89
69 70
71 72
73 74 1 1 1 1 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 75 76
1 1 1 1
77 78
79 80
2 2 2 2 1 1 1 1 1 1 1 1
81 82
1 1 1 1 1 1 1 1 2 2 2 2 83 84
85 86
FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK
PLACE VBUS CAP NEAR EACH VBUS PIN

89 58 55 PPVBUS_USBC1 BYPASS=JF600 59: 0MM BYPASS=JF 0 59::10MM
MIN_LINE_WIDTH=0.2000 BYPASS=JF600.59::10MM BYP SS=JF600.59::10MM
VOLTAGE=20V PLACE_NEAR=JF600.59:5MM CRITICAL CRITICAL CRITICAL CRITICAL
CRITICAL K
DF602 1 CF600 1 CF601 1 CF602 1 CF603
DF600
X3-WLB1608-1
TVS2200
10%
0.01UF 0.01UF
10%
0.01UF
10%
0.01UF
10%
WSON
SDM2U40CSP 4 IN 2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM
A 0201 0201 0201 0201
5 IN
6 IN
BYPASS JF600.5 : 10MM BYPASS=JF600.59::10MM

BYPASS=JF600.59::10MM BYPASS=JF600.59::10MM SYNC_MASTER=KEI_T668_MLB SYNC_DATE=02/01/2020
CRITICAL CRITICAL CRITICAL CRITICAL PAGE TITLE
1 CF606 1 CF607 1 CF608 1 CF605 USB-C: Connector(s)
0.01UF 0.01UF 0.01UF 0.01UF
10% 10% 10% 10%
2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM
ALLOW_APPLE_PREFIX=D 0201 0201 0201 0201
Left Front Port

3 2
** OK2INTEGRATE **
PP3V3_S2SW_USBLS1_ISNS
105 PP1V8_S2_USBLS1_ISNS 56 60 105
104 PP3V3_S2SW_USB0 PP1V8_S2 56 60 101

1 CF750 1 CF751 1 CF752 1 CF753
0.1UF 0.1UF 0.1UF 0.1UF
1 CF700 1 CF701 1 CF702 1 CF703 10%
2 10V
10%
2 10V
10%
2 10V
10%
2 10V
0.1UF 0.1UF 0.1UF 0.1UF X5R-CERM
0201
X5R-CERM
0201
X5R-CERM
0201
X5R-CERM
0201
10% 10% 10% 10%
2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM
0201 0201 0201 0201 VDD3V3 VDD1V8
VDD3V3 VDD1V8 OMIT_TABLE

OMIT_TABLE 6 INT_I2C_EUSBLS1_1V8_L A4 INT UF750
CD2E22
60 INT_I2C_EUSBLS0_1V8_L A4 INT UF700 DSBGA
CD2E22
DSBGA 60 I2C_UPC1_ATCRTMR1_SCL_1V8 A3 SCL G IO0 E2
NC
60 I2C_UPC0_ATCRTMR0_SCL_1V8 A3 SCL GPIO0 E2
NC 60 I2C_UPC1_ATCRTMR1_SDA_1V8 A2 SDA GPIO1 E3
NC
60 I2C_UPC0_ATCRTMR0_SDA_1V8 A2 SDA GPIO1 E3
NC
18 BI EUSB_ATC1_R_P A1 EDP0 DPA A5 USB2_ATC1_LS_P BI 1 7
18 I EUSB_ATC1_R_N B1 EDN0 DNA B5 USB2_ATC1_LS_N BI 107

18 BI EUSB_ATC0_R_P A1 EDP0 DPA A5 USB2_ATC0_LS_MUX_P BI 96 107
18 BI EUSB_ATC0_R_N B1 EDN0 DNA B5 USB2_ATC0_LS_MUX_N BI 96 107
CROSS C2
CROSS C2
PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0
107 TP_EUSB_LS1POS E1 EDP1 DPB E5 NC_USB_LS1POS 107
18 9 BI EUSB_DBG_P USB_DBG_LS_MUX_PBI 96 107 107 TP_EUSB_LS1NEG D1 EDN1 DNB D5 NC_USB_LS1NEG 107

MAKE_BASE=TRUE EUSB_DBG_P E1 EDP1 DPB E5 USB_DBG_LS_MUX_P
18 9 BI EUSB_DBG_N EUSB_DBG_N D1 EDN1 DNB D5 USB_DBG_LS_MUX_N USB_DBG_LS_MUX_NBI 96 107
MAKE_BASE=TRUE 60 ATCRTMR1_RESET_1V8_L E4 RESET*
107 96 ATCRTMR0_RESET_MUX_1V8_L E4 RESET*

105 60 56 PP1V8_S2_USBLS1_ISNS C3 VIOSEL VPP/VSS C4
High:Select 1,8V I2C, GPIOs. VSS
101 60 56 PP1V8_S2 C3 VIOSEL VPP/VSS C4
High:Select 1,8V I C, GPIOs. VSS
TBT LS RX/TX LEVEL SHIFTERS
SOC BBR Retimer PARROT 1 I2C/RESET LEVEL SHIFTERS

PARROT 0 I2C/RESET LEVEL SHIFTERS
RF753 Pull-ups on high-side
RF703 Pull ups on high-side
PP1V25_S2 PP3V3_S2SW_USB0 PP3V3_S2SW_USB1 MF 2
200K 1
do most of the work.
102 60 60 104 104 60
PP3V3_S2SW_USB0 MF 2
200K 1
do most of the work.
1/20 % 01 PP1V8_S2
104 60 56 58 60 101
1/20W 5% 201 PP1V8_S2 56 57 60 101 CF730 1 1 CF731 VREFB_EUSBLS1

0.1UF UF730 0.1UF
VREFB_EUSBLS0 10%
6.3V 2 SN74AXC1T45
10% CF760 RF763 1 1
RF762 1 CF761
CF710 2 6.3V 0.1UF 0.1UF
0.1UF RF713 1 1
RF712 1 CF711 CERM-X5R
0201 SOT-5X3 CERM-X5R
0201 2 1 5.1K
5% 5%
5.1K 10%
5.1K 5.1K 0.1UF 1/20W 1/20W 2 6.3V
2 1 5% 5% 10% VCCA VCCB VREF_B VREF_A MF MF CERM-X5R
1/20W 1/20W 2 6.3V
CERM-X5R
10%
6.3V 201 2 2 201
0201
VREF_B VREF_A MF MF 5 DIR
10%
6.3V 01 2 2 201
0201 CERM-X5R
0201 8 EN
UF760
CERM-X5R UF710 5 IN CIO_ATC0_LSTX_1V2 3 A B 4 CIO_ATC0_LSTX_3V3 OUT 53
LSF0102
0201 8 EN X2SON-COMBO
LSF0102 I2C_UPC1_ATCRTMR1_SDA 3 I2C_UPC1_ATCRTMR1_SDA_1V8
58 55 54 6 B1 A1 60
1 BI
I2C_UPC0_ATCRTMR0_SDA 6 X2SON-COMBO 3 I2C_UPC0_ATCRTMR0_SDA_1V8 RF730 GND 311S00234
57 55 53 BI B1 A1
3 1S00234 47K 5 BI I2C_UPC1_ATCRTMR1_SCL B2 A 4 I2C_UPC1_ATCRTMR1_SCL_1V8 60
5%
57 55 53 BI I2C_UPC0_ATCRTMR0_SCL 5 B2 A2 4 I2C_UPC0_ATCRTMR0_SCL_1V8 1/20W GND
MF
GND 201 2
102 60 PP1V25_S2
1 CF735
0.1UF
10%
2 6.3V
CERM X5R
UF735 02 1
SN74AUP1G17
SON VCC
5 OUT CIO_ATC0_LSRX_1V2 4 2 CIO_ATC0_LSRX_3V3 IN 53

NC
NOSTUFF NC
GND
RF7351
47K
5%
1/20W
MF
201 2
PP1V8_S2 56 58 60 101
PP1V8_S2 CF770 1
56 57 60 101
0.1UF 1
RF770
102 60 PP1V25_S2 PP3V3_S2SW_USB1 60 104
10%
CF720 1 6.3V
CERM-X5R 2 VCC
5%
1.5K
0.1UF 1
RF720 0201
UF770 1/20W
10%
6.3V 1.5K CF740 1 1 CF741 74AUP1G07GF MF
CERM-X5R 2 VCC
5% 0.1UF UF740 0.1UF SOT891 2 201
0201 10% 10%
UF720 1/20W
MF 6.3V 2 SN74AXC1T45 2 6.3V 55 INT_I2C_EUSBLS1_L 4 Y A 2 INT_I2C_EUSBLS1_1V8_L 60
74AUP1G07GF 2 201
CERM-X5R
0201 SOT-5X3 CERM-X5R
0201
OUT
SOT891
NC 5 NC NC 1 NC
55 OUT INT_I2C_EUSBLS0_L 4 Y A 2 INT_I2C_EUSBLS0_1V8_L 60
VCCA VCCB
5 DIR GND
NC 5 NC NC 1 NC 101 60 58 56 PP1V8_S2
G D 5 IN CIO_ATC1_LSTX_1V2 3 A B 4 CIO_ATC1_LSTX_3V3 OU 54
CF765 1
RF7401 GND 0.1UF
10%
47K 6.3V 2
5% CERM-X5R
1/20W
MF 0201 UF775
201 2
VCC
SN74AUP1G17
SON
58 54 IN ATCRTMR1_RESET_L 2 4 ATCRTMR1_RESET_1V8_L 60
PP1V8_S2 56 57 60 101
NC
NC
GND
102 60 PP1V25_S2
CF725 1
0.1UF NC
10%
6.3V 2
1 CF745 NC YNC_MAS ER=R F_U BC_ CE2
PAGE TITLE
SY C_DA E=0 /04 2020
CERM-X5R 0 1UF
0201 UF725
SN74AUP1G17
10%
2 6.3V
CERM-X5R
USB-C: HS Level Shifters
VCC SON UF745 0201
57 55 53 IN ATCRTMR0_RESET_L 2 4 ATCRTMR0_RESET_1V8_L 96 SN74AUP1G17
NC SON VCC
NC
GND 5 OUT CIO_ATC1_LSRX_1V2 4 2 CIO_ATC1_LSRX_3V3 IN 54
NC
NOSTUFF NC
GND
NC
NC RF7451
47K
5%
1/20W
MF
201 2
3 2 1
LF800
90-OHM-0.1A
EXCX4CE
SYM_VER-1
96 BI USB2_ATC0_LS_N 1 4 USB2_UPC0_P1_N BI 57 89 91
96 BI USB2_ATC0_LS_P 2 3 USB2_UPC0_P1_P BI 57 89 91
PLACE_NEAR=UF400:5MM
155S0667
LF810
90-OHM-0.1A
EXCX4CE
SYM_VER-1
107 BI USB2_ATC1_LS_P 1 4 USB2_UPC1_P1_P BI 58
107 BI USB2_ATC1_LS_N 2 3 USB2_UPC1_P1_N BI 58
PLACE_NEAR UF500:5MM
155S0667
NOTE: CHOKE PINOUT IS DIFFERENT BETWEEN LANE 0 AND LANE 1 FOR EASE OF ROUTING
<RDAR://59047957>
58 57 6 UPC_FORCE_PWR
1
RF850
47K
5%
/20W
MF
2 201
PAGE TITLE
USB-C: SUPPORT
RASPUTIN WIFI/BT MODULE
105 PP1V8_S2_WLBT_ISNS PP3V3_S2_WLBT_ISNS 62 105

FOR HOSTINTERFACE TABLES REFER TO 1 CL021 1 CL022 1
CL023 1 CL031 1 CL032 1 CL033
TP 1 PMU_CLK32K_WLBT
RDAR://PROBLEM/53187294 10UF
20%
3.0PF
+/-0.1PF
12PF
5%
3.0PF
/-0.1PF
12PF
5%
10UF
20%
TPL001 TP-P55
3 62 63
2 10V 2 25V 2 25V 2 25V 2 25V 2 10V

X5R-CERM NP0-C0G NP0-C0G NP0-C0G NP0-C0G X5R-CERM 1 WLBT_PWR_EN 33 62 63 94
0402-8 0201 0201 0201 0201 0402-8 TPL002 TP
TP-P55
TP 1 WLBT_WAKE 33 62 63
105 62 PP3V3_S2_WLBT_ISNS TPL003 TP-P55

CRITICAL CRITICAL
1 CL002 1 CL003 1 CL004 CRITICAL CRITICAL TPL004 TP 1 TP_WLAN_JTAG_TCK 62
10UF 3.0PF 12PF TP-P55

20%
2 10V 2
+/-0.1PF 5%
2 25V
1 CL041 1 CL042 1 CL043 TP_WLAN_JTAG_TMS
X5R-CERM
25V
NP0-C0G NP0-C0G 3.0PF 12PF 10UF TPL005 TP 1 62
0402-8 0201 0201 +/-0.1PF 5% 20% TP-P55

2 25V 2 25V 2 10V
NP0-C0G NP0-C0G X5R-CERM TP 1 TP_WLAN_JTAG_TDI 62 63
0201 0201 0402-8 TPL006 TP-P55
TP 1 TP_WLAN_JTAG_TDO 62 63
TPL007 TP 55
CRITICAL CRITICAL CRITICAL CRITICAL TP 1 TP_WLAN_JTAG_TRSTN 62
1 CL012 1 CL013 1 CL014 1 CL051 1 CL052 1 CL053 TPL008 TP-P55

10UF 3.0PF 12PF 3.0PF 12PF 10UF WLAN_JTAG_SEL
20%
2 10V
+/-0.1PF
2 25V
5%
2 25V 2
+/-0.1PF
25V
5%
2 25V 2
20%
10V TPL009 TP 1 62
X5R-CERM NP0-C0G NP0-C0G NP0-C0G NP0-C0G X5R-CERM TP-P55

0402-8 0201 0201 0201 0201 0402-8
PP1V25_S2 62 102
CRITICAL CRITICAL
1 CL061 CL062 BT_TIME_SYNC_1V8
12PF 3.0PF TPL012 TP 1 6 62 63
OMIT_TABLE 5% +/-0.1PF TP-P55

2 25V 2 25V
UL000 VDDIO_ZONE2 85 NP0-C0G NP0-C0G
BT_R1_WAKE
LBEE5XV1YR-506
0201 0201
TPL013 TP 1 PACK_IGNORE=TRUE 62
LGA TP-P55 PACK_OPTION=CARLSBERG

SYM 1 OF 4
63 RF_ANT_0 27 ANT_C0 GPIO HW SETTINGS: 1.8V|HZ|PD WLBT_HOST_WAKE 145 WLBT_WAKE 33 62 63 BT_R1_TIME_SYNC
TP 1 PACK_IGNORE= 63
63
BI
RF_ANT_1 89 ANT_C1 VDDIO|RESET|POST-RESET
OUT
TPL014 RUE
TP-P55 PACK_OPTION=CARLSBERG
BI
1.8V|HZ|PU WL_GPIO_2 149 TP_WLAN_JTAG_TCK 62
63 BI RF_BT_DED 44 BT_DEDICATED
1.8V|HZ|PU WL_GPIO_3 65 TP_WLAN_JTAG_TMS 62
1.8V|HZ|PU WL_GPIO_4 64 TP_WLAN_JTAG_TDI 62 63
133 1.8V|HZ|NP WL_GPIO_5 61 TP_WLAN_JTAG_TDO 62 63

NC BT_GPIO_1 1.8V|HZ|NP
124 1.8V|HZ|PU WL_GPIO_6 62 TP_WLAN_JTAG_TRSTN 62
NC BT_GPIO_2 1.8V|HZ|PD 134
37 1.8V|HZ|PD WL_GPIO_7 NC
63 62 6 BT_TIME_SYNC_1V8 BT_GPIO_3 1.8V|HZ|PD TP 1 UART_WLAN_R2D 6 62
OUT
62 BT_R1_WAKE 123 BT_GPIO_4 1.8V|HZ|PU
1.2V|HZ|HZ WL_GPIO_8 66 UART_WLAN_R2D IN 6 62 TPL017 TP-P55
1.2V|PU|PU WL_GPIO_9 150 UART_WLAN_D2R OUT 6 62
63 62 BT_R1_TIME_SYNC 36 BT_GPIO_5 1.8V|HZ|PU
1.2V|HZ|HZ WL_GPIO_10 67 UART_WLAN_R2D_RTS_L 6 62 TP 1 UART_WLAN_D2R 62
1.2V|PU|PU WL_GPIO_11 151 UART_WLAN_D2R_CTS_L

IN
6 62
TPL018 TP-P55
OUT
NC
38
125
BT_I2S_DI www.teknisi-indonesia.com
1.8V|HZ|HZ
1.2V|HZ|HZ
WL_GPIO_12
WL_GPIO_13
525
161
WLAN_TIME_SYNC_1V8
WLAN_CONTEXT_A
OUT
IN
62 63
9 62 63 TPL019 TP 1 UART_WLAN_R2D_RTS_L 6 62
NC BT_I2S_DO TP P55
39 1.2V|PU|PU WL_GPIO_14 78 WLAN_CONTEXT_B IN 9 62 63
NC BT_I2S_CLK
1.8V|HZ|HZ WL_GPIO_15 504
NC TP 1 UART_WLAN_D2R_CTS_L 6 62
NC
126 BT_I2S_WS
1.8V|HZ|HZ WL_GPIO_16 160 TPL020 TP-P55
NC
1.8V|HZ|HZ WL_GPIO_17 77
NC WLAN_TIME_SYNC_1V8
1.8V|HZ|HZ WL_GPIO_18 524 TPL021 TP 1 62 63
507 RF_SW_CTRL_18 NC TP-P55
NC 1.8V|HZ|HZ WL_GPIO_19 503
528 RF_SW_CTRL_19 NC
NC 1.2V|HZ|HZ WL_GPIO_20 68 WLAN_CONTEXT_A
NC TPL022 TP 1 62 63
TP-P55
PCI_PME_L 60
SPMI_WLBT_CLK_1V8 517 LHL_GPIO0 NC WLAN_CONTEXT_B
62
TPL023 TP 1 9 62 63
62 SPMI_WLBT_DAT_1V8 518 LHL_GPIO1 1.2V PCIE_PERST_L 127 WLBT_RESET_L 8 62 63 TP P55

IN
48 LHL_GPIO2 1.2V PCIE_CLKREQ_L 40 WLBT_CLKREQ_R_L
NC 62
SPMI WLBT CLK 1V8
TPL024 TP 1 PACK_IGNORE=TRUE 62
PCIE_RXD_P 142 PCIE_WLBT_R2D_P 62 TP-P55 PACK_OPTION=CARLSBERG

PCIE_RXD_N 143 PCIE_WLBT_R2D_N 62
94 63 62 33 WLBT_PWR_EN 76 WLBT_REG_ON SPMI WLBT DAT 1V8
TP 1 PACK_IGNORE=TRUE 62
IN
PCIE_TXD_P 139 PCIE_WLBT_D2R_C_P 62
TPL025 TP-P55 PACK_OPTION=CARLSBERG
63 62 33 IN PMU_CLK32K_WLBT 153 CLK_32K
PCIE_TXD_N 140 PCIE_WLBT_D2R_C_N 62
PCIE_REFCLK_P 136 PCIE_CLK100M_WLBT_P IN 8 62
PCIE_REFCLK_N 137 PCIE_CLK100M_WLBT_N IN 8 62
102 62 PP1V25_S2
1 CL071
0.1UF
10%
2 6.3V
CERM-X5R PPL030
P4MM
SM
1 PCIE_CLK100M_WLBT_P 62
0201 PP
UL001 PPL031
P4MM
SM
1 PCIE_CLK100M_WLBT_N 8 62
P
SN74AUP1G17
V C SON
63 62 WLAN_TIME_SYNC_1V8 2 4 WLAN_TIME_SYNC OUT
NC
TP 1 WLBT_RESET_L 8 62 63
RL005 1 10K 2 WLAN_JTAG_SEL 62 GND
NC TPL032 TP-P55
1/20W MF 201
5%
RASPUTIN BOM TABLE: T BLE_5_HE D
RL003 1
MF 1/20W
10K 2
201
WLBT_PACKAGE_OPTION_2
RL006
MF
1
1/20W
100K 2
5%
201
TPL033 TP 1
TP-P55
WLBT_CLKREQ_L 8 62 63
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 5% NOSTUFF

T BLE_5_IT M
339S00763 1 MODULE, WLAN BT, RASPUTIN, ES6.11, M, LGA549 UL000 CRITICAL

SYNC_MASTER=REF_WI ELESS_R IN SYNC_DATE=02/01/2020
PAGE TITLE
62 WLBT_CLKREQ_R_L
RL002
1
1K 2
201
WLBT_CLKREQ_L BI 8 62 63
WIFI/BT: MODULE DRAWING NUMBER SIZE
1/20W 5% MF
GND_VOID=TRUE
PLACE_NEAR=UL000.142:4MM GND_VOID=TRUE PLACE_NEAR=U0600.BE30:10MM
CL010 CL008
8 IN PCIE_WLBT_R2D_C_P 0 1UF 1 2 CERM-X5R PCIE_WLBT_R2D_P 62 62 PCIE_WLBT_D2R_C_P 0 1UF 1 2 CERM-X5R PCIE_WLBT_D2R_P OUT 8
6.3V 10% 0201 6.3V 10% 0201
CL009 CL007
8 IN PCIE_WLBT_R2D_C_N 0 1UF 1 2 CERM-X5R PCIE_WLBT_R2D_N 62 62 PCIE_WLBT_D2R_C_N 0 1UF 1 2 CERM-X5R PCIE_WLBT_D2R_N O T 8
6.3V 10% 0201 6.3V 10% 0201 PLACE_NEAR=U0600.BF30:10MM
PLACE_NEAR=UL000.143:4MM
BOM_COST_GROUP=WIRELESS
4 3
RASPUTIN WIFI/BT MODULE GND

OMIT_TABLE OMIT_TABLE OMIT_TABLE ANTENNA CONNECTORS
UL000 UL000 UL000
1 LBEE5XV1YR-506 119 222 LBEE5XV1YR-506 303 384 LBEE5XV1YR-506 463
JL100
LGA LGA LGA
IR050D15010C
2 120 223 304 385 464 F-ST-SM
6 SYM 2 OF 4 121 224 SYM 3 OF 4 305 386 SYM 4 OF 4 465 1 RF_ANT_0 BI 62 63
7 122 225 306 387 46
8 128 226 307 388 467 PACK_IGNORE=TRUE
PACK_OPTION=SUNWAY
9 129 227 308 389 468
10
15
130
131
228
229
309
310
390
391
469
470 2G_C1
16
17
132
135
230
231
311
312
392
393
471
472 5G_C0 RF_CONN
18
19
138
141
232
233
313
314
394
395
473
474 BT_C0 JL110
20449-001E-03
JL120
20431-001E-01
F-ST-SM
20 144 234 315 396 475 F-ST SM
24 146 235 316 397 47 SIGNAL
1 RF_ANT_0 62 63 1 RF_ANT_0 62 63
25 147 236 317 398 477 GND
26 148 237 318 399 478 PACK_OPTION=IPEX PACK_IGNORE=TRUE

28 154 238 319 400 479 518S0867 PACK_OPTION=ANT_MAC_MINI
29 158 239 320 401 480
30 162 240 321 402 481
33 163 241 322 403 482
34 164 242 323 404 483
35 165 243 324 405 484
41 166 244 325 406 485 JL101
43 167 245 326 407 48 IR050D15010C
F-ST-S
45 168 246 327 408 487
46 169 247 328 409 488
1 RF_ANT_1 BI 62 63
47 170 248 329 410 489 PACK_IGNORE=TRUE

50 171 249 330 411 490 PACK_OPTION=SUNWAY
51 172 250 331 412 491
52 173 251 332 413 492
53
54
174
175
252
253
333
334
414
415
493
494 2G_C0
55
56
176
177
254
255
335
336
416
417
495
49 5G_C1 RF_CONN
JL111 JL121
20431-001E-01
20449-001E-03
57
58 GND GND
178
179
256
257 GND GND
337
338
418
419 GND GND
497
498 BT_C1 F-ST-SM
1 RF_ANT_1 62 63 2
F-ST-SM
SIGNAL
1 RF_ANT_1 62 63
59 180 258 339 420 499 GND
69 181 259 340 421 500
70 182 260 341 422 501 PACK_OPTION=IPEX PACK_IGNORE=TRUE
518S0867 PACK_OPTION=ANT_MAC_MINI
71 183 261 342 423 502
75 184 262 343 424 505
79 185 263 344 425 506
80
81
186
187
264
265
345
346
426
427 www.teknisi-indonesia.com
508
50
84 188 266 347 428 510
189 267 348 429 511
86 190 268 349 430 512
87 191 269 350 431 513 PACK_IGNORE=TRUE
PACK_OPTION=3X_ANTENNA
88 192 270 351 432 514 PACK_IGNORE=TRUE
90 193 271 352 433 515
JL102 PACK_OPTION=3X_ANTENNA UL101 PACK_IGNORE=TRUE
IR050D15010C 2.4G
PACK OPTION=3X_ANTENNA
91 194 272 353 434 516 F-ST-SM
0603
0 0
92 195 273 354 435 519 1 63 RF_BT_DED_ANT RL102 1
1/20W MF
2 5%
201
RF_BT_DED_FOUT 1 IN OUT 3 RF_BT_DED_FIN RL104 1
1/20W MF
25%
0201
RF_BT_DED BI 62
93 196 274 355 436 520 GND
94 197 275 356 437 52 PACK_IGNORE=TRUE 2 4
PACK_OPTION=ANT_T664
95 198 276 357 438 522
96 199 277 358 439 523 1 CL101 1 CL102
1 CL103 1 CL105
0.3PF 0.3PF
97 200 278 359 440 526 0.3PF 0.3PF +/-0.1PF +/-0.1PF
98 201 279 360 441 527
+/-0.1PF +/-0.1PF 2 25V 2 25V
2 25V
C0G-CERM 2 25V
C0G-CERM
C0G-CERM
201
C0G-CERM
201
99
100
202
203
280
281
361
362
442
443
529
530 BT_C0_DED PACK_IGNORE=TRUE
201
NOSTUFF
201
NOSTUFF
PACK_IGNORE=TRUE
NOSTUFF NOSTUFF
101 204 282 363 444 531 PACK_OPTION=3X_ANTENNA PACK_OPTION=3X_ANTENNA PACK_IGNORE=TRUE PACK_IGNORE=TRUE
102 205 283 364 445 532 PACK_OPTION=3X_ANTENNA PACK_OPTION=3X_ANTENNA
JL122
103 206 284 365 446 533 20431-001E-01
104 207 285 366 447 53 F-ST SM
105 208 286 367 448 535 SIGNAL

2 1 RF_BT_DED_ANT 63
106 209 287 368 449 536 GND
107 210 288 369 450 537 PACK_IGNORE=TRUE

108 211 289 370 451 538 PACK_OPTION=ANT_MAC_MINI
109 212 290 371 452 539
110 213 291 372 453 540
111 214 292 373 454 541
112 215 293 374 455 542
113 216 294 375 456 543
114
115
116
117
118
217
218
219
220
221
295
296
297
298
299
376
377
378
379
380
457
458
459
460
461
54
545
546
547
548
WLBT DEBUG CONNECTOR
300 381 462 549
JL103
505070-1222
301 382 M-ST-SM
14 13
302 383
62 WLAN_TIME_SYNC_1V8 2 1 TP_WLAN_JTAG_TDI 62
62 9 WLAN_CONTEXT_A 4 3 TP_WLAN_JTAG_TDO 62
S NC_MASTER=REF_WIRELESS_ ASPUTIN
PAGE TITLE
SY C_DA E=0 /01 2020
62 9
62 33
WLAN_CONTEXT_B
WLBT_WAKE
6
8
5
7
BT_R1_TIME_SYNC
WLBT_CLKREQ_L
62
8 62
WIFI/BT: ANTENNA and GND
94 62 33 WLBT_PWR_EN 10 9 BT_TIME_SYNC_1V8 6 62
62 8 WLBT_RESET_L 12 11 PMU_CLK32K_WLBT 33 62
16 15
BOMOPTION=WLBT_DBG
PACK_OPTION=WLBT_DBG_CONN
BOM_COST_GROUP=WIRELESS
2 1
*** OK2INTEGRATE *** NAND0 S5E0
PP1V25_AWAKESW_VCCQ 64 102
CN030
PP0V88_AWAKESW_NAND 4.3UF
102 64 20%
1 CN032 4V
CERM
1 CN034 1 CN035 1 CN036 1 CN037 1 CN038 1 CN039 1 CN03A
1 CN012 1 CN013 1 CN014 1 CN015 1 CN016 1 CN017 20UF 0402 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
1 CN010 1 CN011 2.2UF 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF
20%
2 10V 1 3
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20UF 20UF 20% 20% 20% 10% 10% 10% X5R X5R X5R X5R X5R X5R X5R X5R
20% 20% 2 10V 2 10V 2 10V 2 6.3V 2 6.3V 2 6.3V 0402 0201 0201 0201 0201 0201 0201 0201
2 10V
X5R 2 10V
X5R
X5R
0201
X5R
0201
X5R
0201
CERM-X5R
0201
CERM-X5R
0201
CERM-X5R
0201 2 4
0402 0402
67 TP_NAND0_S5E0_ANI1_VREF
PP2V5_AWAKE_NAND 65 66 101
67 TP_NAND0_S5E0_ANI0_VREF 1 CN020 1 CN022 1 CN023 1 CN024 1 CN025

20UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20%
MIN_LINE_WIDTH=0.1000 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
RN010 MIN_NECK_WIDTH=0.1000
VOLTAGE=1.2V 0402 0201 0201 0201 0201
PP1V25_AWAKESW_VCCQ 1
2 2 PP1V2_NAND0_S5E0_AVDD1X_PLL
102 65
1%
1/20W
MF
1 CN047 1 CN046
0201 2.2UF 0.1UF
PLACE NEAR=UN000.L2:10MM 20% 10%
2 10V
X5R 2 6.3V
CERM-X5R MIN_LINE_WIDTH=0.1000
FLN001
0201 0201 VOLTAGE=0.9V
10OHM-50%-1A-0.05OHM
107 PP0V9_S5E0_VDD_PLL 1 2 PP0V88_AWAKESW_NAND 64 102
FLN000 MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000 TP_NAND0_S5E0_VPP
0201
PLACE_NEAR=UN000.R4:10MM
PLACE_NEAR=FLN001.2:5MM
10OHM-50%-1A-0.05OHM VOLTAGE=1.2V 1 CN083
1 2 PP1V2_NAND0_S5E0_PCI_AVDD_H 4.7UF
20%
0201 2 4V
PLACE_NEAR=UN000.J6:10MM 1 CN045 1 CN044 CER-X5R
0201
4.7UF 0 1UF
20% 10%
2 4V
CER-X5R 2 6 3V
CERM-X5R
The inductance from CN047, CN046, CN045, CN044 to 0201 0201
their S5E pins shall be less than 1100pH
1 67 IN NAND0_CLK24M_0 M3 CLK_IN OMIT_TABLE EXT_D0/BOOT0 B3 NAND0_LPB_L IN 33 65 67

1 CN085 RN004 EXT_D1/BOOT1 C4 NAND_BFH N 6 65 67
10PF 2 0
0.1%
67 8 N PCIE_CLK100M_NAND0_0_P K11 PCIE_REFCLK_P UN000 EXT_D2/BOOT2/SPINAND_SCLK B5 NAND0_BOOT2 64 65 67
5% 1/20W 67 8 IN PCIE_CLK100M_NAND0_0_N J12 PCIE_REFCLK_N S5E-MCP-STUDY C6
2 25V
C0G TK EXT_D3/SWD_UID0/SPINAND_MISO NAND0_S5E0_SWD_UID0 64 67
LGA
0201 2 0201-1 67 NAND0_CLKREQ0_R_L P5 PCIE_ LKREQ* EXT_D4/SPI_CS B7
OUT
EXT_D5/SWD_UID1/SPINAND_MOSI C8 NAND0_S5E0_SWD_UID1 64 67
67 NAND0_S5E0_PCIE_RESREF H7 PCIE_RESREF B9
GND_VOID=TRUE EXT_D6/BOOT3
8 IN PCIE_NAND0_R2D_C_P<0> CN003 0.22UF 1 2 PCIE_NAND0_R2D_P<0> M11 PCIE_RX0_P EXT_D7/SPF B11 NAND0_PFN_L IN 65 67
10% 6.3V X5R-CERM 0201 GND_VOID=TRUE N12 PCIE_RX0_N D11
GND_VOID=TRUE EXT_DQS/BCM* NAND0_BCM_L 64 65
8 IN PCIE_NAND0_R2D_C_N<0> CN004 0.22UF 1 2 PCIE_NAND0_R2D_N<0> E8

10% 6.3V X5R-CERM 0201 GND_VOID=TRUE EXT_NCE/PERST* NAND0_PCIE_RESET_L IN 8 65 67
GND_VOID=TRUE D7
CN001 0.22UF EXT_NRE/JTAG_TMS SWD_NAND0_SWDIO I 107
8 OUT PCIE_NAND0_D2R_P<0> 1 2 PCIE_NAND0_D2R_C_P<0> R12 PCIE_TX0_P
GND_VOID=TRUE T11 E6
10% 6.3V X5R-CERM 0201 PCIE_TX0_N EXT_NWE/JTAG_TCK SWD_NAND0_SWCLK IN 107
GND_VOID=TRUE
8 OUT PCIE_NAND0_D2R_N<0> CN002 0.22UF 1 2 PCIE_NAND0_D2R_C N<0> EXT_RNB/JTAG_TDO E4 NAND0_S5E0_JTAG_TDO OUT 65 67
10% 6.3V X5R-C RM 0201 GND_ OID=TRUE
EXT_CLE/JTAG_TDI D5 TP_NAND0_S5E0_JTAG_TDI 67
IN
EXT_ALE/JTAG_SEL D9 NAND0_JTAG_SEL 64 65 67
67 65 6 IN NAND0_RESET_L L4 RESET* T3
DROOP* TP_NAND0_S5E0_DROOP_L
67 65 64 NAND0_JTAG_TRST_L G10 TRST* G2
WP* NAND0_WP_L 4 65 67
67 NAND0_S5E0_ZQ_0 C10 ZQ_0

67 NAND0_S5E0_ZQ_1 K3 ZQ_1
PLACE_NEAR=UN000.C10:15MM PLACE_NEAR=UN000.K3:15MM
1 1
RN006 RN005
3 0 300
1% 1%
1/20W 1/20W
MF MF
2 201 2 201 www.teknisi-indonesia.com
67 65 64 NAND0_BOOT2
SYNC_MASTER=REF_STORAGE_S5E SYNC_DATE=04/27/2020
67 65 64 NAND0_JTAG_SEL PP V 5_AWAKESW_VCCQ 64 65 102
PAGE TITLE
NAND0_S5E0_SWD_UID0
67 65 64 NAND0_JTAG_TRST_L
6 64
STORAGE: SSD0 S5E <0>
1 1
RN001 RN007 67 64 NAND0_S5E0_SWD_UID1
1 1 1 0 0
RN000 RN002 RN021 5%
1/20W
5%
1/20W 1 1
47K 47K 0 MF MF RN009 RN008
1% 1% 5% 2 0201 2 0201
1/20W 1/20W 1/20W 47K 47K
MF MF MF 1% 1%
2 201 2 201 2 0201 65 64 NAND0_BCM_L /20W
MF
1/20W
MF
2 201 2 201
7 65 64 NAND0_WP_L
Spec recommends to tie BCM, WP directly to 1.2V rail
Spec recommends to tie Boot2 directly to Gnd
BOM_COST_GROUP=SSD
5 3 2 1
*** OK2INTEGRATE *** NAND0 S5E1
PP1V25_AWAKESW_VCCQ 64 102
SSD_2L
CN130
PP0V88_AWAKESW_NAND SSD_2L 4.3UF SSD_2L SSD_2L SSD_2L SSD_2L SSD_2L SSD_2L SSD_2L
102 65 20%
SSD_2L SSD_2L
SSD_2L SSD_2L SSD_2L SSD_ L SSD_2L SSD_2L 1 CN132 4V
CERM
1 CN134 1 CN135 1 CN136 1 CN137 1 CN138 1 CN139 1 CN13A
1 CN112 1 CN113 1 CN114 1 CN115 1 CN116 1 CN117 20UF 0402 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
1 CN110 1 CN111 2.2UF 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF
20%
2 10V 1 3
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
20UF 20UF 20%
10V
20% 20% 10% 10% 10% X5R X5R X5R X5R X5R X5R X5R X5R
20% 20% 2 X5R 2 10V 2 10V 2 6.3V 2 6.3V 2 6.3V 0402 0201 0201 0201 0201 0201 0201 0201
2 10V
X5R
10V
2 X5R 0201
X5R
0201
X5R
0201
CERM-X5R
0201
CERM-X5R
0201
CERM-X5R
0201 2 4
0402 0402
67 TP_NAND0_S5E1_ANI1_VREF
PP2V5_AWAKE_NAND 64 66 101
TP_NAND0_S5E1_ANI0_VREF SSD_2L SSD_2L SSD_2L SSD_2L SSD_2L

67
1 CN120 1 CN122 1 CN123 1 CN124 1 CN125
20UF 2.2UF 2.2UF 2.2UF 2.2UF
SSD_2L 20% 20% 20% 20% 20%
MIN_LINE_WIDTH=0.1000 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
RN110 MIN_NECK_WIDTH=0.1000
VOLTAGE=1.2V 0402 0201 0201 0201 0201
PP1V25_AWAKESW_VCCQ 1
2 2 PP1V2_NAND0_S5E1_AVDD1X_PLL
102 65 64
1%
SSD_2L SSD_2L
1/20W
MF
1 CN147 1 CN146
0201 2.2UF 0.1UF SSD_2L
PLACE NEAR=UN100.L2:10MM 20% 10%
2 10V
X5R
6.3V
2 CERM-X5R MIN_LINE_WIDTH=0.1000
FLN101
0201 0201 VOLTAGE=0.9V
10OHM-50%-1A-0.05OHM
SSD_2L 107 PP0V9_S5E1_VDD_PLL 1 2 PP0V88_AWAKESW_NAND 65 102
FLN100 MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000 TP_NAND0_S5E1_VPP
0201
PLACE_NEAR=UN100.R4:10MM
PLACE_NEAR=FLN101.2:5MM
10OHM-50%-1A-0.05OHM VOLTAGE=1.2V 1 CN183
1 2 PP1V2_NAND0_S5E1_PCI_AVDD_H 4.7UF
SSD_2L SSD_2L 20%
0201 2 4V
PLACE_NEAR=UN100.J6:10MM 1 CN145 1 CN144 CER-X5R
0201
4.7UF 0 1UF SSD_2L
20% 10%
2 4V
CER-X5R 2 6 3V
CERM-X5R
The inductance from CN147, CN146, CN145, CN144 to 0201 0201
their S5E pins shall be less than 1100pH
SSD_2L 1 SSD_2L 67 IN NAND0_CLK24M_1 M3 CLK_IN OMIT_TABLE EXT_D0/BOOT0 B3 NAND0_LPB_L IN 33 64 67

1 CN185 RN104 EXT_D1/BOOT1 C4 NAND_BFH N 6 64 67
10PF 2 0
0.1%
67 8 N PCIE_CLK100M_NAND0_1_P K11 PCIE_REFCLK_P UN100 EXT_D2/BOOT2/SPINAND_SCLK B5 NAND0_BOOT2 64 67
5% 1/20W 67 8 IN PCIE_CLK100M_NAND0_1_N J12 PCIE_REFCLK_N S5E-MCP-STUDY C6
2 25V
C0G TK EXT_D3/SWD_UID0/SPINAND_MISO NAND0_S5E1_SWD_UID0 65 67
LGA
0201 2 0201-1 67 NAND0_CLKREQ1_R_L P5 PCIE_ LKREQ* EXT_D4/SPI_CS B7
OUT
EXT_D5/SWD_UID1/SPINAND_MOSI C8 NAND0_S5E1_SWD_UID1 65 67
SSD_2L 67 NAND0_S5E1_PCIE_RESREF H7 PCIE_RESREF B9
GND_VOID=TRUE EXT_D6/BOOT3
8 IN PCIE_NAND0_R2D_C_P<1> CN103 0.22UF 1 2 PCIE_NAND0_R2D_P<1> M11 PCIE_RX0_P EXT_D7/SPF B11 NAND0_PFN_L IN 64 67
GND_VOID=TRUE N12
SSD_2L 10% 6.3V X5R-CERM 0201 PCIE_RX0_N D11 NAND0_BCM_L
GND_VOID=TRUE EXT_DQS/BCM* IN 64
8 IN PCIE_NAND0_R2D_C_N<1> CN104 0.22UF 1 2 PCIE_NAND0_R2D_N<1> E8

GND_VOID=TRUE EXT_NCE/PERST* NAND0_PCIE_RESET_L IN 8 64 67
SSD_2L 10% 6.3V X5R-CERM 0201
GND_VOID=TRUE D7
CN101 0.22UF 1 2 EXT_NRE/JT G_TMS SWD_NAND0_SWDIO I 107
8 OUT PCIE_NAND0_D2R_P<1> PCIE_NAND0_D2R_C_P<1> R12 PCIE_TX0_P
GND_VOID=TRUE T11 E6
SSD_2L 10% 6.3V X5R-CERM 0201 PCIE_TX0_N EXT_NWE/JTAG_TCK SWD_NAND0_SWCLK IN 107
GND_VOID=TRUE
8 OUT PCIE_NAND0_D2R_N<1> CN102 0.22UF 1 2 PCIE_NAND0_D2R_C N<1> EXT_RNB/JTAG_TDO E4 NAND0_S5E1_JTAG_TDO OUT 67
10% 6.3V X5R-C RM 0201 GND_ OID=TRUE
EXT_CLE/JTAG_TDI D5 NAND0_S5E0_JTAG_TDO 64 67
IN
EXT_ALE/JTAG_SEL D9 NAND0_JTAG_SEL 64 67
IN
67 64 6 IN NAND0_RESET_L L4 RESET* T3
DROOP* TP_NAND0_S5E1_DROOP_L
67 64 IN NAND0_JTAG_TRST_L G10 TRST* G2
WP* NAND0_WP_L IN 64 67
67 NAND0_S5E1_ZQ_0 C10 ZQ_0

67 NAND0_S5E1_ZQ_1 K3 ZQ_1
PLACE_NEAR=UN100.C10:15MM PLACE_NEAR=UN100.K3:15MM
1 1
RN106 RN105
3 0 300
1% 1%
1/20W 1/20W
MF MF
2 201 2 201
SSD_2L SSD_2L
PP1V25_AWAKESW_VCCQ 64 65 102
1
RN108
47K
1%
1/20W SYNC_MASTER=REF_STORAGE_S5E SYNC_DATE=04/27/2020
MF PAGE TITLE
2 201
67 65 NAND0_S5E1_SWD_UID0 SSD_2L STORAGE: SSD0 S5E <1>
67 65 NAND0_S5E1_SWD_UID1
SSD_2L
1
RN109
47K
1%
/20W
MF
2 201
BOM_COST_GROUP=SSD
3 2 1
***OK2INTEGRATE***
THIS EXTERNAL NAND VCC DISCHARGE CIRCUITRY IS FOR SYSTEM THAT DOES NOT USE OCARINA
101 65 64 PP2V5_AWAKE_NAND
1 1 1 1
RN420 RN421 RN422 RN423
24.9 24.9 24.9 24 9
1% 1% 1% 1%
1/10W 1/10W 1/10W 1/10W
MF-LF MF-LF MF-LF MF-LF
2 603 2 603 2 603 2 603
PP2V5_NAND0_DISCHARGE www.teknisi-indonesia.com
VOLTAGE=2.5
D 376S00019
RN430 QN420
P2V5_NAND0_DISCHARGE_EN 1
10K P2V5_NAND0_DISCHARGE_EN_R 1 G DMN2044UCB4
33 IN BGA
5% ALLOW_APPLE_PREFIX=Q
1/20W S
1
RN431 MF
201
10K
5% 2 3
1/20W
MF
1 CN420
33000PF
2 201 10%
2 6.3V
X5R
201
SYNC_MASTER=REF STORAGE_N N OCARINA_SUPPORT
PAGE TITLE
STORAGE: NON OCARINA SUPPORT
2 1
PPP001
P4MM
SM
67 64 NAND0_CLK24M_0 1
PPP002
P4MM
PP
SSD 24M CLOCK TERMINATIONS

SM
67 65 NAND0_CLK24M_1 1
PP
RP000
PPP003
P MM NAND0_CLK24M_0_R 1
15 2 NAND0_CLK24M_0 64
SM OUT
64 8 PCIE_CLK100M_NAND0_0_N 1
PP 1% NOSTUFF
1/20W
1
MF
201 RP005
PPP004
P4MM 1%
47K
SM 1/20W
64 8 PCIE_CLK100M_NAND0_0_P 1
PP MF
2 201
PPP005
P4MM
SM
65 PCIE_CLK100M_NAND0_1_N PP
RP001
PPP006
P4MM 6 NAND0_CLK24M_1_R 1
15 2 NAND0_CLK24M_1 65 67
SM IN OUT
65 8 PCIE_CLK100M_NAND0_1_P 1
PP 1% NOSTUFF
1/20W
1
MF
201 RP006
47K
1%
1/20W
MF
2 201
107 IN PP0V9_S5E0_VDD_PLL TOP TP TPP001 TP-P5
107 IN PP0V9_S5E1_VDD_PLL TOP TP TPP002 TP-P5
65 64 33 IN NAND0_LPB_L TOP 1 TP TPP003 TP-P5
65 64 6 IN NAND_BFH TOP 1 TP TPP004 TP-P5
65 64 IN NAND0_BOOT2 TOP 1 TP TPP005 TP-P5
64 IN NAND0_S5E0_SWD_UID0 TOP 1 TP TPP006 TP-P5
65 IN NAND0_S5E1_SWD_UID0 TOP TP TPP007 TP-P5
67 65 64 IN NAND0_PFN_L TOP 1 TP TPP010 TP-P5
65 64 8 IN NAND0_PCIE_RESET_L TOP 1 TP TPP011 TP-P5
10 5 IN SWD_NAND0_SWDIO TOP TP TPP012 TP-P5

107 5 IN SWD_NAND0_SWCLK TOP 1 TP TPP013 TP-P5
65 64 IN NAND0_S5E0_JTAG_TDO TOP 1 TP TPP014 TP-P5
64 IN TP_NAND0_S5E0_JTAG_TDI TOP 1 TP TPP015 TP-P5
65 IN NAND0_S5E1_JTAG_TDO TOP 1 TP TPP016 TP-P5
65 64 IN NAND0_JTAG_SEL TOP TP TPP017 TP-P5 RP003

NAND0_CLKREQ0_L 1
0 2 NAND0_CLKREQ0_R_L
67 8 64
65 64 IN NAND0_WP_L TOP 1 TP TPP018 TP-P5
IN
5%
OUT
1/20W
MF
67 8 IN NAND0_CLKREQ0_L TOP 1 TP TPP019 TP-P5 0201
67 8 IN NAND0_CLKREQ1_L TOP 1 TP TPP020 TP-P5 SSD_2L

RP004
64 IN NAND0_S5E0_PCIE_RESREF TOP 1 TP TPP021 TP-P5
67 8 NAND0_CLKREQ1_L 1
0 2 NAND0_CLKREQ1_R_L 65
IN OUT
5%
5 IN NAND0_S5E1_PCIE_RESREF TO TP TPP022 TP-P5 1 20
MF
0201
65 64 6 IN NAND0_RESET_L TOP 1 TP TPP023 TP-P5
65 IN NAND0_S5E1_ZQ_0 TOP 1 TP TPP024 TP-P5 RP002

PMU_SYS_ALIVE 1
0 2 NAND0_PFN_L
107 100 89 33 64 65 67
64 IN NAND0_S5E0_ZQ_0 TOP 1 TP TPP025 TP-P5
IN
5%
O T
1/20W
MF
64 IN NAND0_S5E0_ZQ_1 TOP 1 TP TPP026 TP-P5 0201
65 IN NAND0_S5E1_ZQ_1 TO TP TPP027 TP-P5
65 64 IN NAND0_JTAG_TRST_L TOP 1 TP TPP028 TP-P5
64 IN TP_NAND0_S5E0_ANI1_VREF TOP 1 TP TPP029 TP-P5
64 IN TP_NAND0_S5E0_ANI0_VREF TOP 1 TP TPP030 TP-P5
TP_NAND0_S5E1_ANI1_VREF TOP 1 TP TPP031 TP-P5

65 IN
SYNC_MASTER=WUDI_T668_MLB SYNC_DATE=01/28/2020
A
65 IN TP_NAND0_S5E1_ANI0_VREF TOP TP TPP032 TP-P5 PAGE TITLE
STORAGE: SSD SUPPORT
BOM_COST_GROUP=SSD
2 1
CAMERA SECURE DISABLE
104 PP3V3_S2
BYPASS=UP102::5MM
1 CP102
0.1UF VCC
10%
2 6.3V
CERM-X5R CRITICAL
0201
UP102
HOST SIDE NX3DV642GU
QFN-COMBO
CKPLUS_WAIVE=CLK_DATA_CON CLK1+ 17
7 OUT MIPI_FTCAM_DATA_N<0> 1 CLK+ CKPLUS_WAIVE=CLK_DATA_CON
GND_VOID=TRUE
CKPLUS_WAIVE=NDIFPR_BADTERM 22 MIPI_FTCAM_DATA_ISOL_N IN 69 89
CLK2+ GND_VOID=TRUE
CKPLUS_WAIVE=NDIFPR_BADTERM
CKPLUS_WAI E CLK_DATA_CON CLK1- 1
7 OUT MIPI_FTCAM_DATA_P<0> 2 CLK- CKPLUS_WAIVE=CLK_DATA_CON
GND_VOID=TRUE
CKPLUS_WAIVE=PDIFPR_BADTERM 23 MIPI_FTCAM_DATA_ISOL_P IN 69 89
CLK2- GND_VOID=TRUE
CKPLUS_WAIVE=PDIFPR_BADTERM
CKPLUS_WAIVE=CLK_DATA_CON 1D1+ 15
7 OUT MIPI_FTCAM_CLK_N 3 1D+ CKPLUS_WAIVE=CLK_DATA_CON
GND_VOID=TRUE
CKPLUS_WAIVE=NDIFPR_BADTERM 20 MIPI_FTCAM_CLK_ISOL_N IN 69 89
1D2+ GND_VOID=TRUE
CKPLUS_WAIVE=NDIFPR_BADTERM
CKPLUS_WAIVE=CLK_DATA_CON 1D1- 14
7 OUT MIPI_FTCAM_CLK_P
GND_VOID=TRUE
CKP US W IVE=PDIFPR_BADTERM
4 1D-
www.teknisi-indonesia.com CKPLUS_WAIVE=CLK_DATA_CON
MIPI_FTCAM_C K SOL_P
2
IN 69 89
1D2- GN _VOID=TRUE
CKPLUS_WAIVE=PDIFPR_BADTERM
2D1+
PP1V8_S2 101
13 I2C_FTCAM_DSBL_SDA
42 BI I2C_CAM_1V8_SDA 5 2D+ 1
RP105 1
RP107 1
RP106 1
RP108
PPP100
1 2D2+
19 I2C_FTCAM_ISOL_SDA 100K
5%
100K
5%
100K
5%
100K
5%
PP
1/20W 1/20W 1/20W 1/20W
SM-SP MF MF MF MF
2D1- 12 I2C_FTCAM_DSBL_SCL 2 201 2 201 2 201 2 201
42 BI I2C_CAM_1V8_SCL 6 2D-
PPP101
1 2D2-
18 I2C_FTCAM_ISOL_SCL BI 69 89
PP
SM-SP
8 E* NC 7
CONTROL NC BI 69 89
LOGIC NC 24
74 IN FTCAM_DISABLE_1V8_IC_L 11 S NC I2C PULL VALUES TO BE DETERMINED FROM CHARACTERIZATION
VALUE STATE
GND
L CAMERA DISABLE
H CAMERA ENABLE
PAGE TITLE
SECDIS: MIPI MUX
BOM_COST_GROUP=CAMERA
2 1
107S00020
RP620
0.01
1%
1/3W
MF 5% 1/20W
104 89 41 PP3V3_SW_LCD 1
0306
2 PP3V3_SW_LCD_CONN 69 JP600_PIN_18 DISPLAY:P0 RP640 1
0 2
MF 0201
UART_TCON_HDMI_D2R 6 89
OUT
3 4 VOLTAGE=3.3V
5% 1/20W
48 47 ISNS_PPPANEL_SW_LCD_P 69 JP600_PIN_2 DISPLAY:P1 RP641 1
0 2
MF 0201
104 PPVOUT_LCDBKLT
48 47 ISNS_PPPANEL_SW_LCD_N 5% 1/20W
69 JP600_PIN_8 DISPLAY:P0 RP642 1
0 2
MF 0201
SPI_TCON_CS_L 6 89
IN
5% 1/20W
1 CP600 69 JP600_PIN_10 DISPLAY:P1 RP643 1
0 2
MF 0201
CP620 0.1UF 1 2 10% 16V X5R-CERM 0201 1000PF
7 LPDP_INT_AUX_C_N 10% 5% 1/20W
7
BI
LPDP_INT_AUX_C_P CP621 0.1UF 1 10% 16V X5R-CERM 0201
2 100V
X7R-CERM DISPLAY:P0 RP644 1
0 2
MF 0201
SPI_TCON_MISO 6 89
BI 2 0603 OUT
5% 1/20W
1 1 JP600_PIN_12 DISPLAY:P1 RP645 0 MF 0201
RP612 RP613 69 1 2
1M 1M
5% 5% 5% 1/20W 5% MF
1/20W
MF
1/20W
MF
DISPLAY:P0 RP646 1
0 2
MF 0201
89 SPI_TCON_MOSI RP601 1
33 2 SPI_TCON_MOSI_R 6
IN
2 201 2 201 JP600 1/20W 201
20759-042E-02 5% 1/20W
F-ST-SM 69 JP600_PIN_14 DISPLAY:P1 RP647 1
0 2
MF 0201
43 44 5% 1/20W 5% MF
PWR
DISPLAY:P0 RP648 1
0 2
MF 0201
89 SPI_TCON_CLK RP602 1
33 2 SPI_TCON_CLK_R 6
GND_VOID=TRUE CP612 0.1UF 1 2 10% 16V X5R-CERM 0201 1/20W 201
IN
7 LPDP_INT_DATA_C_N<0> SIGNAL 5% 1/20W

7
IN
LPDP_INT_DATA_C_P<0> CP613 0.1UF 1 10% 16V X5R-CERM 0201
89 AUX_N 1 2 JP600_PIN_2 69
0 2
MF 0201
IN 2 89 AUX_P 3 4 EDP_PANEL_1V8_EN IN 70 89
GND_VOID=TRUE 5 6 LPDP_INT_HPD 7 89
1
RP614
GND_VOID=TRUE CP614 0.1UF 1 2 10% 16V X5R-CERM 0201
GND_VOID=TRUE 89 DP0_N 7 8 JP600_PIN_8 69
OUT
100K
7 IN LPDP_INT_DATA_C_N<1> 1
RP611 1%
GND_VOID=TRUE 9 DP0_P 9 10 JP600_PIN_10 69 1/20W
7 I LPDP_INT_DATA_C_P<1> CP615 0.1UF 1 2 10% 16V X5R-CERM 0201 11 12 JP600_PIN_12 5%
47K MF DISPLAY:P0
GND_VOID=TRUE
69
1/20W 2 201
GND_VOID=TRUE 89 DP1_N 13 14 JP600_PIN_14 69 MF
GND_VOID=TRUE CP616 0.1UF 1 2 10% 16V X5R-CERM 0201
GND_VOID=TRUE 89 DP1_P 15 16 JP600_PIN_16 69
2 201
7 IN LPDP_INT_DATA_C_N<2> 17 18 JP600_PIN_18 69 5% 1/20W
7 IN LPDP_INT_DATA_C_P<2> CP617 0.1UF 1 2 10% 16V X5R-CERM 0201
GND_VOID=TRUE 89 DP2_N 19 20 JP600_PIN_20 69 69 JP600_PIN_34 DISPLAY:P0 RP650 1
0 2
MF 0201
I2C_ALS_1V8_SDA 42 89
BI
GND_VOID=TRUE
GND_VOID=TRUE CP618 0.1UF 1 2 10% 16V X5R-CERM 0201 23 24 I2C_BKLT_SDA 71 89 DISPLAY:P1 RP651 0 5% 1/20W
MF 0201
LPDP_INT_DATA_C_N<3> BI JP600_PIN_30 1 2
7 IN 69
GND_VOID=TRUE 89 DP3_N 25 26 I2C_BKLT_SCL 71 89
7 IN LPDP_INT_DATA_C_P<3> CP619 0.1UF 1 2 10% 16V X5R-CERM 0201
IN
5% 1/20W
GND_VOID=TRUE 29 30 JP600_PIN_30 69 69 JP600_PIN_36 DISPLAY:P0 RP652 1
0 2
MF 0201
I2C_ALS_1V8_SCL 42 89
IN
MIPI_DATA_CONN_N 31 32 JP600_PIN_32 69
5% 1/20W
MIPI_DATA_CONN_P 33 34 JP600_PIN_34 69
0 2
MF 0201
35 36 JP600_PIN_36 69
LP602 MIPI_CLOCK_CONN_N 37 38 JP600_PIN_38 69 5% 1/20W
3.25-OHM-0.1A-2.4GHZ
TAM0605-4SM MIPI_CLOCK_CONN_P 39 40 JP600_PIN_40 69 69 JP600_PIN_38 DISPLAY:P0 RP654 1
0 2
MF 0201
I2C_FTCAM_ISOL_SCL 68 89
SYM_VER-1 IN
41 42 JP600_PIN_42
MIPI_FTCAM_DATA_ISOL_N
1 4 69
LP610 DISPLAY:P1 RP655 0 5% 1/20W
68 OUT
VOLTAGE=5V
FERR 120-OHM-1.5A JP600_PIN_34 1 2
MF 0201
PWR 69
89 68 OUT MIPI_FTCAM_DATA_ISOL_P 2 3
45 46 89 PP5V_CAM 1 2
5% 1/20W
MIN_LINE_WIDTH=0.2000 0402A
0 2
MF 0201
I2C_FTCAM_ISOL_SDA 68 89
47
GND
48 CP610
MIN_NECK_WIDTH=0.1000 1 BI
0.1UF 5% 1/20W
49 50 10%
2 16V 69 JP600_PIN_36 DISPLAY:P1 RP657 1
0 2
MF 0201
51 52 X5R-CERM
LP603
3.25-OHM-0.1A-2.4GHZ 53 54
0201
TAM0605-4SM 55 56
SYM_VER-1
1 4 57 58 5% 1/20W
9 68 OUT MIPI_FTCAM CLK_ISOL_N 59 60 DISPLAY:P0 RP664 1
0 2
MF 0201
UART_TCON_HDMI_R2D 6 89
IN
89 8 OUT MIPI_FTCAM_CLK_ISOL_P 2 3
61 62
5% 1/20W
63 64
0 2
MF 0201
I2C_MLB2JERRY_3V3_SDA 41 89
65 66 BI
107S00116
NO_XNET_CON ECTION=1 67 68 5% 1/20W
RP621 69 JP600_PIN_22 DISPLAY:P1 RP661 1
0 2
MF 0201
I2C_MLB2JERRY_3V3_SCL 41 89
IN
0.1
1% 5% 1/20W
0.5W
MF 69 JP600_PIN_28 DISPLAY:P0 RP662 1
0 2
MF 0201
TP_TCON_SWCLK 89
0306
104 89 PP5V_SW_LCD 1 2 PP5V_SW_LCD_CONN
VOLTAGE=5V 5% 1/20W
3 4
0 2
MF
TP_TCON_SWDIO 89
48 47 ISNS_PP5V_SW_LCD_P
48 47 ISNS_PP5V_SW_LCD_N 5% 1/20W
0 2
MF
105 PP5V_S2_ALSCAM_ISNS 5% 1/20W

0 2
MF 0201
5% 1/20W
0 2
MF
5% 1/20W
0 2
MF 0201
5% 1/20W
0 2
MF 0201
5% 1/20W
0 2
MF 0201
5% 1/20W
0 2
MF 0201
SYNC_MASTER=AITKEN_T6 8_MLB SYNC_DATE=10/02/2019
5% 1/20W PAGE TITLE

0 2
MF 0201
DISPLAY: CONNECTOR, PWR
BOM_COST_GROUP=DISPLAY
104 PP5V_S2
CRITICAL 1 CP717
VDD
0.1UF
10%
UP700 2 10V
X5R-CERM
0201
SLG5AP1443V
TDFN
LCD_PWR_SLEW 7 CAP D 3
2 ON S 5 PP5V_SW_LCD 104
CP709 1
GND 1 CP711 1 CP712
2200PF
10%
10V
0.1UF 10UF
10% 20%
X7R-CERM 2 2 10V 2 10V
0201 X5R-CERM X5R-CERM
0201 0402-7
CONSULT YOUR DISPLAY DRI FOR DETAILS

GENERAL GUIDELINE IS www.teknisi-indonesia.com
3V3 FOR 2020 SYSTEMS
3V8 FOR 2021 SYSTEMS
104 PP3V3_S2
1 CP710
1.0UF
CRITICAL 20% 6.3V
2 X5R
101 PP1V8_S2 VDD 0201-1
BYPASS=UP710.1::3.5MM UP701
CP770 SLG5AP1564V
1
0.1UF
2
STDFN B
10% ON D 3
2 10V
X5R-CERM
0201 S 5 PP3V3_SW_LCD 104
PG 7 NC
1 CP718 1 CP719
GND 0.1UF 10UF
10% 20%
2 10V
X5R-CERM 2 10V
X5R-CERM
0201 0402-7
UP710 1
SLG4AP43605V RP700
STQFN 300
5%
1/16W
94 34 IN LCD_PWR_EN 2 PANEL_EN_IN PANEL_EN_OUT 11 EDP_PANEL_1V8_EN OUT 69 89 MF-LF
2 402
PANEL_PWR_EN 4 EDP_PANEL_PWR_EN
107 IN PMU_SYS_ALIVE 3 SYS_ALIVE
PPPANEL_PANEL_DISCHARGE
13 MIN_NECK_WIDTH=0.1000
5 BLC_VDDIO_EN NC 3 MIN_LINE_WIDTH=0.2000
NC NC VOLTAGE=4V
NC
6 NC BLC_5V_EN 14 EDP_BLC_5V_EN D 376S1140
7
NC NC QP700
NC
8 NC PANEL_DISCHARGE 10 EDP_PANEL_DISCHARGE 1 G DMN2300UFB4
12 NC S X2-DFN1006-3-COMBO
NC SYM_VER_1
1
RP701
100K 2
5%
1/20W
MF
2 201 C M TE E P NE W N C TE
PAGE TITLE
DISPLAY POWER SEQUENCER
2 1
BEN IC: DISPLAY/KBD BACKLIGHT BOOST CONVERTER
ALLOW_APPLE_PREFIX=Q
152S00253 VOLTAGE=55
376S0604 CRITICAL
PLACE_NEAR=QP801.5:3MM MIN_LINE_WIDTH=0.2000
CRITICAL DFLS2100
107S00034 CRITICAL MIN_NECK_WIDTH=0.1000 PLACE_NEAR=LP800.2:4.7MM
740S0159
RP800 QP800 VOLTAGE=13 LP800 SWITCH_NODE=TRUE
371S00180
CRITICAL 0.025 FDC638APZ_SBMS001 MIN_LINE_WIDTH=0.2000
15UH-20%-1.9A-0.24OHM DIDT=TRUE
DP800
POWERDI123-COMBO
1%
FP800 VOLTAGE=13
MIN_NECK_WIDTH=0.1000 1W
MF
VOLTAGE=13
SSOT6-HF 6 PPVIN_LCDBKLT_Q 1 2 PPVOUT_LCDBKLT_SW A K PPVOUT_LCDBKLT 104
3AMP-32V MIN_LINE_WIDTH=0.2000 0612- MIN_LINE_WIDTH=0.2000 5 PIME062D-SM
101 PPBUS_AON 1 2 PPVIN_LCDBKLT_F 2 1 PPVIN_LCDBKLT_R 4
2 PLACE_NEAR=LP 00.1:5MM PLACE_NEAR=LP800.1:5MM OMIT_TABLE
PLACE_NEAR=LP800.1:5MM PLACE_NEAR=LP800:5MM
0603-COMBO
4 3
1
1 CP810 1 CP811 1 CP812 CP876 1
1
RP801 1 CP800 NOSTUFF 4.7UF 4.7UF
10% 10% 0.1UF 12PF
80.6K 1000PF 1 CP801 2 25V
X6S-CERM 2 25V
X6S-CERM
10% 5%
1% 10% 3 0.001UF 2 25V 100V 2 PLACE_NEAR=DP800.K:5MM PLACE_NEAR=DP800.K:6MM PLACE_NEAR=DP800.K:5MM PLACE_NEAR=DP800.K:5MM
1/16W 2 16V 0603 0603 X5R C0G
MF-LF X7R-1
0201
10%
2 50V
402 0201 1 CP860 1 CP861 1 CP862 1 CP863
2 402 CERM 2.2UF 2.2UF 2.2UF 2.2UF
LCDBKLT_EN_L 402 10% 10% 10% 10%
2 100V
X5R 2 100V
X5R 2 100V
X5R 2 100V
X5R
1 1206 1206 1206 1206
RP802 CKPLUS_WAIVE=LIFECYCLE_STATUS
PLACE_NEAR=DP800:4MM 2
63.4K XWP801
1% SM
1/16W
MF-LF
2 402 1
PLACE_NEAR=DP800.K:5MM PLACE_NEAR=DP800.K:5MM PLACE_NEAR=DP800.K:5MM PLACE_NEAR=DP800.K:5.5MM
PP5V_S2 376S0678
LCDBKLT_FB_XWR 1 CP864 1 CP865 1 CP866 1 CP867
104
5 2 2UF 2.2UF 2.2UF 2.2UF
OMIT_TABLE OMIT_TABLE 10% 10% 10% 10%
2 100V 2 100V 2 100V 2 100V
RP8441 1
RP845 CRITICAL VOLTAGE=5
X5R
1206
X5R
1206
X5R
1206
X5R
1206
0 0 MIN_NECK_WIDTH=0.2000
5%
1/16W
5%
1/16W VOLTAGE=5
QP801 GATE_NODE=TRUE
DIDT=TRUE
MF-LF MF-LF MIN_LINE_WIDTH=0.2000 SI7812DN
402 2 VOLTAGE=5 2 402 MIN_NECK_WIDTH=0.1000 PWRPK-1212-8
4 LCDBKLT_FET_DRV_R
MIN_NECK_WIDTH=0.1000 PP5V_BKLT_A PLACE_NEAR=DP800.K:10MM PLACE_NEAR=DP800.K:8MM PLACE_NEAR=DP800.K:6.5MM PLACE_NEAR=DP800.K:10MM
PP5V_BKLT_D 1 CP868 1 CP869 1 CP870 1 CP871

OMIT_TABLE OMIT_TABLE 3 2 1PLACE_NEAR=UP800.1:4MM 2.2UF 2.2UF 2.2UF 2.2UF
1 10% 10% 10% 10%
PLACE_NEAR=UP800.5:5MM PLACE_NEAR=UP800.18:5MM
RP833 2 100V 2 100V 2 100V 2 100V
CP840 1 CP841 1 SYMBOL: 353S4160 10
1%
X5R
1206
X5R
1206
X5R
1206
X5R
1206
1UF 1UF 1/16W
10% 10% MF-LF OMIT_TABLE
10V 2 10V 2
X5R X5R 2 402 NO_XNET_CONNECTION=1
402-1 402-1 1
VOLTAGE=5
GATE_NODE=TRUE RP831
UP TO 22V ALLOWED ON UP800.11
UP800 VOLTAGE=55
DIDT=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6000 1% PLACE_NEAR=DP800.K:6MM PLACE_NEAR=DP800.K:8MM
WITH VDDD,VDDA AT 0V CRITICAL SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.2000 1/16W
LLP MIN_NECK_WIDTH=0.2000
MF-LF 1 CP872 1 CP873
LP8548B1SQ_-04 2 402 2.2UF 2.2UF
BKLT_SD 11 SD OMIT_TABLE SW 2 LCDBKLT_SW 10% 10%
9 1 2 100V 2 100V
48 45 OUT ISNS_LCDBKLT_N VSENSE_N SW X5R
1206
X5R
1206
48 45 ISNS_LCDBKLT_P 10 VSENSE_P FB 21 LCDBKLT_FB
OUT
4 NOSTUFF
GD LCDBKLT_FET_DRV
RP842 BKLT_SENSE_OUT 19 SENSE_OUT 1
RP832 1 CP830
0 17 ISET_KEYB 20 BKLT_ISET_KEYB BI 72 150K 100PF
94 33 IN BL_PWR_EN 1 2 BKLT_EN_R EN 1% 5%
12 1/16W 2 100V
UP800.17 VIH_MIN 1.2V 5% PWM_KEYB KEYB1 13 BKLT_KEYB1 IN 72 MF-LF C0G-CERM
0603
1/20W
VIL_MAX 0.4V MF KEYB2 14 BKLT_KEYB2 72
IF KEYBOARD BACKLIGHT NOT USED, 2 402
0201 BKLT_SCL 15 SCL (5K IPU VDDD)
IN
ALIAS TO NC
BKLT_SDA 16 SDA (5K IPU VDDD) SW2 6 KBDBKLT_SW2 72
BI
FB2 8 VOUT_KEYBDLED_FB2 IN 72
1 1
RP852 RP853
1.8K 1.8K
TO JERRY ONLY 5% 5% PLACE_NEAR=UP800.15:10MM
1/20W 1/20W
MF
2 201
MF
2 201
RP850 NOSTUFF
RP8401
OMIT_TABLE THRM
I2C_BKLT_SCL 1
0 2
CP842 1
1M RP847 1 PAD
89 69 IN 33PF 5% 10K IF KEYBOARD BACKLIGHT USED,
UP800.15 VIH_MIN 1.7V 5% 1/20W MF 0201 5% 1/20W 5%
25V
VIL_MAX 0.4V NPO-C0G 2 MF
201 2
1/20W
MF
CONNECT TO CSA 239
0201
RP851 201 2
0 BKLT_PWM_KEYB_3V3 IN 72
89 9 BI I2C_BKLT_SDA 1 2
5% GND_BKLT_SGND 72 89
UP800.16 VIH_MIN 1.7V 1/20W
VIL_MAX 0.4V MF MIN_LINE_WIDTH=0.4000
R_ON(TYP) 11.65 OHMS
R_ON(MAX) 12.85 OHMS
0201
PLACE_NEAR=UP800.16:10MM
CKPLUS_WAIVE=LIFECYCLE_STATUS XWP800
SM
VOLTAGE=0
1 2
UP800.12 VIH_MIN 1.7V
VIL_MAX 0.4V
BEN IC VERSION TO MATCH VERSION OF JERRY IC IS ON THE PANEL
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION BACKLIGHT BOOST VOLTAGE LEVEL BASED ON NUMBER OF LEDS PER STRING
TA LE_5_ TEM TA LE_5_ EAD
353S4160 1 IC,LP8548B1-04,DC/DC CVTR,BOOST,QFN-24 UP800 BLC_BEN_IC:V4 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TA LE_5_ TEM TA LE_5_ TEM
353S02256 1 IC,LP8548B1A-07,DC/DC BOOST CVTR,QFN24 UP800 BLC_BEN_IC:V7 114S0339 1 RES,MTL FILM,1/16W,18.2K,1,0402,SM,LF RP831 BLC_LEDS_PER_STRING:16 SYNC_MASTER=REF_BLC_BEN SYNC_DATE=11/21/2019
TA LE_5_ TEM PAGE TITLE
BACKLIGHT SWITCH NODE DESENSE OPTION
TA LE_5_ EAD
114S0359 1 RES,MTL FILM,1/16W,28.7K,1,0402,SM,LF RP831 BLC_LEDS_PER_STRING:18
BEN: CONTROLLER
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION BOM OPTION FOR BLC 5V RC FILTER, BASED ON PER PROJECT 5V RIPPLE CHARACTERIZATION.
TA LE_5_ TEM
AS COMPARED TO BLC TEAM'S 50 MV RIPPLE SPEC FOR VDDD & VDDA, SEE <RDAR://50682542>
131S00141 1 CAP,C0G,12PF,5%,100V,0201 CP876 BLC_SW_NODE_DESENSE TA LE_5_ EAD

10K IF KEYBOARD PWM INPUT IS NOT PRESENT (J132, J213) TA LE_5_ TEM
100K IF KEYBOARD PWM INPUT IS PRESENT (J152) 116S0004 2 RES,MTL FILM,0 OHM,1A MAX,0402,SMD RP844,RP845 BLC_5V_SERIES:0_OHM
TA LE_5_ EAD T
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 114S0023 2 RES,MTL FILM,1/16W,10 OHM,1,0402,SMD,LF RP844,RP845 BLC_5V_SERIES:10_OHM
TA LE_5_ TEM A LE_5_ TEM
117S0007 1 RES,MF,1/20W,10K OHM,5,0201,SMD RP847 BLC_KBD_BOOST_USED:NO 138S0614 2 CAP,CER,X5R,1UF,10%,10V,0402 CP840,CP841 BLC_5V_CAP:1_UF

TA LE_5_ TEM TA LE_5_ TEM
118S0014 1 RES,MF,100KOHM,1,1/20W,0201 RP847 BLC_KBD_BOOST_USED:YES 138S00070 2 CAP,CER,X5R,4.7UF,20%,25V,0402 CP840,CP841 BLC_5V_CAP:4P7_UF

8 6 2 1
BEN IC: KEYBOARD LED DRIVER
THIS PAGE IS ONLY TO BE INCLUDED IF THE KEYBOARD BACKLIGHT
IS CONTROLLED BY THE BEN ON PAGE 238
DP900
LP900
10UH-20%-1.4A-0.17OHM
PLACE_NEAR=LP900.2:10MM PMEG6010ER/S500
SOD123W
105 PP5V_S2_KBDLED_ISNS 1 2 A K PPVOUT_KBDLED 104
PST041H-SM OMIT_TABLE
PLACE_NEAR=LP900:5MM
1 CP940 1 CP941 1 CP942 1 CP976
2.2UF 2.2UF 0.1UF
10% 10% 10% 12PF
2 25V
X5R-CERM
25V
X5R-CERM 2 16V
X5R CE M
5%
603 603 0201 2 100V
C0G PLACE_NEAR=DP900:5MM PLACE_NEAR=DP900:5MM PLACE_NEAR=DP900:5MM PLACE_NEAR=DP900:5MM
0201 1 CP950 1 CP951 1 CP952 1 CP953
2.2UF 2.2UF 2.2UF 2.2UF
10% 10% 10% 10%
2 50V
X5R 2 50V
X5R 2 50V
X5R 2 50V
X5R
0603 0603 0603 0603
71 BI KBDBKLT_SW2
DIDT=TRUE PLACE_NEAR=DP900:5MM PLACE_NEAR=DP900:5MM PLACE_NEAR=DP900:5MM PL CE_NEAR=DP900:5MM
SWITCH_NODE=TRUE
VOLTAG =42V 1 CP954 1 CP955 1 CP956 1 CP957
2.2UF 2.2UF 2.2UF 2.2UF
10% 10% 10% 10%
2 50V
X5R 2 50V
X5R 2 50V
X5R 2 50V
X5R
XWP900
SM
0603 0603 0603 0603
71 BI VOUT_KEYBDLED_FB2 2 1
KEYBOARD BACKLIGHT MIN_LINE_WIDTH=0.5000
VOLTAGE=40V PLACE_NEAR=CP950.1:10MM
POWER & CONTROL PLACE_NEAR=DP900:5MM
SIGNALS FROM
1 CP958
0.001UF
10%
2 50V
X7R-CERM
SYSTEM 0402 KEYBOARD BACKLIGHT
CONNECTOR SIGNALS
KEYBOARD BKLT PWM LEVEL-SHIFTER

UP900.4: VOH_MIN = 2.3V
VOL_MAX = 0.1V @ PWM_KEYB I_MAX OF 1UA RP910
BKLT_KEYB1 1
10 2 KBDLED_CATHODE1
71 OUT IN 81 89
104 PP3V3_S2 1/16W MF-LF 402
102 PP1V25_S2 RP911

PLACE_NEAR=UP900.6:5MM PLACE_NEAR=UP900.1:5MM 311S00243 71 BKLT_KEYB2 1
10 2 KBDLED_CATHODE2 81 89
CP900 1 CP901 1
UP900
OUT
IN
0.1UF 0.1UF 1/16W MF-LF 402
10% 10% SN74AXC1T45
16V 16V SOT-5X3
X5R-CERM 2 X5R-CERM 2
0201 0201
VCCA VCCB
5
RP901 DIR
KBD_BKLT_PWM 1
0 2 SOC_KBD_BKLT_PWM_RES 3 4 BKLT_PWM_KEYB_3V3
5 IN A B OUT 71
5%
1/20W
MF
0201
1 RP900 GND
47K BKLT_ISET_KEYB BI 71
UP900.3: 5% MIN_LINE_WIDTH=0.1000
1/20W MIN_NECK_WIDTH=0.0800
VIH MIN = VCCA X 0.65 = 0.78V MF 1 RP903
2 201 31.6K
1%
1/20W
MF
201
2
GND_BKLT_SGND 71 89
OFF=PAGE SIGNALS ON THIS VERTICAL LINE CONNECT TO BEN UP800

ON PAGE 238
SYNC_MASTER=REF_BLC_BEN SYNC_DATE=11/21/2019
PAGE TITLE
BEN: KEYBOARD
KEYBOARD SWITCH NODE DESENSE OPTION

TA LE_5_ EAD

TA LE_5_ TEM
131S00141 1 CAP,C0G,12PF,5%,100V,0201 CP976 BLC_KBD_SW_NODE_DESENSE

8 7
Lid Detect Sensors

PACK_OPTION=AMR_INTERPOSER_LEFT
998-19652
JR200
INTERPOSER-AMR-MLB
SMT-PAD
8 1
7 2 AMR_LEFT_OR_ND_1V8 OUT 74 89
6 3 PP1V8_AON 73 89 104
5 4
OMIT_TABLE PP1V8_AON
0 89 73
ALLOW_APPLE_PREFIX=
RR200 1 1
RR201 BYPASS=UR200::5MM
5%
1M
5%
1M CR200 1
1/20W 1/20W 0.1UF

MF MF 10%
201 2 2 201
6.3V 2
CERM-X5R
6
UR200
0201 74LVC1G32
PACK_IGNORE=TRUE 2 SOT891 RR203
PACK_OPTION=AMR_INTERPOSER_RIGHT
IPD_LID_OPEN_R_1V8 1
1K 2 IPD_LID_OPEN_1V8 OUT 33 85 87 89
998-19652 Clamshell Open = High
1 5%
JR201 Clamshell Closed = Low NC 1/20W
MF
INTERPOSER-AM -MLB PACK_IGNORE=TRUE 5 3 2 1
SMT-PAD PACK_OPTION=NO_AMR_INTERPOSER_LEFT
8 1
NC
7 2 PACK_OPTION=NO_AMR_INTERPOSER_RIGHT
6 3 PP1V8_AON 73 89 104
5 4
OMIT_TABLE
ALLOW_APPLE_PREFIX=J AMR_RIGHT_OR_ND_1V8 OUT 74 80 89
MGL_1V8 OUT 74
RR202 1
100K
5%
1/20W
MF
201 2
PAGE TITLE
SECDIS: AMR
BOM_COST_GROUP=SOC
*** OK2INTEGRATE *** UNLESS 1V8 IS NOTED, SIGNALS ARE 1.2V 101 74 PP1V8_S2
ROOM=SECURE_DISABLE
1 CR306
0.1UF
BYPASS=UR301.1::5MM 10%
2 6.3V
CURRENT PER RAIL 101 74 PP1V8_S2
CERM-X5R
0201
UR301
SLG4AP44010
RAIL TYPICAL PEAK 2 STQFN ROOM=SECURE_DISABLE
NC
102 74 PP1V2_S2 NC
3 RR314
1.2 S2 0.8MA 33MA 4 NC CLK_2MHZ 7 CLK_2MHZ_SECDIS_1V8_R 1
10 2
1.8 S2 0.8MA 14MA NC
6 5% 201
NC 1/20W MF
8
NC
PLACE_NEAR=UR301.7:15MM
SUPER IMPORTANT PACK OPTIONS:
NOTES ARE ON CSA 2 OF THE REFERENCE DESIGN
ROOM=SECURE_DISABLE
READ, LEARN, IMPLEMENT

UR300
LCMXO2-2000ZE-1UWAP9
6 IN FTCAM_DISABLE_L FTCAM_DISABLE_L E7 PB3A (IPD)* PT10A D5
NC
MAKE_BASE=TRUE PACK_OPTION=PROD_SECDIS
107 IN NC_IRCAM ENABLE_IN_IC F7 PB3B (IPD) WLCSP PT10B D4 MGL_1V8 N 73
NC
G7 PB5A/CSSPIN OMIT_TABLE PT12C/TDO A6 SECDIS_TDO_IC 74
JTAG SIGNALS ARE 1.8V
PT12D/TDI C5 SECDIS_TDI 74
6 IN DMIC_DISABLE_L DMIC_DISABLE_L F6 PB8A/MCLK/CCLK (IPD)* INPUTS ARE HARD-TIED TO RAILS IN POR DESIGNS
107 OUT NC_DMIC_DATA2_SEC_OUT_IC MAKE_BASE=TRUE PACK_OPTION=PROD_SECDIS
F5 PB8B/SO/SPISO PT16C/TCK B4 SECDIS_TCK 74 THE OUTPUT (TDO) IS NC'D IN POR DESIGNS
100 90 89 33 9 5 IN PMU_RESET_L E4 PB11A/PCLKT2_0 PT16D/TMS B5 SECDIS_TMS 74
107 NC_FTCAM_ENABLE_IN E3 PB11B/PCLKC2_0 (IPD) PT17A/PCLKT0_1 C4 AMR_RIGHT_OR_ND_1V8 IN 73 80 89
(IPD) PT17B/PCLKC0_1 D3 NC_DMIC_CLK2_IN_IC IN 107

9 OUT PD _DMIC_DATA4 PDM_DMIC_DATA4 CKPLUS WAIVE=CLK DATA CON G4 PB16A/PCLKT2_1
9 OUT PDM_DMIC_DATA3 PDM_DMIC_DATA3 CKPLUS WAIVE=CLK DATA CON G3 PB16B/PCLKC2_1 PT18C/SCL/PCLKT0_0 B3 CLK_2MHZ_SECDIS_1V8
SMC_LID_OPEN_R F4 PB12A PT18D/SDA/PCLKC0_0 C3 NC_DMIC_CLK2_1V8_OUT_R_IC
107 IN NC_SEP_IRCAM_DISABLE_IC_L F3 PB12B (IPD) PT20A A3 DMIC_CLK_ENABLE 74
RR313 PT20B B2 NC_IRCAM_ENABLE_SEC_1V8_OUT OUT 107

74 SECDIS_SN_TIE_OFF G2 PB25A/SN
LID_OPEN LID_OPEN 1
1K 2 G1 F2 NC_FTCAM_ENABLE_SEC_1V8_OUT
9 OUT NC PB25B/SI_SISPI PT20C/JTAGENB OUT 107
F1
5% PT20D/PROGRAMN
1/20W A7 PL2A/L_GPLLT_IN NC
MF 201 NC PT23A E2 DMIC_DATA0_1V8_IN IN 80
6 IN DISABLE_STROBE DISABLE_STROBE B6 PL2B/L_GPLLC_IN (IPD)*
MAKE_BASE=TRUE PACK_OPTION=PROD_SECDIS PT23B C2 DMIC_DATA1_1V8_IN IN 80
PDM_DMIC_CLK4 CKPLUS WAIVE=SYNONYM CHECK C7 PL3A/PCLKT5_0 (IPD)*
DMIC_CLK1_1V8_OUT_R C6 PL3B/PCLKC5_0 PT24A C1 FTCAM_DISABLE_1V8_IC_L OUT 68
(IPD) PT24B D2 NC_DMIC_DATA2_1V8_IN IN 107

DMIC_CLK0_1V8_OUT_R E6 PL5A
PT24C/INITN B1 AMR_LEFT_OR_ND_1V8 IN 73 89
PDM_DMIC_CLK3 CKPLUS WAIVE=SYNONYM CHECK E5 PL5B A1
CKPLUS_WAIVE=TERMSHORTED GND PT24D/DONE NC
ROOM=SECURE_DISABLE
PACK_IGNORE=TRUE
PACK_OPTION=DEV_SECDIS
PINS MARKED (IPD)* ONLY HAVE RR309
ROOM=SECURE_DISABLE 1
10 2 DMIC_CLK2_1V8_OUT_IC
1 1 1 INTERNAL PULLDOWNS IN THE OUT
RR300 RR310 RR311 RR312 SECDIS_EVT VERSION OF THE PART 5% 201
PDM_DMIC_CLK4 PDM_DMIC_CLK4 1
0 2
47K 47K 47K PLACE_NEAR=UR300.C3:15MM 1/20W MF
9 IN 1% 1% 1%
MAKE_BASE=TRUE 1/20W 1/20W 1/20W PACK_IGNORE=TRUE PACK_IGNORE=TRUE
5% 0201 MF MF MF PACK_OPTION=PROD_SECDIS_3DMIC PACK_OPTION=PROD_SECDIS_3DMIC
1/20W MF
PACK_OPTION=PROD_SECDIS 2 201 2 201 2 201 OMIT_TABLE
PACK_OPTION=PROD_SECDIS
PACK_OPTION=PROTO_PULLDOWN_SECDIS
PACK_OPTION=PROTO_PULLDOWN_SECDIS
ROOM=SECURE_DISABLE
RR301 PACK_OPTION=PROTO_PULLDOWN_SECDIS
DMIC_CLK1_1V8_OUT 1
10 2
PLACE_NEAR=UR300.C6:15MM
89 80 OUT
OMIT_TABLE 5%
1/20W
201
MF
AB E_5_H AD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

ROOM=SECURE_DISABLE AB E_5_I EM
RR302 336S00038 1 IC,PLD,MACHX02,2112 LUT,1.2V,ANN,WLCSP49 UR300 SECDIS_PROTO
DMIC_CLK0_1V8_OUT 1
10 2
PLACE_NEAR=UR300.E6:15MM AB E_5_I EM
89 80 OUT 336S00039 1 IC,PLD,MACHX02,2112 LUT,1.2V,AP5,WLCSP49 UR300 SECDIS_EVT

OMIT_TABLE 5%
1/20W
201
MF
AB E_5_I EM
336S00041 1 IC,PLD,MACHX02,2112 LUT,1.2V,XXX,WLCSP49 UR300 SECDIS_EXT_CLK

ROOM=SECURE_DISABLE ROOM=SECURE_DISABLE
BYPASS=UR300.D7::5MM BYPASS=UR300.D1::5MM
CKPLUS_WAIVE=TERMSHORTED
ROOM=SECURE_DISABLE
B
PACK_IGNORE=TRUE BYPASS=UR300.G6::5MM
PACK_OPTION=DEV_SECDIS AB E_5_H AD
102 74 PP1V2_S2
ROOM=SECURE_DISABLE PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
RR303 117S0004 3 RES,MF,1/20W,10 OHM,5,0201,SMD RR301,RR302,RR309 DMIC_CLK_10OHM

AB E_5_I EM
1 CR300 1 CR301 1 CR302

PDM_DMIC_CLK3 PDM_DMIC_CLK3 1
0 2 AB E_5_I EM 0.1UF 0.1UF 0.1UF
9 IN
MAKE_BASE=TRUE 117S0080 3 RES,MF,1/20W,33 OHM,5,0201,SMD RR301,RR302,RR309 DMIC_CLK_33OHM 10% 10% 10%
5% 0201 2 6.3V
CERM-X5R 2 6 3V
CERM-X5R 2 6.3V
CERM-X5R
1/20W MF 0201 0201 0201
PP1V2_S2 ROOM=SECURE_DISABLE
102 74
1 ROOM=SECURE_DISABLE ROOM=SECURE_DISABLE
RR307 BYPASS=UR300.B7::5MM BYPASS=UR300.A2::5MM
7K
SERIAL PROGRAMMING DISABLE 5%
1/20W ROOM=SECURE_DISABLE
MF BYPASS=UR300.A5::5MM
2 201 101 74 PP1V8_S2
74 SECDIS_SN_TIE_OFF
ROOM=SECURE_DISABLE ROOM=SECURE_DISABLE 1 CR303 1 CR304 1 CR305
JTAG FOR DEV & PROTO0 BOARDS ONLY PACK_OPTION=JTAG_SECDIS:NO PACK_OPTION=JTAG_SECDIS:NO
0.1UF
10%
2 6.3V
0.1UF
10%
2 6.3V 2 6.3V
0.1UF
10%
ROOM=SECURE_DISABLE CERM-X5R CERM-X5R CERM-X5R

101 74 PP1V8_S2 0201 0201 0201
JR300 101 74 PP1V8_S2 101 74 PP1V8_S2
505070-1222
M-ST-SM 1 1 1
13 14
PACK_OPTION=JTAG_SECDIS:YES CKPLUS_WAIVE=TERMSHORTED RR304 RR305 RR308
PACK_OPTION=JTAG_SECDIS:YES 5%
4.7K
5%
4.7K MUST BE SAME RAIL AS DMICS 1%
47K
1 2 1/20W 1/20W 1/20W
MF MF MF SYNC_MASTER=REF_SECDIS_SAK SYNC_DATE=04/22/2020
74 SECDIS_TDO_IC 3 SECDIS_TMS 74
2 201 2 201 2 201 PAGE TITLE
74 SECDIS_TDI 5 6 SECDIS_TCK 74 74 SECDIS_TMS 74 DMIC_CLK_ENABLE SECDIS: FPGA

74 SECDIS_TCK 7 8 SECDIS_TDI 74 74 SECDIS_TDI
74 SECDIS_TMS 9 10 SECDIS_TDO_IC 74 74 SECDIS_TCK
11 12
JTAG PORT TIE-OFFS 1 PACK_OPTION=JTAG_SECDIS:YES
RR306 CKPLUS_WAIVE=TERMSHORTED
15 16 4.7K
PACK_OPTION=JTAG_SECDIS:YES 5%
1/20W PACK_OPTION=JTAG_SECDIS:NO
MF
CKPLUS_WAIVE=TERMSHORTED 2 201 GND
APN: 516S00115 I HAVE ROTATIONAL SYMMETRY MAKE_BASE=TRUE
ROOM=SECURE_DISABLE
BOM_COST_GROUP=SOC
102 77 76 75 PP1V25_AWAKE_IO PP1V8_AWAKE 75 77 78 102 102 77 76 75 PP1V25_AWAKE_IO PP1V8_AWAKE 75 77 78 102

PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA SPKRAMP_LVL_4B_BGA SPKRAMP_LVL_4B_BGA SPKRAMP_LVL_4B_BGA
PLACE_NEAR=UR400.B4:5MM PLACE_NEAR=UR400.B6:5MM PLACE_NEAR=UR430.B4:5MM PLACE_NEAR=UR430.B6:5MM
1 CR400 1 CR401 1 CR430 1 CR431
0.1UF 0 1UF 0.1UF 0.1UF
10% 10% 10% 10%
2 25V
X5R 2 25V
X5R 2 25V
X5R 2 25V
X5R
0201 0201 0201 0201
VCCB VCCA PACK_IGNORE=TRUE VCCB VCCA PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA SPKRAMP_LVL_4B_BGA
33 33
UR400 75 TDM_1V8_SPKRAMP_L_BCLK_R RR400 1 2 TDM_1V8_SPKRAMP_L_BCLK
5% 1/20W MF OUT 75 107
UR430 75 TDM_1V8_SPKRAMP_R_BCLK_R RR430 1 2 TDM_1V8_SPKRAMP_R_BCLK
5% 1/20W MF OUT 75 107
SN74AVC4T234 PLACE_NEAR=UR400.A7:10MM PACK_IGNORE=TRUE SN74AVC4T234 PLACE_NEAR=UR430.A7:10MM PACK_IGNORE=TRUE

BGA 33 BGA 33
75 18 IN TDM_SPKRAMP_L_BCLK C7 B1 A1 A7 75 TDM_1V8_SPKRAMP_L_FSYNC_R RR401 1 2 TDM_1V8_SPKRAMP_L_FSYNC
5% 1/20W MF 201 OUT 75 107 75 18 IN TDM_SPKRAMP_R_BCLK C7 B1 A1 A7 75 TDM_1V8_SPKRAMP_R_FSYNC_R RR431 1 2 TDM_1V8_SPKRAMP_R_FSYNC
5% 1/20W MF OUT 75 107
75 18 IN TDM_SPKRAMP_L_FSYNC C5 B2 A2 A5 PLACE_NEAR=UR400.A5:10MM PACK_IGNORE=TRUE 75 18 IN TDM_SPKRAMP_R_FSYNC C5 B2 A2 A5 PLACE_NEAR=UR430.A5:10MM PACK_IGNORE=TRUE

75 18 TDM_SPKRAMP_L_R2D C3 B3 A3 A3 33 75 18 TDM_SPKRAMP_R_R2D C3 B3 A3 A3 33
IN
SPKRAMP_RESET_L C1 B4 A4 A1 75 TDM_1V8_SPKRAMP_L_R2D_R RR402 1 2 TDM_1V8_SPKRAMP_L_R2D
5% 1/20W UT 75 107
IN
C1 B4 A4 A1 75 TDM_1V8_SPKRAMP_R_R2D_R RR432 1 2 TDM_1V8 SPKRAMP_R_R2D
5% 1/20W MF OUT 75 107
107 75 N
PLACE_NEAR=UR400.A3:10MM NC PLACE_NEAR=UR430.A3:10MM
SPKRAMP_1V8_RESET_L OUT 75 77 78 80
GND GND
PACK_IGNORE=TRUE PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_QFN SPKRAMP_LVL_4B_QFN SPKRAMP_LVL_4B_QFN SPKRAMP_LVL_4B_QFN

PLACE_NEAR=UR400 14:5MM PLACE_NEAR=UR400.13:5MM PLACE_NEAR=UR430.14:5MM PLACE_NEAR=UR430.13:5MM
1 CR400 1 CR401 1 CR430 1 CR431
0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10%
2 25V
X5R 2 25V
X5R 2 25V
X5R 2 25V
X5R
0201 0201 0201 0201
VCCA VCCB VCCA VCCB
UR400 UR430
SN74AVC4T774-COMBO SN74AVC4T774-COMBO
QFN SPKRAMP_LVL_4B_QFN QFN SPKRAMP_LVL_4B_QFN
75 18 TDM_SPKRAMP_L BCLK 1 A1 B1 12 33 75 18 TDM_SPKRAMP_R_BCLK 1 A1 B1 12 33
15 DIR1 75 TDM_1V8_SPKRAMP_L_BCLK_R RR400 1 2 TDM_1V8_SPKRAMP_L_BCLK
5% 1/20W MF 01
75 107
15 DIR1 75 TDM_1V8_SPKRAMP_R_BCLK_R RR430 1 2 TDM_1V8_SPKRAMP_R_BCLK
5% 1/20W MF
75 107
PLACE_NEAR=UR400.12:10MM PLACE_NEAR=UR400.12:10MM
SPKRAMP_LVL_4B_QFN SPKRAMP_LVL_4B_QFN
75 18 TDM_SPKRAMP_L_FSYNC 2 A2 B2 11 33 75 18 TDM_SPKRAMP_R_FSYNC 2 A2 B2 11 33
16 DIR2
75 TDM_1V8_SPKRAMP_L_FSYNC_R RR401 1 2 TDM_1V8_SPKRAMP_L_FSYNC
5% 1/20W MF 201
75 107
16 DIR2
75 TDM_1V8_SPKRAMP_R_FSYNC_R RR431 1 2 TDM_1V8_SPKRAMP_R_FSYNC
5% 1/20W MF
75 107
75 18 TDM_SPKRAMP_L_R2D 3 A3 B3 10 33 75 18 TDM_SPKRAMP_R_R2D 3 A3 B3 10 33
5 DIR3
75 TDM_1V8_SPKRAMP_L_R2D_R RR402 1 2 TDM_1V8_SPKRAMP_L_R2D
5% 1/20W MF 201
75 107
5 DIR3
75 TDM_1V8_SPKRAMP_R_R2D_R RR432 1 2 TDM_1V8_SPKRAMP_R_R2D
5% 1/20W MF
75 107
SPKRAMP_RESET_L 4 A4 B4 9 SPKRAMP_1V8_RESET_L 4 A4 B4 9
107 75 75 77 78 80
NC
6 DIR4 6 DIR4
7 OE* 7 OE*
GND GND

PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ SPKRAMP_LVL_1B_DTQ SPKRAMP_LVL_1B_DTQ SPKRAMP_LVL_1B_DTQ
PLACE_NEAR=UR410.1:5MM PLACE_NEAR=UR410.6:5MM PLACE_NEAR=UR440.1:5MM PLACE_NEAR=UR440.6:5MM
1 CR410 PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
1 CR411 1 CR440 PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
1 CR441
0.1UF 0.1UF 0.1UF 0.1UF
10%
2 25V
UR410 10%
2 25V
10%
2 25V
UR440 10%
2 25V
X5R SN74AXC1T45 X5R X5R SN74AXC1T45 X5R
0201 X2SON 0201 0201 X2SON 0201
VCCA VCCB VCCA VCCB

5 5
RR410 DIR RR440 DIR
TDM_SPKRAMP_L_D2R 33 TDM_1V8_SPKRAMP_L_D2R TDM_SPKRAMP_R_D2R 33 TDM_SPKRAMP_R_D2R_R TDM_1V8_SPKRAMP_R_D2R

75 18 OUT 1 2 TDM_SPKRAMP_L_D2R_R 3 A
75 B 4 IN 75 107 75 18 OUT 1 2 3 A B 4 IN 75 107
5%
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
1/20W PLACE_NEAR=UR410.3:10MM
MF
201
GND
5%
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
1/20W PLACE_NEAR=UR440.3:10MM
MF
201
75
GND AUDIO
1.2V <-> 1.8V
102 77 76 75 PP1V25_AWAKE_IO
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
PP1V8_AWAKE
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
PACK_IGNORE=TRUE
75 77 78 102
SPKRAMP_LVL_1B_DEA
102 77 76 75 PP1V25_AWAKE_IO
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
PP1V8_AWAKE
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
75
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
7 78 102
LEVEL SHIFTERS
1 CR410 UR410 1 CR411 1 CR440 UR440 1 CR441 MAX PROP DELAY:
0.1UF SN74AXC1T45 0.1UF 0.1UF SN74AXC1T45 0.1UF
10% X2SON-1 10% 10% X2SON-1 10%
2 25V
X5R 2 25V
X5R 2 25V
X5R 2 25V
X5R TP (4-BIT) + TP (1-BIT) < 35 NS
0201 VCCA VCCB 0201 0201 VCCA VCCB 0201
5 5
RR410 DIR RR440 DIR
TDM_SPKRAMP_L_D2R 1
33 2 TDM_SPKRAMP_L_D2R_R 3 4 TDM_1V8_SPKRAMP_L_D2R TDM_SPKRAMP_R_D2R 1
33 2 TDM_SPKRAMP_R_D2R_R 3 4 TDM_1V8_SPKRAMP_R_D2R
75 18 A B 75 107 75 18 A B 75 107
PACK_IGNORE=TRUE PACK_IGNORE=TRUE
5% SPKRAMP_LVL_1B_DEA 75 5% SPKRAMP_LVL_1B_DEA 75
1/20W PLACE_NEAR=UR410.3:10MM / 0W PLACE_NEAR=UR44 3 1 MM
MF GND MF GND
201 201
102 77 76 75 PP1V25_AWAKE_IO 102 77 76 75 PP1V25_AWAKE_IO

SPKRAMP_LVL_1B_SON SPKRAMP_LVL_1B_SON
1 CR410 1 CR440
0.1UF 0.1UF SYNC_MASTER=REF_SPKRAMP_TAS5770 SYNC_DATE=04/16/2020
10% 10%
25 2 2 V PAGE TITLE
X R X5R
0201 SPKRAMP_LVL_1B_SON
UR410
0201 SPKRAMP_LVL_1B_SON
UR440 AUDIO SUPPORT
RR410 SN74AUP1G17 RR440 SN74AUP1G17
SON VCC SON VCC
TDM_SPKRAMP_L_D2R 1
33 2 TDM_SPKRAMP_L_D2R_R 4 2 TDM_1V8_SPKRAMP_L_D2R TDM_SPKRAMP_R_D2R 1
33 2 TDM_SPKRAMP_R_D2R_R 4 2 TDM_1V8_SPKRAMP_R_D2R
75 18 75 107 75 18 75 107
NC NC
5% SPKRAMP_LVL_1B_SON 75 NC 5% SPKRAMP_LVL_1B_SON 75 NC
1/20W PLACE_NEAR=UR410.4:10MM GND 1/20W PLACE_NEAR=UR440.4:10MM GND
MF MF
201 201
2 1
CHANGES FROM PREVIOUS DESIGNS:
- REMOVED LDO TO GENERATE LOCAL 1.8V
<RDAR://50645294>
AUDIO JACK CODEC I2C ADDRESS - CHANGED VL SUPPLY FROM 1.8V TO 1.2V
<RDAR://TBD>
AD1 AD0 ADDRESS
- SUPPLIED VD_FILT EXTERNALLY
GND GND 0X48 <-- <RDAR://TBD>
- CHANGED VP SUPPLY FROM 3.3V TO 3.8V
GND 1.8V 0X49
<RDAR://TBD>
1.8V GND 0X4A
1.8V 1.8V 0X4B
LR500 LR501
FERR-22-OHM-1A-0.055OHM FERR-22-OHM-1A-0.055OHM
BYPASS=UR500.A7:B6:5MM
102 PP1V25_AWAKE_IO 1 2 PP1V2_CODEC_VL_VD PP1V8_CODEC_VA 2 1 PP1V8_AWAKE 102
0201 MIN_LINE_WIDTH=0.1000 MIN_LINE_WIDTH=0.1000 0201 * SEE NOTE
EDC CURRENT = 2 MA MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000 NO_XNET_CONNECTION=1
VOLTAGE=1.225V VOLTAGE=1.8V BYPASS=UR500.B1:C2:4MM EDC CURRENT = 380MA
TDC CURRENT = 10M CR500 1
CR501 1 TDC CURRENT = 150MA
1.0UF
20%
6.3V 2
2.2UF
20%
X5R 10V
0201-1 X5R-CERM 2
402
89 76 GND_AUDIO_CODEC
LR502
FERR-22-OHM-1A-0.055OHM
BYPASS=UR500.A3:B3:5MM PP1V8_CODEC_VCP 2 1
CR502 1 MIN_NECK_WIDTH=0.1500
VOLTAGE=1.8V
BYPASS=UR500.D6:F6:6MM
0201
0.1UF
10%
6.3V 2 CR503 1
CERM-X5R
0201
2.2UF
20%
10V
LR503 X5R-CERM 2
FERR-22-OHM-1A-0.055OHM
* SEE NOTE
402 XWR500
SM
101 PP3V8_AON 1 2 PP3V8_CODEC_VP CODEC_VCP_FILTP CODEC_VCP_FILT_GND 1 2
0201 MIN_LINE_WIDTH=0.3000 MIN_LINE_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000
EDC CURRENT = 850MA MIN_NECK_WIDTH=0.1500 MIN_NECK_WIDTH=0.1500 MIN_NECK_WIDTH=0.1500
VOLTAGE=3.8V
TDC CURRENT = 110MA
BYPASS=UR500.D7:C7:5MM NO_XNET_CONNECTION=1
BYPASS=UR500.E6:F6:4MM
CR504 1 CR505 1 PP1V25_AWAKE_IO
10UF 75 77 102
20% 4.7UF
10V
X5R-CERM 2
20%
16V 2 PP1V25_S2 102
0402-7 X5R NOSTUFF NOSTUFF
0402-1
1 1
NO_XNET_CONNECTION=1 RR502 RR503
BYPASS=UR500.F6:G6:4MM 47K 47K
5% 5%
80 OUT AUDIO_JACK_LEFT_OUT CR506 1 1/20W
MF
1/20W
MF
AUDIO_JACK_RIGHT_OUT 4.7UF
80 OUT
* SEE NOTE 20% 2 201 2 201
NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 16V 2
AUDIO JACK PINOUT X5R
VP VL VD_FILT VA VCP
RR5001 1
RR501 +VCP_FILT E6
0402-1 CODEC_INT_L OUT 6 -> TO SOC
1K 1K CRITICAL G6 CODEC_VCP_FILTN CODEC_WAKE_L
RING SENSE 5% 5% -VCP_FILT OUT 33 -> TO PMU
1/20W 1/20W MIN_LINE_WIDTH=0.2000
TIP SENSE MF
201 2
MF D5 HPSENSA UR500 GNDCP F6 MIN_NECK_WIDTH=0.1500
CODEC_RESET_L <- FROM SOC
2 201 E5 HPOUTA CS42L83A IN 9 80
GND_AUDIO_CODEC C4
89 76
WLCSP-SKT VL_SEL
F5 HPSENSB 1
80 IN AUDIO_JACK_LEFT_SNS G5 HPOUTB DIGLDO_PDN* D4 RR504
AUDIO_JACK_RIGHT_SNS 47K
80 IN B7 5%
LEFT F1 INT* 1/20W
HS4 MF
LEFT SENSE
80 AUDIO_JACK_CH_GND E2 HS_CLAMP2 WAKE* C6 2 201
IN
RIGHT 80 IN AUDIO_JACK_GB_GND E1 HSIN+ C5
* SEE NOTE G2 RESET*
RIGHT SENSE HS3
F2 HS_CLAMP1
GLOBAL GND SPDIF_TX A6
80 IN AUDIO_JACK_CH_MIC D1 HSIN- NC
CHINA MIC
80 IN AUDIO_JACK_GB_MIC SWIRE_SEL D3
* SEE NOTE F4
CHINA GND HS4_REF B5
G4 ASP_LRCK/FSYNC TDM_CODEC_FSYNC IN 18
GLOBAL MIC HS3_REF
80 IN AUDIO_JACK_RING_SNS G3 RING_SENSE SWIRE_SD/ASP_SDIN A5 TDM_CODEC_R2D IN 18
80 AUDIO_JACK_TIP_SNS E4 TIP_SENSE ASP_SDOUT A4 TDM_CODEC_D2R_R 1

33 2
RR505 TDM_CODEC_D2R 6
IN OUT
PLACE_NEAR=UR500.A4:5MM 5% 1/20W MF 201
SWIRE_CLK/ASP_SCLK B4 TDM_CODEC_BCLK 18
CODEC_HSBIAS_FILT F3 IN
HSBIAS_FILT
MIN_LINE_WIDTH=0.2000 E3
MIN_NECK_WIDTH=0.1000 HSBIAS_FILT_REF C3
TO / FROM AD0
AD1 B2
AUDIO JACK 1 CR508
4.7UF SDA A1 I2C_CODEC_SDA BI 41
CONNECTOR 20%
2 16V SCL A2 I2C_CODEC_SCL 41
X5R IN
0402-1 FLYP E7 CODEC_FLYP
BYPASS=UR500.F3:E3:4MM F7 MIN_LINE_WIDTH=0.2000
FLYC CODEC_FLYC MIN_NECK_WIDTH=0.1000
CODEC_HSBIAS_FILT_REF FLYN G7 CODEC_FLYN NO_XNET_CONNECTION=1
MIN_LINE_WIDTH=0.2000 BYPASS=UR500.E7:F7:4MM
FILT_P C1 CODEC_FILT
CR509 1
GNDL GNDD GNDHS GNDA MIN_NECK_WIDTH=0.1000 2.2UF
20%
10V
MIN_LINE_WIDTH=0.2000 X5R-CERM 2
NO_XNET_CONNECTION=1 MIN_NECK_WIDTH=0.1000 402
BYPASS=UR500.C1:C2 4 MM
CR510 1 BYPASS=UR500.F7:G7:4MM
NOTES: XWR501 10UF CR511 1
SM 20%
10V 2
X5R
2.2 F
- SEE TEST POINT SIGNALS & LOCATIONS ON REF DESIGN PAGE 1 1 2 PLACE_NEAR=UR500 G1:1MM 20
0603-1 10V
X5R-CERM 2
MIN_LINE_WIDTH=0.2000 402
- THE FOLLOWING SIGNALS SHOULD HAVE A LOW DCR PATH: 89 76 GND_AUDIO_CODEC MIN_NECK_WIDTH=0 1000
VOLTAGE=0V
- VP SUPPLY
- VCP SUPPLY
- AUDIO_JACK_LEFT/RIGHT_OUT
- AUDIO_JACK_GB/CH_GND
- GB_MIC SIGNAL CONNECTS TO CH_GND AT A/J CONNECTOR. SYNC_MASTER=REF_CODEC_CLIFDEN

CH_MIC SIGNAL CONNECTS TO GB_GND AT A/J CONNECTOR. PAGE TITLE
AUDIO JACK CODEC

- VP SUPPLY RAIL ACCEPTS 3.0V TO 5.25V AND NEEDS TO
COME UP FIRST AND TURN OFF LAST (NEED TO STAY UP
WHEN THE OTHER RAILS GO DOWN)
VP CURRENT CONSUMPTION WITH PART IN LOWEST POWER STATE:
3.1UA (1V8 OFF, RST# LOW)
3.6UA (1V8 ON, RST# LOW)
36UA (1V8 ON, RST# HIGH)
BOM_COST_GROUP=AUDIO
8 7 2
102 78 PP1V8_AWAKE PPBUS_SPKRAMP_LEFT_ISNS 105 102 78 77 75 PP1V8_AWAKE

MAX CURRENT EDC = 4A (PER AMP)
SPKRAMP_A SPKRAMP_A SPKRAMP_A SPKRAMP_A SPKRAMP_A SPKRAMP_A SPKRAMP_A SPKRAMP_A SPKRAMP_A
PLACE_NEAR=UR600.C1:6MM PLACE_NEAR=UR600.C1:4MM PLACE_NEAR=UR600.D2:6MM PLACE_NEAR=UR600.D2:4MM PLACE_NEAR=UR600.C5:5MM PLACE_NEAR=UR600.C5:10MM PLACE_NEAR=UR600.C5:10MMPLACE_NEAR=UR600.C5:10MMPLACE_NEAR=UR600.C5:10MM
1CR600 1CR601 1 CR602 1 CR603 1 CR604 1 CR605 1 CR606 1 CR607 1 CR608 SPKRAMP_A RR605
1UF 0.1UF 1UF 0.1UF 0.1UF 10UF 10UF 10UF 10UF SPKRAMP_A_ADDR 1
0 2
77
20% 10% 20% 10% 10% 20% 20% 20% 20% 0X62
2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 25V
X5R 2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM 2 35V
X5R-CERM 5%
0201 0201 0201 0201 0201 0603 0603 0603 0603 1/20W
MF
0201
AVDD IOVDD VBAT
80 78 77 75 I SPKRAMP_12V8_RESET_L C3 SDZ*
UR600
TAS5770AC0
DSBGA
B2
BYPASS=UR600.B2:B3:10MM
CR609 0.1UF 10
0201 SPKRAMP_A RR601
AMP A 77 SPKRAMP_B_ADDR
SPKRAMP_B RR635
1
470 2
SPKRAMP_A BST_P SPKRAMP_A_BOOTP 1 2 0X64 5%
I2C_1V8_SPKRAMP_L_SDA A3 MIN_LINE_WIDTH=0.1000 25V X5R 0% 1
0 2 0603 SPKRAMP_A_OUTP
1/20W
MF
80 41 BI F3 SDA OUT_P * SEE NOTE OUT 79 89
SPKRAMP_A SPKRAMP_A MF 1/4W MIN_LINE_WIDTH=0.2000 SPKRAMP_A 201
OUT_P B3 SPKRAMP_A_OUTP_R SPKRAMP_A MIN_NECK_WIDTH=0.1000
80 41 I2C_1V8_SPKRAMP_L_SCL F4 SCL MIN_LINE_WIDTH=0.2000 * SEE NOTE PACK_IGNORE=TRUE
IN A1 SPKRAMP_A_VSENSEP
SPKRAMP_A VSNS_P MIN_NECK_WIDTH=0 1000
0.1UF * SEE NOTE SPKRAMP_A IN 79 SPKRAMP_C RR664
80 78 77 6 OUT SPKRAMP_INT_L
SPKRAMP_A
D4 IRQZ
BST_N A2 SPKRAMP_A_BOOTN CR610 1 2
10%
0201 SPKRAMP_A RR602 77 SPKRAMP_C_ADDR 2
470 1
SPKRAMP_A_ADDR D3 MODE A5 MIN_LINE_WIDTH=0.1000 25V X5R 0% 1
0 2 0603 SPKRAMP_A_OUTN 0X66
5%
77 OUT_N * SEE NOTE OUT 79 89
BYPASS=UR600.A2 A5:10MM MF 1/4W MIN_LINE_WIDTH 0.2000 SPKRAMP_A 1/20W
OUT_N B5 SPKRAMP_A_OUTN_R NO_XNET_CONNECTION=1 SPKRAMP_A MIN_NECK_WIDTH=0.1000 MF
107 80 IN TDM_1V8_SPKRAMP_L_R2D F2 SDIN MIN_LINE_WIDTH=0.2000 SEE NOTE 201
SPKRAMP_A SPKRAMP_A PLACE_NEAR=UR600.E1:10MM E1 SDOUT VSNS_N B1 MIN_NECK_WIDTH=0 1000 SPKRAMP_A_VSENSEN IN 79
33 * SEE NOTE SPKRAMP_A
107 80 OUT TDM_1V8_SPKRAMP_L_D2R
SPKRAMP_A
RR600 1 2 TDM_SPKRAMP_A_D2R_R
5% 1/20W AREG D5 SPKRAMP_A_AREG SPKRAMP_A SPKRAMP_A
TDM_1V8_SPKRAMP_L_FSYNC
E2 FSYNC CR611 1 1 CR612
107 80 IN
SPKRAMP_A DREG D1 SPKRAMP_A_DREG 220PF 220PF
F1 SBCLK 10% 10%
107 80 IN TDM_1V8_SPKRAMP_L_BCLK 25V
X7R-CERM 2 2 25V
X7R-CERM
SPKRAMP_A E4 PDMD0 201 201
E3 PDMCK0 NOSTUFF NOSTUFF
SPKRAMP_A SPKRAMP_A SPKRAMP_A SPKRAMP_A
E5 PDMD1 PLACE_NEAR=UR600.D1:3 MMPLACE_NEAR=UR600.D1:5 MMPLACE_NEAR=UR600.D5:3 MMPLACE_NEAR=UR600.D5:5 MM
F5 PDMCK1
1 CR613 1 CR614 1 CR615 1 CR616
PGND
0.1UF 1UF 0.1UF 1UF
10% 20% 10% 20%
GND
2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R
0201 0201 0201 0201
PACK_IGNORE=TRUE
SPKRAMP_EXT_PU
102 76 75 PP1V25_AWAKE_IO
102 78 77 75 PP1V8_AWAKE PPBUS_SPKRAMP_LEFT_ISNS 105
SPKRAMP_B SPKRAMP_B SPKRAMP_B SPKRAMP_B SPKRAMP_B SPKRAMP_B SPKRAMP_B SPKRAMP_B SPKRAMP_B 1
PLACE_NEAR=UR630.C1:6MM PLACE_NEAR=UR630.C1:4MM PLACE_NEAR=UR630.D2:6MM PLACE_NEAR=UR630.D2:4MM PLACE_NEAR=UR630.C5:5MM PLACE_NEAR=UR630.C5:10MM PLACE_NEAR=UR630.C5:10MMPLACE_NEAR=UR630.C5:10MMPLACE_NEAR=UR630.C5:10MM RR691
1CR630 1CR631 1 CR632 1 CR633 1 CR634 1 CR635 1 CR636 1 CR637 1 CR638 5%
47K
1UF 0.1UF 1UF 0 1UF 0.1UF 10UF 10UF 10UF 10UF 1/20W
20% 10% 20% 10% 10% 20% 20% 20% 20% PACK_IGNORE=TRUE MF
2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 25V
X5R 2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM 2 35V
X5R-CERM SPKRAMP_EXT_PU 2 201
0201 0201 0201 0201 0201 0603 0603 0603 0603
AVDD IOVDD VBAT
80 78 77 75 IN SPKRAMP_1V8_RESET_L C3 SDZ*
UR630
TAS5770AC0
DSBGA
B2
CR639 0.1UF 10%

0201 SPKRAMP_B RR631
AMP B 80 78 77 75 IN SPKRAMP_1V8_RESET_L
SPKRAMP_B BST_P SPKRAMP_B_BOOTP 1 2
I2C_1V8_SPKRAMP_L_SDA A3 MIN_LINE_WIDTH=0.1000 25V X5R 0 SPKRAMP_B_OUTP 1
41 BI
SPKRAMP_B F3 SDA OUT_P
B3
0% 1
MF
2 0603
1/4W
* SEE NOTE
MIN_LINE_WIDTH=0.2000 SPKRAMP_B OUT 79 89 RR692
F4 SCL SPKRAMP_B OUT_P SPKRAMP_B_OUTP_R SPKRAMP_B MIN_NECK_WIDTH=0.1000 47K
41 IN I2C_1V8_SPKRAMP_L_SCL MIN_LINE_WIDTH=0.2000 * SEE NOTE 5%
SPKRAMP_B VSNS_P A MIN_NECK_WIDTH=0 1000 SPKRAMP_B_VSENSEP IN 79 1/20W
0.1UF * S E NOTE SPKRAMP_B MF
SPKRAMP_B
D4 IRQZ
BST_N A2 SPKRAMP_B_BOOTN CR640 1 2
10%
0201 SPKRAMP_B RR632 2 201
D3 MODE A5 MIN_LINE_WIDTH=0.1000 0 SPKRAMP_B_OUTN
7 SPKRAMP_B_ADDR OUT_N 25V X5R 0% 1 2 0603 * SEE NOTE OUT 9 89
BYPASS=UR630.A2:A5:10MM MF 1/4W MIN_LINE_WIDTH=0.2000 SPKRAMP_B
OUT_N B5 SPKRAMP_B_OUTN_R NO_XNET_CONNECTION=1 SPKRAMP_B MIN_NECK_WIDTH=0.1000
107 I TDM_1V8_SPKRAMP_L_R2D F2 SDIN M N_LINE_WIDTH=0.2000 * E NOTE
SPKRAMP_B SPKRAMP_B PLACE_NEAR=UR630.E1:10MM E1 SDOUT VSNS_N B1 MI _NECK_WIDTH=0 1000 SPKRAMP_B_VSENSEN IN 9
33 * SEE NOTE SPKRAMP_B
107 OUT TDM_1V8_SPKRAMP_L_D2R
SPKRAMP_B
RR630 1 2 TDM_SPKRAMP_B_D2R_R
5% 1/20W MF 201 AREG D5 SPKRAMP_B_AREG SPKRAMP_B SPKRAMP_B
TDM_1V8_SPKRAMP_L_FSYNC
107 IN
SPKRAMP_B DREG D1 SPKRAMP_B_DREG 220PF 220PF
F1 SBCLK 10% 10%
107 IN TDM_1V8_SPKRAMP_L_BCLK 25V
X7R-CERM 2 2 25V
X7R-CERM
SPKRAMP_B E4 PDMD0 201 201
SPKRAMP_B SPKRAMP_B SPKRAMP_B SPKRAMP_B
F5 PDMCK1
1 CR643 1 CR644 1 CR645 1 CR646
PGND
0.1UF 1UF 0.1UF 1UF
10% 20% 10% 20%
GND
2 25
X5R 2 16
CER-X5R 2 25
X5R 2 16
CER-X5R
0201 0201 0201 0201
102 78 77 75 PP1V8_AWAKE =PPBUS_AON_C_SPKRAMP

PACK_IGNORE=TRUE PACK IGNORE=TRUE PACK IGNORE=TRUE PACK IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE
SPKRAMP_C SPKR MP_C SPKR MP_C SPKR MP_C SPKRAMP_C SPKRAMP_C SPKRAMP_C SPKRAMP_C SPKRAMP_C
PLACE_NEAR=UR660.C1:6MM PLACE_NEAR=UR660.C1:4MM PLACE_NEAR=UR660.D2:6MM PLACE_NEAR=UR660.D2:4MM PLACE_NEAR=UR660.C5 5MM PLACE_NEAR=UR660.C5:10MM PLACE_NEAR=UR660.C5:10MMPLACE_NEAR=UR660.C5:10MMPLACE_NEAR=UR660.C5:10MM
1CR660 1CR661 1 CR662 1 CR663 1 CR664 1 CR665 1 CR666 1 CR667 1 CR668
1UF 0.1UF 1UF 0.1UF 0.1UF 10UF 10UF 10UF 10UF NOTES:
20% 10% 20% 10% 10% 20% 20% 20% 20%
2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R 2 25V
X5R
25
X R
25
X R CERM
25
X R CERM
25
X R CERM
35
X R CERM
0201 0201 0201 0201 0201 0603 0603 0603 0603 - CHECK THAT SPKRAMP_INT_L
HAS IPU ON SOC SIDE.
AVDD IOVDD VBAT
80 78 77 75 IN SPKRAMP_1V8_RESET_L
PACK_IGNORE=TRUE C3 SDZ*
UR660
TAS5770AC0
DSBGA
B2
CR669 0.1UF 10% PACK_IGNORE=TRUE

2 0201 SPKRAMP_C RR661
AMP C - VSENSEP/N SIGNALS CONNECT
TO OUTP/N SIGNALS AT THE
SPEAKER CONNECTOR PINS.
SPKRAMP_C BST_P SPKRAMP_C_BOOTP 1
=I2C_1V8_SPKRAMP_C_SDA A3 MIN_LINE_WIDTH=0.1000 25V X5R 0% 1
0 2 0603 SPKRAMP_C_OUTP
BI PACK_IGNORE=TRUE F3 SDA OUT_P
MFPACK_IG ORE=TRUE
1/4W
* SEE NOTE PACK_IGNO TRUE
OUT - THE FOLLOWING SIGNALS SHOULD
SPKRAMP_C PACK_IGNORE=TRUE B3 MIN_LINE_WIDTH=0.2000 SPKRAMP_C
F4 SCL SPKRAMP_C OUT_P SPKRAMP_C_OUTP_R SPKRAMP_C MIN_NECK_WIDTH=0.1000 HAVE A VERY LOW DCR PATH:
IN =I2C_1V8_SPKRAMP_C_SCL
PACK_IGNORE=TRUE MIN_LINE_WIDTH=0.2000 * SEE NOTE
SPKRAMP_C VSNS_P A1 MIN_NECK_WIDTH=0 1000 SPKRAMP_C_VSENSEP
PACK_IGNORE IN
T E - SPKRAMP_XX_OUTP/N_R
0.1UF ACK_IGNORE=TRUE * SEE NOTE SPKRAMP_C
80 78 77 6 OUT PSPKRAMP_INT_L
CK_IGNORE=TRUE
S KRAMP_C
D4 IRQZ
BST_N A2 PKRAMP_C_BOOTN CR670 1 2
10%
0201 SPKRAMP_C RR662 - SPKRAMP_XX_OUTP/N
SPKRAMP_C_ADDR D3 MODE A5 MIN_LINE_WIDTH=0.1000 25V X5R 0% 1
0 2 0603 SPKRAMP_C_OUTN - PVDD SUPPLY
77 OUT_N * SEE NOTE PACK_IGNOR TRUE
OUT
BYPASS=UR660.A2:A5:10MM MFPACK_IGNORE=TRUE
1/4W MIN_LINE_WIDTH=0.2000 SPKRAMP_C
OUT_N B5 SPKRAMP_C_OUTN_R NO_XNET_CONNECTION=1 SPKRAMP_C MIN_NECK_WIDTH=0.1000 - FOR THERMALS PGND PINS MUST
IN =TDM_1V8_SPKRAMP_C_R2D
PACK_IGNORE=TRUE PACK_IGNORE=TRUE F2 SDIN MIN_LINE_WIDTH=0.2000 * SEE NOTE
SPKRAMP_C SPKRAMP_C PLACE_NEAR=UR660.E1:10MM E1 SDOUT VSNS_N B1 MIN_NECK_WIDTH=0 1000 SPKRAMP_C_VSENSEN
PACK_IGNORE IN
TRUE CONNECT TO GND LAYERS USING
33 PACK_IGNORE=TRUE PACK_IGNORE=TRUE
* SEE NOTE SPKRAMP_C
=TDM_1V8_SPKRAMP_C_D2R
OUT PACK_IGNORE=TRUE
SPKRAMP_C
RR660 1 2 TDM_SPKRAMP_C_D2R_R
5% 1/20W MF 201 AREG D5 SPKRAMP_C_AREG SPKRAMP_C SPKRAMP_C COPIOUS AMOUNT OF VIAS.
=TDM_1V8_SPKRAMP_C_FSYNC
PACK_IGNORE=TRUE
IN
SPKRAMP_C DREG D1 SPKRAMP_C_DREG 220PF 220PF
F1 SBCLK 10% 10
IN =TDM_1V8_SPKRAMP_C_BCLK
PACK_IGNORE=TRUE 25V
X7R-CERM 2 2 25V
X7R-CERM
SPKRAMP_C E4 PDMD0 201 201
PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE SYNC_MASTER=REF_SPKRAMP_TAS5770 SYNC_DATE=04/16/2020
SPKRAMP_C SPKRAMP_C SPKRAMP_C SPKRAMP_C PAGE TITLE
E5 PDMD1 PLACE_NEAR=UR660.D1:3 MM LA E_NEAR=UR660.D1:5 MM LA E_NEAR=UR660.D5:3 MM LA E_NEAR=UR660.D5:5 MM
F5 PDMCK1
1 CR673
0.1UF
1 CR674
1UF
1 CR675
0.1UF
1 CR676
1UF
AUDIO AMPLIFIERS (1/2)
PGND 10% 20% 10% 20%
GND
2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R
0201 0201 0201 0201
7
102 78 77 75 PP1V8_AWAKE PBUS_SPKRAMP_RIGHT_ISNS 105 102 78 77 75 PP1V8_AWAKE

SPKRAMP_D SPKRAMP_D SPKRAMP_D SPKRAMP_D SPKRAMP_D SPKRAMP_D SPKRAMP_D SPKRAMP_D SPKRAMP_D
1CR700 1CR701 1 CR702 1 CR703 1 CR704 1 CR705 1 CR706 1 CR707 1 CR708 SPKRAMP_D RR705
1UF 0.1UF 1UF 0.1UF 0.1UF 10UF 10UF 10UF 10UF SPKRAMP_D_ADDR 1
2.2K 2
78
20% 10% 20% 10% 10% 20% 20% 20% 20% 0X68
2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 25V
X5R 2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM 2 35V
X5R-CERM 5%
0201 0201 0201 0201 0201 0603 0603 0603 0603 1/20W
MF
201
AVDD IOVDD VBAT
80 78 77 75 I SPKRAMP_1V8_RESET_L C3 SDZ*
UR700
TAS5770AC0
DSBGA
B2
CR709 0.1UF 10%

0201 SPKRAMP_D RR701
AMP D 78 SPKRAMP_E_ADDR
0X6A
SPKRAMP_E RR734
2
2.2K 1
SPKRAMP_D BST_P SPKRAMP_D_BOOTP 1 2 5
I2C_1V8_SPKRAMP_R_SDA A3 MIN_LINE_WIDTH=0.1000 25V X5R 0% 1
0 2 0603 SPKRAMP_D_OUTP
1/20W
MF
80 41 BI F3 SDA OUT_P * SEE NOTE OUT 79 89
SPKRAMP_D MF 1/4W MIN_LINE_WIDTH=0.2000 SPKRAMP_D 201
SPKRAMP_D OUT_P B3 SPKRAMP_D_OUTP_R SPKRAMP_D MIN_NECK_WIDTH=0.1000
80 41 I2C_1V8_SPKRAMP_R_SCL F4 SCL MIN_LINE_WIDTH=0.2000 * SEE NOTE PACK_IGNORE=TRUE
IN A1 SPKRAMP_D_VSENSEP
SPKRAMP_D VSNS_P MIN_NECK_WIDTH=0 1000
0.1UF * SEE NOTE SPKRAMP_D IN 79 SPKRAMP_F RR765
SPKRAMP_D
D4 IRQZ
BST_N A2 SPKRAMP_D_BOOTN CR710 1 2
10%
0201 SPKRAMP_D RR702 78 SPKRAMP_F_ADDR 1
10K 2
SPKRAMP_D_ADDR D3 MODE A MIN_LINE_WIDTH=0 1000 25V X5R 0% 1
0 2 0603 SPKRAMP_D_OUTN 0X6C
1%
78 OUT_N * SEE NOTE OUT 79 89
BYPASS=UR700.A2 A5:10MM MF 1/4W MIN_LINE_WIDTH=0.2000 SPKRAMP_D 1/20W
OUT_N B5 SPKRAMP_D_OUTN_R NO_XNET_CONNECTION=1 SPKRAMP_D MIN_NECK_WIDTH=0.1000 MF
107 80 IN TDM_1V8_SPKRAMP_R_R2D F2 SDIN MIN_LINE_WIDTH=0.2000 SEE NOTE 201
SPKRAMP_D SPKRAMP_D PLACE_NEAR=UR700.E1:10MM E1 SDOUT VSNS_N B1 MIN_NECK_WIDTH=0 1000 SPKRAMP_D_VSENSEN IN 79
33 * SEE NOTE SPKRAMP_D
107 80 OUT TDM_1V8_SPKRAMP_R_D2R
SPKRAMP_D
RR700 1 2 TDM_SPKRAMP_D_D2R_R
5% 1/20W AREG D5 SPKRAMP_D_AREG SPKRAMP_D SPKRAMP_D
TDM_1V8_SPKRAMP_R_FSYNC
107 80 IN
SPKRAMP_D DREG D1 SPKRAMP_D_DREG 220PF 220PF
F1 SBCLK 10% 10%
107 80 IN TDM_1V8_SPKRAMP_R_BCLK 25V
X7R-CERM 2 2 25V
X7R-CERM
SPKRAMP_D E4 PDMD0 201 201
SPKRAMP_D SPKRAMP_D SPKRAMP_D SPKRAMP_D
F5 PDMCK1
1 CR713 1 CR714 1 CR715 1 CR716
PGND
0.1UF 1UF 0.1UF 1UF
10% 20% 10% 20%
GND
2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R
0201 0201 0201 0201
102 78 77 75 PP1V8_AWAKE PPBUS_SPKRAMP_RIGHT_ISNS 105

SPKRAMP_E SPKRAMP_E SPKRAMP_E SPKRAMP_E SPKRAMP_E SPKRAMP_E SPKRAMP_E SPKRAMP_E SPKRAMP_E
1UF 0.1UF 1UF 0 1UF 0.1UF 10UF 10UF 10UF 10UF
20% 10% 20% 10% 10% 20% 20% 20% 20%
2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 25V
X5R 2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM 2 35V
X5R-CERM
0201 0201 0201 0201 0201 0603 0603 0603 0603
AVDD IOVDD VBAT

UR730
TAS5770AC0
0.1UF
AMP E
SPKRAMP_E C3 SDZ*
DSBGA
BST_P B2 SPKRAMP_E_BOOTP CR739 1 2
10%
0201 SPKRAMP_E RR731
I2C_1V8_SPKRAMP_R_SDA A3 MIN_LINE_WIDTH=0.1000 25V X5R 0% 1
0 2 0603 SPKRAMP_E_OUTP
41 BI F3 SDA OUT_P * SEE NOTE OUT 79 89
SPKRAMP_E MF 1/4W MIN_LINE_WIDTH=0.2000 SPKRAMP_E
OUT_P B3 SPKRAMP_E_OUTP_R SPKRAMP_E MIN_NECK_WIDTH=0.1000
41 I2C_1V8_SPKRAMP_R_SCL F4 SCL SPKRAMP_E MIN_LINE_WIDTH=0.2000 * SEE NOTE
IN A SPKRAMP_E_VSENSEP
SPKRAMP_E VSNS_P MIN_NECK_WIDTH=0 1000 IN 79
0.1UF * SEE NOTE SPKRAMP_E
SPKRAMP_E
D4 IRQZ
BST_N A2 SPKRAMP_E_BOOTN CR740 1 2
10%
0201 SPKRAMP_E RR732
D3 MODE A5 MIN_LINE_WIDTH=0.1000 0 SPKRAMP_E_OUTN
7 SPKRAMP_E_ADDR OUT_N 25V X5R 0% 1 2 0603 * SEE NOTE OUT 9 89
BYPASS=UR730.A2:A5:10MM MF 1/4W MIN_LINE_WIDTH=0.2000 SPKRAMP_E
OUT_N B5 SPKRAMP_E_OUTN_R NO_XNET_CONNECTION=1 SPKRAMP_E MIN_NECK_WIDTH=0.1000
107 I TDM_1V8_SPKRAMP_R_R2D F2 SDIN M N_LINE_WIDTH=0.2000 * SEE NOTE
SPKRAMP_E SPKRAMP_E PLACE_NEAR=UR730.E1:10MM E1 SDOUT VSNS_N B1 MI _NECK_WIDTH=0 1000 SPKRAMP_E_VSENSEN IN 9
33 * SEE NOTE SPKRAMP_E
107 OUT TDM_1V8_SPKRAMP_R_D2R
SPKRAMP_E
RR730 1 2 TDM_SPKRAMP_E_D2R_R
5% 1/20W MF 201 AREG D5 SPKRAMP_E_AREG SPKRAMP_E SPKRAMP_E
TDM_1V8_SPKRAMP_R_FSYNC
107 IN
SPKRAMP_E DREG D1 SPKRAMP_E_DREG 220PF 220PF
F1 SBCLK 10% 10%
107 IN TDM_1V8_SPKRAMP_R_BCLK 25V
X7R-CERM 2 2 25V
X7R-CERM
SPKRAMP_E E4 PDMD0 201 201
SPKRAMP_E SPKRAMP_E SPKRAMP_E SPKRAMP_E
F5 PDMCK1
1 CR743 1 CR744 1 CR745 1 CR746
PGN
0.1UF 1UF 0.1UF 1UF
10% 20% 10% 20%
GND
2 25
X5R 2 16V
CER-X5R 2 25
X5R 2 16
CER-X5R
0201 0201 0201 0201
102 78 77 75 PP1V8_AWAKE =PPBUS_AON_F_SPKRAMP

PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE
SPKRA P_F SPKRAMP_F SPKRAMP_F SPKRAMP_F SPKRAMP_F SPKRAMP_F SPKRAMP_F SPKRAMP_F SPKRAMP_F
1UF 0.1UF 1UF 0.1UF 0.1UF 10UF 10UF 10UF 10UF
20% 10% 20% 10% 10% 20% 20% 20% 20%
2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R 2 25V
X5R
25V
X R 2 25V
X5R-CERM 2 25V
X5R-CERM
25V
X R-CERM
35V
X5R-CERM
0201 0201 0201 0201 0201 0603 0603 0603 0603
AVDD IOVDD VBAT NOTES:
PACK_IGNORE=TRUE C3 SDZ*
UR760
TAS5770AC0
DSBGA
B2
CR769 0.1UF 10% PACK_IGNORE=TRUE

2 0201 SPKRAMP_F RR761
AMP F - VSENSEP/N SIGNALS CONNECT
TO OUTP/N SIGNALS AT THE
SPEAKER CONNECTOR PINS.
SPKRAMP_F BST_P SPKRAMP_F_BOOTP 1
=I2C_1V8_SPKRAMP_F_SDA A3 MIN_LINE_WIDTH=0.1000 25V X5R 0% 1
0 2 0603 SPKRAMP_F_OUTP
BI PACK_IGNORE=TRUE F3 SDA OUT_P
MFPACK_IG ORE=TRUE
1/4W
* SEE NOTE PACK_IGNO TRUE
OUT - THE FOLLOWING SIGNALS SHOULD
SPKRAMP_F PACK_IGNORE=TRUE B3 MIN_LINE_WIDTH=0.2000 SPKRAMP_F
F4 SCL SPKRAMP_F OUT_P SPKRAMP_F_OUTP_R SPKRAMP_F MIN_NECK_WIDTH=0.1000 HAVE A VERY LOW DCR PATH:
IN =I2C_1V8_SPKRAMP_F_SCL
PACK_IGNORE=TRUE MIN_LINE_WIDTH=0.2000 * SEE NOTE
SPKRAMP_F VSNS_P A1 MIN_NECK_WIDTH=0 1000 SPKRAMP_F_VSENSEP
PACK_IGNORE IN
T E - SPKRAMP_XX_OUTP/N_R
0.1UF ACK_IGNORE=TRUE * SEE NOTE SPKRAMP_F
80 78 77 6 OUT PSPKRAMP_INT_L
CK_IGNORE=TRUE
S KRAMP_F
D4 IRQZ
BST_N A2 SPKRAMP_F_BOOTN CR770 1 2
10%
0201 SPKRAMP_F RR762 - SPKRAMP_XX_OUTP/N
SPKRAMP_F_ADDR D3 MODE A5 MIN_LINE_WIDTH=0.1000 25V X5R 0% 1
0 2 0603 SPKRAMP_F_OUTN - PVDD SUPPLY
78 OUT_N * SEE NOTE PACK_IGNOR TRUE
OUT
BYPASS=UR760.A2:A5:10MM MFPACK_IGNORE=TRUE
1/4W MIN_LINE_WIDTH=0.2000 SPKRAMP_F
OUT_N B5 SPKRAMP_F_OUTN_R NO_XNET_CONNECTION=1 SPKRAMP_F MIN_NECK_WIDTH=0.1000 - FOR THERMALS PGND PINS MUST
IN =TDM_1V8_SPKRAMP_F_R2D
PACK_IGNORE=TRUE PACK_IGNORE=TRUE F2 SDIN MIN_LINE_WIDTH=0.2000 * SEE NOTE
SPKRAMP_F SPKRAMP_F PLACE_NEAR=UR760.E1:10MM E1 SDOUT VSNS_N B1 MIN_NECK_WIDTH=0 1000 SPKRAMP_F_VSENSEN
PACK_IGNORE IN
TRUE CONNECT TO GND LAYERS USING
33 PACK_IGNORE=TRUE PACK_IGNORE=TRUE
* SEE NOTE SPKRAMP_F
=TDM_1V8_SPKRAMP_F_D2R
OUT PACK_IGNORE=TRUE
SPKRAMP_F
RR760 1 2 TDM_SPKRAMP_F_D2R_R
5% 1/20W MF 201 AREG D5 SPKRAMP_F_AREG SPKRAMP_F SPKRAMP_F COPIOUS AMOUNT OF VIAS.
=TDM_1V8_SPKRAMP_F_FSYNC
PACK_IGNORE=TRUE
IN
SPKRAMP_F DREG D SPKRAMP_F_DREG 220PF 220PF
F1 SBCLK 10% 10%
IN =TDM_1V8_SPKRAMP_F_BCLK
PACK_IGNORE=TRUE 25V
X7R-CERM 2 2 25V
X7R-CERM
SPKRAMP_F E4 PDMD0 201 201
PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE PACK_IGNORE=TRUE SYNC_MASTER=REF_SPKRAMP_TAS5770 SYNC_DATE=04/16/2020
SPKRAMP_F SPKRAMP_F SPKRAMP_F SPKRAMP_F PAGE TITLE
E5 PDMD1 LA E_NEAR=UR760.D1:3 MM LA E_NEAR=UR760.D1:5 MM LA E_NEAR=UR760.D5:3 MM LA E_NEAR=UR760.D5:5 MM
F5 PDMCK1
1 CR773
0.1UF
1 CR774
1UF
1 CR775
0.1UF
1 CR776
1UF
AUDIO AMPLIFIERS (2/2)
PGND 10% 20% 10% 20%
GND
2 25V
X5R 2 16V
CER-X5R 2 25V
X5R 2 16V
CER-X5R
0201 0201 0201 0201
2 1
LEFT AUDIO AMP CONNECTOR LEFT AUDIO AMP PBUS BULK CAPS
XWR800 PPBUS_SPKRAMP_LEFT_ISNS 105
CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE
77 OUT SPKRAMP_A_VSENSEP 2 1
128S0264 128S0264 128S0264
SM APN:518S00019 1 1 1
CR800 CR801 CR802
XWR801 CRITICAL 68UF 68UF 68UF
20% 20% 20%
77 OUT SPKRAMP_A_VSENSEN 2 1 JR800 2 16V
POLY-TANT
2 16V
POLY-TANT
2 16V
POLY-TANT
SM FF14A-14C-R11DL-B-3H CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM
NO_XNET_CONNECTION=1 F-RT-SM1
16
14
89 77 IN SPKRAMP_A_OUTP
13
12
11
89 77 IN SPKRAMP_A_OUTN
10
102 79 PP1V25_AWAKE_IO 9
8
NOSTUFF 89 77 IN SPKRAMP_B_OUTP
7
1
RR800 6
47K 5
5%
1/20W 89 77 IN SPKRAMP_B_OUTN
MF 4
201 2
3
2
89 6 OUT SPKR_ID0 1
XWR802
77 OUT SPKRAMP_B_VSENSEP 2 1
SM
XWR803
77 OUT SPKRAMP_B_VSENSEN 2 1
SM
RIGHT AUDIO AMP CONNECTOR RIGHT AUDIO AMP PBUS BULK CAPS
XWR850 PPBUS_SPKRAMP_RIGHT_ISNS105
CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE
78 OUT SPKRAMP_D_VSENSEP 2 1
128S0264 128S0264 128S0264
SM APN:518S00019 1 1 1
CR850 CR851 CR852
XWR851 CRITICAL 68UF 68UF 68UF
20% 20% 20%
78 OUT SPKRAMP_D_VSENSEN 2 1 JR850 2 16V
POLY-TANT
2 16V
POLY-TANT
2 16V
POLY-TANT
SM FF14A-14C-R11DL-B-3H CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM
NO_XNET_CONNECTION=1 F-RT-SM1
16
14
89 78 IN SPKRAMP_D_OUTP
13
12
11
89 78 IN SPKRAMP_D_OUTN
10
1 2 9 PP1V25_AWAKE_IO 9
8
NOSTUFF 89 78 IN SPKRAMP_E_OUTP
7
1
RR850 6
47K 5
5%
1/20W 89 78 IN SPKRAMP_E_OUTN
MF 4
201 2
3
2
89 6 OUT SPKR_ID1 1
XWR852
78 OUT SPKRAMP_E_VSENSEP 2 1
SM
XWR853
78 OUT SPKRAMP_E_VSENSEN 2 1
SM
SYNC_MASTER=KELVIN T668_MLB
PAGE TITLE
SY C_DA E=0 /18 2019
A
AUDIO CONNECTORS: AMPS
6 2 1
AUDIO JACK FLEX CONNECTOR DIGITAL MIC FLEX CONNECTOR
DMIC_CLK0_1V8_OUT IN 74 89
APN: 516S1064
MATES WITH APN: 516S0573 ON FLEX RR941
APN: 518S0818
0 DMIC_DATA0_1V8_IN
JR900 JR940 2 OUT 4
51338-0374 FF14A-6C-R11DL-B-3H 5%
1/20W
F-ST-SM F-RT-SM
MF
32 31 7 0201
PLACE_NEAR=JR940.2:8MM
89 80 AUD_CONN_LEFT_OUT 2 1 AUD_CONN_LEFT_OUT 80 89
1 LR940
4 3 AUD_CONN_SLEEVE 80 89
2 89 AUD_DMIC0_DATA_CONN VOLTAGE=1.8V
FERR-470-OHM
89 80 AUD_CONN_SLEEVE 6 5 AUD_CONN_RIGHT_OUT 80 89
3 89 PP1V8_DMIC 1 2 PP1V8_S2 101
89 80 AUD_CONN_RIGHT_OUT 8 7 4 0201
89 80 AUD_CONN_RING2 10 9 AUD_CONN_RING2 80 89
5 89 AUD_DMIC1_DATA_CONN
AUD_CONN_RING_SENSE 12 11 AUD_CONN_TIP_SENSE 6 DMIC_CLK1_1V8_OUT
1 CR940
89 80 80 89 I 4 9
1UF
89 80 AUD_CONN_RIGHT_SNS 14 13 AUD_CONN_LEFT_SNS 80 89
20%
2 16V
89 80 AUD_CONN_SLEEVE_XW 16 15 AUD_CONN_RING2_XW 80 89
8
RR943 CER-X5R
0201
18 17 0
MIN_LINE_WIDTH=0.2000 1 2 DMIC_DATA1_1V8_IN OUT 74
20 19 MIN_NECK_WIDTH=0 1000 PP1V8_TOUCHID_FILT_CONN 86 89
5%
90 89 34 33 OUT PMU_ONOFF_L 22 21 TOUCHID_INT_1V8_CONN OUT 86 89 1/20W
MF
89 18 OUT SPI_TOUCHID_MOSI 24 23 SPI_TOUCHID_MISO IN 6 86 89 0201
89 18 OUT SPI_TOUCHID_CLK 26 25 TOUCHID_BOOST_EN OUT 86 89 PLACE_NEAR=JR940.5:8MM
89 86 PP16V0_TOUCHID_FILT_CONN MIN_LINE_WIDTH=0 2000 28 27 PP1V8_AON 104
89 86 80 PP3V0_TOUCHID_FILT_CONN MIN_LINE_WIDTH=0 2000 30 29 AMR_RIGHT_OR_ND_1V8 OUT 73 74 89
89 86 80 PP3V0_TOUCHID_FILT_CONN MIN_LINE_WIDTH=0 2000 34 33
1 CR990 1 CR991 1 CR992 1 CR993 1 CR994 1 CR995 1 CR996 1 CR997

100PF 100PF 100PF 100PF 100PF 100PF 100PF 100PF
5% 5% 5% 5% 5% 5% 5% 5%
2 50V
C0G 2 50V
C0G 2 50V
C0G
50V
2 C0G 2 50V
C0G 2 50V
C0G 2 50V
C0G 2 50V
C0G
0201 0201 0201 0201 0201 0201 0201 0201
ESD:PROJECT DEPENDENT
CODEC_RESET_L IN 9 76
NOSTUFF
1 CR900
1000PF
10%
2 25V
X7R
CRITICAL 0201
FLR901
120-OHM-25%-1.3A
76 IN AUDIO_JACK_LEFT_OUT 1 2 AUD_CONN_LEFT_OUT 80 89
0402 CRITICAL
FLR902
120-OHM-25%-1.3A
76 IN AUDIO_JACK_RIGHT_OUT 1 2 AUD_CONN_RIGHT_OUT 80 89
CRITICAL 0 2
FLR903
120-OHM-25%-1.3A
76 OUT AUDIO_JACK_GB_GND 1 2 AUD_CONN_RING2 80 89
0402 CRITICAL TPR901 TPR900
FLR904 A 1 SPKRAMP_INT_L 6 77 78 1
A SPKRAMP_1V8_RESET_L 75 7 78
120-OHM-25%-1.3A TP P5 TP-P5
76 OUT AUDIO_JACK_CH_GND 1 2 AUD_CONN_SLEEVE 80 89 TPR902
1 TDM_1V8_SPKRAMP_L_BCLK
TPR920
1 TDM_1V8_SPKRAMP_R_BCLK
CRITICAL 0402 A PLACE_NEAR=UR600.F1:20MM
7 107 A PLACE_NEAR=UR700.F1:20MM
78 107
TP-P5 TP-P5
FLR905 TPR903 TPR921
120-OHM-25%-1.3A TDM_1V8_SPKRAMP_L_FSYNC 1 TDM_1V8_SPKRAMP_R_FSYNC
A PLACE_NEAR=UR600.E2:20MM
77 107 A PLACE_NEAR=UR700.E2:20MM
78 107
76 OUT AUDIO_JACK_LEFT_SNS 1 2 AUD_CONN_LEFT_SNS 80 89 TP-P5 TP-P5

0402 CRITICAL TPR904
1 TDM_1V8_SPKRAMP_L_R2D
TPR922
1 TDM_1V8_SPKRAMP_R_R2D
FLR906 A PLACE_NEAR=UR600.F2:20MM
77 107 A PLACE_NEAR=UR700.F2:20MM
78 107
120-OHM-25%-1.3A TP-P5 TP-P5
AUDIO_JACK_RIGHT_SNS 1 2 AUD_CONN_RIGHT_SNS
TPR905
1 TDM_1V8_SPKRAMP_L_D2R
TPR923
1 TDM_1V8_SPKRAMP_R_D2R
76 OUT 80 89 A PLACE NEAR SOC
77 107 A PLACE NEAR SOC
78 107
0402 TP P5 TP-P5
LR907 TPR906
1 I2C_1V8_SPKRAMP_L_SCL
TPR924
1 I2C_1V8_SPKRAMP_R_SCL
FERR-470-OHM A 4 77 A 41 78
TP-P5 TP-P5
76 OUT AUDIO_JACK_TIP_SNS 1 2 AUD_CONN_TIP_SENSE 80 89
TPR907 TPR925
0201
A 1 I2C_1V8_SPKRAMP_L_SDA 41 77 1
A I2C_1V8_SPKRAMP_R_SDA 41 78
LR908 TP-P5 TP-P5

FERR-470-OHM
76 OUT AUDIO_JACK_RING_SNS 1 2 AUD_CONN_RING_SENSE 80 89
CRITICAL 0201
FLR909
120-OHM-25%-1.3A
76 OUT AUDIO_JACK_GB_MIC 1 2 AUD_CONN_SLEEVE_XW 80 89
0402 CRITICAL
FLR910 C M TE
PAGE TITLE
E V N T M NC TE
A
120-OHM 25%-1.3A
76 OUT AUDIO_JACK_CH_MIC 1 2 AUD_CONN_RING2_XW 80 89
AUDIO CONNECTORS: DMIC, JACK
0402
2 1
518S0818
JT000
FF14A-6C-R11DL-B-3H
F-RT-SM
7
NC
NC 4
89 KBDLED_CATHODE1_R 5
MIN_NECK_WIDTH=0.1000 6
518S00116
JT002
FF14A-10C-R11DL-B-3H
F-RT-SM1
11
RT046 1
PPVOUT_KBDLED 1
0 2 89 PPVOUT_S0_KBDLED_CONN 2
104
5% MIN_NECK_WIDTH=0.2000
1 CT059 1 CT055 1/16W VOLTAGE=40V NC
MF-LF 89 72 KBDLED_CATHODE1 4
2.2UF 001UF 402 MIN_LINE_WIDTH=0.2000 5
10% 1 % MIN_NECK_WIDTH=0.1000
2 50V 2 50V
X5R X7R-CERM 89 72 KBDLED_CATHODE2 6
0603 0402 MIN_LINE_WIDTH=0.2000 7
8
NC
89 KBDLED_CATHODE2_R 9
12
5 8S0818
JT001
FF14A-6C-R11DL-B-3H
F-RT-SM
7
1
2
NC 3
NC 4
5
SYNC_MASTER=T668_MLB SYNC_DATE=05/16/2019
PAGE TITLE
KEYBOARD BLC CONNECTORS
6
*** OK2PLACE ***
TIE TO SAME VOLTAGE AS TPAD
CONTROLLER, EITHER 1V8 OR 3V3 KEYBAORD IOX1 ALL PLATFORMS CONNECT TO 1V8 3.3V RSLOC ISOLATION KEYS/ASIC RESET
105 82 PP1V85_S2_KBD_ISNS PP1V85_S2_KBD_ISNS 82 83 105
104 82 PP3V3_AON
1 CT110 1 CT112 1 CT113 1 CT114 PLACE_NEAR=UT103.10:5MM PLACE_NEAR=UT103.10:2MM
1.0UF 0.1UF 0.1UF 10UF 1 CT150 1 CT151
20% 10% 10% 20%
2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 10V
X5R-CERM
1.0UF 0.1UF
20% 10%
0201-1 0201 0201 0402-7 2 6.3V 2 6.3V
138S0692 132S0444 132S0444
X5R CERM-X5R
0201-1 0201
TO/FROM TRACKPAD IOX1 DOESN'T SEND THE INTERRUPT

INSTEAD, IOX2 SENDS INT WHEN
138S0692 132S0444
A KEY IS PRESSED
22 1 105 3 PP1V85_S2_KBD_ISNS
82 IOXP1_INT_L INT* P0_0 KBD_DRIVE_Y0 IN 83 89
2 (2.97 < VDD < 3.63)
18 P0_1 KBD_DRIVE_Y1 83 89
RT110 CKPLUS_WAIVE=I2C_PULLUP
ADDR UT101 P0_2
3
KBD_DRIVE_Y2
IN
83 89
1
RT190 IN_X:
VDD
OUT_X:
33 IN 0
19 PCAL6416A 4 VIH_MIN 2.0V VOH_MIN 2.4V
117 89 85 82 IN I2C_KBD_SCL 2 1 IOXP_I2C_SCL
20
SCL
HWQFN
P0_3
5
KBD_DRIVE_Y3 IN 83 89 5%
1/20W
VIL_MAX 0.8V
100K IPD
UT103 VOL_MAX 0.4V
12.5K IPU OE
PLACE_NEAR=JT400.8:10MM 1% SDA P0_4 KBD_DRIVE_Y4 IN 83 89 MF SLG4AP4815V
1/20W 6
2 MF 24 P0_5 KBD_DRIVE_Y5 83 89
2 0201 TQFN
DZT110 201 2 IOXP1_RESET_L RESET*
P0_6
7
KBD_DRIVE_Y6
IN
IN 83 89 OUT123_EN 4
OE
343S00073
5.5V-0.28PF 8 (OD)
0201-THICKSTNCL P0_7 KBD_DRIVE_Y7 83 89 9
1 CT111 10
IN
KBD_RIGHT_SHIFT_KEY 1
IN 1
OUT 1 KBD_RIGHT_SHIFT_L 82
1 0.1UF P1_0 KBD_DRIVE_Y8 IN 83 89

ADD NEW IO FOR KBD_DRIVE_Y8
FOR J293/313/314/316 AND AFTER
89 83 IN (OD)
8
10% 11 CONNECT THE DRIVE_Y8 TO ESD 2 OUT 2 KBD_LEFT_OPTION_L 82
2 6 3V
CERM-X5R P1_1 IN KBD_LEFT_OPTION_KEY IN 2 (OD)
0201 12
HW_ID1 2
RT1441 1K OUT 3
7
KBD_CONTROL_L
P1_2 3 82
132S0444 311S0665 13 ADD HW ID PIN STRAPPING 89 83 IN KBD_CONTROL_KEY IN 3
RT111 WRITE: 0X40

P1_3
14 NC 1% 1/20W
BOMOPTION=KBD_NEW
MF 201 STUFF FOR NEW KBD MATRIX
NOSTUFF FOR OLD KBD MATRIX (OD)
RT152
CKPLUS_WAIVE=I2C_PULLUP P1_4 NC OUT_ALL# 6 RSLOC_RST_L 33 PMU_RSLOC_RST_L
I2C_KBD_SDA 2
33 1 IOXP_I2C_SDA READ: 0X41 15 1 2 OUT 33 34 89 90
117 89 85 82 BI P1_5 NC
16 1%
PLACE_NEAR=JT400.9:10MM 1% P1_6 KBD_ID_DETECT1 82 1/20W
1/20W 17 MF
2 MF P1_7 CAPSLOCK_LED_EN 82 GND EPAD 201
DZT111 201
5.5V-0.28PF
0201-THICKSTNCL
RT112
89 85 OUT KBD_INT_L 2
33 1 IOXP2_INT_L
TIE TO SAME VOLTAGE AS TPAD
CONTROLLER, EITHER 1V8 OR 3V3 KEYBAORD IOX2 ALL PLATFORMS CONNECT TO 1V8
PLACE_NEAR=JT400.9:10MM 1% 105 82 PP1V85_S2_KBD_ISNS PP1V85_S2_KBD_ISNS 82 83 105

1/20W
2 MF
DZT112 201
1
1 CT120 1 CT121 1 CT122
5.5V-0.28PF RT121 1.0UF
20%
0.1UF
10%
0.1UF
10%
0201-THICKSTNCL 100K
5% 2 6.3V
X5R 2 6.3V
CERM-X5R 2 10V
X5R-CERM
1/20W 0201-1 0201 0201
1 MF
2 201 138S0692 132S0444
22 1
INT* P0_0 KBD_SENSE_X0 IN 82 83 89
2
18 P0_1 KBD_SENSE_X1 82 83 89
2 IOXP2_ADDR ADDR UT102 P0_2
3
KBD_SENSE_X2
IN
82 83
IN
19 PCAL6416A 4
KBD_SENSE_X3
SCL P0_3 IN 82 83 89
20 HWQFN 5
KBD_SENSE_X4
SDA P0_4 IN 82 83 89
6
24 P0 5 KBD_SENSE_X5 IN 82 83 89
82 O P2_RESET_L RE ET* 7
P0_6 KBD_SENSE_X6 IN 82 83 89
8
P0_7 KBD_SENSE_X7 82 83 89
1 CT123 10
IN
0.1UF P1_0 KBD_SENSE_X8 IN 82 83 89
10% 11
2 6.3V
CERM-X5R P1_1 KBD_SENSE_X9 IN 82 83 89
12
0201 P1_2 KBD_SENSE_X10 IN 82 83 89
132S0444 311S0665 13
WRITE: 0X42 14
READ: 0X43 15
P1_5 KBD_CONTROL_L 82
16
P1_6 KBD_LEFT_OPTION_L 82
17
PP1V85_S2_KBD_ISNS 82 83 105 P1_7 KBD_RIGHT_SHIFT_L 82
RT130 10K 1 2
5% 1/20W MF 201
KBD_SENSE_X0 82 83 89
RT131 10K 1 2
5% 1/20W MF 201
RT132 10K 1 2
5% 1/20W MF 201
RT133 10K 1 2
5% 1/20W MF 201
RT134 10K 1 2 KBD_SENSE_X4 82 83 89
RT135 10K 1 2
5%
5%
1/20W
1/20W
MF 201
F 201
KBD_SENSE_X5 82 83 89 NOTE: THIS CAN BE THE SAME RAIL AS
THE CAPSLOCK LED, OR IT CAN BE A RAIL
CAPSLOCK LED DRIVER
RT136 10K 1 2
5% 1/20W MF 201
KBD_SENSE_X6 82 83 89 THAT COMES UP AFTER CURRENT CONTROLLED LED DRIVING FROM J214/J223/J230
DIFFERENT FROM RESISTANCE CONTROL LED DRIVING FROM J152
RT137 10K 1 2
5% 1/20W MF 201
104 PP3V3_S2
RT138 10K 1 2
5% 1/20W MF 201
RT139 10K 1 2
5% 1/20W MF 201
1 CT105
RT140 10K 1 2 KBD_SENSE_X10 82 83 89
1.0UF
5% 1/20W MF 201 20%
RT141 10K 1 2
5% 1/20W MF 201
KBD_SENSE_X11 82 83 89 2 6.3V
X5R
VIN
RT142 10K 1 2 KBD_SENSE_X12 82 83 89
0201-1
RT143 1K 2 1
5% 1/20W MF 201
IOXP2_ADDR 82
138S0692 UT105
1% 1/20W MF 201 RT161 VIH_MIN 1.2V FAN5622 R_SET 19.1K RT118
VIL_MAX 0.4V SSOT23 15 MA SINK
CAPSLOCK_LED_EN 1K LED_CTRL 1 KBD_LED1 1.00 2 KBD_CAP_CATHODE
82 1 2 CTRL LED1 6 1 IN 83 89
PP1V85_S2_KBD_ISNS 82 105 5% LED2 4 1%

1/20W LED_ISET 5 ISET 1/20W
MF MF-LF
201 <R_SET> 0201
RT120 10K 1 2 IOXP2_RESET_L 2
1 1
GND
RT122 10K 1 2
5% 1/20W MF 201
IOXP1_RESET_L 82
RT162 RT160
5% 1/20W MF 201 200K 19.1K
RT123 1.3K 2 1
1% 1/20W MF 201
I2C_KBD_SCL 82 85 89 117
3V3 KBD CONN SERIES R 5%
1/20W
1%
1/20W
RT124 1 3K 2 1
1% 1/20W MF 201
I2C_KBD_SDA 82 85 89 117
KBD DRI REQUEST, TO MEASURE CAPSLOCK LED CURRENT
MF
201 2
MF
201 2
RT125 100K 1 2
5% 1/20W MF 201
IOXP1_INT_L 82
RT103 TO KBD CONN AND ESD

PP3V3_AON 1
0 2 PP3V3_AON_KBD_CONN
104 82 83
5% MIN_LINE_WIDTH=0.2000
1/20W VOLTAGE=3.3V
MF
0201 SYNC_MASTER=REF_KBD_SUPPORT
PAGE TITLE
ID_DETECT SERIES R KEYBOARD IOX, SUPPORT
RT117
KBD_ID_DETECT1 1
1K 2 KBD_ID1
82 IN 83 89
5% KBD_ID PIN ON KBD CONNECTOR

1/20W ANSI: NO CONNECT
MF ISO: TIED HIGH TO PP1V8
201 JIS: TIED LOW TO GND
BOM_COST_GROUP=KEYBOARD
5 4 2 1
KEYBOARD ESD
DZT202 DZT201 DZT204
PESD3V3L5UF PESD3V3L5UF PESD3V3L5UF
SOT886 SOT886 SOT886
KBD_CAP_CATHODE 1 6 KBD_DRIVE_Y0 1 6 KBD_CONTROL_KEY KBD_SENSE_X10 1 6 KBD_SENSE_X11
89 83 82 BI BI 82 83 89
NC BI 83 89 89 83 82 BI BI 82 83 89
5 KBD_DRIVE_Y6 82 83 89 KBD_LEFT_OPTION_KEY 82 83 9
5 KBD_SENSE_X4 82 83 89
I BI BI
89 83 82 KBD_DRIVE_Y5 3 4 KBD_DRIVE_Y7 82 83 89 89 83 82 PP3V3_AON_KBD_CONN 3 4 KBD_RIGHT_SHIFT_KEY 82 83 89 89 83 82 KBD_SENSE_X9 3 4 KBD_SENSE_X12 82 83 89

BI BI BI BI BI
DZT203 DZT206 DZT205

PESD3V3L5UF PESD3V3L5UF PESD3V3L5UF
SOT886 SOT886 SOT886
89 83 82 KBD_SENSE_X8 1 6 KBD_SENSE_X7 82 83 89 89 83 82 KBD_DRIVE_Y4 1 6 KBD_DRIVE_Y3 82 83 89 89 83 82 KBD_SENSE_X3 1 6 KBD_SENSE_X5 82 83 89

BI BI BI BI BI BI
5 KBD_SENSE_X6 82 83 89
5 KBD_DRIVE_Y1 82 83 89
5 KBD_SENSE_X2 82 83 89
BI BI BI
89 83 82 KBD_DRIVE_Y8 3 4 KBD_ID1 82 83 89 105 83 82 PP1V85_S2_KBD_ISNS 3 4 KBD_DRIVE_Y2 82 83 89 89 83 82 KBD_SENSE_X0 3 4 KBD_SENSE_X1 82 83 89

BI BI BI BI BI BI
MEMBRANE ZIF CONNECTOR

518S0752
CRITICAL
FF14A-30C-R11DL-B-3H
JT200
F-RT-SM
31
105 83 2 PP1V85_S2_KBD_ISNS 1
89 83 82 BI KBD_ID1 2
3
89 83 82 BI KBD_DRIVE_Y8 4
8 83 82 BI KBD_SENSE_X0 9
89 82 BI KBD_SENSE_X1 10
89 83 82 B KBD_SENSE_X3 13
89 83 82 BI KBD_SENSE_X12 15
89 83 82 BI KBD_SENSE_X11 17
89 83 82 BI KBD_SENSE_X10 18
89 82 BI KBD_SENSE_X7 20
89 83 82 B KBD_DRIVE_Y7 23
89 83 82 BI KBD_CAP_CATHODE 26
89 83 82 BI PP3V3_AON_KBD_CONN 27
89 83 82 BI KBD_RIGHT_SHIFT_KEY 28
8 83 82 BI KBD_LEFT_OPTION_KEY 29
89 82 BI KBD_CONTROL_KEY 30
32
PAGE TITLE
KEYBOARD SIGNAL CONNECTOR, ESD
BOM_COST_GROUP=KEYBOARD
2 1
TRACKPAD SPI BUS LEVEL SHIFTER (+1.2V TO +1.8V)
102 84 PP1V25_AWAKE_IO PP1V85_S2_IPD 84 104
SN74AVC4T774 Truth Table
BYPASS=UT360::5MM BYPASS=UT360::5MM NOSTUFF NOSTUFF NOSTUFF
RT303 1 CT360 1 1 CT361 RT361 1
RT362 1
RT3631 RT3731 CTRL INPUTS OUTPUT CIRCUITS
47K
5%
0.1UF
10%
6.3V 2
0.1UF
10% 100K
5%
100K
5%
100K
5%
100K
5%
OPERATION
2 6.3V
1/20W
MF
201 2
CERM-X5R
0201
VCCA
UT360
VCCB CERM-X5R
0201
1/20W
MF
201 2
1/20W
MF
201 2
1/20W
MF
201 2
1/20W
MF
201 2
/OE DIR A PORT B PORT
SN74AVC4T774-COMBO
6 IN SPI_IPD_CS_L 1
15
A1
QFN
B1 12 SPI_TPAD_CS_CONN_L OUT 85 89 L L Enabled Hi-Z B data to A data
DIR1
20
18 IN SPI_IPD_CLK 2
16
A2 B2 11 SPI_TPAD_CLK_CONN_R RT375 1
1/20W 5%
2
MF 201
SPI_TPAD_CLK_CONN OUT 85 89 L H Hi-Z Enabled A data to B data
DIR2 PLACE_NEAR=UT360.11:2MM
20
18 IN SPI_IPD_MOSI 3
5
A3
311S00129
B3 10 SPI_TPAD_MOSI_CONN_R RT376 1
1/20W 5%
2
MF 201
SPI_TPAD_MOSI_CONN OUT 85 89 H X Hi-Z Hi-Z Isolation
RT304 DIR3 PLACE_NEAR=UT360.10:2MM
SPI_IPD_MISO 20 SPI_IPD_MISO_R 4
6 OUT 1 2 A4 B4 9 SPI_TPAD_MISO_CONN IN 85 89
1/20W 5% MF 201
PLACE NEAR=UT360.5:2MM 6 DIR4
7 OE*
GND
RT3741 RT3711 RT3721
100K 100K 100K
1 1 1 5% 5% 5%
RT377 RT379 RT378 1/20W
MF
1/20W
MF
1/20W
MF
47K 47K 47K 201 2 201 2 201 2
5% 5% 5%
1/20W 1/20W 1/20W
MF MF MF
201 2 201 2 201 2
IPD LDO TRACKPAD SPI ENABLE LEVEL SHIFTER

1.85 V FOR TRACKPAD AND KEYBOARD IOX 102 84 PP1V25_AWAKE_IO PP1V8_AWAKE 102
UT301 LOAD CAP:3.2UF NOM BYPASS=UT355::5MM BYPASS=UT355::5MM

SCY99258 NOSTUFF
EDP:0.42 A CT355 1 1CT356 1
101 PP3V8_AON 4 IN
XDFN-COMBO-THICKSTNCL 0.1UF 0.1UF RT354
OUT 1 PP1V85_S2_IPD 84 104
10%
6.3V 2 VCC_A VCC_B
10% 100K
353S01993 2 6.3V 5%
IPD_P1V8_PWR_EN_RC 3 EN CERM-X5R
UT355 CERM-X5R 1/20W
1 CT301 1 CT302 1 CT303
0201
N74AUP1T34-COMBO
0201 MF
1UF GND E AD SON 2 201
10% 1UF 2.2UF
2 10V
X5R-CERM 10% 20% 6 IN IPD_SPI_EN 2 A B 4 SPI_TPAD_EN_CONN OUT 85 9
0402 2 10V 2 6.3V
X5R-CERM X5R-CERM 5
BYPASS=UT301.4::3MM 0402 0201 1 NC NC 1
BYPASS=UT301.1::3MM RT352 311S0 177 RT353
47K GND 100K
RT301 5%
1/20W
5%
1/20W
IPD_PWR_EN_GATE 2
255K 1
MF MF
84 201 2 2 201
1%
1/20W
MF
201
RT398 DT301
X3DFN2
1
1K 2 IPD_PWR_EN_RES K A
5%
1/20W NSR01L30MXT5G-COMBO
NOSTUFF
RT3991
47K
MF
201 371S00062
1 CT304 IPD SPI INTERRUPT LEVEL SHIFTER
5% 0.01UF
1/20W 10%
MF 2 25V
201 2 X5R-CERM
0201 102 PP1V25_S2 PP1V8_S2 101
1
RT380 1 CT380 1
RT381
10K 0.1UF 100K
5% 10% 5%
VCC
1/20W 2 6.3V
CERM-X5R 1/20W
MF UT380 0201 MF
2 20 74AUP1G07GF 2 201
3.3V S2 LDO FOR TPAD 106 OUT IPD_SPI_INT_L 4 Y

SOT891
A 2 SPI_TPAD_INT_CONN_L IN 85 89
NC 5 NC NC 1 NC
101 PP3V8_AON OPEN DRAIN AT TPAD MCU
GND
CT390 1
1.0UF
AND GATE FOR IPD_PWR_EN
20%
6.3V 2 104 89 PP1V8_AON
X5R PLACE_NEAR=UT311.6:5MM
0201-1
150mA max
+/-1.5% DC max error
1 CT311
UT390 0.1UF
10%
TLV70733PDQN 6.3V
2 CERM-X5R
4 DQN
IN OUT 1 PP3V3_S2_TPAD 104
0201
IPD_P3V3_PWR_EN_RC 3 EN 353S3332 UT311
THRM 6
NSR01L30MXT5G-COMBO GND PAD 74LVC1G08FW5
P5VS2_PWR_EN_RC 2 DFN1010
DT302
X3DFN2
RT397 1 CT391 37 34 33 IN B
4 IPD_PWR_EN_GATE
1K 1.0UF Y 84
84 IPD_PWR_EN_GATE A K IPD_PWR_EN_D 1 2 20% 92 34 33 IN IPD_PWR_EN 1

2 6.3V
X5R
A NC SYNC_MASTER=WUDI_T668_MLB SYNC_DATE=04/16/2020
5% 0201-1
37 S00062 3 PAGE TITLE
1/20W
MF
201
NC
RADAR:61370457 J293 ANG GATE FOR IPD_PWR_EN AND 5VS2_EN
TRACKPAD SUPPORT
RT396
1
470K 2
5%
NOSTUFF
1/20W
MF 1 CT392 RT311
201
0.01UF 1
0 2
10%
2 25V
X5R-CERM 5%
0201 1/20W
MF
0201
BOM_COST_GROUP=TRACKPAD
2 1
MATES WITH 518S00080 ON TRACKPAD FLEX
516S00187
JT400
DF40C-50DS-0.4V-51
F-ST-SM
43 IN I2C_SMC_IPD_1V8_SCL 2 1 IPD_LID_OPEN_1V8 IN 33 73 87 89
43 BI I2C_SMC_IPD_1V8_SDA 4 3 TPAD_KBD_WAKE_L OUT 34 89
89 82 OUT KBD_INT_L 6 5
117 89 82 BI I2C_KBD_SDA 8 7 SPI_TPAD_INT_CONN_L OUT 84 89
10 9
117 89 82 OUT I2C_KBD_SCL 12 11 SPI_TPAD_MOSI_CONN IN 84 89
14 13 SPI_TPAD_CS_CONN_L IN 84 89
16 15 SPI_TPAD_MISO_CONN OUT 84 89
18 17 SPI_TPAD_EN_CONN I 84 89 LT400
20 19 SPI_TPAD_CLK_CONN 84 89
FERR-120-OHM-1.5A
IN
22 21 89 PP5V_S2_TPAD_CONN 1 2 PP5V_S2_TPAD_ISNS 105
VOLTAGE=5 0402A
24 23
26 25 PP1V85_S2_TPAD_ISNS 105 CT400 1
28 27 0.1UF
10%
30 29 PP3V3_S2_TPAD_ISNS 105
25V 2
X5R
32 31 402
34 33
36 35
38 37
40 39
42 41
101 PPBUS_AON 44 43
46 45
48 47
50 49
XWT401
SM
89 ACT_GND 2 1
PAGE TITLE
TRACKPAD CONNECTOR
BOM_COST_GROUP=TRACKPAD
TOUCHID POWER SEQUENCING REQUIREMENTS

POWER ON: 1V8 -> 3V3 -> 16V0
EMC FILTER
16V BOOST LOAD CAP:6.6UF NOM
MIN_NECK_WIDTH=0.1000 FLT600 MIN_NECK_WIDTH=0.1000
VOLTAGE=16V 80-OHM-25%-500MA VOLTAGE=16V
EDP:13.75MA PP16V0_TOUCHID 1 2 PP16V0_TOUCHID_FILT_CONN 80 8
PLACE_NEAR=UT600:5MM UT600 0201
BYPASS=UT600.C3::4MM
LT601 MIN_LINE_WIDTH=0.2000 LM3638A0 1 CT624 1 CT625 1 CT626 BYPASS=UT600.C3::4MM
1.0UH-0.4A-0.636OHM MIN_NECK_WIDTH=0.1000
VOLTAGE=16V BGA 2.2UF
20%
2.2UF
20% 5%
56PF BYPASS=UT600.C3::5MM 1 CT627
1 2 PP16V0_TOUCHID_SW B1 100PF
SW 2 25V
X5R 2 25V
X5R 2 25V
NP0-C0G 5%
0402 DIDT=TRUE 0402-3 0402-3 0201 2 25V
C0G
105 86 PP3V8_MESA_ISNS A2 VIN VOUT C3 0201 OUTPUT VOLTAGE 16.0V +/- 2%
BYPASS=UT600.A2::3MM B2 EN_M IOUT (MAX AVG) 6MA

89 80 TOUCHID_BOOST_EN A3 EN_S
CT610 1 IN
OCP (MIN) 13 MA
10UF C2 LDOIN PMID C1 PP17V0_LDOIN
20% 1 ACTIVE DISCHARGE 15 MA SINK
6.3V 2
CERM-X5R RT620
100K PGND AGND 1 CT623
0402-9 5% MAX OUTPUT CAP 0.5UF @ 16V
1/20W 353S00671 2.2UF
MF 20%
201 2 25V
X5R
2 0402-3
VOLTAGE=17V
3.0V LDO MIN_LINE_WIDTH=0.2000

VOLTAGE=3V
EMC FILTER
UT610 LOAD CAP:14.3UF NOM FLT610 MIN_NECK_WIDTH=0.1000
NCP160AMX300 EDP:100MA 80-OHM-25%-500MA VOLTAGE=3V
4 XDFN-COMBO-THICKSTNCL
105 86 PP3V8_MESA_ISNS IN
OUT 1 PP3V0_TOUCHID 1 2 PP3V0_TOUCHID_FILT_CONN 80 89
86 PP1V8_TOUCHID 3 EN BYPASS=UT610.1::3MM 0201

1 CT611 CT616
1.0UF GND EPAD 1 CT620 1 CT621 1 CT622 1 CT628 1 CT629 OUTPUT VOLTAGE 3.0V +/- 2%
20% 1.0UF
2 6.3V
X5R 353S00599 20% 2.2UF 2.2UF 2.2UF 0.1UF 100PF
0201-1 2 6.3V
X5R
20% 20% 20% 10% 5% IOUT (MAX AVG) 250MA
0201-1 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
CERM-X5R 2 25V
C0G
BYPASS=UT610.4::3MM 0201 0201 0201 0201 0201 DROPOUT VOLTAGE 155MV
OCP (MIN) 250 MA
ACTIVE DISCHARGE 280 OHM TYP
102 PP1V25_S2
RT610 1 1.85 V LDO

47K LOAD CAP:3.4UF NOM
1%
1/20W EDP:0.5MA
MF
201 2
UT620 MIN_LINE_WIDTH=0.2000
SCY99217AMX185TBG MIN_NECK_WIDTH=0.1000
X2DFN VOLTAGE=1.8V
105 86 PP3V8_MESA_ISNS 4 IN OUT 1 PP1V8_TOUCHID 86
OUTPUT VOLTAGE 1.825 V +/- 2%
353S02314 BYPASS=UT620.1::3MM
1 CT612 TOUCHID_PWR_EN 3 EN 1 CT614 IOUT (MAX AVG) 250 MA
1.0UF 94 6 IN
20%
2 6.3V
X5R
GND EPAD 1.0UF
20% EMC FILTER DROPOUT VOLTAGE 75MV TYP @ 100MA
2 6.3V
0201-1
BYPASS=UT620.4::3MM
X5R
0201-1 FLT620 MIN_LINE_WIDTH=0.2000
OCP (MIN) 250 MA
80-OHM-25%-500MA MIN_NECK_WIDTH=0.1000
VOLTAGE=1.8V
1 2 PP1V8_TOUCHID_FILT_CONN 80 89 ACTIVE DISCHARGE 280 OHM TYP
BYPASS=UT620.1::3MM 0201
MIN OUTPUT CAP 1.0 UF
CT618 1 1 CT617
2.2UF 100PF
20% 5%
UT620 CHANGED FROM 353S00754 TO 353S02212 FOR 1.2V EN SIGNAL SUPPORT. 6.3V 2 25V
X5R-CERM 2 C0G
0201 0201
RT650
TOUCHID_INT_1V8_CONN 1
665 2 TOUCHID_INT SPI_TOUCHID_MISO
89 80 IN OUT 6 89 80 6 BI
1%
1/20W
MF
1
RT651 1 RT641
201 1.33K 100K
1%
1/20W
MF
5%
1/20W
MF PAGE TITLE
A
2 201 201
2
TOUCHID SUPPORT
BOM_COST_GROUP=TOUCH ID
8 2 1
**OK2INTEGRATE** DFR V3 SUPPORT
89 88 87 41 PP1V8_AWAKE_DFR
2
S
RT702 QT700 DFR TOUCH CONN DFR DISP CONN
IPD_LID_OPEN_1V8 100K
73 33 2 1 IPD_LID_OPEN_1V8_R 1 DMP31D0UFB4
89 85 IN
5% G DFN1006H4-3 JT700 JT710
1/20W DF40SG(1.5)-26DS-0.4V
MF
201
AA07-S022VA1 F-ST-SM
D F-ST-SM
24 28 27 LT710
3.25-OHM-0.1A-2.4GHZ
3 2 TAM0605-4SM
2 GND 1 4 SYM_VER-2 1 MIPI_DFR_CLK_P IN 7
GND_VOID=TRUE
89 DFR_LID_OPEN_L 2 1 TP_DFR_TOUCH_PANEL_DETECT 9
89 87 DFR_DISP_VSYNC 4 3 89 MIPI_DFR_CLK_CONN_FILT_P
89 TP_DFR_TOUCH_RSVD 4 3 DFR_DISP_VSYNC 87 8
1 89 UT DFR_1V8_DISP_TE 6 5 89 MIPI_DFR_CLK_CONN_FILT_N 3 2 MIPI_DFR_CLK_N IN 7
RT706 6 5 GND_VOID=TRUE
LT711
100K 89 88 IN SPI_1V8_DFR_CS_L 8 7 SPI_1V8_DFR_MISO OUT 88 89 8 GND 7 3.25-OHM-0.1A-2.4GHZ
5% GND_VOID=TRUE
1/20W 89 88 IN SPI_1V8_DFR_MOSI 10 9 SPI_1V8_DFR_CLK IN 88 89 TAM0605-4SM
MF 89 88 6 OUT DFR_1V8_DISP_INT 10 9 89 MIPI_DFR_DATA_CONN_FILT_P 4 SYM_VER-2 1 MIPI_DFR_DATA_P<0> IN 7
201 2 12 11
89 88 6 IN DFR_1V8_DISP_RESET_L 12 11 89 MIPI_DFR_DATA_CONN_FILT_N
41 IN I2C_DFR_RES_SCL 14 13 DFR_1V8_TOUCH_INT_L OUT 88 89 GND_VOID=TRUE
41 BI I2C_DFR_RES_SDA 16 15 DFR_1V8_TOUCH_CLK32K_RESET_L IN 88 89 14 GND 13 3 2 MIPI_DFR_DATA_N<0> IN 7
LT700 89 88 6 IN DFR_1V8_TOUCH_RESET_L 18 17
16 15
1.2UH-20%-0.12A-1.17OHM 89 88 87 41 PP1V8_AWAKE_DFR 20 19 TP_DFR_TOUCH_ROM_WC 89
18 17 PP1V8_AWAKE_DFR 41 87 88 89
104 PP5V_S2 1 2 89 PP5V_S2_DFR_FILT 22 21 PP1V8_AWAKE_DFR 1 87 88 89
0402 MIN_NECK_WIDTH=0.1200 20 19
MIN_LINE_WIDTH=0.2000 NOSTUFF
VOLTAGE=5V BYPASS=JT700.21::5MM 89 87 PP3V3_AWAKE_DFR 22 21 I2C_DFR_RES_SCL 41
CT700 1 CT701 1 25
24 23 I2C_DFR_RES_SDA
IN
41
4.7UF
20%
4.7UF
20%
26 1 CT706 BI
25V 2 25V 2 0.1UF 26 GND 25

X5R X5R 10%
0402 0402 2 6.3V
X5R
0201 CT710 1
30 29
BYPASS=JT710.17::3MM
0.1UF
10%
1 CT711
6.3V 2 1 0UF
X5R 20
0201 2 6.3V
X5R
0201-1
105 PP3V8_AON_DFR_ISNS DFR 1.8V LDO EDP: 230MA 105 PP3V8_AON_DFR_ISNS DFR 3.3V LDO EDP: 3.1A NOTE: THIS IS INRUSH CURRENT SPEC ONLY.THE LDO WILL CURRENT LIMIT THIS VALUE.
BYPASS=UT700.4::3MM TDP: 2MA BYPASS=UT710.4::3MM TDP: 109MA
CT702 1 UT700 VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000 CT712 1 UT710 VOLTAGE=3.3V
SCY99217AMX180 MIN_NECK_WIDTH=0.1200 SCY99217AMX330 MIN_NECK_WIDTH=0.1200
1UF X2DFN-COMBO 1UF X2DFN-COMBO
10%
10V
4 IN OUT 1 PP1V8_AWAKE_DFR 41 87 88 89 10%
10V
4 IN OUT 1 PP3V3_AWAKE_DFR 87 89
X5R-CERM 2 X5R-CERM 2
0402 BYPASS=UT700 3MM
0402
DFR_PWR_EN_R 3 EN 89 88 87 41 PP1V8_AWAKE_DFR 3 EN BYPASS=UT710.1::3MM
NOSTUFF GND EPAD CT703 1 GND EPAD CT713 1
RT701 1 CT704 1UF 1UF

RT711 1
10% 10%
10V
DFR_PWR_EN 1
0 2
47K 1UF 10V X5R-CERM 2
94 88 6 IN 5% 20% X5R-CERM 0402
1/20W 16V 2 0402
5% MF CER-X5R
1/20W 201 2 0201
MF
0201
OUTPUT VOLTAGE 1.8V +/- 2% OUTPUT VOLTAGE 3.3V +/- 2%
IOUT (MAX AVG) 250MA IOUT (MAX AVG) 250MA PAGE TITLE
DROPOUT VOLTAGE 80MV TYP @ 250MA DROPOUT VOLTAGE 80MV TYP @ 250MA DFR SUPPORT 1
OCP (MIN) 250 MA OCP (MIN) 250 MA
ACTIVE DISCHARGE 280 OHM TYP ACTIVE DISCHARGE 280 OHM TYP
MAX OUTPUT CAP MAX OUTPUT CAP
BOM_COST_GROUP=TOUCH BAR
**OK2INTEGRATE** DFR V3 SUPPORT
102 88 PP1V25_AWAKE_IO
102 88 PP1V25_AWAKE_IO PP1V8_AWAKE_DFR 41 87 88 89
BYPASS=UT820::5MM BYPASS=UT820::5MM 89 88 87 41 PP1V8_AWAKE_DFR BYPASS=UT860 5MM
1 CT820 1 CT821 1
1 CT860 SPI0 MISO IS A BOOTSTRAP PIN, TRI-STATE BUFFER PROVIDES ISOLATION
0.1UF 0.1UF RT860 0.1UF
10% 10% 100K 10%
2 10V
X5R-CERM 2 10V
X5R CERM 5% 2 10V
X5R-CERM
0201
VCCA VCCB
02 1 1/ 0
MF 0201 UT860
201 A2 74AUP1G126
2 BGA-YZP
UT820 SPI_1V8_DFR_MISO B1 C2 SPI_DFR_MISO_R SPI_DFR_MISO
SPI_DFR_CS_L 2 1A 74AVC2T45 89 87 IN RT85633 1 2 OUT 4 6
1B 7 SPI_1V8_DFR_CS_L 126
A Y
106 88 6 IN VSSOP OUT 87 89 OE 1/20W 5% 201 MF
88 9 IN DFR_TOUCH_CLK32K_RESET_L 3 2A 2B 6 DFR_1V8_TOUCH_CLK32K_RESET_R_L RT85733 1 2 DFR_1V8_TOUCH_CLK32K_RESET_L OUT 87 89
A1
1/20W 5% 201 MF
5 DIR C1
DFR_PWR_EN IN 6 87 94
GND
BYPASS=UT880::5MM
PP1V25_AWAKE_IO PP1V8_AWAKE_DFR
1 CT880
102 88
BYPASS=UT830::5MM BYPASS=UT830::5MM
41 87 88 9
0.1UF
10%
1 CT831 1 CT830 2 10V
X5R-CERM
0.1UF 0.1UF 0201
10% 10% UT880
2 10V
X5R-CERM 2 10V
X5R-CERM SN74AUP1G17
VCC SON
0201 0201
VCCA VCCB DFR_1V8_DISP_TE 2 4 DFR_DISP_TE
89 87 IN OUT 7
NC
UT830 NC
74AVC2T45 1 GND
18
88 IN SPI_DFR_MOSI 2 1A VSSOP 1B 7 SPI_1V8_DFR_MOSI_R RT85433 1 2
1/20W 5% 201 MF
SPI_1V8_DFR_MOSI OUT 87 89 RT880
100K
18
88 IN SPI_DFR_CLK 3 2A 2B 6 SPI_1V8_DFR_CLK_R RT85533 1 2 SPI_1V8_DFR_CLK OUT 87 89 5%
1/20W 5% 201 MF 1/20W
5 DIR MF
201
2
GND
BYPASS=UT890::5MM
89 88 87 41 PP1V8_AWAKE_DFR 1 CT890
RT890 0.1UF
1 100K 10%
5% 2 10V
X5R-CERM
1/20W
MF 0201
201
1 2 88 PP1V25_AWAKE_IO 2
UT890
SN74AUP1G17
VCC SON
1 1
RT800 RT801 89 87 IN DFR_1V8_TOUCH_INT_L 2 4 DFR_TOUCH_INT_L OUT 6
47K 47K NC
NC
5% 5% GND
1/20W 1/20W
MF MF
201 2 201 2
106 88 6 SPI_DFR_CS_L
88 9 DFR_TOUCH_CLK32K_RESET_L
89 87 6 DFR_1V8_TOUCH_RESET_L
89 87 6 DFR_1V8_DISP_INT
89 87 6 DFR_1V8_DISP_RESET_L
88 18 SPI_DFR_MOSI
88 18 SPI_DFR_CLK
RT802 1 RT803 1 RT804 1 RT805 1 RT806 1

47K 47K 100K 100K 100K
5% 5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF
201 2 201 2 201 2 201 2 201 2
PAGE TITLE
DFR SUPPORT 2
BOM_COST_GROUP=TOUCH BAR
2 1
DFU/DEBUG POWER RAILS AJ/MESA DMIC
18 IN EUSB_ATC0_R_P TOP 1 TP TPU600 TP-P5 101 IN PPBUS_AON OP 1 TP TPU6A0 TP-P5 80 IN AUD_CONN_LEFT_OUT TOP 1 TP TPU6K0 TP-P5 80 74 N DMIC_CLK0_1V8_OUT TOP 1 TP TPU6T9 TP-P5
18 IN EUSB_ATC0_R_N TOP 1 TP TPU601 TP-P5 TOP 1 TP TPU6A1 TP-P5 80 IN AUD_CONN_SLEEVE TOP 1 TP TPU6K1 TP-P5 80 IN AUD_DMIC0_DATA_CONN TOP 1 TP TPU6U0 TP-P5
90 56 33 5 IN SOC_FORCE_DFU TOP 1 TP TPU602 TP-P5 TOP 1 TP TPU6A2 TP-P5 80 IN AUD_CONN_RIGHT_OUT TOP 1 TP TPU6K2 TP-P5 80 IN PP1V8_DMIC TOP 1 TP TPU6U1 TP-P5
94 56 19 5 IN SOC_DFU_STATUS TOP 1 TP TPU603 TP-P5 TOP 1 TP TPU6A3 TP-P5 80 IN AUD_CONN_RING2 TOP 1 TP TPU6K3 TP-P5 80 74 IN DMIC_CLK1_1V8_OUT TOP 1 TP TPU6U2 TP-P5
56 18 6 IN UART_DEBUGPRT_R2D TOP 1 TP TPU604 TP-P5 TOP 1 TP TPU6A4 TP-P5 80 IN AUD_CONN_TIP_SENSE TOP 1 TP TPU6K4 TP-P5 80 IN AUD_DMIC1_DATA_CONN TOP 1 TP TPU6U3 TP-P5
56 18 6 IN UART_DEBUGPRT_D2R TOP 1 TP TPU605 TP-P5 TOP 1 TP TPU6A5 TP-P5 80 IN AUD_CONN_LEFT_SNS TOP 1 TP TPU6K5 TP-P5 GND TOP 1 TP TPU6U4 TP-P5
56 18 9 N SWD_SOC_SWCLK TOP 1 P TPU606 TP-P5 TOP 1 TP TPU6A6 TP-P5 80 IN AUD_CONN_RING2_XW TOP 1 TP TPU6K6 TP-P5
56 18 9 IN SWD_SOC_SWDIO TOP 1 TP TPU607 TP-P5 TOP 1 TP TPU6A7 TP-P5 80 IN AUD_CONN_RING_SENSE TOP 1 TP TPU6K7 TP-P5
56 9 IN UART_SMC_DEBUGPRT_R2D TOP 1 TP TPU608 TP-P5
101 PP3V8_AON TOP 1 TP TPU6A8 TP-P5
80 IN AUD_CONN_RIGHT_SNS TOP 1 TP TPU6K8 TP-P5
56 9 IN UART_SMC_DEBUGPRT_D2R TOP 1 TP TPU609 TP-P5
IN
PPVDD_PCPU_AWAKE TPU6A9 IN AUD_CONN_SLEEVE_XW TOP 1 TP TPU6K9 TP-P5
106 IN TP_SOC_AMUX_OUT TOP 1 TP TPU610 TP-P5
101
101
IN
PPVDD_GPU_AWAKE
TOP
TOP
1 TP
1 TP TPU6B0
TP-P5
TP-P5
86 IN PP1V8_TOUCHID_FILT_CONN TOP 1 TP TPU6L0 TP-P5 TRACKPAD
18 9 IN SMC_FIXTURE_MODE_L TOP 1 TP TPU611 TP-P5
101
IN
PPVDD_CPU_SRAM_AWAKE TOP 1 TP TPU6B1 TP-P5
86 80 6 IN SPI_TOUCHID_MISO TOP 1 TP TPU6L1 TP-P5
87 85 73 33 IPD_LID_OPEN_1V8 TOP 1 TP TPU6U5 TP-P5
43 9 IN I2C_SMC_UPC_SDA TOP 1 TP TPU612 TP-P5
101
IN
PPVDD_ECPU_AWAKE TOP 1 TP TPU6B2 TP-P5
80 18 IN SPI_TOUCHID_MOSI TOP 1 TP TPU6L2 TP-P5
43
IN
I2C_SMC_IPD_1V8_SCL TOP 1 TP TPU6U6 TP-P5
43 9 IN I2C_SMC_UPC_SCL TOP 1 TP TPU613 TP-P5
102
IN
PP1V8_AWAKE TOP 1 TP TPU6B3 TP-P5
86 80 IN TOUCHID_INT_1V8_CONN TOP 1 TP TPU6L3 TP-P5
85 34
IN
TPAD_KBD_WAKE_L TOP 1 TP TPU6U7 TP-P5
107 100 67 33 IN PMU_SYS_ALIVE TOP 1 TP TPU614 TP-P5
102
IN
PP1V25_AWAKE_IO TOP 1 TP TPU6B4 TP-P5
80 18 IN SPI_TOUCHID_CLK TOP 1 TP TPU6L4 TP-P5
43
IN
I2C_SMC_IPD_1V8_SDA TOP 1 TP TPU6U8 TP-P5
94 55 33 5 IN PMU_ACTIVE_READY TOP 1 TP TPU615 TP-P5
101
IN
PPVDD_SOC_S1 TOP 1 TP TPU6B5 TP-P5
86 80 IN TOUCHID_BOOST_EN TOP 1 TP TPU6L5 TP-P5
85 82
IN
KBD_INT_L TOP 1 TP TPU6U9 TP-P5
90 80 34 33 N PMU_ONOFF_L TOP 1 P TPU616 TP-P5
101
IN
PPVDD_DISP_S1 TOP 1 TP TPU6B6 TP-P5
104 73 IN PP1V8_AON TOP 1 TP TPU6L6 TP-P5
85 4
IN
SPI_TPAD_INT_CONN_L TOP 1 TP TPU6V0 TP-P5
90 82 34 33 IN PMU_RSLOC_RST_L TOP 1 TP TPU617 TP-P5
101
IN
PPVDD_DCS_S1 TOP 1 TP TPU6B7 TP-P5
86 80 IN PP16V0_TOUCHID_FILT_CONN TOP 1 TP TPU6L7 TP-P5
117 85 82
IN
I2C_KBD_SDA TOP 1 TP TPU6V1 TP-P5
100 96 91 33 6 IN SOC_SOCHOT_L TOP 1 TP TPU618 TP-P5
101
IN
PP1V8_S2 TOP 1 TP TPU6B8 TP-P5
0 74 73 IN AMR_RIGHT_OR_ND_1V8 TOP 1 TP TPU6L8 TP-P5
85 84
IN
SPI_TPAD_MOSI_CONN TOP 1 TP TPU6V2 TP-P5
100 90 74 33 9 5 IN PMU_RESET_L TOP 1 TP TPU619 TP-P5
IN
TOP 1 TP TPU6F0 TP-P5
86 IN PP3V0_TOUCHID_FILT_CONN TOP 1 TP TPU6L9 TP-P5
117 85 82
IN
I2C_KBD_SCL TOP 1 TP TPU6V3 TP-P5
90 33 IN PMU_SHDN TOP 1 TP TPU620 TP-P5
102 PP1V2_S2 TOP 1 TP TPU6B9 TP-P5
OP 1 TP TPU6M0 TP-P5
85 84
IN
SPI_TPAD_CS_CONN_L TOP 1 TP TPU6V4 TP-P5
96 56 IN USB_DBG_LS_N TOP 1 TP TPU634 TP-P5
102
IN
PP3V3_S2_UPC TOP 1 TP TPU6C0 TP-P5
GND TOP 1 TP TPU6M1 TP-P5
85 84
IN
SPI_TPAD_MISO_CONN TOP 1 TP TPU6V5 TP-P5
96 56 IN USB_DBG_LS_P TOP 1 TP TPU635 TP-P5
102
IN
PP1V25_S2 TOP 1 TP TPU6C1 TP-P5 85 84
IN
SPI_TPAD_EN_CONN TOP 1 TP TPU6V6 TP-P5
91 61 57 IN USB2_UPC0_P1_N TOP 1 TP TPU636 TP-P5
104 84
IN
PP1V8_AON TOP 1 TP TPU6C2 TP-P5 76 GND_AUDIO_CODEC TOP 1 TP TPU6M2 TP-P5 85 84
IN
SPI_TPAD_CLK_CONN TOP 1 TP TPU6V7 TP-P5
91 61 57 IN USB2_UPC0_P1_P TOP 1 TP TPU637 TP-P5
102
IN
PP1V2_AWAKE_PLL TOP 1 TP TPU6C3 TP-P5
IN
85
IN
PP5V_S2_TPAD_CONN TOP 1 TP TPU6V8 TP-P5
IN IN
101 IN PP0V88_S1 TOP 1 TP TPU6C4 TP-P5 TOP 1 TP TPU6V9 TP-P5
103 IN PP0V805_S1_VDD_FIXED TOP 1 TP TPU6C5 TP-P5 SPEAKER 104 IN PP1V85_S2_IPD TOP 1 TP TPU6W0 TP-P5
101 IN PP0V6_S1_VDDQL TOP 1 TP TPU6C6 TP-P5
79 77 SPKRAMP_A_OUTP TOP 1 TP TPU6M3 TP-P5
105 IN PP3V3_S2_TPAD_ISNS TOP 1 TP TPU6W1 TP-P5
BATTERY 101 IN PP0V764_S1_SRAM TOP 1 TP TPU6C7 TP-P5

IN
TOP 1 TP TPU6M4 TP-P5
TOP 1 TP TPU6W2 TP-P5
103 IN PP1V2_S2_CIO TOP 1 TP TPU6C8 TP-P5
T P TPU6M5 TP-P5
101 IN PPVBAT_AON TOP 1 TP TPU621 TP-P5 101 IN PP1V06_S2 W_DRAM TOP 1 TP TPU6C9 TP-P5
79 77 SPKRAMP_A_OUTN TOP
TP
1 TP TPU6M6 TP-P5
85 IN ACT_GND TOP 1 TP TPU6W4 TP-P5
TOP 1 TP TPU622 TP-P5 102 IN PP0V855_S2SW_CIO TOP 1 TP TPU6D0 TP-P5
IN
TOP 1 TP TPU623 TP-P5 102 IN PP0V72_S2_VDD_LOW TOP 1 TP TPU6D1 TP-P5
TOP 1 TP TPU624 TP-P5 102 IN PP0V88_AWAKESW_NAND TOP 1 TP TPU6D2 TP-P5
79 77 SPKRAMP_B_OUTP TOP 1 TP TPU6M9 TP-P5
TOP 1 TP TPU625 TP-P5 102 IN PP1V25_AWAKESW_VCCQ TOP 1 TP TPU6D3 TP-P5
IN
TOP 1 TP TPU6N0 TP-P5
GND TOP 1 TP TPU6W8 TP-P5
TOP 1 TP TPU626 TP-P5 101 IN PP2V5_AWAKE_NAND TOP 1 TP TPU6D4 TP-P5
TOP 1 T TPU627 TP-P5 104 IN PP3V3_S2SW_USB1 TOP 1 TP TPU6D5 TP-P5
79 77 SPKRAMP_B_OUTN TOP 1 TP TPU6N2 TP-P5
TOP 1 TP TPU628 TP-P5 104 IN PP3V3_S2SW_USB0 TOP 1 TP TPU6D6 TP-P5
IN
43 IN I2C_SMC_PWR_3V3_SCL TOP 1 TP TPU629 TP-P5 104 IN PP3V3_AON TOP 1 TP TPU6D7 TP-P5
TOP 1 TP TPU6N4 TP-P5 DFR
43 IN I2C_SMC_PWR_3V3_SDA TOP 1 TP TPU630 TP-P5 104 IN PP3V3_S2 TOP 1 TP TPU6D8 TP-P5
7 6 SPKR_ID0 TOP TPU6N5 TP-P5
21 IN SYS_DETECT_L TOP 1 TP TPU631 TP-P5 104 IN PP5V_S2 TOP 1 TP TPU6D9 TP-P5
IN
GND TOP
TP
1 TP TPU6N6 TP-P5
87 IN TP_DFR_TOUCH_PANEL_DETECT TOP 1 TP TPU6W9 TP-P5
21 IN SYS_DETECT TOP 1 TP TPU632 TP-P5 TOP 1 TP TPU6E0 TP-P5 87 IN DFR_LID_OPEN_L TOP 1 TP TPU6X0 TP-P5
GND TOP 1 TP TPU633 TP-P5 102 IN PP1V4_LDO_PREREG TOP 1 TP TPU6E1 TP-P5 87 IN DFR_DISP_VSYNC TOP 1 TP TPU6X1 TP-P5
104 69 41 IN PP3V3_SW_LCD TOP 1 TP TPU6E2 TP-P5 79 78 IN SPKRAMP_D_OUTP TOP 1 TP TPU6N7 TP-P5 87 IN TP_DFR_TOUCH_RSVD TOP 1 TP TPU6X2 TP-P5
TOP 1 TP TPU6E3 TP-P5 TOP 1 TP TPU6N8 TP-P5 88 87 IN SPI_1V8_DFR_MISO TOP 1 TP TPU6X3 TP-P5
CHARGER 104 IN PP3V3_S2SW_SNS TOP 1 TP TPU6E4 TP-P5 TOP 1 TP TPU6N9 TP-P5 88 87 IN SPI_1V8_DFR_CS_L TOP 1 TP TPU6X4 TP-P5
57 56 55 IN PP3V3_UPC0_LDO TOP 1 TP TPU6E5 TP-P5 79 78 IN SPKRAMP_D_OUTN TOP 1 TP TPU6P0 TP-P5 88 7 IN SPI_1V8_DFR_CLK TOP 1 TP TPU6X5 TP-P5
101 IN PPDCIN_USBC_AON TOP 1 TP TPU640 TP-P5 104 IN PPVOUT_LCDBKLT TOP 1 TP TPU6E6 TP-P5 TOP 1 TP TPU6P1 TP-P5 88 87 IN SPI_1V8_DFR_MOSI TOP 1 TP TPU6X6 TP-P5
TPU641 PPVBAT_AON_CHGR_REG TPU6E7 TPU6P2 DFR_1V8_TOUCH_INT_L TPU6X7
TOP 1 TP TP-P5 97 22 IN TOP 1 TP TP-P5 TOP 1 TP TP-P5 88 87 IN TOP 1 TP TP-P5
TOP 1 TP TPU642 TP-P5 TOP 1 TP TPU6E8 TP-P5 SPKRAMP_E_OUTP
79 78 IN TOP 1 TP TPU6P3 TP-P5 41 IN I2C_DFR_RES_SCL TOP 1 TP TPU6X8 TP-P5
TOP 1 TP TPU643 TP-P5 TOP 1 TP TPU6E9 TP-P5 TO 1 TP TPU6P4 TP-P5 88 87 IN DFR_1V8_TOUCH_CLK32K_RESET_L TOP 1 TP TPU6X9 TP-P5
TOP 1 TP TPU644 TP-P5 TOP 1 TP TPU6P5 TP-P5 41 IN I2C_DFR_RES_SDA TOP 1 TP TPU6Y0 TP-P5
TOP 1 TP TPU645 TP-P5 79 78 IN SPKRAMP_E_OUTN TOP 1 TP TPU6P6 TP-P5 88 87 6 IN DFR_1V8_TOUCH_RESET_L TOP 1 TP TPU6Y1 TP-P5
98 22 IN PPDCIN_AON_CHGR_R TOP 1 TP TPU646 TP-P5 TOP 1 TP TPU6P7 TP-P5 87 IN TP_DFR_TOUCH_ROM_WC TOP 1 TP TPU6Y2 TP-P5
GND TOP 1 TP TPU647 TP-P5 TOP 1 TP TPU6P8 TP-P5 88 87 41 IN PP1V8_AWAKE_DFR TOP 1 TP TPU6Y3 TP-P5
DISPLAY 79 6 IN SPKR_ID1 TOP 1 TP TPU6P9 TP-P5 TOP 1 TP TPU6Y4 TP-P5
69 AUX_N TOP 1 TP TPU6G0 TP-P5

GND TOP 1 TP TPU6Q0 TP-P5 TOP 1 TP TPU6Y5 TP-P5
FAN 69
IN
AUX_P TOP 1 TP TPU6G1 TP-P5
TOP 1 TP TPU6Y6 TP-P5
69
IN
DP0_P TOP 1 TP TPU6G2 TP-P5 GND_VOID=TRUE
87 IN PP5V_S2_DFR_FILT TOP 1 TP TPU6Y7 TP-P5
52 IN PP5V_S2_TO_FAN TOP 1 TP TPU650 TP-P5
69
IN
DP0_N TOP 1 TP TPU6G3 TP-P5 GND_VOID=TRUE KEYBOARD GND TOP 1 TP TPU6Y8 TP-P5
TOP 1 TP TPU651 TP-P5
69
IN
52 IN FAN_RT_PWM TOP 1 TP TPU652 TP-P5
69
IN
DP1_N TOP 1 TP TPU6G5 TP-P5 GND_VOID=TRUE
105 IN PP1V85_S2_KBD_ISNS TOP 1 TP TPU6Q1 TP-P5
87 MIPI_DFR_CLK_CONN_FILT_P TOP 1 TP TPU6Y9 TP-P5
52 IN FAN_RT_TACH TOP 1 TP TPU653 TP-P5
69
IN
83 82 IN KBD_ID1 TOP 1 TP TPU6Q2 TP-P5
87
IN
MIPI_DFR_CLK_CONN_FILT_N TOP 1 TP TPU6Z0 TP-P5
52 IN TP_FAN_RT_OTP1 TOP 1 TP TPU654 TP-P5
69
IN
83 82 IN KBD_DRIVE_Y2 TOP 1 TP TPU6Q3 TP-P5
88 87
IN
DFR_1V8_DISP_TE TOP 1 TP TPU6Z1 TP-P5
52 IN TP_FAN_RT_OTP2 TOP 1 TP TPU655 TP-P5
69
IN
87
IN
MIPI_DFR_DATA_CONN_FILT_P TOP 1 TP TPU6Z2 TP-P5
52 IN GND_FAN TOP 1 TP TPU656 TP-P5
69
IN
88 87 6
IN
DFR_1V8_DISP_INT TOP 1 TP TPU6Z3 TP-P5
TOP 1 T TPU657 TP-P5
69 68
IN
MIPI_FTCAM_DATA_ISOL_N TOP 1 TP TPU6H0 TP-P5
8
IN
MIPI_DFR_DATA_CONN_FILT_N TOP 1 TP TPU6Z4 TP-P5
IN
MIPI_FTCAM_DATA_ISOL_P TPU6H1 83 82 IN KBD_SENSE_X0 TOP 1 TP TPU6Q7 TP-P5
IN
DFR_1V8_DISP_RESET_L TPU6Z5
USBC 69 68
69 68
IN
MIPI_FTCAM_CLK_ISOL_N
TOP
TOP
1 TP
1 TP TPU6H2
TP-P5
TP-P5 GND_VOID=TRUE
83 82 IN KBD_SENSE_X1 TOP 1 TP TPU6R0 TP-P5
88 87 6
87
IN
PP3V3_AWAKE_DFR
TOP
TOP
1 TP
1 TP TPU6Z6
TP-P5
TP-P5
59 57 55 PPVBUS_USBC0 TOP 1 TP TPU660 TP-P5 69 68
IN
MIPI_FTCAM_CLK_ISOL_P TOP 1 TP TPU6H3 TP-P5 GND_VOID=TRUE
IN
OP 1 TP TPU6Z7 TP-P5
IN
TOP 1 TP TPU661 TP-P5 104 69
IN
PP5V_SW_LCD TOP 1 TP TPU6H4 TP-P5
TOP 1 TP TPU6Z8 TP-P5
TOP 1 TP TPU662 TP-P5 69 6
IN
UART_TCON_HDMI_D2R TOP 1 TP TPU6H5 TP-P5

IN
EDP_PANEL_1V8_EN TOP 1 TP TPU6H6 TP-P5
83 82 IN KBD_SENSE_X9 TOP 1 TP TPU6R4 TP-P5 GND TOP 1 TP TPU6Z9 TP-P5
59 57 USBC0_SBU1 TOP 1 TP TPU664 TP-P5 69 7

IN
LPDP_INT_HPD TOP 1 TP TPU6H7 TP-P5
59 57
IN
USBC0_SBU2 TOP 1 TP TPU665 TP-P5 69 6
IN
SPI_TCON_CS_L TOP 1 TP TPU6H8 TP-P5
59 57 56
IN
USBC0_CC1 TOP 1 TPU666 TP-P5 69 6
IN
SPI_TCON_MISO TOP 1 TP TPU6H9 TP-P5
59 57 56
N
USBC0_CC2 TOP 1 TP
P
TPU667 TP-P5 69
IN
SPI_TCON_MOSI TOP 1 TP TPU6I0 TP-P5
IN
GND TOP 1 TP TPU668 TP-P5 69
IN
SPI_TCON_CLK TOP 1 TP TPU6I1 TP-P5
69 42
IN
I2C_ALS_1V8_SDA TOP 1 TP TPU6I2 TP-P5
83 82 IN KBD_SENSE_X7 TOP 1 TP TPU6S0 TP-P5
59 58 55 PPVBUS_USBC1 TOP 1 TP TPU669 TP-P5 69 42

IN
I2C_ALS_1V8_SCL TOP 1 TP TPU6I3 TP-P5
83 82 IN KBD_SENSE_X8 TOP 1 TP TPU6S1 TP-P5
IN
IN
I2C_FTCAM_ISOL_SCL TOP 1 TP TPU6I4 TP-P5
83 82 IN KBD_DRIVE_Y5 TOP 1 TP TPU6S2 TP-P5

IN
I2C_FTCAM_ISOL_SDA TOP 1 TP TPU6I5 TP-P5

IN
I2C_BKLT_SDA TOP 1 TP TPU6I6 TP-P5
59 58 56 USBC1_CC1 TOP 1 TP TPU673 TP-P5 71 69

IN
I2C_BKLT_SCL TOP 1 TP TPU6I7 TP-P5
59 58 56
IN
USBC1_CC2 TOP 1 TP TPU674 TP-P5 69 6
IN
UART_TCON_HDMI_R2D TOP 1 TP TPU6I8 TP-P5
83 82 IN KBD_CAP_CATHODE TOP 1 TP TPU6S6 TP-P5
59 58
IN
USBC1_SBU1 TOP 1 TPU675 TP-P5 69 41
IN
I2C_MLB2JERRY_3V3_SDA TOP 1 TP TPU6I9 TP-P5
83 82 IN PP3V3_AON_KBD_CONN TOP 1 TP TPU6S7 TP-P5
59 58
N
USBC1_SBU2 TOP 1 TP
P
TPU676 TP-P5 69 41
IN
I2C_MLB2JERRY_3V3_SCL TOP 1 TP TPU6J0 TP-P5
83 82 IN KBD_RIGHT_SHIFT_KEY TOP 1 TP TPU6S8 TP-P5
IN
GND TOP 1 TP TPU677 TP-P5 69
IN
TP_TCON_SWCLK TOP 1 TP TPU6J1 TP-P5
83 82 IN KBD_LEFT_OPTION_KEY TOP 1 TP TPU6S9 TP-P5
69
IN
TP_TCON_SWDIO TOP 1 TP TPU6J2 TP-P5
83 82 IN KBD_CONTROL_KEY TOP 1 TP TPU6T0 TP-P5
59 TP_USBC0_PP20V TOP 1 TP TPU678 TP-P5

IN
81 IN PPVOUT_S0_KBDLED_CONN TOP 1 TP TPU6T1 TP-P5
SYNC_MASTER=KELVIN_T668_MLB
PAGE TITLE
59
IN
TP_USBC1_PP20V TOP 1 TP TPU679 TP-P5
IN KBDLED_CATHODE1_R TOP 1 TP TPU6T2 TP-P5
FCT
IN
81 72 IN KBDLED_CATHODE1 TOP 1 TP TPU6T3 TP-P5
69 PP5V_CAM TOP 1 TP TPU6J3 TP-P5

81 72 IN KBDLED_CATHODE2 TOP 1 TP TPU6T4 TP-P5
IN
GND TOP 1 TP TPU6J4 TP-P5
81 IN KBDLED_CATHODE2_R TOP 1 TP TPU6T5 TP-P5
AMR GND TOP 1 TP TPU6T6 TP-P5
74 73 I AMR_LEFT_OR_ND_1V8 TOP 1 T TPU699 TP-P5

72 71 GND_BKLT_SGND TOP 1 TP TPU6T7 TP-P5
IN
TOP 1 TP TPU6T8 TP-P5
83 82 IN KBD_DRIVE_Y8 TOP 1 TP TPU6J5 TP-P5
4
UPC RESET RESET
POWER BUTTON RSLOC FORCE DFU (RESET PMU) (RESET SOC ONLY)
DEBUG_BUTTON DEBUG_BUTTON DEBUG_BUTTON DEBUG_BUTTON DEBUG_BUTTON
PLACE_SIDE=BOTTOM PLACE_SIDE=BOTTOM PLACE_SIDE=BOTTOM PLACE_SIDE=BOTTOM PLAC _SIDE=BOTTOM
1.4 MM TALL 1.4 MM TALL 1.4 MM TALL 1.4 MM TALL 1.4 MM TALL
SV000 SV002 SV004 SV006 SV008
SKSGPCE010 SKSGPCE010 SKSGPCE010 SKSGPCE010 SKSGPCE010
SM SM SM SM M
1 2 1 2 1 2 1 2 1 2
3 4 3 4 3 4 3 4 3 4
GND GND GND GND GND
DEBUG_BUTTON DEBUG_BUTTON DEBUG_BUTTON DEBUG_BUTTON DEBUG_BUTTON

PLACE_SIDE=TOP PLACE_SIDE=TOP PLACE_SIDE=TOP PLACE_SIDE=TOP PLACE_SIDE=TOP
0.60 MM TALL 0.60 MM TALL 0.60 MM TALL 0.60 MM TALL 0.60 MM TALL
SV001 SV003 SV005 SV007 SV009
SKSWCEE010 SKSWCEE010 SKSWCEE010 SKSWCEE010 SKSWCEE010
SM SM SM SM SM
1 2 PMU_ONOFF_L OUT 33 34 80 89 1 2 PMU_RSLOC_RST_L OUT 33 34 82 89 1 2 SOC_FORCE_DFU OUT 5 33 56 89 1 2 UPC_PMU_RESET_3V3 OUT 34 57 58 100 1 2 PMU_RESET_L OUT 5 9 33 74 89 100
PP1V25_S2_DFU_BTN_R PP3V3_UPC_PMU_RESET_R
DEBUG_BUTTON DEBUG_BUTTON
RV005 1 RV007 1
1K 1K
5% 5%
1/20W 1/20W
MF MF
201 2 201 2
02 PP1V25_S2 104 PP3V3_AON
PMU SHUTDOWN
DEBUG_BUTTON
PLACE_SIDE=BOTTOM
1.4 MM TALL
SV010
SKSGPCE010
SM
1 2
3 4
GND
DEBUG_BUTTON
PLACE_SIDE=TOP
0.60 MM TALL
SV011
SKSWCEE010
SM
1 2 PMU_SHDN OUT 33 89
PP1V8_AON_DBGSHDNBTN_R
DEBUG_BUTTON
RV011 1
1K
5%
1/20W
MF
201 2
104 PP1V8_AON
PAGE TITLE
DEBUG: BUTTONS
BOM_COST_GROUP=DEBUG
2 1
CHARGER ARKANOID CONN
CHGR_DBG
JV100
505070-1222
M-ST-SM
13 14
106 43 I2C_SMC_PWR_SDA 1 2
106 43 I2C_SMC_PWR_SCL 3 4
5 6
7 8
9 10
11 12
15 16
100 96 89 33 6 SOC_SOCHOT_L 1 TP TPV190

TP-P55 PLACE_SIDE=TOP
33 MPMU_FAULT_OUT_L 1 TP TPV191
33 29 PMU_SCRASH_L 1 TP TPV192
33 PMU_CRASH_L 1 TP TPV194
89 61 57 USB2_UPC0_P1_P 1 PPV100
P4MM SM
PP
89 61 57 USB2_UPC0_P1_N 1 PPV101
P4MM SM
PP
PAGE TITLE
DEBUG: MISC
2 1
AON LEDS (BLUE)
101 94 93 92 PP3V8_AON
104 IN PP3V3_AON 104 IN PP1V8_AON

2
2 2
XWV810
SM XWV820 XWV830
NO_XNET_CONNECTION=1 SM SM
1 NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1
1 1
XW_PP3V3_AON_LED XW_PP1V8_AON_LED
XW_P3V8_AON_LED DBG_LED DBG_LED
376S00076 376S00076
QV820
SSM3K16CTAP
QV830
SSM3K16CTAP
SOT883L SOT883L
DBG_LED 1 VGS_MAX 10 V DBG_LED 1 VGS_MAX 10 V DBG_LED
VTH_MAX 0.9 V VTH_MAX 0.9 V
998-19870 998-19870 998-19870
DBG_LED DBG_LED DBG_LED
DSV810 RV810 RV820 DSV820 RV830 DSV830
A DSV810_D 1
6.8K 2 2 3
DSV820_R 1
6.8K 2 DSV820_D K A
2 3
DSV830_R 6.8K 2 DSV830_D K A
5% 5% 5%
BLUE-22.5MCD-2MA 1/20W 1/20W BLUE-22.5MCD-2MA 1/20W BLUE-22.5MCD-2MA
SM MF MF SM MF SM
201 201 201
VF_AVG = 2.59 V VF_AVG = 2.59 V VF_AVG = 2.59 V
DBGLED_RETURN 92 93 94
S2 LEDS (MAGENTA)
I_MAX = 300 MA
101 94 93 92 PP3V8_AON
01 4 93 92 PP3V8_AON R_MAX = 130 MOHM
DBG_LED 998-20409
8 34 3 IN IPD_PWR_EN 102 IN PP1V25_S2 1 N PP5V_S2 1
RV899 DBG_LED
47K SV899
2 2 2 1%
1/20W
SSSS810701
SM
XWV840
SM
XWV850
SM
XWV860
SM
MF
2 201
1 1 1 94 93 92 DBGLED_RETURN DBGLED_RETURN 2 3
XW_PP5V_S2_LED MAKE_BASE=TRUE
XW_IPD_PWR_EN XW_PP1V225_S2_LED VOLTAGE=0V
376S00076 376S00076 376S00076
QV840 QV850 QV860
1
SSM3K16CTAP
SOT883L
VGS_MAX 10 V
SSM3K16CTAP
SOT883L
VGS_MAX 10 V 1
SSM3K16CTAP
SOT883L
VGS_MAX 10 V NC
VTH_MAX 0.9 V VTH_MAX 0.9 V VTH_MAX 0.9 V
RV840 DSV840 RV850 DSV850 RV860 DSV860
2 3
DSV840_R 1
8.2K 2 DSV840_D K A
2 3
DSV850_R 1
8.2K 2 DSV850_D K A
2 3
DSV860_R 1
8.2K 2 DSV860_D K A
5% 5% 5%
1/20W MAGENTA-45MCD-2MA 1/20W MAGENTA-45MCD-2MA 1/20W MAGENTA-45MCD-2MA
MF SM MF SM MF SM
201 201 201
S2 LEDS (MAGENTA)
101 94 93 92 PP3V8_AON
101 IN PP1V8_S2 102 IN PP1V2_S2 104 IN PP3V3_S2

2 2 2
XWV870
SM
XWV880
SM
XWV890
SM
1 1 1
XW_PP1V8_S2_LED XW_PP1V2_S2_LED XW_PP3V3_S2_LED
376S00076 376S00076 376S00076
QV870
SSM3K16CTAP
QV880
SSM3K16CTAP
QV890
SSM3K16CTAP
SOT883L SOT883L SOT883L
1 VGS_MAX 10 V 1 VGS_MAX 10 V 1 VGS_MAX 10 V
RV870 DSV870 RV880 DSV880 RV890 DSV890
2 3
DSV870_R 1
8.2K 2 DSV870_D K A
2 3
DSV880_R 1
8.2K 2 DSV880_D K A
2 3
DSV890_R 1
8.2K 2 DSV890_D K A SYNC_MASTER=T668_MLB SYNC_DATE=07/24/2019
PAGE TITLE
5%
1/20W
MF
MAGENTA-45MCD-2MA
SM
5%
1/20W
MF
MAGENTA-45MCD-2MA
SM
5%
1/20W
MF
MAGENTA 45MCD-2MA
SM
DEBUG: LEDS (1/3)
201 201 201
2 1
S2SW LEDS (ORANGE)
101 94 93 92 PP3V8_AON
101 IN PP1V06_S2SW_DRAM 104 IN PP1V8_S2SW_VDD1

2 2
XWV960
SM
XWV970
SM
NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1
1 1
XW_PP1V06_S2SW_DRAM_LED XW_PP1V8_S2SW_DRAM_LED
DBG_LED DBG_LED
376S00076 376S00076
QV960
SSM3K16CTAP
QV970
SSM3K16CTAP
SOT883L SOT883L
1 VGS_MAX 10 V 1 VGS_MAX 10 V
DBG_LED DBG_LED
DBG_LED DBG_LED
DSV960 DSV970
RV960 RV970
2 3
DSV960_R 1
2.2K 2 DSV960_D K A
2 3
DSV970_R 1
2.2K 2 DSV970_D K A
5% 5%
1/20W ORANGE-11.5MCD-2MA 1/20W ORANGE-11.5MCD-2MA
MF SM MF SM
201 201
VF_AVG = 1.8 V VF_AVG = 1.8 V
S1 LEDS (YELLOW)
101 94 93 92 PP3V8_AON
101 IN PPVDD_DISP_S1 103 IN PP0V805_S1_VDD_FIXED

2 2
XWV900
SM
XWV910
SM
O_XNET_CONNECTION=1 NO XNET_CONNECTION=1
1 1
XW_PPVDD_DISP_S1_LED XW_PP0V805_S1_VDD_FIXED_LED
DBG_LED DBG_LED
1 1
RV901 RV911
2K 2K
1% 1%
1/20W 1/20W
MF MF
2 201 2 201
DSV900_B DBG_LED DSV910_B DBG_LED
DBG_LED DBG_LED
RV900 DSV900 RV910 DSV910
DSV900_C 1
2.2K 2 DSV900_D K A DSV910_C 1
2.2K 2 DSV910_D K A
5% 5%
1/20W YELLOW-7.2MCD-2MA 1/20W YELLOW-7.2MCD-2MA
MF SM MF SM
DBG_LED 201 DBG_LED 201
VF_AVG = 1.8 V VF_AVG = 1.8 V
6 372S00042 3 372S00042
2 QV900 5 QV900
SNST3904DXV6T5G SNST3904DXV6T5G
SOT563 SOT563
VBE,SAT @ 1 MA ~ 0.6 V
1 HFE,MIN @ 4 HFE,MIN @
VBE,SAT 1 M ~ 0.6 V
1 MA = 70 @ 1 MA = 70
AWAKE LEDS (GREEN)

101 94 93 92 PP3V8_AON
101 IN PPVDD_PCPU_AWAKE 101 IN PPVDD_GPU_AWAKE

2 2
XWV920
SM
XWV930
SM
1 1
XW_PPVDD_PCPU_AWAKE_LED XW_PPVDD_GPU_AWAKE_LED 102 IN PP1V25_AWAKE_IO 102 IN PP1V25_AWAKESW_VCCQ
DBG_LED DBG_LED 2 2
1 1
RV921 RV931 XWV940
SM
XWV950
SM
2K 2K
1% 1% NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1
1/20W 1/20W 1 1
MF MF
2 201 2 201
XW_PP1V2_AWAKE_IO_LED XW_PP1V225_AWAKESW_VCCQ_LED
DBG_LED DBG_LED
DSV920_B DBG_LED DSV930_B DBG_LED
DBG_LED DBG_LED 376S00076 376S00076
RV920 DSV920 RV930 DSV930 QV940 QV950

SSM3K16CTAP SSM3K16CTAP
DSV920_C 1
12K 2 DSV920_D K A DSV930_C 1
12K 2 DSV930_D K A 1
SOT883L
1
SOT883L
VGS_MAX 10 V VGS_MAX 10 V
5% 5% DBG_LED DBG_LED
1/20W GREEN-90MCD-2MA 1/20W GREEN-90MCD-2MA DBG_LED DBG_LED
DBG_LED
MF
201 SM
DBG_LED
MF
201 SM
RV940 DSV940 RV950 DSV950 SYNC_MASTER=T668_MLB
PAGE TITLE
VF_AVG = 2.53 V VF_AVG = 2.53 V
372S00042 372S00042 12K 12K
2
6
QV920 5
3
QV920
2 3
DSV940_R 1 2 DSV940_D K A
2 3
DSV950_R 1 2 DSV950_D K A DEBUG: LEDS (2/3)
5% 5%
SNST3904DXV6T5G SNST3904DXV6T5G 1/20W GREEN-90MCD-2MA 1/20W GREEN-90MCD-2MA
SOT563 SOT563 MF MF
201 SM 201 SM
1 HFE,MIN @
VBE,SAT 1 MA ~ 0.6 V
@ 1 MA = 70 4 HFE,MIN @
VBE,SAT 1 MA ~ 0.6 V
@ 1 MA = 70 VF_AVG = 2.53 V VF_AVG = 2.53 V
2
MODULE LEDS (WHITE)
101 94 93 92 PP3V8_AON
71 33 IN BL_PWR_EN 70 34 IN LCD_PWR_EN 88 7 6 IN DFR_PWR_EN 86 IN TOUCHID_PWR_EN 63 62 33 IN WLBT_PWR_EN

2 2 2 2 2
XWW000
SM
XWW010
SM
XWW020
SM
XWW030
SM
XWW040
SM
NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1
1 1 1 1 1
XW_BL_PWR_EN XW_LCD_PWR_EN XW_DFR_PWR_EN XW_TOUCHID_PWR_EN XW_WLBT_PWR_EN
DBG_LED DBG_LED DBG_LED DBG_LED DBG_LED
376S00076 376S00076 376S00076 376S00076 376S00076
QW000
SSM3K16CTAP
QW010
SSM3K16CTAP
QW020
SSM3K16CTAP
QW030
SSM3K16CTAP
QW040
SSM3K16CTAP
SOT883L SOT883L SOT883L SOT883L SOT883L
1 VGS_MAX 10 V 1 VGS_MAX 10 V 1 VGS_MAX 10 V 1 VGS_MAX 10 V 1 VGS_MAX 10 V
VTH_MAX 0.9 V VTH_MAX 0.9 V VTH_MAX 0.9 V VTH_MAX 0.9 V VTH_MAX 0.9 V
RW000 DSW000 RW010 DSW010 RW020 DSW020 RW030 DSW030 RW040 DSW040
2 3
DSW000_R 1
6.8K 2 DSW000_D K A
2 3
DSW010_R 1
6.8K 2 DSW010_D K A
2 3
DSW020_R 6 8K 2 DSW020_D A
2 3
DSW030_R 1
6.8K 2 DSW030_D K A
2 3
DSW040_R 1
6.8K 2 DSW040_D K A
5% 5% 5% 5% 5%
1/20W WHITE 57MCD-2MA 1/20W WHITE-57MCD-2MA 1/20W WHITE-57MCD-2MA 1/20W WHITE-57MCD-2MA 1/20W WHITE-57MCD 2MA
MF SM MF SM MF SM MF SM MF SM
201 201 201 201 201
VF_AVG = 2.59 V VF_AVG = 2.59 V VF_AVG = 2.59 V VF_AVG = 2.59 V VF_AVG = 2.59 V
STATUS LEDS (WHITE)

101 94 93 92 PP3V8_AON
89 56 19 IN SOC_DFU_STATUS 89 55 33 5 IN PMU_ACTIVE_READY
2 2
XWW050
SM
XWW070
SM
1 1
XW_SOC_DFU_STATUS XW_PMU_ACTIVE_READY SOC_SW_DBG
www.teknisi-indonesia.com IN 9

376S00076 376S00076 376S00076
QW050
SSM3K16CTAP
QW070
SSM3K16CTAP
QW080
SSM3K16CTAP
SOT883L SOT883L SOT883L
1 VGS_MAX 10 V 1 VGS_MAX 10 V 1 VGS_MAX 10 V
RW050 DSW050 RW070 DSW070 RW080 DSW080
2 3
DSW050_R 1
6.8K 2 DSW050_D K A
2 3
DSW070_R 1
6.8K 2 DSW070_D K A
2 3
DSW080_R 1
6.8K 2 DSW080_D K A
5% 5% 5%
1/20W WHITE-57MCD-2MA 1/20W WHITE-57MCD-2MA 1/20W WHITE-57MCD-2MA
MF SM MF SM MF SM
201 201 201
VF_AVG = 2.59 V VF_AVG = 2.59 V
PAGE TITLE
DEBUG: LEDS (3/3)
NOSTUFF
P3V8AON HIGH BANDWIDTH CURRENT SENSE AMPLIFIER RW240
1
0 2 PP5V_DBG_VMAIN_AMPS 95
NO_XNET_CONNECTION=1 0%
1/16W
DBG_VMAINISNS DBG_VMAINISNS MTL-FILM
0402
RW200 RW202 116S00006
P3V8AON_ISNS1_P 1
100 2 P3V8_PISUM1_NEG 1
301 2 PP5V_DBG_VMAIN_AMPS
25 IN 95 95 DBG_VMAINISNS
0.1%
1/16W
0.1%
1/16W
PLACE_NEAR=UW200.8:3MM
VOLTAGE=5 RW241
T
0402
MF
0402
NOSTUFF DBG_VMAINISNS DBG_VMAINISNS
PPSUPPLY_P3V8AONISNS_AMP2 1
0 2 PP3V8_DBG_VMAIN_AMPS 95
1 CW204 1 CW200 1 CW201 0%
0.01UF 0.1UF 1UF PLACE_NEAR=UW220.8:3MM
1/16W
DBG_VMAI I N 10% 10% 10% NOSTUFF BG_VMAINISNS DBG_VMAINISNS MTL-FILM
2 10V 2 16V 2 6.3V 0402
RW204 X7R
0201-1
X7R-CERM
0402
CERM
402
1 CW224 1 CW220 1 CW221 116S00006
100 0.01UF 0.1UF 1UF
25 IN P3V8AON_ISNS2_P 1 2 10% 10% 10%
2 10V
X7R 2 16V
X7R-CERM 2 6.3V
CERM
0.1% 0201-1 0402 402
1/16W
TF NOSTUFF
0402
NO_XNET CONNECTION=1 DBG_VMAINISNS RW228
0 PP5V_DBG_VMAIN_AMPS
DBG_VMAINISNS 353S3959 1 2 95
RW206 UW200 5%
1/20W
P3V8AON_ISNS3_P 1
100 2 P3V8_PISUM_POS 5 8 OPA2350 MF
0201
25 IN MSOP
0.1% V+ DBG_VMAINISNS
1/16W 7 P3V8IDIF1_OUT_POS NOSTUFF
TF
0402
V-
CW222 RW226
P3V8IDIF1_FB_POS 6 1.5PF
4 1 2 1
0 2 PP3V8_DBG_VMAIN_AMPS 95
DBG_VMAINISNS 5%
103S0194 114S0092 +/-0.1PF 1/20W
50V
DBG_VMAINISNS DBG_VMAINISNS RW215 C0G
402
MF
0201
1
0 2
103S00072 103S00072
RW210 RW212 DBG_VMAINISNS DBG_VMAINISNS DBG_VMAINISNS DBG_VMAINISNS
1
1.00K2 P3V8IDIF1_FB_R_POS 1
49.9 2 5%
1/20W
MF RW220 RW222 RW224 RW227
0.1%
1/16W
1%
1/16W
0201
P3V8IDIF1_SW_POS 1
2K 2 1
10K 2 P3V8IDIF2_FB_R_POS 1
10K 2 P3V8IDIF2_OUT_REF 1
0 2
NOSTUFF
MF MF-LF NOSTUFF
402
CW202 402
RW216
0.1%
1/16W
0.1%
1/16W DBG_VMAINISNS
0.1%
1/16W
5%
1/20W
15PF 0
TF MF MF MF
1 2 1 2
0402 0402 353S3959 0402 0201
5%
5% UW220
DBG_VMAINISNS 50V
1/20W
MF P3V8IDIF2_FB_POS 3 8 OPA2350
1 CERM MSOP
RW208 0402
0201
V+
05 1 P3V8IDIF2_OUT
0 1%
1/16 NOSTUFF V-
MF NOSTUFF P3V8IDIF2_FB_NEG 2
0402 2 CW203 RW217 4
DBG_VMAINISNS
15PF 0 518S0562
1 2 1 2
DBG_VMAINISNS DBG_VMAINISNS DBG_VMAINISNS
JW222
5% COAX-2.00MM-U.FL
103S0194 5% 114S0092 F-ST-SM1
50V
CERM
1/20W
MF RW221 RW223 RW225
DBG_VMAINISNS 0402 DBG_VMAINISNS 0201
P3V8IDIF1_SW_NEG 1
2K 2 1
10K 2 P3V8IDIF2_FB_R_NEG 1
10K 2
2
RW209 RW211 DBG_VMAINISNS

0.1% 0.1% 0.1%
1
1.00K2 P3V8IDIF1_FB_R_NEG 1
49.9 2 RW218 1/16W
TF
1/16W
MF
1/16W
MF
1
0.1% 1% 1
0 2
0402 0402 0402
DBG_VMAINISNS
1/16W 1/16W 103S00072 103S00072 3
MF
402
MF-LF
402
5%
1/20W CW223
DBG_VMAINISNS MF
0201
1.5PF VER-1
353S3959 1 2
UW200 +/-0.1PF
50V
P3V8IDIF1_FB_NEG 2 8 OPA2350 C0G
DBG_VMAINISNS MSOP 402
V+
RW207 1 P3V8IDIF1_OUT_NEG
P3V8AON_ISNS3_N 1
100 2 P3V8_PISUM_NEG 3 V-
25 IN
0.1% 4
/16W
TF
04 2
DBG_VMAINISNS
RW205
P3V8AON_ISNS2_N 1
100 2
25 IN
0.1%
1/16W
TF
0402
DBG_ MAINISNS DBG_VMAINISNS
RW201 RW203 STUFF THESE TO ENABLE VMAIN SENSE AMP
P3V8AON_ISNS1_N 1
100 2 95 P3V8_PISUM1_NEG 1
301 2
25 IN
0.1 0.1%
1/16W
TF
1/16W
MF
NOTE: IF THESE ARE STUFFED, THEN THERE WILL BE DBG_VMAINISNS
0402 0402 DBG_VMAINISNS 353S3959
SOME LEAKAGE IN OFF ONTO 5V_S2 THROUGH UW200
RW230 UW220
<RDAR://57211269> 1
100 2 P3V8IDIFSP_INP 5 8 OPA2350
MSOP
1% V+
1/16W 7 P3V8IDIFSP_OUT
MF-LF
402
NOSTUFF 6 V-
RW2A0 4
PP5V_S2 1
0 2 PP5V_DBG_VMAIN_AMPS
104 95
0% MIN_LINE_WIDTH=0.2000 DBG_VMAINISNS
1/16W VOLTAGE=5V
MTL-FILM
0402 RW231
116S00006
P3V8IDIFSP_FB 1
100 2
NOSTUFF 1%
1/16W
RW2A1 MF-LF
402
PP3V8_AON 1
0 2 PP3V8_DBG_VMAIN_AMPS
CHAD NOTES: 101
0%
95
1/16W VOLTAGE=3.8V
EFFECTIVE CURRENT SENSE R = 0.4444 MOHM MTL-FILM
0402 SYNC_MASTER=T668_MLB SYNC_DATE=06/20/2019
116S00006
1 MOHM || 1 MOHM || 4 MOHM PAGE TITLE
STAGE 1 GAIN = 11.243 DEBUG: P3V8AON ISENSE

STAGE 1 BANDWIDTH ~ 3.38 MHZ
STAGE 1 OUTPUT SCALE = 5.00 MV/A
STAGE 2 GAIN = 10.00
STAGE 2 BANDWIDTH ~ 3.80 MHZ
STAGE 2 OUTPUT SCALE = 50.0 MV/A
2 1
SOC USB DFU MUX
4 PP3V3_AON
20K LIMITS USB MINI-B
VITAMIN-C:YES VITAMIN-C MK2 CONNECTOR
FROM BACK POWERING MLB
1 RX412
5%
20K 516S1074
1/20W SILK_PART=VITAMIN-C
MF
2 201 VITAMIN-C:YES
VITAMIN-C:YES PP3V3_AON_DFUMUX JX401

VOLTAGE=3.3V VITAMIN-C:YES AA25D-S038VA1
BYPASS=UX410::5MM MIN_LINE_WIDTH=0.1000 F-ST-SM
CX410 1 MIN_NECK_WIDTH=0.1000 1 RX410 39 40
0.1UF 100K
5%
10%
10V 9 2UA MAX IDD
LVL SHFTR
1/20W SOC ATC0 DFU 1 2 SOC_SOCHOT_L
VIT-C CONN X5R-CERM 2 MF OUT 6 3 89 91 100
0201 VCC 2 201 96 USB2_ATC0_LS_VITAMINC_P 3 4 DFUMUX_SEL 96
96 USB2_ATC0_LS_VITAMINC_P 5 M+ Y+ 1 USB2_ATC0_LS_MUX_P BI 60 96 107 96 USB2_ATC0_LS_VITAMINC_N 5 6 KISMUX_SEL 96
96 USB2_ATC0_LS_VITAMINC_N 4 M-
UX410 Y- 2 USB2_ATC0_LS_MUX_N BI 60 96 107 7 8 SOC_DOCK_CONNECT_VITAMINC 96
PI3USB102EZLE 96 USB_DBG_LS_VITAMINC_P 9 10 NC_DC_MUX_SEL 107
96 61 BI USB2_ATC0_LS_P 7 D+ TQFN-THICKSTNCL 96 USB_DBG_LS_VITAMINC_N 11 12 SWD_SOC_SWDIO BI 56 57

96 61 USB2_ATC0_LS_N 6 D- CRITICAL 13 14 SWD_SOC_SWCLK
BI OUT 56 57
SWD_SOC_SWDIO
VITAMIN-C:YES SOC KIS DBG RFU NC
15 16 NC_DEBUG_JTAG_SOC_TDO IN 107
KOBA SWD_SOC_SWCLK
JTAG_SOC_TDO
DEBUG SPI ACE 8 OE* SEL 10 DFUMUX_SEL 96
NC
17 18 NC_DEBUG_JTAG_SOC_TDI OUT 107 JTAG_SOC_TDI
GND
19 20 UART_DEBUGPRT_R2D IN 56 57
SEL OUTPUT
VITAMIN-C:NO 21 22 UART_DEBUGPRT_D2R SOC UART
3 RFU NC OUT 56 57
RX414 NC
23 24 UART_SMC_DEBUGPRT_R2D IN 56 57
L VIT-C (M)
96 61 USB2_ATC0_LS_P 1
0 2 USB2_ATC0_LS_MUX_P 60 96 107 25 26 UART_SMC_DEBUGPRT_D2R SMC UART
OUT 56 57
H TYPE-C (D) 5% 27 28 VITC_RTMR_RESET_L
1/20W RFU NC 96
MF
NC
29 30 VITC_RTMR_PWR_EN 96
201
NO_XNET_CONNECTION=1 101 PP3V8_AON 31 32 PP1V8_S2 101
VITAMIN-C:NO 33 34 PP1V25_S2 1
35 36
RX416
USB2_ATC0_LS_N 1
0 2 USB2_ATC0_LS_MUX_N
37 38 VITAMIN-C:YES VITAMIN-C:YES VITAMIN-C:YES
96 61 60 96 107 VITAMIN C:YES VITAMIN C:YES
5% 1 CX405 1 CX406
1 CX401 1 CX402 1 CX403
1/20W 41 42 0.1UF 0 1UF 0.1UF
MF 0.1UF 0.1UF 10% 10% 10%
10% 10% 2 16V 2 16V 2 16V
SOC DBG MUX 201
NO_XNET_CONNECTION=1 2 16V
X5R-CERM 2 16V
X5R-CERM
X5R-CERM
0201
X5R-CERM
0201
X5R-CERM
0201
0201 0201 PP5V_S2 104
104 PP3V3_AON
VITAMIN-C:YES
VITAMIN-C:YES
1 RX413 BYPASS=JX401::10MM BYPASS=JX401::10MM 1 CX404 BYPASS=JX401::5MM BYPASS=JX401::5MM
2.2UF BYPASS=JX401::5MM
20K 20%
5% 2 25V
X6S-CERM
1/20W 0402
MF
2 201 BYPASS=JX401::5MM
VITAMIN-C:YES P3V3_AON_DBGMUX
VOLTAGE=3.3V VITAMIN-C:YES
BYPASS=UX411::5MM MIN_LINE_WIDTH=0.1000
CX411 1 MIN_NECK_WIDTH=0.1000 1 RX411
0.1UF 100K
10% 5%
10V 9 2UA MAX IDD 1/20W
VIT-C CONN X5R-CERM 2 LVL SHFTR
MF
0201 VCC 2 201
96 USB_DBG_LS_VITAMINC_P 5 M+ Y+ 1 USB_DBG_LS_MUX_P BI 60 96 107
96 USB_DBG_LS_VITAMINC_N 4 M
UX411 Y- 2 USB_DBG_LS_MUX_N BI 60 96 107
PI3USB102EZLE
96 89 56
96 89 56
BI
BI
USB_DBG_LS_P
USB_DBG_LS_N
7 D+ TQFN-THICKSTNCL
6 D- CRITICAL www.teknisi-indonesia.com
VITAMIN-C:YES
DEBUG SPI ACE KISMUX_SEL
8 OE* SEL 10 96
GND
SEL OUTPUT VITAMIN-C:NO
3
L VIT-C (M) RX415
USB_DBG_LS_P 0 USB_DBG_LS_MUX_P
H TYPE-C (D) 96 89 56 1 2 60 96 07
5%
1/20W TO SOC
MF
201 1V2 NUB AOP, S2 FROM ACE GPIO 7, PMOS OPEN DRAIN
NO_XNET_C NNECTION=1
47K PD ON SOC PAGE RX491 1V2 S2
VITAMIN-C:NO
SOC_DOCK_CONNECT 1
100 2 UPC0_GPIO7
9 OUT IN 56 57 107
RX417 5%
USB_DBG_LS_N 1
0 2 USB_DBG_LS_MUX_N
1/20W
MF
96 89 56 60 96 107
201
5%
1/20W
MF VITAMIN-C:YES FROM VITAMIN C
PARROT DBG MUX 201
NO_XNET_CONNECTION=1 RX492 GPIO 7, 1V2 S2
PP3V3_AON 1
10 2 SOC_DOCK_CONNECT_VITAMINC
104 96
VITAMIN-C:YES
5%
1 RX418 1/20W
MF
20K 201
5%
1/20W
MF
VITAMIN-C:YES 2 201
PP3V3_AON_PRTMUX
BYPASS=UX412::10MM VOLTAGE=3.3V
CX415 1 MIN_NECK_WIDTH=0.1000
0.1UF
10%
10V
X5R-CERM 2
0201 9 2UA MAX IDD
VIT-C CONN VCC
96 VITC_RTMR_RESET_L 5 M+ Y+ 1 ATCRTMR0_RESET_MUX_1V8_L 60 96 107
96 VITC_RTMR_PWR_EN 4 M-
UX412 Y- 2 USBC0_3V3LDO_EN_MUX BI 96 107
PI3USB102EZLE
96 60 BI ATCRTMR0_RESET_1V8_L 7 D+ TQFN-THICKSTNCL
96 57 USBC0_3V3LDO_EN 6 D- CRITICAL
BI
VITAMIN-C:YES
RTMRMUX_OE_L 8 OE* SEL 10 DFUMUX_SEL 96
ITAMIN-C:YES
SEL OUTPUT GND
1 RX422 VITAMIN-C:NO
L VIT-C (M) 20K 3
H TYPE-C (D)
5%
1/20W RX420 SYNC_MASTER=MANAN_T668_MLB SYNC_DATE=02/03/2020
MF
ATCRTMR0_RESET_1V8_L 1
0 2 ATCRTMR0_RESET_MUX_1V8_L60
PAGE TITLE
2 201 96 60 96 107
DEBUG: VITAMIN-C
5%
1/20W
MF
201
VITAMIN-C:NO
RX421
USBC0_3V3LDO_EN 1
0 2 USBC0_3V3LDO_EN_MUX
96 57 96 107
5%
1/20W
MF
01
NO_XNET_CON ECTION=1
6 5 2 1
3
CHARGE SOC - DISPLAY SOC - DCS
89 22 PPVBAT_AON_CHGR_REG 101 PPVDD_DISP_S1 101 PPVDD_DCS_S1
CY000 1 CY001 1 CY002 1 CY003 1 CY080 1 CY081 1 CY090 1 CY091 1 CY092 1 CY093 1
3.0PF 3.0PF 12PF 12PF 3.0PF 12PF 3.0PF 12PF 3.0PF 12PF
+/-0.1PF +/-0.1PF 5% 5% +/-0.1PF 5% +/-0.1PF 5% +/- .1PF 5%
25 25V 25V 25V 25V 25V 25V 25V 25V 25V
NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0- 0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0- 0G 2 NP0-C0G 2
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201
SOC - VDDQL
SOC PCPU
101 PP0V6_S1_VDDQL
101 PPVDD_PCPU_AWAKE
PLACE_SIDE=BOTTOM PLACE_SIDE=BOTTOM CY0A0 1 CY0A1 1 CY0A2 1 CY0A3 1 CY0A4 1 CY0A5 1 CY0A6 1 CY0A7 1 CY0A8 1 CY0A9 1
CY010 1 CY011 1 CY012 1 CY013 1 CY014 1 CY015 1 3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 3.0PF 12PF
+/-0.1PF 5% +/-0 1PF 5% +/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5%
3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 25V
NP0-C0G 2
25V 2
NP0-C0G
25V
NP0-C0G 2
25V 2
NP0-C0G
25V
NP0-C0G 2
25V 2
NP0-C0G
25V
NP0-C0G 2
25V 2
NP0-C0G
25V
NP0-C0G 2
25V 2
NP0-C0G
+/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5%
25V 25V 25V 25V 25V 25V 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201
NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2
0201 0201 0201 0201 0201 0201
SOC GPU
PLACE_SIDE=BOTTOM PLACE_SIDE=BOTTOM
101 PPVDD_GPU_AWAKE CY0AA 1 CY0AB 1 CY0AC 1 CY0AD 1 CY0AI 1 CY0AJ 1 CY0AK 1

PLACE_SIDE=BOTTOM PLACE_SIDE=BOTTOM
3.0PF 12PF 3.0PF 12PF 12PF 3.0PF 12PF
+/-0.1PF 5% +/-0 1PF 5% 5% +/-0.1PF 5%
CY020 1 CY021 1 CY022 1 CY023 1 CY024 1 CY025 1 CY026 1 CY027 1 25V
NP0-C0G 2
25V
NP0-C0G 2
2 V
NP0-C0 2
25V
NP0-C0G 2
25V
NP0-C0G 2
25V
NP0 C0G 2
25V
NP0-C0G 2
3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 0201 0201 0201 0201 0201 0201 0201
+/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5%
25V 25V 25V 25V 25V 25V 25V
NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2
0201 0201 0201 0201 0201 0201 0201
PACK_IGNORE=TRUE SOC - ECPU

SOC - SOC
101 PPVDD_ECPU_AWAKE
101 PPVDD_SOC_S1
CY0B0 1 CY0B1 1 CY0B2 1 CY0B3 1 CY0B5 1
CY030 1 CY031 1 CY032 1 CY033 1 CY034 1 CY035 1 CY036 1 3.0PF 12PF 3.0PF 12PF 12PF
+/-0.1PF 5% +/-0 1PF 5% 5%
3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 12PF 25V
NP0-C0G 2
25V 2
NP0-C0G
25V
NP0-C0G 2
25V 2
NP0-C0G
25V 2
NP0-C0G
+/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5% 5%
25V 25V 25V 25V 25V 25V 25V 0201 0201 0201 0201 0201
NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2
0201 0201 0201 0201 0201 0201 0201
PACK_IGNORE=TRUE
SOC - VDD1 SOC - 1.2V CIO SOC - 0.88V S1
104 PP1V8_S2SW_VDD1 103 PP1V2_S2_CIO 101 PP0V88_S1
CY040 1 CY041 1 CY042 1 CY043 1 CY0C1 1 CY0D0 1 CY0D1 1

3.0PF 12PF 3.0PF 12PF 12PF 3.0PF 12PF
+/-0.1PF 5% +/-0.1PF 5% 5% +/-0.1PF 5%
25V 25V 25V 25V
25V 25V 25V
0201 0201 0201 0201 0201 0201 0201
SOC - DRAM
SOC - 1.25V S2 SOC - VDD_FIXED
101 PP1V06_S2SW_DRAM
102 98 PP1V25_S2 103 14 PP0V805_S1_VDD_FIXED
CY050 1 CY051 1 CY052 1 CY053 1 CY054 1 CY055 1 CY056 1 CY057 1
3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 3.0PF 12PF CY0E0 1 CY0E1 1 CY0F0 1 CY0F1 1 CY0F2 1 CY0F3 1
+/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5%
25V
NP0-C0G 2
25V
NP0-C0G 2
25V
NP0-C0G 2
25V
NP0-C0G 2
25V
NP0-C0G 2
25V
NP0-C0G 2
25V
NP0-C0G 2
25V
NP0-C0G 2
12PF 12PF 3.0PF 12PF 3.0PF 12PF
5% 5% +/-0.1PF 5% +/-0 1PF 5%
0201 0201 0201 0201 0201 0201 0201 0201 25V 25V 25V 25V 25V 25V
NP0-C0G 2 NP0-C0 2 NP0-C0G 2 NP0-C0G 2 NP0-C0 2 NP0-C0G 2
0201
PLACE_NEAR=U0600.AP39:2MM
0 01
PLACE_NEAR=U060 .AY23 2MM
0201 0201 0 01 0201
CY058 1 CY059 1 CY05A 1 CY05B 1 CY05C 1 CY05D 1

3.0PF 12PF 3.0PF 12PF 3.0PF 12PF
+/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5% SOC - VDDIO12 GRP3 SOC - VDDIO12 GRP4
25V 25V 2 25V 25V 2 25V 25V 2
NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G
0201 0201 0201 0201 0201 0201
11 PP1V25_AWAKE_GRP3 11 PP1V25_AWAKE_GRP4
SOC - SOC SRAM

CY0G1 1 CY0G2 1
12PF 12PF
5% 5%
25V 2 25V 2
101 PP0V764_S1_SRAM NP0-C0G
0201
NP0-C0G
0201
CY060 1 CY061 1 CY062 1 CY063 1 CY064 1 CY065 1 CY066 1 CY067 1

3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 3 0PF 12PF
+/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5% +/ 0.1PF 5%
25V 25V 2 25V 25V 2 25V 25V 2 25V 25V 2
NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G
0201 0201 0201 0201 0201 0201 0201 0201
SOC - VDDIO12 GRP5 SOC - VDDIO18 GRP1

SOC - CPU SRAM
11 PP1V25_AWAKE_GRP5 102 11 PP1V8_AWAKE
101 PPVDD_CPU_SRAM_AWAKE
CY0G3 1 CY0G4 1
CY070 1 CY071 1 CY072 1 CY073 1 12PF 12PF

5% 5%
3.0PF 12PF 3.0PF 12PF 25V
NP0-C0G 2
25V
NP0-C0G 2
+/-0.1PF 5% +/-0.1PF 5%
25V 25V 2 25V 25V 2 0201 0201
NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G
0201 0201 0201 0201
PAGE TITLE
DESENSE (1/3)
BOM_COST_GROUP=DESENSE
4 3 2 1
P3V8AON VIN PBUS
105 PPBUS_VMAIN_VIN_ISNS 101 PPBUS_AON
CY110 1 CY111 1 CY112 1 CY113 1 CY114 1 CY115 1 CY160 1 CY161 1 CY162 1 CY163 1
3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 3 0PF 12PF 3.0PF 12PF
+/-0.1PF 5% +/-0.1PF +/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5%
25V 25V 2 25V 25V 25V 25V 2 25V 25V 2 25V 25V 2
NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201
BUCK 13
CY116 1 CY117 1 CY118 1 CY1C0 1 CY1C1 1 CY1C2 1 CY1C3 1
12PF 12PF 12PF 12PF 12PF 12PF 12PF 102 7 PP1V25_S2
5% 5% 5% 5% 5% 5% 5%
25V 25V 25V 25V 25V 25V 25V
0201 0201 0201 0201 0201 0201 0201 CY170 1 CY171 1 CY172 1 CY173 1 CY174 1 CY175 1
3.0PF 12PF 3.0PF 12PF 3.0PF 12PF
+/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5%
25 25V 2 25V 25V 2 25V 25V 2
NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G
0201 0201 0201 0201 0201 0201
P3V8AON
101 PP3V8_AON
CY176 1 CY177 1
CY120 1 CY121 1 CY122 1 CY123 1 CY124 1 CY125 1 CY12A 1 CY12B 1 3.0PF 12PF
+/-0.1PF 5%
3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 25V
NP0-C0 2
25V
NP0-C0G 2
+/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5%
25V 25V 2 25V 2 25V 25V 2 25V 25V 2 0201 0201
NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G
0201 0201 0201 0201 0201 0201 0201
1V8 AON
CY126 1 CY127 1 CY128 1 CY129 1 CY12C 1 CY12D 1
3.0PF 12PF 3.0PF 12PF 3.0PF 12PF 104 PP1V8_AON
+/-0.1PF 5% +/-0.1PF 5% +/-0.1PF 5%
25V 25V 2 2 V 25V 2 25V 2 V 2
NP0-C0G 2 NP0-C0G NP -C0 2 NP0-C0G NP0-C0G 2 NP0 C0G
0201 0201 0201 0201 0201 0201 CY180 1 CY181 1 CY182 1 CY183 1
3.0PF 3.0PF 12PF 12PF
+/-0.1PF +/-0.1PF 5% 5%
25V 25V 25V 2 25V 2
NP0-C0G 2 NP0-C0G 2 NP0-C0G NP0-C0G
0201 0201 0201 0201
5V S2
104 PP5V_S2 www.teknisi-indonesia.com

DCIN
CY130 1 CY131 1
3.0PF 12PF
+/-0.1PF
25V
5%
25V 89 22 PPDCIN_AON_CHGR_R
NP0-C0G 2 NP0-C0G 2
0201 0201
CY190 1 CY191 1
3.0PF 3.0PF
+/-0.1PF +/-0.1PF
25V 25V
NP0-C0G 2 NP0-C0G 2
0201 0201
5V S2 VIN
105 PPBUS_AON_5VS2_VIN_ISNS
LCD BACKLIGHT
CY140 1 CY141 1 CY142 1 CY143 1
3.0PF 12PF 3.0PF 12PF
+/-0.1PF
25V
5%
25V 2
+/-0.1PF
25V
5%
25V 2 104 PPVOUT_LCDBKLT
NP0-C0G 2 NP0-C0G NP0-C0G 2 NP0-C0G
0201 0201 0201 0201
CY1A0 1 CY1A1 1
3PF 12PF
+/-0.1PF 5%
100V 2 100V 2
C0G CERM
0201 0402
131S00140 131S00041
KBD BACKLIGHT
104 PPVOUT_KBDLED
CY150 1 CY151 1
DCIN
3PF 12PF
+/-0.1PF 5%
100V 2 100V 2
C0G
0201
CERM
0402 101 PPDCIN_USBC_AON
131S00140 131S00041
CY1B0 1 CY1B1 1
3.0PF 3.0PF
+/-0.1PF +/-0.1PF
25V 25V
NP0 C0G 2 NP0-C0G 2
0201 0201
PAGE TITLE
DESENSE (2/3)
2 1
3V3 S2 MASTER PMU HIGH SIDE INPUT
104 PP3V3_S2 105 PP3V8_AON_MPMU_ISNS_VIN
CY200 1 CY201 1 CY2D0 1 CY2D1 1

3.0PF 12PF 12PF 12PF
+/-0.1PF 5% 5% 5%
25V 25V 2 25V 2 25V 2
NP0-C0G 2 NP0-C0G NP0-C0G NP0-C0G
0201 0201 0201 0201
2V5 AWAKE NAND
101 PP2V5_AWAKE_NAND 101 PP1V8_S2
CY210 1 CY211 1 CY212 1 CY213 1 CY2E0 1

3.0PF 12PF 3.0PF 12PF 12PF
+/-0.1PF 5% +/-0.1PF 5% 5%
25V 25V 25V 25V 25V
NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2
0201 0201 0201 0201 0201
0V88 AWAKESW NAND
102 PP0V88_AWAKESW_NAND
CY220 1 CY221 1 CY222 1 CY223 1

3.0PF 12PF 3.0PF 12PF
+/-0.1PF 5% +/-0.1PF 5%
25V 25V 25V 25V
NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2
0201 0201 0201 0201
1V25 AWAKESW VCCQ
102 PP1V25_AWAKESW_VCCQ
CY230 1 CY231 1 CY232 1 CY233 1 www.teknisi-indonesia.com

3.0PF 12PF 3.0PF 12PF
+/-0.1PF 5% +/-0.1PF 5%
25V 25V 25V 25V
NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2
0201 0201 0201 0201
VMAIN SWITH NODE PHASE 1
25 P3V8AON_VSW1
CY240 1
12PF
5%
25V
NP0-C0G 2
0201
25 24 P3V8AON_SW2
CY250 1
12PF
5%
25V 2
NP0-C0G
0201

25 24 P3V8AON_SW3 PAGE TITLE
CY260 1 CY261 1 DESENSE (3/3)

12PF 12PF
5% 5%
25V 25V
NP0-C0G 2 NP0-C0G 2
0201 0201
2 1
EMC REQUESTS FOR CAPS ON SOME SIGNALS
NO-STUFF'ED UNTIL WE GET CONFIRMATION / DATA IF THEY ARE NEEDED
<RDAR://58576418>
10 8 67 33 PMU_SYS_ALIVE
NOSTUFF
1 CZ000
100PF
5%
2 50V
C0G
0201
90 89 74 33 9 5 PMU_RESET_L
NOSTUFF
1 CZ001
100PF
5%
2 50V
C0G
0201
33 9 SOC_WDOG
NOSTUFF
1 CZ002
100PF
5%
2 50V
C0G
0201
96 91 89 33 6 SOC_SOCHOT_L
NOSTUFF
CZ003
1
100PF
5%
2 C0GV
0201
90 58 57 34 UPC_PMU_RESET_3V3
NOSTUFF
1 CZ004
100PF
5%
2 50V
C0G
0201
PAGE TITLE
EMC
BOM_COST_GROUP=EMC
VBAT MPMU BUCK 2 MPMU BUCK 8
21 PPVBAT_AON PPVBAT_AON 89 31 PPVDD_SOC_S1 PPVDD_SOC_S1 89 PPVDD_DISP_S1 PPVDD_DISP_S1 89
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.1500 MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.6000 MIN_LINE_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000
VOLTAGE=13.05V VOLTAGE=0.857 VOLTAGE=0.942
PPVBAT_AON 22 PPVDD_SOC_S1 12 PPVDD_DISP_S1 2
PPVDD_SOC_S1 97 PPVDD_DISP_S1 3
PPVDD_DISP_S1 97
USBC DCIN
PPDCIN_USBC_AON PPDCIN_USBC_AON
55
MAKE_BASE=TRUE
89
MPMU BUCK 3 MPMU BUCK 9
VOLTAGE=13.1 32 PP1V8_S2 PP1V8_S2 89
MAKE_BASE=TRUE PPVDD_DCS_S1 PPVDD_DCS_S1 89
MIN_NECK_WIDTH=0.1000 MAKE_BASE=TRUE
PPDCIN_USBC_AON 22 MIN LINE WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
VOLTAGE=1 8 MIN_LINE_WIDTH=0.2000
PPDCIN_USBC_AON 44 48 VOLTAGE=0.842
PPDCIN_USBC_AON 98 PP1V8_S2 39
PPVDD_DCS_S1 3
PP1V8_S2 31
PPVDD_DCS_S1 97
PP1V8_S2 27
PBUS PP1V8_S2 22 23
PP1V8_S2 52
22 PPBUS_AON PPBUS_AON 89
MAKE_BASE=TRUE PP1V8_S2 32
PP1V8_S2
VOLTAGE=13.1
PP1V8_S2
28
56 57 60
SPMU BUCK 10
PPBUS_AON 44 PP1V8_S2 56 60 27 PP0V6_S1_VDDQL PP0V6_S1_VDDQL 89
MAKE_BASE=TRUE
PPBUS_AON 46 PP1V8_S2 46 MIN_NECK_WIDTH=0.1000
PPBUS_AON 46 PP1V8_S2 92 VOLTAGE=0.6
PPBUS_AON 1 PP1V8_S2 56 58 60
PP0V6_S1_VDDQL 10
PP US_AON PP1V8_S2 46
PP0V6_S1_VDDQL 97
PPBUS_AON 31 PP1V8_S2 42
PPBUS_AON PP1V8_S2
98
PP1V8_S2
51
70
MPMU BUCK 11
PP1V8_S2 20 32 PPVDD_ECPU_AWAKE PPVDD_ECPU_AWAKE 9
MAKE_BASE=TRUE
PP1V8_S2 68 MIN_NECK_WIDTH=0.1000
PP1V8_S2 80 VOLTAGE=1.06
ICEMAN VMAIN PP1V8_S2 42
PPVDD_ECPU_AWAKE 12
PP1V8_S2 84
25 PP3V8_AON PP3V8_AON 89
MAKE_BASE=TRUE PP1V8_S2 96 PPVDD_ECPU_AWAKE 97
MIN_LINE_WIDTH=0.2000 PP1V8_S2 99
VOLTAGE=3.8
PP3V8_AON 45
PP3V8_AON 45
PP3V8_AON 84
PP3V8_AON 76
PP3V8_AON
PP3V8_AON
21
SPMU BUCKwww.teknisi-indonesia.com
4 SPMU BUCK 12
PP3V8_AON 45 27 PP1V06_S2SW_DRAM PP1V06_S2SW_DRAM 89 27 PP0V88_S1 PP0V88_S1 89
MAKE_BASE=TRUE MAKE_BASE=TRUE
PP3V8_AON 35 MIN_NECK_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000
PP3V8_AON 45 VOLTAGE=1.06 VOLTAGE=0.88
PP3V8_AON 92 93 94
PP1V06_S2SW_DRAM 10 PP0V88_S1 28
PP3V8_AON 84
PP1V06_S2SW_DRAM 28 PP0V88_S1 97
PP3V8_AON 35
PP1V06_S2SW_DRAM 97
PP3V8_AON 20
PP1V06_S2SW_DRAM 93
PP3V8_AON 95
PP3V8_AON 39
PP3V8_AON 6
PP3V8_AON 98
SPMU BUCK 5
27 PP0V764_S1_SRAM PP0V764_S1_SRAM 89
MAKE_BASE=TRUE
VOLTAGE=0.764
PP0V764_S1_SRAM 13 48
PP0V764_S1_SRAM 97
ICEMAN LDO5
24 PP5V_AON PP5V_AON
MAKE_BASE=TRUE
VOLTAGE=5.1
PP5V_AON 24
SPMU BUCK 6
27 PP2V5_AWAKE_NAND PP2V5_AWAKE_NAND 89
MAKE_BASE=TRUE
VOLTAGE=2.5
MPMU BUCK 0 PP2V5_AWAKE_NAND 64 65 66
PP2V5_AWAKE_NAND 99
31 PPVDD_PCPU_AWAKE PPVDD_PCPU_AWAKE 89
MAKE_BASE=TRUE
VOLTAGE=1.06
PPVDD_PCPU_AWAKE 12
PPVDD_PCPU_AWAKE 93 MPMU BUCK 7

PPVDD_PCPU_AWAKE 97
32 PPVDD_CPU_SRAM_AWAKE PPVDD_CPU_SRAM_AWAKE 89
MAKE_BASE=TRUE SYNC_MASTER=KEI_T668_MLB SYNC_DATE=11/06/2019
MIN_NECK_WIDTH=0.1000 PAGE TITLE
MPMU BUCK 1 VOLTAGE=1.06
PPVDD_CPU_SRAM_AWAKE 13 48
POWER ALIASES 1
34 31 PPVDD_GPU_AWAKE PPVDD_GPU_AWAKE 89
MAKE_BASE=TRUE PPVDD_CPU_SRAM_AWAKE 97
VOLTAGE=1.06
PPVDD_GPU_AWAKE 12
PPVDD_GPU_AWAKE 93
PPVDD_GPU_AWAKE 97
1
SPMU BUCK 13 MPMU BUCK 13 SW 3 SPMU LDO 4
27 PP1V25_S2 PP1V25_S2 89 32 PP1V25_AWAKE_IO PP1V25_AWAKE_IO 89 28 PP0V72_S2_VDD_LOW PP0V72_S2_VDD_LOW 89
MIN_LINE_WIDTH=0.2000 MIN_LI E_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000
VOLTAGE=1.25 VOLTAGE=1 225 VOLTAGE=0.72
PP1V25_S2 11 PP1V25_AWAKE_IO 4 5 6 8 11 PP0V72_S2_VDD_LOW 14
PP1V25_S2 11 PP1V25_AWAKE_IO 14 PP0V72_S2_VDD_LOW 14
PP1V25_S2 14 PP1V25_AWAKE_IO 14 PP0V72_S2_VDD_LOW 14
PP1V25_S2 14 PP1V25_AWAKE_IO 14 PP0V72_S2_VDD_LOW 14 48
PP1V25_S2 28 29 PP1V25_AWAKE_IO 14 PP0V72_S2_VDD_LOW 14
PP1V25_S2 32 PP1V25_AWAKE_IO 14
PP1V25_S2 PP1V25_AWAKE_IO
PP1V25_S2
27
31 PP1V25_AWAKE_IO
88
79
MPMU LDO 5
PP1V25_S2 3 PP1V25_AWAKE_IO 93 33 NC_MPMU_VLDO5 NC_MPMU_VLDO5
PP1V25_S2 55 57 58 PP1V25_AWAKE_IO 4
PP1V25_S2 34 PP1V25_AWAKE_IO 75 76 77
PP1V25_S2 PP1V25_AWAKE_IO
PP1V25_S2
28
92 PP1V25_AWAKE_IO
34
76
SPMU LDO 6
PP1V25_S2 60 PP1V25_AWAKE_IO 41 28 NC SPMU VLDO6 NC SPMU VLDO6
PP1V25_S2 3
PP1V25_S2 43
PP1V25_S2 51 MPMU LDO 7

PP1V25_S2 41
33 PP3V3_S2_UPC PP3V3_S2_UPC 89
PP1V25_S2 42 MAKE_BASE=TRUE
PP1V25_S2 43 MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
PP1V25_S2 43
PP1V25_S2 PP3V3_S2_UPC
PP1V25_S2
86
62
SPMU BUCK 3 SW 4 55 57 58
PP1V25_S2 76
PP1V25_S2 (NOT USED EXTERNALLY, SPMU GPIOS ONLY)

20
PP1V25_S2
PP1V25_S2
96
90
SPMU LDO 8
PP1V25_S2 84 28 PP1V2_AWAKE_PLL PP1V2_AWAKE_PLL 89
MAKE_BASE=TRUE
PP1V25_S2 97 98 MIN_NECK_WIDTH=0.1000
PP1V25_S2 41
SPMU BUCK 13 SW 5 VOLTAGE=1.2
PP1V2_AWAKE_PLL 10
28 PP1V25_AWAKESW_VCCQ PP1V25_AWAKESW_VCCQ 89
MAKE_BASE=TRUE PP1V2_AWAKE_PLL 14
MIN_NE K_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000 PP1V2_AWAKE_PLL 14
VOLTAGE=1.225
PP1V2_AWAKE_PLL 14
www.teknisi-indonesia.comPP1V25_AWAKESW_VCCQ
PP1V25_ W KESW_VCCQ
64 65
93
PP1V25_AWAKESW_VCCQ 99 MPMU LDO 9

NOT TO BE USED TO SOURCE POWER TO OTHER DEVICES
33 PP1V8_AON_MPMU PP1V8_AON_MPMU
MAKE_BASE=TRUE
VOLTAGE=1.8V
PP1V8_AON_MPMU
SPMU BUCK 12 SW 6 29 33 34 35
28 PP0V88_AWAKESW_NAND PP0V88_AWAKESW_NAND 89
MAKE_BASE=TRUE
MPMU BUCK 14 VOLTAGE=0.88
PP0V88_AWAKESW_NAND
34 PP1V4_LDO_PREREG PP1V4_LDO_PREREG
MAKE_BASE=TRUE
89
PP0V88_AWAKESW_NAND
64
65
SPMU LDO 9
PP0V88_AWAKESW_NAND NOT TO BE USED TO SOURCE POWER TO OTHER DEVICES
VOLTAGE=1.4
28 PP1V8 AON SPMU PP1V8 AON SPMU
MAKE_BASE=TRUE
PP1V4_LDO_PREREG 34 VOLTAGE=1.8
SPMU BUCK 12 SW 7 MPMU LDO 10

MPMU BUCK 3 SW 1 TIED TO SW6
33 NC_MPMU_VLDO10 NC_MPMU_VLDO10
32 PP1V8_AWAKE PP1V8_AWAKE 89 MAKE_BASE=TRUE NO_TEST=1
MAKE_BASE=TRUE
VOLTAGE=1.8
PP1V8_AWAKE
PP1V8_AWAKE
11 97
4
MPMU LDO 1
PP1V8_AWAKE NC_MPMU_VLDO1 NC_MPMU_VLDO1
PP1V8_AWAKE 17
7 33
MAKE_BASE=TRUE NO_TEST=1 SPMU LDO 11
PP1V8_AWAKE 4 28 PP0V855_S2SW_CIO PP0V855_S2SW_CIO 89
MAKE_BASE=TRUE
PP1V8_AWAKE 76 MIN_NECK_WIDTH=0.1000
PP1V8_AWAKE 75 77 78 VOLTAGE=0.855
PP1V8_AWAKE 41
PP0V855_S2SW_CIO
PP1V8_AWAKE 41 MPMU LDO 2 PP0V855_S2SW_CIO
14
14
(NOT USED)
SYNC_MASTER=KEI_T668_MLB
PAGE TITLE
MPMU BUCK 3 SW 2 POWER ALIASES 2
(NOT USED)
MPMU LDO 3
33 PP1V2_S2 PP1V2_S2 89
MAKE_BASE=TRUE
VOLTAGE=1.225
PP1V2_S2 74
PP1V2_S2 92
4 2 1
SPMU LDO12 SPMU LDO18
28 PP0V805_S1_VDD_FIXED PP0V805_S1_VDD_FIXED 89 28 NC_SPMU_VLDO18 NC_SPMU_VLDO18
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1
VOLTAGE=0.805
PP0V805_S1_VDD_FIXED 14 MPMU LDO19

PP0V805_S1_VDD_FIXED 14 (NOT USED)

PP0V805_S1_VDD_FIXED 14 97
SPMU LDO20
28 PP1V2_S2_CIO PP1V2_S2_CIO 89
MAKE_BASE=TRUE
VOLTAGE=1.2
PP1V2_S2_CIO 14
PP1V2_S2_CIO 1
PP1V2_S2_CIO 97
MPMU LDO13
MPMU LDO14
SPMU LDO15
28 NC_SPMU_VLDO15 NC_SPMU_VLDO15
MPMU LDO16
SPMU LDO17
28 NC_SPMU_VLDO17 NC_SPMU_VLDO17
PAGE TITLE
POWER ALIASES 3
2 1
KEYBOARD BACKLIGHT 1V85 IPD 3V3 PANEL SWITCH
72 PPVOUT_KBDLED PPVOUT_KBDLED 84 PP1V85_S2_IPD PP1V85_S2_IPD 89 70 PP3V3_SW_LCD PP3V3_SW_LCD 41 6 89
MAKE_BASE=TRUE MAKE_BASE=TRUE MAK _BASE=TRUE
VOLTAGE=40 VOLTAGE=1.85 VOLTAGE=3.3V
PPVOUT_KBDLED 81 PP1V85_S2_IPD 46
PPVOUT_KBDLED PP1V85_S2_IPD
98 47
5V PANEL SWITCH
70 PP5V_SW_LCD PP5V_SW_LCD 69 89
MAKE_BASE=TRUE
DISPLAY BACKLIGHT MIN_LINE_WIDTH=0.2000
VOLTAGE=5V
71 PPVOUT_LCDBKLT PPVOUT_LCDBKLT 89
MAKE_BASE=TRUE
VOLTAGE=47
USB0 3V3
PPVOUT_LCDBKLT 69
53 PP3V3_S2SW_USB0 PP3V3_S2SW_USB0 89
PPVOUT_LCDBKLT 98 MAKE_BASE=TRUE
VOLTAGE=3.3
3V3 S2 VR PP3V3_S2SW_USB0 53 55
PP3V3_S2SW_USB0 60
38 PP3V3_S2 PP3V3_S2 89
MAKE_BASE=TRUE PP3V3_S2SW_USB0 60
VOLTAGE=3.3
PP3V3_S2 46
PP3V3_S2
PP3V3_S2
72
68
USB1 3V3
PP3V3_S2 39 54 PP3V3_S2SW_USB1 PP3V3_S2SW_USB1 89
MAKE_BASE=TRUE
PP3V3_S2 92 MIN_NECK_WIDTH=0.1000
PP3V3_S2 70 VOLTAGE=3.3
PP3V3_S2 38
PP3V3_S2SW_USB1 54
PP3V3_S2 82
PP3V3_S2 99
PP3V3_S2SW_USB1 46
PP3V3_S2 43
PP3V3_S2SW_USB1 60
PP3V3_S2 52
3V3 AON LDO (NEEDS REVIEW)

35 PP3V3_AON PP3V3_AON 89
MAKE_BASE=TRUE
3V3 S2 TRACKPAD VR (NEEDS REVIEW)
VOLTAGE=3.3
84 PP3V3_S2_TPAD PP3V3_S2_TPAD
MAKE_BASE=TRUE
PP3V3_AON 82 MIN_NECK_WIDTH=0.1000
PP3V3_AON 92 VOLTAGE=3.3
PP3V3_AON 43
PP3V3_S2_TPAD 47
PP3V3_AON 34
PP3V3_AON 90
PP3V3_AON 96
PP3V3_AON 96
PP3V3_AON 96
1V8 S2 SWITCH
39 PP1V8_S2SW_VDD1 PP1V8_S2SW_VDD1
MAKE_BASE=TRUE
VOLTAGE=1.8
PP1V8_S2SW_VDD1 10
PP1V8_S2SW_VDD1 97
PP1V8_S2SW_VDD1
3V3 SENSOR SWITCH 93
39 PP3V3_S2SW_SNS PP3V3_S2SW_SNS 89
MAKE_BASE=TRUE
VOLTAGE=3.3
PP3V3_S2SW_SNS 44 45 46 47
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
43 50
48
1V8 AON LDO
35 PP1V8_AON PP1V8_AON 84 89
MAKE_BASE=TRUE
VOLTAGE=1.8V
5V S2 PP1V8_AON 73 89
PP1V8_AON 92
36 PP5V_S2 PP5V_S2 89
MAKE_BASE=TRUE PP1V8_AON 80
MIN_LINE_WIDTH=0.2000 PP1V8_AON 23
VOLTAGE=5
PP1V8_AON 90
PP5V_S2 70 PP1V8_AON 98
PP5V_S2 52 PP1V8_AON 34
PP5V_S2 46
PP5V_S2 57 58
PP5V_S2 57 58
PP5V_S2 71
PP5V_S2 26 SYNC_MASTER=KEI_T668_MLB SYNC_DATE=11/06/2019

PP5V_S2 PAGE TITLE
PP5V_S2
PP5V_S2
7
47
92
POWER ALIASES 4
PP5V_S2 95
PP5V_S2 87
PP5V_S2 36
PP5V_S2 96
PP5V_S2 98
2 1
5
3V8 AON SENSE RESISTOR LEFT AMP SENSE RESISTOR ALSCAM 5V SENSE RESISTOR
44 PPBUS_VMAIN_VIN_ISNS PPBUS_VMAIN_VIN_ISNS 46 PPBUS_SPKRAMP_LEFT_ISNS PPBUS_SPKRAMP_LEFT_ISNS 47 PP5V_S2_ALSCAM_ISNS PP5V_S2_ALSCAM_ISNS
VOLTAGE=3.8 VOLTAGE=13.1 VOLTAGE=5
PPBUS_VMAIN_VIN_ISNS 24 25 PPBUS_SPKRAMP_LEFT_ISNS 79 PP5V_S2_ALSCAM_ISNS 6
PPBUS_VMAIN_VIN_ISNS 98 PPBUS_SPKRAMP_LEFT_ISNS 77
PPBUS_SPKRAMP_LEFT_ISNS 77
TPAD 5V SENSE RESISTOR

3V3 S2 VR HIGH SIDE SENSE RESISTOR 47 PP5V_S2_TPAD_ISNS PP5V_S2_TPAD_ISNS
MAKE_BASE=TRUE
44 PPBUS_AON_3V3S2_VIN_ISNS PPBUS_AON_3V3S2_VIN_ISNS
MAKE_BASE=TRUE
RIGHT AMP SENSE RESISTOR MIN_NECK_WIDTH=0.1000
VOLTAGE=5
VOLTAGE=13.1 46 PPBUS_SPKRAMP_RIGHT_ISNS PPBUS_SPKRAMP_RIGHT_ISNS
MAKE_BASE=TRUE PP5V_S2_TPAD_ISNS 85
PPBUS_AON_3V3S2_VIN_ISNS 38 VOLTAGE=13.1
PPBUS_SPKRAMP_RIGHT_ISNS 79
TPAD 3.3V RESISTOR
5V S2 VR HIGH SIDE SENSE RESISTOR PPBUS_SPKRAMP_RIGHT_ISNS 78
PP3V3_S2_TPAD_ISNS PP3V3_S _TPAD_ISNS 89
PPBUS_SPKRAMP_RIGHT_ISNS 78 MAKE_BASE=TRUE
44 PPBUS_AON_5VS2_VIN_ISNS PPBUS_AON_5VS2_VIN_ISNS MIN_LINE_WIDTH=0.2000
MAKE_BASE=TRUE VOLTAGE=5
VOLTAGE=13.1
PP3V3_S2_TPAD_ISNS 85
PPBUS_AON_5VS2_VIN_ISNS 36
PPBUS_AON_5VS2_VIN_ISNS 98
3V3 S2 WLANBT LOAD SIDE SENSE RESISTOR TPAD 1.85V SENSE RESISTOR
46 PP3V3_S2_WLBT_ISNS PP3V3_S2_WLBT_ISNS 7 PP1V85_S2_TPAD_ISNS PP1V85_S2_TPAD_ISNS
MAKE_BASE=TRUE MAKE_BASE=TRUE
MASTER PMU HIGH SIDE SENSE RESISTOR MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3
MIN_N CK WIDTH=0.1000
VOLTAGE=5
45 PP3V8_AON_MPMU_ISNS_VIN PP3V8_AON_MPMU_ISNS_VIN
MAKE_BASE=TRUE PP3V3_S2_WLBT_ISNS 62 PP1V85_S2_TPAD_ISNS 85
VOLTAGE=3.8
PP3V8_AON_MPMU_ISNS_VIN 31 33 34
PP3V8_AON_MPMU_ISNS_VIN 31
PP3V8_AON_MPMU_ISNS_VIN 99
USB2 LEVEL SHIFTER 3.3V (UF750) SENSE RESISTOR
46 PP3V3_S2SW_USBLS1_ISNS PP3V3_S2SW_USBLS1_ISNS
MAKE_BASE=TRUE
SLAVE PMU HIGH SIDE SENSE RESISTOR VOLTAGE=3.3V
PP3V3_S2SW_USBLS1_ISNS 60
45 PP3V8_AON_SPMU_ISNS_VIN PP3V8_AON_SPMU_ISNS_VIN
MAKE_BASE=TRUE
VOLTAGE=3.8
USB2 LEVEL SHIFTER 1.8V (UF750) SENSE RESISTOR
PP3V8_AON_SPMU_ISNS_VIN 27 28
46 PP1V8_S2_USBLS1_ISNS www.teknisi-indonesia.com
PP1V8_S2_USBLS1_ISNS
MAKE_BASE=TRUE
ATC 3V3 LDO HIGH SIDE SENSE RESISTOR VOLTAGE=1.8
PP1V8_S2_USBLS1_ISNS 56 60
45 PP3V8_AON_ATC_ISNS PP3V8_AON_ATC_ISNS
MAKE_BASE=TRUE
VOLTAGE=3.8
WLAN BT 1V8 S2 CURRENT SENSE (Ixxx)
PP3V8_AON_ATC_ISNS 53
46 PP1V8_S2_WLBT_ISNS PP1V8_S2_WLBT_ISNS
PP3V8_AON_ATC_ISNS 54 MAKE_BASE=TRUE
VOLTAGE=1.8
PP1V8_S2_WLBT_ISNS
MESA HIGH SIDE SENSE RESISTOR 62
PP3V8_MESA_ISNS PP3V8_MESA_ISNS
45
MAKE_BASE=TRUE
KEYBOARD 1.85V SENSE RESISTOR
VOLTAGE=3.8
6 PP1V85_S2_KBD_ISNS PP1V85_S2_KBD_ISNS 89
MAKE_BASE=TRUE
PP3V8_MESA_ISNS 86 MIN_LINE_WIDTH=0.2000
VOLTAGE=1.85
DFR 1.8/3.3V HIGH SIDE CURRENT SENSE (Ixxx)

PP1V85_S2_KBD_ISNS 82 83
45 PP3V8_AON_DFR_ISNS PP3V8_AON_DFR_ISNS
MAKE_BASE=TRUE PP1V85_S2_KBD_ISNS 82
VOLTAGE=3.8
PP3V8_AON_DFR_ISNS
PP3V8_AON_DFR_ISNS
87
87
KEYBOARD LED 5V SENSE RESISTOR
46 PP5V_S2_KBDLED_ISNS PP5V_S2_KBDLED_ISNS
MAKE_BASE=TRUE
VOLTAGE=5
PP5V_S2_KBDLED_ISNS 72
PAGE TITLE
POWER ALIASES 5
5 4 3 2 1
5
TGA AP GPIO NC & TP TGA GPIO NC
NC_SOC_GPIO08 NC_SOC_GPIO08 NC_SOC_GPIO01 NC_SOC_GPIO01
TGA PCIE GP1 NC 6
6
6 TP_SWD_UPC_SWDIO1 TP_SWD_UPC_SWDIO1 6 NC_SOC_GPIO15 NC_SOC_GPIO15
8 NC_PCIE_USBHC_D2R_POS NC_PCIE_USBHC_D2R_POS MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1
6 NC_SOC_GPIO16 NC_SOC_GPIO16
8 NC_PCIE_USBHC_D2R_NEG NC_PCIE_USBHC_D2R_NEG MAKE_BASE=TRUE NO_TEST=1
6 NC_ENET_SYNC_1588 NC_ENET_SYNC_1588
NC_PCIE_USBHC_R2D_C_POS NC_PCIE_USBHC_R2D_C_POS
8
MAKE_BASE=TRUE NO_TEST=1 TGA AOP GPIO NC & RESOLVE MAKE_BASE=TRUE NO_TEST=1
8 NC_PCIE_USBHC_R2D_C_NEG NC_PCIE_USBHC_R2D_C_NEG
MAKE_BASE=TRUE NO_TEST=1 9 NC_R1_DUMP_TRIG NC_R1_DUMP_TRIG
8 NC_PCIE_CLK100M_USBHC_POS NC_PCIE_CLK100M_USBHC_POS
MAKE_BASE=TRUE NO_TEST=1 9 NC_AOP_FUNC1 NC_AOP_FUNC1
8 NC_PCIE_CLK100M_USBHC_NEG NC_PCIE_CLK100M_USBHC_NEG
MAKE_BASE=TRUE NO_TEST=1 9 NC_R1_RTC_SYNC
MAKE_BASE=TRUE
NC_R1_RTC_SYNC
NO_TEST=1
TGA SOC
8 NC_USBHC_RESET_L NC_USBHC_RESET_L 18 5 TP_SOC_AMUX_OUT TP_SOC_AMUX_OUT 89
MAKE_BASE=TRUE NO_TEST=1 9 NC_R1_INT NC_R1_INT MAKE_BASE=TRUE
9 NC_SPI_R1_CS_L NC_SPI_R1_CS_L
TGA PCIE GP2 NC 9 NC_AOP_FUNC5 NC_AOP_FUNC5
TGA UART NC
8 NC_PCIE_ENET_D2R_POS NC_PCIE_ENET_D2R_POS SPI_GYRO_CS_L SPI_GYRO_CS_L 9 51 6 NC_UART3_D2R_CTS_L NC_UART3_D2R_CTS_L
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1
8 NC_PCIE_ENET_D2R_NEG NC_PCIE_ENET_D2R_NEG GYRO_INT GYRO_INT 9 51 6 NC_UART3_R2D_RTS_L NC_UART3_R2D_RTS_L
8 NC_PCIE_ENET_R2D_C_POS NC_PCIE_ENET_R2D_C_POS GYRO_MOTION_INT GYRO_MOTION_INT 9 51 6 NC_UART3_D2R NC_UART3_D2R
8 NC_PCIE_ENET_R2D_C_NEG NC_PCIE_ENET_R2D_C_NEG 9 NC_AOP_FUNC10 NC_AOP_FUNC10 6 NC_UART3_R2D NC_UART3_R2D
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1
8 NC_PCIE_CLK100M_ENET_POS NC_PCIE_CLK100M_ENET_POS
9 NC_ALS_INT_L NC_ALS_INT_L
MAKE_BASE=TRUE NO_TEST=1 6 NC_UART4_D2R_CTS_L NC_UART4_D2R_CTS_L TGA MTR
8 NC_PCIE_CLK100M_ENET_NEG NC_PCIE_CLK100M_ENET_NEG 9 NC_AOP_FUNC14 NC_AOP_FUNC14 8 NC_MTR_VREF_NEG NC_MTR_VREF_NEG
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 6 NC_UART4_R2D_RTS_L NC_UART4_R2D_RTS_L MAKE_BASE=TRUE NO_TEST=1
8 NC_ENET_CLKREQ_L NC_ENET_CLKREQ_L 8 NC_MTR_VREF_POS NC_MTR_VREF_POS
MAKE_BASE=TRUE NO_TEST=1 6 NC_UART4_D2R NC_UART4_D2R MAKE_BASE=TRUE NO_TEST=1
8 NC_ENET_RESET_L NC_ENET_RESET_L 8 NC_MTR_VREF_ANAP NC_MTR_VREF_ANAP
MAKE_BASE=TRUE NO_TEST=1 6 NC_UART4_R2D NC_UART4_R2D MAKE_BASE=TRUE NO_TEST=1
8 NC_MTR_VREF_ANAN NC_MTR_VREF_ANAN
6 NC_UART7_RXD NC_UART7_RXD
TGA BOARD ID RESOLVE TGA AOP PDM NC 6 NC_UART7_TXD
MAKE_BASE=TRUE
NC_UART7_TXD
NO_TEST=1
SPI_DFR_CS_L SPI_DFR_CS_L 6 88 9 NC_PDM_CLK1 NC_PDM_CLK1
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1
9 NC_PDM_DATA1 NC_PDM_DATA1
TGA SSPIO 106 9 NC_PDM_CLK2 NC_PDM_CLK2 10 TGA AOP I2CM1 NC
6 NC_SSPI0_MOSI NC_SSPI0_MOSI 106 9 NC_PDM_CLK5
MAKE_BASE=TRUE
NC_PDM_CLK5
NO_TEST=1
106
TGA MIPI NC 9 NC_I2C_AOP_ENET_SCL NC_I2C_AOP_ENET_SCL
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1
7 NC_MIPI0C_CLK_POS NC_MIPI0C_CLK_POS
106 9 NC_PDM_CLK6 NC_PDM_CLK6 106 MAKE_BASE=TRUE NO_TEST=1 9 NC_I2C_AOP_ENET_SDA NC_I2C_AOP_ENET_SDA
7 NC_MIPI0C_CLK_NEG NC_MIPI0C_CLK_NEG
106 9 NC_PDM_DATA2 NC_PDM_DATA2 106 MAKE_BASE=TRUE NO_TEST=1
7 NC_MIPI0C_DATA_0_POS NC_MIPI0C_DATA_0_POS
TGA SOC I2S NC 7 NC_MIPI0C_DATA_0_NEG NC_MIPI0C_DATA_0_NEG

TGA PDM NC
7 NC_MIPI0C_DATA_1_POS NC_MIPI0C_DATA_1_POS 106 9 NC_PDM_CLK2 NC_PDM_CLK2 106
6 NC_SOC_I2S1_MCK NC_SOC_I2S1_MCK MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1
NC_MIPI0C_DATA_1_NEG NC_MIPI0C_DATA_1_NEG NC_PDM_CLK5 NC_PDM_CLK5
6 NC_SOC_I2S0_MCK NC_SOC_I2S0_MCK
TGA AOP I2C 7
106 9
106
7 NC_MIPI_FTCAM_DATA_POS1 NC_MIPI_FTCAM_DATA_POS1 106 9 NC_PDM_CLK6 NC_PDM_CLK6 106

9 I2C_AOP_ALS_SCL I2C_AOP_ALS_SCL 42 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1
MAKE_BASE=TRUE
NC_MIPI_FTCAM_DATA_NEG1 NC_MIPI_FTCAM_DATA_NEG1 NC_PDM_DATA2 NC_PDM_DATA2
TGA I2S3 NC www.teknisi-indonesia.com
106 9 106
9 I2C_AOP_ALS_SDA I2C_AOP_ALS_SDA 42 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1
MAKE_BASE=TRUE
6 NC_I2S3_BCLK NC_I2S3_BCLK
NC_I2S3_D2R NC_I2S3_D2R
6
MAKE_BASE=TRUE NO_TEST=1 TGA LPDP AUX, TX NC
6 NC_I2S3_R2D NC_I2S3_R2D
TGA AOP SPMI NC 7 NC_LPDPRX_AUX0 NC_LPDPRX_AUX0
6 NC_I2S3_LRCLK NC_I2S3_LRCLK 9 NC_AOP_SPMI0_SCLK NC_AOP_SPMI0_SCLK
NC_LPDPRX_AUX1 NC_LPDPRX_AUX1
6 NC_I2S3_MCLK
MAKE_BASE=TRUE
NC_I2S3_MCLK
NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 7
MAKE_BASE=TRUE NO_TEST=1 TGA SMC GPIO NC & RESOLVE
MAKE_BASE=TRUE NO_TEST=1 9 NC_AOP_SPMI0_SDATA NC_AOP_SPMI0_SDATA 7 NC_LPDPRX_AUX2 NC_LPDPRX_AUX2
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 9 NC_SMC_GPIO1 NC_SMC_GPIO1
MAKE_BASE=TRUE NO_TEST=1 52 9 SMC_FAN_PWM SMC_FAN_PWM
MAKE_BASE=TRUE
TGA ISP GPIOS NC TGA NUB & NUB GPIO & NUB SWD 7
7 NC_LPDPRX_AUX5 NC_LPDPRX_AUX5
TP_SOC_DOCK_ATTENTION TP_SOC_DOCK_ATTENTION 9 18 MAKE_BASE=TRUE NO_TEST=1
NC_ISP_GPIO1 NC_ISP_GPIO1
7
9 NC_BKLT_PWR_ON_SMC_LED_SEL
MAKE_BASE=TRUE
NC_BKLT_PWR_ON_SMC_LED_SEL 7 NC_LPDPRX_AUX6 NC_LPDPRX_AUX6
TGA AOP UART2 NC
7 NC_FTCAM_RESET_L NC_FTCAM_RESET_L MAKE_BASE=TRUE NO_TEST=1
MAKE_BASE=TRUE NO_TEST=1 7 NC_LPDPRX_AUX7 NC_LPDPRX_AUX7 9 NC_AOP_UART2_D2R NC_AOP_UART2_D2R
9 IPD_SPI_INT_L IPD_SPI_INT_L 84 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1
MAKE_BASE=TRUE
7 NC_LPDPRX_AUX8 NC_LPDPRX_AUX8 9 NC_AOP_UART2_R2D NC_AOP_UART2_R2D
9 CHGR_INT_L CHGR_INT_L 23 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1
TGA SMC I2C RESOLVE 9 NC_ENET_I2C_LOM_INT_L
MAKE_BASE=TRUE
NC_ENET_I2C_LOM_INT_L 7 NC_LPDPRX_AUX9 NC_LPDPRX_AUX9
9 I2C_SMC_PWR_SCL I2C_SMC_PWR_SCL 43 91 7 NC_LPDPRX_AUX10 NC_LPDPRX_AUX10
MAKE_BASE=TRUE 9 NC_ACDC_ID NC_ACDC_ID MAKE_BASE=TRUE NO_TEST=1
9 I2C_SMC_PWR_SDA I2C_SMC_PWR_SDA 43 91 NC_LPDPRX_AUX11 NC_LPDPRX_AUX11
MAKE_BASE=TRUE 9 NC_ACDC_BURST_EN_L NC_ACDC_BURST_EN_L MAKE_BASE=TRUE NO_TEST=1
9 I2C_SMC_IPD_SCL I2C_SMC_IPD_SCL 43 7 NC_LPDP_TX4POS NC_LPDP_TX4POS
NC_SPI_DP2HDMI_HOLD_L NC_SPI_DP2HDMI_HOLD_L
9 I2C_SMC_IPD_SDA
MAKE_BASE=TRUE
I2C_SMC_IPD_SDA 43
9
7 NC_LPDP_TX4NEG
MAKE_BASE=TRUE
NC_LPDP_TX4NEG
NO_TEST=1
TGA ISP I2C0/1/3 NC
MAKE_BASE=TRUE 9 NC_HDMI_CEC_AOP_TX NC_HDMI_CEC_AOP_TX MAKE_BASE=TRUE NO_TEST=1
7 NC_LPDP_TX5POS NC_LPDP_TX5POS 7 NC_ISP_I2C0_SCL NC_ISP_I2C0_SCL
9 NC_HDMI_CEC_AOP_RX NC_HDMI_CEC_AOP_RX MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1
7 NC_LPDP_TX5NEG NC_LPDP_TX5NEG 7 NC_ISP_I2C0_SDA NC_ISP_I2C0_SDA
9 NC_HDMI_HPD_AOP NC_HDMI_HPD_AOP MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1
TGA DISPLAY NC & RESOLVE 9 NC_SWD_NUB_R1_SWDIO
MAKE_BASE=TRUE
NC_SWD_NUB_R1_SWDIO
NO_TEST=1
7 NC_ISP_I2C1_SCL NC_ISP_I2C1_SCL
7 NC_SPI_DISP_BKLT_MISO NC_SPI_DISP_BKLT_MISO 7 NC_ISP_I2C1_SDA NC_ISP_I2C1_SDA
7 NC_SPI_DISP_BKLT_MOSI_R NC_SPI_DISP_BKLT_MOSI_R 7 NC_ISP_I2C3_SCL NC_ISP_I2C3_SCL
7 NC_DISP_BKLT_LSYNC
MAKE_BASE=TRUE
NC_DISP_BKLT_LSYNC
NO_TEST=1
TGA MISC 7 NC_ISP_I2C3_SDA
MAKE_BASE=TRUE
NC_ISP_I2C3_SDA
NO_TEST=1

7 NC_BKLT_FAULT_INT_L NC_BKLT_FAULT_INT_L 5 NC_SWD_TMS3 NC_SWD_TMS3
I2C_DISP_BKLT_SCL I2C_DISP_BKLT_SCL NC_NAND0_PCIE_RESET1_L NC_NAND0_PCIE_RESET1_L
41 7
MAKE_BASE=TRUE
8
MAKE_BASE=TRUE NO_TEST=1 TGA ISP SPMI NC
41 7 I2C_DISP_BKLT_SDA I2C_DISP_BKLT_SDA 6 PMU_VDDHI_UVWARN_L PMU_VDDHI_UVWARN_L 33 34
MAKE_BASE=TRUE MAKE_BASE=TRUE 7 NC_ISP_SPMI0_CLK NC_ISP_SPMI0_CLK
7 NC_DISPLAY_POL NC_DISPLAY_POL
MAKE_BASE=TRUE NO_TEST=1 7 NC_ISP_SPMI0_DATA NC_ISP_SPMI0_DATA SYNC_MASTER=AITKEN_T668_MLB SYNC_DATE=09/18/2019
NC_DISP_FSYNC NC_DISP_ SYNC PAGE TITLE
7
7 NC_DISP_TOUCH_EB
MAKE_BASE=TRUE
NC_DISP_TOUCH_EB
MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1 7
NC_ISP_SPMI1_CLK
NC_ISP_SPMI1_DATA
NC_ISP_SPMI1_CLK
MAKE_BASE=TRUE
NC_ISP_SPMI1_DATA
NO_TEST=1 SIGNAL ALIASES 1
7 NC_DISP_TOUCH_BSYNC0 NC_DISP_TOUCH_BSYNC0
TGA SPI 7 NC_SENSOR1_CLK
MAKE_BASE=TRUE
NC_SENSOR1_CLK
NO_TEST=1
7 NC_DISP_TOUCH_BSYNC1 NC_DISP_TOUCH_BSYNC1
MAKE_BASE=TRUE NO_TEST=1 6 NC_SOC_SPI2_SSIN NC_SOC_SPI2_SSIN 7 NC_SENSOR2_CLK NC_SENSOR2_CLK
7 NC_DISP_SPMI_CLK NC_DISP_SPMI_CLK
MAKE_BASE=TRUE NO_TEST=1 7 NC_SENSOR3_CLK NC_SENSOR3_CLK
7 NC_DISP_SPMI_DATA NC_DISP_SPMI_DATA
MAKE_BASE=TRUE NO_TEST=1 6 NC_SPMI2_CLK NC_SPMI2_CLK
5 4 3 2 1
LATTICE SECDIS FPGA AUDIO AMPLIFIER TDM SE
74 NC_SEP_IRCAM_DISABLE_IC_L NC_SEP_IRCAM_DISABLE_IC_L 75 TDM_1V8_SPKRAMP_L_BCLK TDM_1V8_SPKRAMP_L_BCLK 77 80 20 NC_I2C_SE_SCL NC_I2C_SE_SCL
74 NC_IRCAM_ENABLE_IN_IC NC_IRCAM_ENABLE_IN_IC TDM_1V8_SPKRAMP_L_BCLK 77 20 NC_I2C_SE_SDA NC_I2C_SE_SDA
74 NC_IRCAM_ENABLE_SEC_1V8_OUT NC_IRCAM_ENABLE_SEC_1V8_OUT 75 TDM_1V8_SPKRAMP_L_FSYNC TDM_1V8_SPKRAMP_L_FSYNC 77 80
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE
74 NC_DMIC_CLK2_IN_IC NC_DMIC_CLK2_IN_IC TDM_1V8_SPKRAMP_L_FSYNC 77
NC_DMIC_DATA2_1V8_IN NC_DMIC_DATA2_1V8_IN TDM_1V8_SPKRAMP_L_R2D TDM_1V8_SPKRAMP_L_R2D
74
75
MAKE_BASE=TRUE
77 80
DISPLAY POWER SEQUENCER
74 NC_DMIC_DATA2_SEC_OUT_IC NC_DMIC_DATA2_SEC_OUT_IC TDM_1V8_SPKRAMP_L_R2D 77
MAKE_BASE=TRUE NO_TEST=1 70 PMU_SYS_ALIVE PMU_SYS_ALIVE 33 67 89 100
MAKE_BASE=TRUE
74 NC_FTCAM_ENABLE_IN NC_FTCAM_ENABLE_IN 75 TDM_1V8_SPKRAMP_L_D2R TDM_1V8_SPKRAMP_L_D2R 77 80
74 NC_FTCAM_ENABLE_SEC_1V8_OUT NC_FTCAM_ENABLE_SEC_1V8_OUT TDM_1V8_SPKRAMP_L_D2R 77
NC_DMIC_CLK2_1V8_OUT_R_IC NC_DMIC_CLK2_1V8_OUT_R_IC TDM_1V8_SPKRAMP_R_BCLK TDM_1V8_SPKRAMP_R_BCLK
74
MAKE_BASE=TRUE
75
MAKE_BASE=TRUE
78 8
VITAMIN C
TDM_1V8_SPKRAMP_R_BCLK 78
96 NC_DEBUG_JTAG_SOC_TDO NC_DEBUG_JTAG_SOC_TDO
75 TDM_1V8_SPKRAMP_R_FSYNC TDM_1V8_SPKRAMP_R_FSYNC 78 80
MAKE_BASE=TRUE 96 NC_DEBUG_JTAG_SOC_TDI NC_DEBUG_JTAG_SOC_TDI
ACE2 GPIOS TDM_1V8_SPKRAMP_R_FSYNC 78
96 NC_DC_MUX_SEL
MAKE_BASE=TRUE
NC_DC_MUX_SEL
NO_TEST=1
57 55 UPC_SMC_I2C_INT_L UPC_SMC_I2C_INT_L 75 TDM_1V8_SPKRAMP_R_R2D TDM_1V8_SPKRAMP_R_R2D 78 80
MAKE_BASE=TRUE MAKE_BASE=TRUE 96 60 ATCRTMR0_RESET_MUX_1V8_L ATCRTMR0_RESET_MUX_1V8_L
MAKE_BASE=TRUE
58 UPC_SMC_I2C_INT_L TDM_1V8_SPKRAMP_R_R2D 78
UPC_I2C_INT_L UPC_I2C_INT_L TDM_1V8_SPKRAMP_R_D2R TDM_1V8_SPKRAMP_R_D2R

57 55
MAKE_BASE=TRUE
6 75
MAKE_BASE=TRUE
78 80
USBC CIO
58 UPC_I2C_INT_L TDM_1V8_SPKRAMP_R_D2R 78
53 USBC_ATC0_R2D_P<1> USBC_ATC0_R2D_P<1> 53
MAKE_BASE= RUE
56 UPC0_GPIO7 UPC0_GPIO7 56 57 96
MAKE_BASE=TRUE 53 USBC_ATC0_R2D_N<1> USBC_ATC0_R2D_N<1> 53
SPEAKERAMP RESET 53 USBC_ATC0_R2D_P<2>

MAKE_BASE=TRUE
USBC_ATC _R2D_P<2> 53
MAKE_BASE=TRUE
75 SPKRAMP_RESET_L SPKRAMP_RESET_L 6
USBC_ATC0_R2D_N<2> USBC_ATC0_R2D_N<2> ATC0
TGA LPDP RX NC MAKE_BASE=TRUE 53
MAKE_BASE=TRUE
53
LANE SWAP
53 USBC_ATC0_D2R_C_P<1> USBC_ATC0_D2R_C_P<1> 53
7 NC_LPDPRX_RX_P_0 NC_LPDPRX_RX_P_0 MAKE_BASE=TRUE
7 NC_LPDPRX_RX_N_0
MAKE_BASE=TRUE
NC_LPDPRX_RX_N_0
NO_TEST=1
USBC LDO ENABLES 53 USBC_ATC0_D2R_C_N<1> USBC_ATC0_D2R_C_N<1>
MAKE_BASE=TRUE
53
53 USBC0_3V3LDO_EN_MUX USBC0_3V3LDO_EN_MUX 53 USBC_ATC0_D2R_C_P<2> USBC_ATC0_D2R_C_P<2> 53
7 NC_LPDPRX_RX_P_1 NC_LPDPRX_RX_P_1 MAKE_BASE=TRUE MAKE_BA E=TRUE
96 USBC0_3V3LDO_EN_MUX 53 USBC_ATC0_D2R_C_N<2> USBC_ATC0_D2R_C_N<2> 53
7 NC_LPDPRX_RX_N_1 NC_LPDPRX_RX_N_1 MAKE_BASE=TRUE
54 USBC1_3V3LDO_EN USBC1_3V3LDO_EN 58 54 USBC_ATC1_R2D_P<1> USBC_ATC1_R2D_P<1> 54
7 NC_LPDPRX_RX_P_2 NC_LPDPRX_RX_P_2 MAKE_BASE=TRUE MAKE_BASE=TRUE
54 USBC_ATC1_R2D_N<1> USBC_ATC1_R2D_N<1> 54
7 NC_LPDPRX_RX_P_3
MAKE_BASE=TRUE
NC_LPDPRX_RX_P_3
NO_TEST=1
USBC LDO HPD 54 USBC_ATC1_R2D_P<2> USBC_ATC1_R2D_P<2>
MAKE_BASE=TRUE
54
5 NC_ATC1_HPD NC_ATC1_HPD 54 USBC_ATC1_R2D_N<2> USBC_ATC1_R2D_N<2> 54
7 NC_LPDPRX_RX_N_3 NC_LPDPRX_RX_N_3 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE
5 NC_ATC0_HPD NC_ATC0_HPD 54 USBC_ATC1_D2R_C_P<1> USBC_ATC1_D2R_C_P<1> 54
7 NC_LPDPRX_RX_P_4 NC_LPDPRX_RX_P_4 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE
54 USBC_ATC _D2R_C_N<1> USBC_ATC1_D2R_C_N<1> 54
USBC_ATC1_D2R_C_P<2> USBC_ATC1_D2R_C_P<2>
NC_LPDPRX_RX_P_5 NC_LPDPRX_RX_P_5 CHARGER 54 54
7 MAKE_BASE=TRUE
54 USBC_ATC1_D2R_C_N<2> USBC_ATC1_D2R_C_N<2> 54
7 NC_LPDPRX_RX_N_5 NC_LPDPRX_RX_N_5 22 NC_CHGR_EN_VR1 NC_CHGR_EN_VR1 MAKE_BASE=T UE
7 NC_LPDPRX_RX_P_6 NC_LPDPRX_RX_P_6
USBC0_D2R_P<1> USBC0_D2R_P<1>
7 NC_LPDPRX_RX_N_6 NC_LPDPRX_RX_N_6
NAND REFERENCE 53
MAKE_BASE=TRUE
59
53 USBC0_D2R_N<1> USBC0_D2R_N<1> 59
7 NC_LPDPRX_RX_P_7 NC_LPDPRX_RX_P_7 64 SWD_NAND0_SWCLK SWD_NAND0_SWCLK 5 67 107 MAKE_BASE=TRUE
53 USBC0_D2R_P<2> USBC0_D2R_P<2> 59
7 NC_LPDPRX_RX_N_7 NC_LPDPRX_RX_N_7 64 SWD_NAND0_SWDIO SWD_NAND0_SWDIO 5 67 107 MAKE_BASE=TRUE
53 USBC0_D2R_N<2> USBC0_D2R_N<2> 59 USBC0
7 NC_LPDPRX_RX_P_8 NC_LPDPRX_RX_P_8 65 SWD_NAND0_SWCLK SWD_NAND0_SWCLK 5 67 107 MAKE_BASE= RUE
53 USBC0_R2D_CR_P<1> USBC0_R2D_CR_P<1> 59
LANE SWAP
7 NC_LPDPRX_RX_N_8 NC_LPDPRX_RX_N_8 65 SWD_NAND0_SWDIO SWD_NAND0_SWDIO 5 67 107 MAKE_BASE=TRUE
53 USBC0_R2D_CR_N<1> USBC0_R2D_ R_N<1> 59
7 NC_LPDPRX_RX_P_9 NC_LPDPRX_RX_P_9 64 PP0V9_S5E0_VDD_PLL PP0V9_S5E0_VDD_PLL 67 MAKE_BASE=TRUE
7 NC_LPDPRX_RX_N_9 NC_LPDPRX_RX_N_9 65 PP0V9_S5E1_VDD_PLL PP0V9_S5E1_VDD_PLL 67 MAKE_BASE=TRUE
53 USBC0_R2D_CR_N<2> USBC0_R2D_CR_N<2> 59
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USBC1_R2D_CR_N<1> USBC1_R2D_CR_N<1>
USB LEVEL SHIFTER 54
MAKE_BASE=TRUE
59
60 TP_EUSB_LS1NEG TP_EUSB_LS1NEG MAKE_BASE=TRUE
MAKE_BASE=TRUE
54 USBC1_R2D_CR_N<2> USBC1_R2D_CR_N<2> 59
60 TP_EUSB_LS1POS TP_EUSB_LS1POS MAKE_BASE=TRUE
MAKE_BASE=TRUE
60 NC_USB_LS1NEG NC_USB_LS1NEG 107
MAKE_BASE=TRUE
60 NC_USB_LS1POS NC_USB_LS1POS 107
MAKE_BASE=TRUE
96 60 USB2_ATC0_LS_MUX_P USB2_ATC0_LS_MUX_P
MAKE_BASE=TRUE
96 60 USB2_ATC0_LS_MUX_N USB2_ATC0_LS_MUX_N
MAKE_BASE=TRUE
96 60 USB_DBG_LS_MUX_P USB_DBG_LS_MUX_P
MAKE_BASE=TRUE
96 60 USB_DBG_LS_MUX_N USB_DBG_LS_MUX_N
MAKE_BASE=TRUE
60 USB2_ATC1_LS_P USB2_ATC1_LS_P 61
MAKE_BASE=TRUE
60 USB2_ATC1_LS_N USB2_ATC1_LS_N 61
MAKE_BASE=TRUE
107 NC_USB_LS1POS NC_USB_LS1POS
MAKE_BASE=TRUE
SYNC_MASTER=T668_MLB
PAGE TITLE
107 NC_USB_LS1NEG NC_USB_LS1NEG
MAKE_BASE=TRUE SIGNAL ALIASES 2
2 1
SCSET RULES
DIELECTRIC BASED SPACING RULES
RULE DEFINITION LIST OF VALUES

EXAMPLE 1,3-5,7L,8L-10L
A_DIELECTRIC_(N)X
Calculates dielectric distance from stackup,
shortest distance is used unless L'is defined
2-10
EXAMPLE 2,1DL,3D-5D,7V,8VL-10VL
A_DIELECTRIC_(N)XD XV,XVL,X
Calculates dielectric distance from Hybrid Table and
stackup, shortest distance is used unless 'L' defined
PLEASE USE HYBRID TABLE
EXAMPLE 2_4,3L_5L
A_DIELECTRIC_(N)XIN_(N)XOUT
Calculates dielectric distance from stackup,
shortest distance is used unless L' is defined
PAGE TITLE
17.2 RULES
PHYSICAL CONSTRAINT SET, CLASS ASSIGNMENT PHYSICAL CONSTRAINT SET, CLASS ASSIGNMENT
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE
OVERRIDE
DOMAIN DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP AA*,DP BB* (LINE STARTS WITH FLAG DP:) Y/N CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP AA*,DP BB* (LINE STARTS WITH FLAG DP:) Y/N
I2C P A_45_OHM_SE *SMB*SCL*,*SMB*SDA*,*I2C*SCL*,*I2C*SDA*,*I2C*INT* Y GROUND P DEFAULT GND Y
SPI P A_45_OHM_SE *SPI*MISO*,*SPI*MOSI*,*SPI*CLK*,*SPI*CS* Y ANALOG_GROUND P DEFAULT *AGND*,GND_* Y
SPMI P A_45_OHM_SE *SPMI* Y AUDIO_CONN_HEADPHONE_OUT P WIDTH_0P400 UDIO_JACK_LEFT_OUT,AUDIO_JACK_RIGHT_OUT Y
SWD P A_45_OHM_SE SWD_NAND*,SWD_NUB* Y AUDIO_CONN_HEADPHONE_OUT P WIDTH_0P400 AUD_CONN_LEFT_OUT,AUD_CONN_RIGHT_OUT Y
JTAG P A 45 OHM SE *JTAG*SEL,*JTAG*TCK,*JTAG*TDI,*JTAG*TDO,*JTAG*TMS Y AUDIO_CONN_RETURN P WIDTH_0P500 AUDIO_JACK_GB_GND,AUDIO_JACK_CH_GND Y
CLOCK_24M P A_45_OHM_SE SOC_24M_O_R,NAND0_CLK24M* Y AUDIO_CONN_RETURN P WIDTH_0P500 AUD_CONN_RING2,AUD_CONN_SLEEVE Y
SOC_XTAL_24M_IN P A_45_OHM_SE SOC_XTAL24M_IN Y AUDIO_CONN_SENSE P WIDTH_0P100 AUDIO_JACK_LEFT_SNS,AUDIO_JACK_RIGHT_SNS Y
SOC_XTAL_24M_OUT P A_45_OHM_SE SOC_XTAL24M_OUT Y AUDIO_CONN_SENSE P WIDTH_0P100 AUDIO_JACK_TIP_SNS,AUDIO_JACK_RING_SNS Y
CLOCK_32K P A_45_OHM_SE PMU_CLK32K* Y AUDIO_CONN_SENSE P WIDTH_0P100 AUD_CONN_LEFT_SNS,AUD_CONN_RIGHT_SNS Y
TDM_LEFT P A_45_OHM_SE TDM_SPKRAMP_L*.TDM_SPKRAMP_A*,TDM_SPKRAMP_B* Y AUDIO_CONN_SENSE P WIDTH_0P100 AUD_CONN_TIP_SENSE,AUD_CONN_RING_SENSE Y
TDM_RIGHT P A_45_OHM_SE TDM_SPKRAMP_R*,TDM_SPKRAMP_D*,TDM_SPKRAMP_E* Y SPEAKERAMP_OUTPUT P SPKRAMP_OUT_DIFF DP:DP_SPKRAMP_*_OUT Y
TDM_CODEC P A_45_OHM_SE TDM_CODEC* Y SENSE_DIFF P SENSE_DIFF DP:DP_CHGR_CS*,DP_ISNS_*,DP_*VSNS_XW,DP_*_VSEN_XW Y
SPKR_ICC P A_45_OHM_SE SPKRAMP_ICC,SPKRAMP_*_ICC_R Y SENSE_DIFF P SENSE_DIFF DP:DP_SPMU_TDEV,DP_SPKRAMP_*_VSENSE Y
UART P A_45_OHM_SE UART_* Y SENSE_DIFF P SENSE_DIFF DP:DP_P3V8AON_ISEN*,DP_THMSNS*,DP_ISNS_*LCD Y
RESETS P A_45_OHM_SE *RST*,*RESET*,*PERST*,!PP3V3_UPC_PMU_RESET_R Y SENSE_DIFF P SENSE_DIFF DP:DP_SOC_*_RCAL,DP_P3V8IDIF2_FB Y
WDOG P A_45_OHM_SE SOC_WDOG Y SENSE_DIFF P SENSE_DIFF DP:DP_P3V8AON_VSNS,DP_ATCRTMR*_THERM_D Y
SOCHOT P A_45_OHM_SE SOC_SOCHOT_L Y RF_ANTENNA P WIDTH_0P100 RF_ANT_0,RF_ANT_1 Y
POWER_BUTTON P A_45_OHM_SE *PMU_ONOFF* Y PMU_BUCK_FB P VR_FEEDBACK BUCK*_FB* Y
FAULT P A_45_OHM_SE *FAULT*,!FAULT_LED_RST_L Y POWER P POWER PP* Y
DMIC PDM P A 45 OHM SE PDM_DMIC_DATA*,DMIC_DATA*,PDM_DMIC_CLK*,DMIC_CLK* Y CAPSLOCK_LED P WIDTH_0P150 KBD_CAP_CATHODE,KBD_LED1 Y
FAN_CTRL P A_45_OHM_SE SMC_FAN_* Y DBGLED_RETURN P WIDTH_0P200 DBGLED_RETURN Y
USBC_SOC_BSB0_D2R_1 P A_85_OHM_DIFF DP:DP_USBC_ATC0_D2R_C_1 Y
USBC_SOC_BSB0_R2D_1 P A_85_OHM_DIFF DP:DP_USBC_ATC0_R2D_1 Y
USBC SOC BSB0 R2D 2 P A 85 OHM DIFF DP:DP USBC ATC0 R2D 2 Y
USBC_SOC_BSB0_AUX P A_85_OHM_DIFF DP:DP_USBC_ATC0_AUX Y
USBC_SOC_BSB0_LSX P A_45_OHM_SE CIO_ATC0_LS* Y
USBC_BSB0_CONN_D2R_1 P A_85_OHM_DIFF DP:DP_USBC0_D2R_CR_1 Y
USBC_BSB0_CONN_R2D_1 P A 85 OHM DIFF DP:DP USBC0 R2D C 1 Y
USBC_BSB0_CONN_R2D_2 P A_85_OHM_DIFF DP:DP_USBC0_R2D_C_2 Y
USBC_BSB0_CONN_AUXLSX P A_85_OHM_DIFF DP:DP_USBC0_AUXLSX Y
USBC_UPC0_CONN_TOP P A_85_OHM_DIFF DP:DP_U BC0_USB_TOP Y
USBC_UPC0_CONN_BOT P A_85_OHM_DIFF DP:DP_USBC0_USB_BOT Y
USBC_UPC0_CONN_CC P WIDTH_0P400 USBC0_CC* Y
USBC_UPC0_CONN_SBU P A_45_OHM_SE USBC0_SBU* Y
USBC_SOC_RTMR0_USB2 P A_85_OHM_DIFF_TIGHT DP:DP_EUSB_ATC0 Y
USBC_RTMR0_MUX_USB2 P A_85_OHM_DIFF_TIGHT DP:DP_USB2_ATC0_LS_MUX Y
USBC_MUX_UPC0_USB2 P A_85_OHM_DIFF_TIGHT DP:DP_USB2_ATC0_LS,DP_USB2_ATC0_LS_R Y
USBC_MUX_VITC_USB2 P A_85_OHM_DIFF_TIGHT DP:DP_USB2_ATC0_LS_VITAMINC Y
USBC_SOC_BSB1_R2D_1 P A_85_OHM_DIFF DP:DP_US C_ATC1_R2D_1 Y
USBC_SOC_BSB1_R2D_2 P A_85_OHM_DIFF DP:DP_USBC_ATC1_R2D_2 Y
USBC_SOC_BSB1_AUX P A_85_OHM_DIFF DP:DP_USBC_ATC1_AUX Y
USBC_SOC_BSB1_LSX
USBC_BSB1_CONN_D2R_1
P
P
A_45_OHM_SE
A_85_OHM_DIFF
CIO_ATC1_LS*
DP:DP_USBC1_D2R_CR_1
Y
Y www.teknisi-indonesia.com
USBC_BSB1_CONN_R2D_1 P A_85_OHM_DIFF DP:DP_USBC1_R2D_C_1 Y
USBC BSB1 CONN R2D 2 P A_85_OHM_DIFF DP:DP_USBC1_R2D_C_2 Y
USBC_BSB1_CONN_AUXLSX P A_85_OHM_DIFF DP:DP_USBC1_AUXLSX Y
USBC_UPC1_CONN_TOP P A_85_OHM_DIFF DP:DP_USBC1_USB_TOP Y
USBC_UPC1_CONN_BOT P A_85_OHM_DIFF DP:DP_U BC1_USB_BOT Y
USBC_UPC1_CONN_CC P WIDTH_0P400 USBC1_CC* Y
USBC_UPC1_CONN_SBU P A_45_OHM_SE USBC1 SBU* Y
USBC_SOC_RTMR1_USB2 P A_85_OHM_DIFF_TIGHT DP:DP_EUSB_ATC1 Y
USBC_RTMR1 UPC1_USB2 P A_85_OHM_DIFF_TIGHT DP:DP_USB2_ATC1_LS Y
USBC_SOC_RTMR_USB2_DBG P A_85_OHM_DIFF_TIGHT DP:DP_EUSB_DBG Y
USBC_RTMR_MUX_USB2_DBG P A_85_OHM_DIFF_TIGHT DP:DP_USB_DBG_LS_MUX Y
USBC_MUX_UPC_USB2_DBG P A 85 OHM DIFF TIGHT DP:DP_USB_DBG_LS,DP_USB_DBG_LS_R Y
USBC_MUX_VITC_USB2_DBG P A_85_OHM_DIFF_TIGHT DP:DP_USB_DBG_LS_VITAMINC Y
USBC_LSX P A_45_OHM_SE *ATC*LS*X Y
MIPI_FTCAM_CLK P A_85_OHM_DIFF_TIGHT DP:DP_MIPI_FTCAM_CLK,DP_MIPI_CLOCK_CONN Y
MIPI_FTCAM_DATA P A_85_OHM_DIFF_TIGHT DP:DP_MIPI_FTCAM_DATA_0,DP_MIPI_DATA_CONN Y
MIPI_DFR_CLK P A_85_OHM_DIFF_TIGHT DP:DP_MIPI_DFR_CLK_CONN_FILT Y
MIPI_DFR_DATA P A_85_OHM_DIFF_TIGHT DP:DP_MIPI_DFR_DATA_CONN_FILT Y
PCIE_WIFI_D2R P A_85_OHM_DIFF_TIGHT DP:DP_PCIE_WLBT_D2R_C Y
PCIE_WIFI_R2D P A_85_OHM_DIFF_TIGHT DP:DP_PCIE_WLBT_R2D_C Y
PCIE_WIFI_CLK P A_85_OHM_DIFF_TIGHT DP:DP_PCIE_CLK100M_WLBT Y
PCIE_NAND0_D2R P A 85 OHM DIFF TIGHT DP:DP_PCIE_NAND0_D2R_C_0 Y
PCIE_NAND0_R2D P A_85_OHM_DIFF_TIGHT DP:DP_PCIE_NAND0_R2D_C_0 Y
PCIE_NAND0_CLK P A_85_OHM_DIFF_TIGHT DP:DP_PCIE_CLK100M_NAND0_0 Y
PCIE_NAND1_D2R P A_85_OHM_DIFF_TIGHT DP:DP_PCIE_NAND0_D2R_C_1 Y
PCIE_NAND1_R2D P A_85_OHM_DIFF_TIGHT DP:DP_PCIE_NAND0_R2D_C_1 Y
PCIE_NAND1_CLK P A 85 OHM DIFF TIGHT DP:DP_PCIE_CLK100M_NAND0_1 Y
PCIE_CLKREQ P A_45_OHM_SE *CLKREQ* Y
PANEL_L DP_DATA P A_85_OHM_DIFF_TIGHT DP:DP_DP0,DP_DP1,DP_DP2,DP_DP3 Y
PANEL_L DP_AUX P A_85_OHM_DIFF_TIGHT DP:DP_AUX Y
RCAL_PCIE P WIDTH_0P100 SOC_ST_PCIE_RCAL*,SOC_GP_PCIE_RCAL* Y
RCAL_CIO P WIDTH 0P100 SOC_ATCPHY0_RCAL*,SOC_ATCPHY1_RCAL* Y
RCAL_MIPI P WIDTH_0P100 *MIPI*REXT Y
RCAL_EUSB P WIDTH_0P100 SOC_ATC*_USB_RESREF,SOC_USBDBG_RESREF Y
BOARD_ID P A_45_OHM_SE BO RD_ID* Y
BOARD_REV P A_45_OHM_SE BOARD_REV* Y
WIRELESS_TIME_SYNC P A_45_OHM_SE *TIME_SYNC* Y
KBD_PWM P A_45_OHM_SE *KBD_BKLT_PWM*,BKLT_PWM_KEYB_3V3 Y SYNC_MASTER=T668_MLB SYNC_DATE=05/13/2019
PAGE TITLE
17.2 PHYSICAL CSETS

SPACING CONSTRAINT SET, CLASS ASSIGNMENT SPACING CONSTRAINT SET, CLASS ASSIGNMENT
OVERRIDE
OVERRIDE
DOMAIN DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP AA*,DP BB* (LINE STARTS WITH FLAG DP:) Y/N CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP AA*,DP BB* (LINE STARTS WITH FLAG DP:) Y/N
I2C S A_DIELECTRIC_3X = Y AUDIO_CONN_HEADPHONE_OUT S A_DIELECTRIC_3X = Y
SPI S A_DIELECTRIC_3X = Y AUDIO_CONN_RETURN S A_DIELECTRIC_2X = Y
SPMI S A_DIELECTRIC_3X = Y AUDIO_CONN_SENSE S A_DIELECTRIC_2X = Y
SWD S A_DIELECTRIC_3X Y SPEAKERAMP_OUTPUT S A_DIELECTRIC_2X = Y
JTAG S A DIELECTRIC 2X = Y SENSE DIFF S A DIELECTRIC 2X = Y
CLOCK_24M S A_DIELECTRIC_8X = Y RF_ANTENNA S RF_ANTENNA = Y
SOC_XTAL_24M_IN S A_DIELECTRIC_8X = Y PMU_BUCK_FB S DEFAULT = Y
SOC_XTAL_24M_OUT S A_DIELECTRIC_8X = Y S DEFAULT = Y
CLOCK_32K S A_DIELECTRIC_8X = Y CAPSLOCK_LED S DEFAULT = Y
TDM LEFT S A DIELECTRIC 3X = Y DBGLED RETURN S DEFAULT = Y
TDM_RIGHT S A_DIELECTRIC_3X = Y
TDM_CODEC S A_DIELECTRIC_3X = Y
SPKR_ICC S A_DIELECTRIC_3X = Y
UART S A_DIELECTRIC_2X Y
RESETS S A DIELECTRIC 3X = Y
WDOG S A_DIELECTRIC_3X = Y
SOCHOT S A_DIELECTRIC_3X = Y
POWER_BUTTON S A_DIELECTRIC_3X = Y
FAULT S A_DIELECTRIC_3X = Y
DMIC_PDM S A DIELECTRIC 3X = Y
FAN_CTRL S A_DIELECTRIC_2X = Y
USBC_SOC_BSB0_D2R_1 S A_DIELECTRIC_9X = Y
USBC_SOC_BSB0_R2D_1 S A_DIELECTRIC_9X Y
USBC SOC BSB0 R2D 2 S A DIELECTRIC 9X = Y
USBC_SOC_BSB0_AUX S A_DIELECTRIC_7X = Y
USBC_SOC_BSB0_LSX S A_DIELECTRIC_7X = Y
USBC_BSB0_CONN_D2R_1 S A_DIELECTRIC_9X = Y
USBC_BSB0_CONN_R2D_1 S A DIELECTRIC 9X = Y
USBC_BSB0_CONN_R2D_2 S A_DIELECTRIC_9X = Y
USBC_BSB0_CONN_AUXLSX S A_DIELECTRIC_7X = Y
USBC_UPC0_CONN_TOP S A_DIELECTRIC_5X = Y
USBC_UPC0_CONN_BOT S A_DIELECTRIC_5X Y
USBC_UPC0_CONN_CC S A_DIELECTRIC_2X = Y
USBC_UPC0_CONN_SBU S A_DIELECTRIC_2X = Y
USBC_SOC_RTMR0_USB2 S A_DIELECTRIC_6X = Y
USBC_RTMR0_MUX_USB2 S A_DIELECTRIC_6X = Y
USBC_MUX_UPC0_USB2 S A_DIELECTRIC_6X = Y
USBC_MUX_VITC_USB2 S A_DIELECTRIC_6X = Y
USBC_SOC_BSB1_R2D_1 S A_DIELECTRIC_10X = Y
USBC_SOC_BSB1_R2D_2 S A_DIELECTRIC_10X Y
USBC_SOC_BSB1_AUX S A_DIELECTRIC_7X = Y
USBC_SOC_BSB1_LSX
S
S
A_DIELECTRIC_7X
A_DIELECTRIC_10X
=
=
Y
Y www.teknisi-indonesia.com
USBC_BSB1_CONN_R2D_1 S A_DIELECTRIC_10X = Y
USBC BSB1 CONN R2D 2 S A_DIELECTRIC_10X = Y
USBC_BSB1_CONN_AUXLSX S A_DIELECTRIC_7X = Y
USBC_UPC1_CONN_TOP S A_DIELECTRIC_5X = Y
USBC_UPC1_CONN_BOT S A_DIELECTRIC_5X = Y
USBC_UPC1_CONN_CC S A_DIELECTRIC_2X Y
USBC UPC1 CONN SBU S A_DIELECTRIC_2X = Y
USBC_SOC_RTMR1_USB2 S A_DIELECTRIC_6X = Y
USBC_RTMR1_UPC1_USB2 S A_DIELECTRIC_6X = Y
USBC_SOC_RTMR_USB2_DBG S A_DIELECTRIC_6X = Y
USBC_RTMR_MUX_USB2_DBG S A_DIELECTRIC_6X = Y
USBC MUX UPC USB2 DBG S A_DIELECTRIC_6X = Y
USBC_MUX_VITC_USB2_DBG S A_DIELECTRIC_6X = Y
USBC_LSX S A_DIELECTRIC_6X = Y
MIPI_FTCAM_CLK S A_DIELECTRIC_6X = Y
MIPI_FTCAM_DATA S A_DIELECTRIC_6X Y
MIPI DFR CLK S A DIELECTRIC 6X = Y
MIPI_DFR_DATA S A_DIELECTRIC_6X = Y
PCIE_WIFI_D2R S A_DIELECTRIC_7X = Y
PCIE_WIFI_R2D S A_DIELECTRIC_7X = Y
PCIE_WIFI_CLK S A_DIELECTRIC_7X = Y
PCIE NAND0 D2R S A DIELECTRIC 7X = Y
PCIE_NAND0_R2D S A_DIELECTRIC_7X = Y
PCIE_NAND0_CLK S A_DIELECTRIC_7X = Y
PCIE_NAND1_D2R S A_DIELECTRIC_7X = Y
PCIE_NAND1_R2D S A_DIELECTRIC_7X Y
PCIE_NAND1_CLK S A DIELECTRIC 7X = Y
PCIE_CLKREQ S A_DIELECTRIC_2X = Y
PANEL_LPDP_DATA S A_DIELECTRIC_6X = Y
PANEL_LPDP_AUX S A_DIELECTRIC_6X = Y
RCAL_PCIE S A_DIELECTRIC_2X = Y
S A DIELECTRIC 2X = Y
RCAL_MIPI S A_DIELECTRIC_2X = Y
RCAL_EUSB S A_DIELECTRIC_2X = Y
BOARD_ID S A_DIELECTRIC_2X = Y
BOARD_REV S A_DIELECTRIC_2X Y
WIRELESS TIME SYNC S A DIELECTRIC 2X = Y
KBD_PWM S A_DIELECTRIC_2X = Y SYNC_MASTER=T668_MLB SYNC_DATE=05/13/2019
GROUND S DEFAULT = Y PAGE TITLE
ANALOG_GROUND S DEFAULT = Y 17.2 SPACING CSETS, ISO
4 2
SPACING CONSTRAINT SET ASSIGNMENT, CLASS-CLASS SPACING CONSTRAINT SET ASSIGNMENT, CLASS-CLASS SPACING CONSTRAINT SET ASSIGNMENT, CLASS-CLASS
CLASS TO CLASS SPACING CLASS TO CLASS SPACING CLASS TO CLASS SPACING
CLASS NAME CLASS NAME CONSTRAINT SET CLASS NAME CLASS NAME CONSTRAINT SET CLASS NAME CLASS NAME CONSTRAINT SET
I2C GROUND DEFAULT I2C POWER DEFAULT USBC_SOC_BSB0_D2R_1 USBC_SOC_BSB0_D2R_2 A_DIELECTRIC_6X
SPI GROUND DEFAULT SPI POWER DEFAULT USBC_SOC_BSB0_R2D_1 USBC_SOC_BSB0_R2D_2 A_DIELECTRIC_6X
SPMI GROUND DEFAULT SPMI POWER DEFAULT USBC_BSB0_CONN_D2R_1 USBC_BSB0_CONN_D2R_2 A_DIELECTRIC_6X
SWD GROUND DEFAULT SWD POWER DEFAULT USBC_BSB0_CONN_R2D_1 USBC_BSB0_CONN_R2D_2 A_DIELECTRIC_6X
JTAG GROUND DEFAULT JTAG POWER DEFAULT USBC_SOC_BSB1_D2R_1 USBC_SOC_BSB1_D2R_2 A_DIELECTRIC_6X
CLOCK_24M GROUND DEFAULT CLOCK_24M POWER DEFAULT USBC_SOC_BSB1_R2D_1 USBC_SOC_BSB1_R2D_2 A_DIELECTRIC_6X
CLOCK_32K GROUND DEFAULT CLOCK_32K POWER DEFAULT USBC_BSB1_CONN_D2R_1 USBC_BSB1_CONN_D2R_2 A_DIELECTRIC_6X
TDM_LEFT GROUND DEFAULT TDM_LEFT POWER DEFAULT USBC_BSB1_CONN_R2D_1 USBC_BSB1_CONN_R2D_2 A_DIELECTRIC_6X
TDM_RIGHT GROUND DEFAULT TDM_RIGHT POWER DEFAULT PANEL_LPDP_DATA PANEL_LPDP_DATA A_DIELECTRIC_5X
TDM_CODEC GROUND DEFAULT TDM_CODEC POWER DEFAULT SOC_XTAL_24M_IN SOC_XTAL_24M_OUT A_DIELECTRIC_2X
SPKR_ICC GROUND DEFAULT SPKR_ICC POWER DEFAULT
UART GROUND DEFAULT UART POWER DEFAULT
RESETS GROUND DEFAULT RESETS POWER DEFAULT
WDOG GROUND DEFAULT WDOG POWER DEFAULT
SOCHOT GROUND DEFAULT SOCHOT POWER DEFAULT
POWER_BUTTON GROUND DEFAULT POWER_BUTTON POWER DEFAULT
FAULT GROUND DEFAULT FAULT POWER DEFAULT
DMIC_PDM GROUND DEFAULT DMIC_PDM POWER DEFAULT
FAN_CTRL GROUND DEFAULT FAN_CTRL POWER DEFAULT
USBC_SOC_BSB0_D2R_1 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_SOC_BSB0_D2R_1 POWER A_DIELECTRIC_7X
USBC_SOC_BSB0_R2D_1 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC SOC BSB0 R2D 1 POWER A_DIELECTRIC_7X
USBC_SOC_BSB0_R2D_2 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_SOC_BSB0_R2D_2 POWER A_DIELECTRIC_7X
USBC_SOC_BSB0_AUX GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_SOC_BSB0_AUX POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_SOC_BSB0_LSX GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_SOC_BSB0_LSX POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_BSB0_CONN_D2R_1 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_BSB0_CONN_D2R_1 POWER A_DIELECTRIC_7X
USBC_BSB0_CONN_D2R_2 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC BSB0 CONN D2R 2 POWER A_DIELECTRIC_7X
USBC_BSB0_CONN_R2D_1 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_BSB0_CONN_R2D_1 POWER A_DIELECTRIC_7X
USBC_BSB0_CONN_AUXLSX GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_BSB0_CONN_AUXLSX POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_UPC0_CONN_TOP GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_UPC0_CONN_TOP POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_UPC0_CONN_BOT GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_UPC0_CONN_BOT POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_UPC0_CONN_CC GROUND DEFAULT USBC_UPC0_CONN_CC POWER DEFAULT
USBC_UPC0_CONN_SBU GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_UPC0_CONN_SBU POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_SOC_RTMR0_USB2 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_SOC_RTMR0_USB2 POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_RTMR0_MUX_USB2 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_RTMR0_MUX_USB2 POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_MUX_UPC0_USB2 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_MUX_UPC0_USB2 POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_MUX_VITC_USB2 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_MUX_VITC_USB2 POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_SOC_BSB1_AUX GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_SOC_BSB1_AUX POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_SOC_BSB1_LSX GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_SOC_BSB1_LSX POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_BSB1_CONN_D2R_1 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_BSB1_CONN_D2R_1 POWER A_DIELECTRIC_7X
USBC_BSB1_CONN_R2D_1
GROUND
GROUND
DEFAULT_WITH_7X_LINE2SHAPE
DEFAULT_WITH_7X_LINE2SHAPE
USBC_BSB1_CONN_R2D_1
POWER
POWER
A_DIELECTRIC_7X
A_DIELECTRIC_7X
USBC_BSB1_CONN_AUXLSX GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_BSB1_CONN_AUXLSX POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_UPC1_CONN_TOP GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_UPC1_CONN_TOP POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_UPC1_CONN_BOT GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_UPC1_CONN_BOT POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_UPC1_CONN_CC GROUND DEFAULT USBC_UPC1_CONN_CC POWER DEFAULT
USBC_UPC1_CONN_SBU GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_UPC1_CONN_SBU POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_SOC_RTMR1_USB2 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_SOC_RTMR1_USB2 POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_RTMR1_UPC1_USB2 GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_RTMR1_UPC1_USB2 POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_SOC_RTMR_USB2_DBG GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_SOC_RTMR_USB2_DBG POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_RTMR_MUX_USB2_DBG GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_RTMR_MUX_USB2_DBG POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_MUX_UPC_USB2_DBG GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_MUX_UPC_USB2_DBG POWER DEFAULT_WITH_7X_LINE2SHAPE
USBC_MUX_VITC_USB2_DBG GROUND DEFAULT_WITH_7X_LINE2SHAPE USBC_MUX_VITC_USB2_DBG POWER DEFAULT_WITH_7X_LINE2SHAPE
MIPI_FTCAM_CLK GROUND DEFAULT_WITH_7X_LINE2SHAPE MIPI_FTCAM_CLK POWER DEFAULT_WITH_7X_LINE2SHAPE
MIPI_FTCAM_DATA GROUND DEFAULT_WITH_7X_LINE2SHAPE MIPI_FTCAM_DATA POWER DEFAULT_WITH_7X_LINE2SHAPE
MIPI_DFR_CLK GROUND DEFAULT_WITH_7X_LINE2SHAPE MIPI_DFR_CLK POWER DEFAULT_WITH_7X_LINE2SHAPE
MIPI_DFR_DATA GROUND DEFAULT_WITH_7X_LINE2SHAPE MIPI_DFR_DATA POWER DEFAULT_WITH_7X_LINE2SHAPE
PCIE_WIFI_D2R GROUND DEFAULT_WITH_7X_LINE2SHAPE PCIE_WIFI_D2R POWER DEFAULT_WITH_7X_LINE2SHAPE
PCIE_WIFI_R2D GROUND DEFAULT_WITH_7X_LINE2SHAPE PCIE_WIFI_R2D POWER DEFAULT_WITH_7X_LINE2SHAPE
PCIE_WIFI_CLK GROUND DEFAULT_WITH_7X_LINE2SHAPE PCIE_WIFI_CLK POWER DEFAULT_WITH_7X_LINE2SHAPE
PCIE_NAND0_D2R GROUND DEFAULT_WITH_7X_LINE2SHAPE PCIE_NAND0_D2R POWER DEFAULT_WITH_7X_LINE2SHAPE
PCIE_NAND0_R2D GROUND DEFAULT_WITH_7X_LINE2SHAPE PCIE_NAND0_R2D POWER DEFAULT_WITH_7X_LINE2SHAPE
PCIE_NAND0_CLK GROUND DEFAULT_WITH_7X_LINE2SHAPE PCIE_NAND0_CLK POWER DEFAULT_WITH_7X_LINE2SHAPE
PCIE_NAND1_D2R GROUND DEFAULT_WITH_7X_LINE2SHAPE PCIE_NAND1_D2R POWER DEFAULT_WITH_7X_LINE2SHAPE
PCIE_NAND1_R2D GROUND DEFAULT_WITH_7X_LINE2SHAPE PCIE_NAND1_R2D POWER DEFAULT_WITH_7X_LINE2SHAPE
PCIE_NAND1_CLK GROUND DEFAULT_WITH_7X_LINE2SHAPE PCIE_NAND1_CLK POWER DEFAULT_WITH_7X_LINE2SHAPE
PCIE_CLKREQ GROUND DEFAULT PCIE_CLKREQ POWER DEFAULT
PANEL_LPDP_DATA GROUND DEFAULT_WITH_7X_LINE2SHAPE PANEL_LPDP_DATA POWER DEFAULT_WITH_7X_LINE2SHAPE
PANEL_LPDP_AUX GROUND DEFAULT_WITH_7X_LINE2SHAPE PANEL_LPDP_AUX POWER DEFAULT_WITH_7X_LINE2SHAPE
RCAL_PCIE GROUND DEFAULT RCAL_PCIE POWER DEFAULT
RCAL_CIO GROUND DEFAULT RCAL_CIO POWER DEFAULT
RCAL_MIPI GROUND DEFAULT RCAL_MIPI POWER DEFAULT
BOARD_ID GROUND DEFAULT BOARD_ID POWER DEFAULT
BOARD_REV GROUND DEFAULT BOARD_REV POWER DEFAULT
WIRELESS_TIME_SYNC GROUND DEFAULT WIRELESS_TIME_SYNC POWER DEFAULT
KBD_PWM GROUND DEFAULT KBD_PWM POWER DEFAULT
AUDIO_CONN_HEADPHONE_OUT GROUND DEFAULT AUDIO_CONN_HEADPHONE_OUT POWER DEFAULT
AUDIO_CONN_RETURN GROUND DEFAULT AUDIO_CONN_RETURN POWER DEFAULT
AUDIO_CONN_SENSE GROUND DEFAULT AUDIO_CONN_SENSE POWER DEFAULT
SPEAKERAMP_OUTPUT GROUND DEFAULT SPEAKERAMP_OUTPUT POWER DEFAULT SYNC_MASTER=T668_MLB SYNC_DATE=05/13/2019
PAGE TITLE
SENSE_DIFF GROUND DEFAULT SENSE_DIFF POWER DEFAULT
SOC_XTAL_24M_IN GROUND DEFAULT SOC_XTAL_24M_IN POWER DEFAULT 17.2 SPACING CSETS, CLASS-CLASS
SOC_XTAL_24M_OUT GROUND DEFAULT SOC_XTAL_24M_OUT POWER DEFAULT
POWER GROUND DEFAULT POWER POWER DEFAULT
2 1
POR BOM VARIANT TABLES
DRAM VENDOR, FAB SITE, AND LEAKAGE ARE ALTERNATES IN THE SAME 639 DEBUG BOM VARIANT TABLES
T BLE_BOMG OUP_HEAD T BLE_BOMG OUP_HEAD
BOM NUMBER BOM NAME BOM OPTIONS BOM NUMBER BOM NAME BOM OPTIONS
T BLE_BOMG OUP_ITEM T BLE_BOMG OUP_ITEM
639-12952 MLB1,8GB,TS-256GB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_08GB,X1799_NAND_256GB_TS 939-09328 MLB,INT-CPU,INT-SSD,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:INTERPOSER,X1799_NAND_INTERPOSER

639-12953 MLB1,16GB,TS-256GB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_16GB,X1799_NAND_256GB_TS 939-09329 MLB,NO-CPU,INT-SSD,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:OFF,X1799_NAND_INTERPOSER

T BLE_BOMG OUP_ITEM T BLE_BOMG OUP I
639-12954 MLB1,8GB,HY-256GB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_08GB,X1799_NAND_256GB_HY 939-09330 MLB,INT-CPU,NO-SSD,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:INTERPOSER,X1799_NO_NAND

639-12955 MLB1,16GB,HY-256GB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_16GB,X1799_NAND_256GB_HY 939-09331 MLB,NO-CPU,NO-SSD,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:OFF,X1799_NO_NAND

639-12956 MLB1,8GB,TS-512GB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_08GB,X1799_NAND_512GB_TS 939-09510 MLB,RF-TUNING,X1799 SCH,PCB,RF_CONN

T BLE_BOMG OUP_ITEM
639-12957 MLB1,16GB,TS-512GB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_16GB,X1799_NAND_512GB_TS

T BLE_BOMG OUP_ITEM
639-12958 MLB1,8GB,WD-512GB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_08GB,X1799_NAND_512GB_WD

T BLE_BOMG OUP_ITEM
639-12959 MLB1,16GB,WD-512GB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_16GB,X1799_NAND_512GB_WD

T BLE_BOMG OUP_ITEM
639-12960 MLB1,8GB,HY-512GB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_08GB,X1799_NAND_512GB_HY

T BLE_BOMG OUP_ITEM
639-12961 MLB1,16GB,HY-512GB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_16GB,X1799_NAND_512GB_HY

T BLE_BOMG OUP_ITEM
639-12962 MLB1,8GB,TS-1TB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_08GB,X1799_NAND_1TB_TS

T BLE_BOMG OUP_ITEM

T BLE_BOMG OUP_ITEM
639-12964 MLB1,8GB,HY-1TB,X1799 ALT_CMN,ALTERNATE:PART,X1799_CMN_BOM,X1799_DEV_BOM,CPU:B0_08GB,X1799_NAND_1TB_HY

T BLE_BOMG OUP_ITEM

T BLE_BOMG OUP_ITEM

T BLE_BOMG OUP_ITEM

T BLE_BOMG OUP_ITEM

T BLE_BOMG OUP_ITEM
BOM VARIANT TABLES
2 1
6 5 4 3
CPU NAND0
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
939-08813 1 PCBA,KANHA,X1711 U0600 CRITICAL CPU:INTERPOSER 998-18368 1 IC,NAND,S5E MCP ROUTING STUDY,LGA110 UN000 CRITICAL NAND0:S5E_STUDY
998-22385 1 SOC,TGA B0+8G,1Y,8C,LP,DEV,CX,M,S,M2502 U0600 CRITICAL CPU:B0_08GB 335S00437 1 NAND,3DV5,128GB,S5E,512G,H,SLGA110 UN000 CRITICAL NAND0:128GB_2DP_HY
998-22389 1 SOC,TGA B0+16G,1X,8C,LP,DEV,DX,M,S,M2502 U0600 CRITICAL CPU:B0_16GB 335S00462 1 NAND,3DV4,128GBT,XXX,S5E,256G,5,SLGA110 UN000 CRITICAL NAND0:128GB_4DP_TS
NOTE: PER <RDAR://55481499>, DRAM VENDOR, FAB SITE, AND LEAKAGE ARE NOT CUSTOEMR FACING, SO DON'T NEED SEPARATE 639 BOMS
639 BOMS WILL SET MICRON SCK LP AS THE PRIMARY, BUT ALL OTHER COMBINATIONS ARE SET AS ALTERNATES IN THE SAME 639 BOM 335S00446 1 NAND,3DV5,128GB,S5E,256G,S,SLGA110 UN000 CRITICAL NAND0:128GB_4DP_SS
335S00480 1 NAND,3DV4,160GBT,XXX,S5E,256G,K,SLGA110 UN000 CRITICAL NAND0:160GB_5DP_TS

TBT
335S00438 1 NAND,3DV5,256GBT,S5E,512G,H,SLGA110 UN000 CRITICAL NAND0:256GB_4DP_HY
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
335S00464 1 NAND,3DV4,256GBT,XXX,S5E,256G,T,SLGA110 UN000 CRITICAL NAND0:256GB_8DP_TS
998-13316 2 IC,BURNSIDE BRIDGE,USB/TB RETIMER,BGA105 UF000,UF100 CRITICAL ATCRTMR:DEV
335S00472 1 NAND,3DV4,256GBT,XXX,S5E,256G,SD,SLGA110 UN000 CRITICAL NAND0:256GB_8DP_WD
338S00561 2 IC,TBT,BBR,SLMN7,PRQ,A1,BGA105 UF000,UF100 CRITICAL ATCRTMR:A1_PRQ
UPC 335S00490 1 NAND,3DV4,288GBT,XXX,S5E,256G,SD,SLGA110 UN000 CRITICAL NAND0:288GB_9DP_WD
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 335S00482 1 NAND,3DV5,320GBT,S5E,512G,H,SLGA110 UN000 CRITICAL NAND0:320GB_5DP_HY
353S02158 2 IC,CD3217,ACE2,B2,USB PWR SW W/HV,BGA123 UF400,UF500 CRITICAL USBCPC:LAPTOP_B2 335S00439 1 NAND,3DV5,512GB,S5E,512G,H,SLGA110 UN000 CRITICAL NAND0:512GB_8DP_HY

AMR ASSEMBLY 335S00483 1 NAND,3DV5,576GBT,S5E,512G,H,SLGA110 UN000 CRITICAL NAND0:576GB_9DP_HY
335S00468 1 NAND,3DV4,1TBT,XXX,S5E,512G,T,SLGA110 UN000 CRITICAL NAND0:1TB_16DP_TS
677-19902 1 SUBASSY (T&R) PCBA,AMR INTERPOSER,X1795 JR200 CRITICAL AMR:X1795
335S00458 1 NAND,3DV5,1024GBT,S5E,512G,H,SLGA110 UN000 CRITICAL NAND0:1TB_16DP_HY
939-08815 1 PCBA,BANDIPUR,X1711 UN000 CRITICAL NAND0:INTERPOSER

TBT ROM
335S00133 1 IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8 UF260 CRITICAL TBT_ROM:BLANK_WINBOND
NAND1
335S00232 1 IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8 UF260 CRITICAL TBT_ROM:BLANK_MACRONIX
998-18368 1 IC,NAND,S5E MCP ROUTING STUDY,LGA110 UN100 CRITICAL NAND1:S5E_STUDY
341S01581 1 ROM,TBT/ACE (VXXXX) PRE-PROTO-1,X1740 UF260 CRITICAL TBT_ROM:PRE_P1
335S00437 1 NAND,3DV5,128GB,S5E,512G,H,SLGA110 UN100 CRITICAL NAND1:128GB_2DP_HY
341S01601 1 ROM,TBT/ACE (VXXXX) NEW, PRE-PROTO1,X1799 UF260 CRITICAL TBT_ROM:PRE_P1_V2
335S00462 1 NAND,3DV4,128GBT,XXX,S5E,256G,5,SLGA110 UN100 CRITICAL NAND1:128GB_4DP_TS
341S01618 1 ROM,TBT/ACE (VXXXX), PROTO1,X1799 UF260 CRITICAL TBT_ROM:P1
335S00446 1 NAND,3DV5,128GB,S5E,256G,S,SLGA110 UN100 CRITICAL NAND1:128GB_4DP_SS
341S01672 1 ROM,TBT/ACE (VXXXX), PROTO2,X1799 UF260 CRITICAL TBT_ROM:P2
341S01726 1 ROM,TBT/ACE (VXXXX) EVT,X1799 UF260 CRITICAL TBT_ROM:EVT
SPMU 335S00464 1 NAND,3DV4,256GBT,XXX,S5E,256G,T,SLGA110 UN100 CRITICAL NAND1:256GB_8DP_TS
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 335S00472 1 NAND,3DV4,256GBT,XXX,S5E,256G,SD,SLGA110 UN100 CRITICAL NAND1:256GB_8DP_WD
998-20066 1 IC,PMU,SPMU,A0,OTP-JPC,WLCSP196 U7700 CRITICAL SPMU_IC:A0_JPC 335S00481 1 NAND,3DV4,288GBT,XXX,S5E,256G,K,SLGA110 UN100 CRITICAL NAND1:288GB_9DP_TS
998-22526 1 IC,PMU,SPMU,A1,OTP-JPE,WLCSP196 U7700 CRITICAL SPMU_IC:A1_JPE 335S00490 1 NAND,3DV4,288GBT,XXX,S5E,256G,SD,SLGA110 UN100 CRITICAL NAND1:288GB_9DP_WD

MPMU
335S00439 1 NAND,3DV5,512GB,S5E,512G,H,SLGA110 UN100 CRITICAL NAND1:512GB_8DP_HY
998-20064 1 IC,PMU,MPMU,A0,OTP-JPC,WLCSP440 U8100 CRITICAL MPMU_IC:A0_DEV
998-22339 1 IC,PMU,MPMU,B0,OTP-JPE,WLCSP440 U8100 CRITICAL MPMU_IC:B0_JPE
335S00468 1 NAND,3DV4,1TBT,XXX,S5E,512G,T,SLGA110 UN100 CRITICAL NAND1:1TB_16DP_TS
998-22614 1 IC,PMU,MPMU,B0,OTP-JPF,WLCSP440 U8100 CRITICAL MPMU_IC:B0_JPF
335S00458 1 NAND,3DV5,1024GBT,S5E,512G,H,SLGA110 UN100 CRITICAL NAND1:1TB_16DP_HY
939-08815 1 PCBA,BANDIPUR,X1711 UN100 CRITICAL NAND1:INTERPOSER

EUSB LEVEL SHIFTER
998-20641 2 IC,PRT,CD2E224,B0,OTP-6,CSP25 UF700,UF750 CRITICAL EUSB_LS:B0_OTP6
338S00628 2 IC,PARROT,CD2E226B,B0,LSB1,OTP-6,CSP25 UF700,UF750 CRITICAL EUSB_LS:B0_LSB1_OTP6
CERES
998-19915 1 IC,SN210V,CERES,DEV KEY,B1,SW=V7,WLCSP81 U5000 CRITICAL SE:DEV_SW_V7
998-21255 1 IC,SN210V,B1,CERES,DEV,SW=H3,WLCSP81 U5000 CRITICAL SE:DEV_SW_H3
338S00630 1 IC,SN210V,B1,CERES,PROD,VER=MU,WLCSP81 U5000 CRITICAL SE:PROD_SW_MU
PAGE TITLE
BOM OPTION TABLES
2 1
COMMON BOM GROUPS SYSTEM PARTS
TABLE_BO GRO P_HE D
BOM GROUP BOM OPTIONS PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
TABLE_BO GRO P_IT M
X1799_COMMON_PARTS SCH,PCB,ALT_CMN,COMMON,ALTERNATE:PART,X1799_GROUP1,X1799_GROUP2,X1799_GROUP3,X1799_GROUP4,X1799_GROUP5 051-05399 1 SCHEM,COFFEE,X1799 SCH CRITICAL SCH

TABLE_BO GRO P_IT M
X1799_GROUP1 ATCRTMR:A1_PRQ,USBCPC:LAPTOP_B2,EUSB_LS:B0_LSB1_OTP6,WIFI:DEV_ES6P1,AMR:X1795,TBT_ROM:EVT,P3V8AON_IC:A1_R0B0 820-02020 1 PCBF,MLB,X1799 PCB CRITICAL PCB

TABLE_BO GRO P_IT M
X1799_GROUP2 BLC_BEN_IC:V7,BLC_KBD_BOOST_USED:YES,BLC_LEDS_PER_STRING:16,BLC_5V_SERIES:10_OHM,BLC_5V_CAP:4P7_UF,CLIP:YES,CLIP_SMALL:YES 685-00341 1 COMMON PARTS,MLB,X1799 COMMON_PARTS CRITICAL X1799_CMN_BOM

TABLE_BO GRO P_IT M
X1799_GROUP3 BOARD_REV3,BOARD_REV1,BOOT_CONFIG2,BOARDID2,SE:PROD_SW_MU,WIFI:MUR_ES6P1,PBUS_3S,RF_CONN,SSD_2L,NAND 985-01178 1 DEV PARTS,MLB,X1799 DEV_PARTS CRITICAL X1799_DEV_BOM

TABLE_BO GRO P_IT M
X1799_GROUP4 SPMU_IC:A1_JPE,MPMU_IC:B0_JPF,UPC_ATCRTMR_INT,UPC_EUSBLS_INT,SLED:YES,FENCE_USBC_C770,FENCE_COMBO,FENCE_SPMU_C770
X1799_GROUP5 P1V2_PREREG:BUCK14,SECDIS_EXT_CLK,KBD_NEW,DISPLAY:P1,IPD_PMU_GPIO:EVT,P3V8AON_LPM,DMIC_CLK_33OHM
TABLE_BO GRO P_IT M
COMMON PARTS BOM

TAB E_B MGR UP_H AD
BOM NUMBER BOM NAME BOM OPTIONS

DEV BOM GROUPS
TAB E_B MGR UP_I EM
685-00341 COMMON PARTS,MLB,X1799 X1799_COMMON_PARTS

TABLE_BO GRO P_HE D
BOM GROUP BOM OPTIONS

X1799_DEV_PARTS1 DBG_FAN,WLBT_DBG,USBC_DBG,DEBUG_BUTTON,SYS_DET_BTN,DBG_LED,SENSOR_IMU
TABLE_BO GRO P_IT M
DEV PARTS BOM

TAB E_B MGR UP_H AD
TABLE_BO GRO P_IT M
BOM NUMBER BOM NAME BOM OPTIONS

X1799_DEV_PARTS2 DBG_VMAINISNS,VITAMIN-C:YES,SNSRES_DEV,CHGR_DBG TAB E_B MGR UP_I EM
985-01178 DEV PARTS,MLB,X1799 X1799_DEV_PARTS1,X1799_DEV_PARTS2
NAND BOM GROUPS

TABLE_BO GRO P_HE D
BOM GROUP BOM OPTIONS

TABLE_BO GRO P_IT M
X1799_NAND_256GB_TS NAND0:160GB_5DP_TS,NAND1:128GB_4DP_TS
TABLE_BO GRO P_IT M
X1799_NAND_256GB_HY NAND0:128GB_2DP_HY,NAND1:128GB_2DP_HY
TABLE_BO GRO P_IT M
X1799_NAND_512GB_TS NAND0:288GB_9DP_TS,NAND1:256GB_8DP_TS
TABLE_BO GRO P_IT M
X1799_NAND_512GB_WD NAND0:288GB_9DP_WD,NAND1:256GB_8DP_WD
TABLE_BO GRO P_IT M
X1799_NAND_512GB_HY NAND0:320GB_5DP_HY,NAND1:256GB_4DP_HY
TABLE_BO GRO P_IT M
X1799_NAND_1TB_TS NAND0:512GB_16DP_TS,NAND1:512GB_16DP_TS
TABLE_BO GRO P_IT M
X1799_NAND_1TB_HY NAND0:576GB_9DP_HY,NAND1:512GB_8DP_HY
TABLE_BO GRO P_IT M
X1799_NAND_2TB_TS NAND0:1TB_16DP_TS,NAND1:1TB_16DP_TS
TABLE_BO GRO P_IT M
X1799_NAND_2TB_HY NAND0:1TB_16DP_HY,NAND1:1TB_16DP_HY
TABLE_BO GRO P_IT M
X1799_NAND_INTERPOSER NAND0:INTERPOSER,NAND1:INTERPOSER
TABLE_BO GRO P_IT M
X1799_NO_NAND NAND0:OFF,NAND1:OFF
PAGE TITLE
BOM GROUPS
2 1
4
SYSTEM EE SYSTEM EE WIFI MODULE DCDC
T BLE_A T_ EAD TA LE_ALT_H AD T BLE_ALT_H AD TA LE_ALT_H AD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER PART NUMBER PART NUMBER PART NUMBER
T BLE_A T_ TEM TA LE_ALT_I EM T BLE_ALT_I EM TA LE_ALT_I EM
353S01346 353S01320 ALT_CMN ALL <RDAR://56390543> 138S1068 138S00215 ALT_CMN ALL <RDAR://61797939> 339S00758 339S00763 ALT_CMN ALL 138S0863 138S0853 ALT_CMN ALL <RDAR://56380033>
T BLE_A T_ TEM TA LE_ALT_I EM TA LE_ALT_I EM
376S1080 376S0820 ALT_CMN ALL <RDAR://57125638> 311S00248 311S00243 ALT_CMN ALL <RDAR://61794063> 152S00398 152S00204 ALT_CMN ALL <RDAR://56380033>
107S0276 107S00020 ALT_CMN ALL <RDAR://57126636>

T BLE_A T_ TEM

TA LE_ALT_I EM
BLC 152S00963 152S00885 ALT_CMN ALL <RDAR://56380033>

TA LE_ALT_I EM
T BLE_ALT_H AD
T BLE_A T_ TEM TA LE_ALT_I EM
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: TA LE_ALT_I EM
311S00176 311S00153 ALT_CMN ALL <RDAR://57133089> 376S00292 376S1140 ALT_CMN ALL <RDAR://58350656> PART NUMBER 138S00047 138S00073 ALT_CMN ALL <RDAR://56380033>
T BLE_A T_ TEM TA LE_ALT_I EM T BLE_ALT_I EM TA LE_ALT_I EM
353S02030 353S01993 ALT_CMN ALL <RDAR://57133661> 311S0196 311S00245 ALT_CMN ALL <RDAR://62345781> 138S0738 138S1101 ALT_CMN ALL <RDAR://55465318> 152S01317 152S01268 ALT_CMN ALL <RDAR://57328156>
T BLE_A T_ TEM T BLE_ALT_I EM TA L T_I EM
T BLE_A T_ TEM T BLE_ALT_I EM TA LE_ALT_I EM
T BLE_A T_ TEM T T_I EM TA LE_ALT_I EM
376S00224 376S00282 ALT_CMN ALL <RDAR://57168696> 128S0364 128S0264 ALT_CMN ALL <RDAR://56380033>

T BLE_A T_ TEM
PD 152S00680 152S00198 ALT_CMN ALL <RDAR://56380033>

TA LE_ALT_I EM
T BLE_ALT_H AD
T BLE_A T_ TEM
311S00060 311S0273 ALT_CMN ALL <RDAR://57172430> PART NUMBER 152S00383 152S00198 ALT_CMN ALL <RDAR://56380033>
T BLE_A T_ TEM T BLE_ALT_I EM TA LE_ALT_I
371S00220 371S00181 ALT_CMN ALL <RDAR://57196734> 806-24548 806-24455 ALT_CMN ALL <RDAR://60043307> 152S00997 152S00476 ALT_CMN ALL <RDAR://56380033>
311S00013 311S0508 ALT_CMN ALL <RDAR://57211339> 376S00303 376S00012 ALT_CMN ALL <RDAR://56380033>

T BLE_A T_ TEM
SOC 8G 376S00204 376S00203 ALT_CMN ALL <RDAR://56380033>

TA LE_ALT_I EM
T BLE_ALT_H AD
T BLE_A T_ TEM
T BLE_A T_ TEM T BL T_I EM TA LE_ALT_I EM
377S0155 3 7S0184 ALT_CMN ALL <RDAR://57230484> 998-22387 998-22385 ALT_CMN ALL <RDAR://55481499> 376S1147 376S00281 ALT_CMN ALL <RDAR://59078633>

T BLE_A T_ TEM
www.teknisi-indonesia.com 152S00343 152S00839 ALT_CMN ALL <RDAR://57238826>

TA LE_ALT_I EM

T BLE_A T_ TEM
SOC 16G 152S01090 152S01085 ALT_CMN ALL <RDAR://57230783>

TA LE_ALT_I EM
T BLE_ALT_H AD
T BLE_A T_ TEM
T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM

T BLE_A T_ TEM
138S00280 38S00138 ALT_CMN ALL <RDAR://61547071> PAGE TITLE

T BLE_A T_ TEM
BOM ALTERNATES
PACK_OPTIONS TO INCLUDE IN NETLIST REF_SPKRAMP_TAS5770
SPKRAMP_A,SPKRAMP_B J293 HAS 4 AMPS, 2 LEFT AND 2 RIGHT.
SPKRAMP_D,SPKRAMP_E LEFT ARE A, B. RIGHT ARE D, E.
SPKRAMP_LVL_4B_QFN USE SAME LEVEL SHIFTERS AS TRACKPAD SPI
SPKRAMP_LVL_1B_SON USE 1.2V BUFFER WITH 1.8V CAPABLE INPUT AS 1.8 TO 1.2 LEVEL SHIFTER
PACK_OPTIONS TO INCLUDE IN NETLIST REF_CHARGER_SUONA

CHGR_60W J293'S CHARGER IS B379 WHICH IS 61W, SO WE USE
CHGR_TP_TOP,CHGR_TP_BOT,CHGR_TP 60-100W OPTION PER REF CHARGER SUONA CONFIG TABLE
ENABLE ALL CHARGER TEST POINTS
PACK_OPTIONS TO INCLUDE IN NETLIST REF_USBC_ACE2

USBC_SPI_UPC0 SET SPI UPC TO BE 0, BACK LEFT
USBC_DEBUG_UPC0 SET DEBUG UPC TO BE 0, BACK LEFT
USBC_LAPTOP ENABLE PORTS FOR CHARGING
USBC01_VR5V_LOCAL_NO LEAVE ACE2 5V ENABLE GPIOS SEPARATE, AS 5V DEDICATED LOCAL VR NOT USED
PKGS:SMALL_PITCH ENABLE SMALL PITCH PARTS ON USBC PAGES (OTHER PROJECTS USING BIGGER PITCH OPTIONS)
PACK_OPTIONS TO INCLUDE IN NETLIST REF_SOC_H13G

FTCAM J293 HAS A FTCAM, SO TURN ON FTCAM MIPI REXT RESISTOR
DFR J293 HAS A DFR, SO TURN ON DFR MIPI REXT RESISTOR
80UM_STEN J293 WILL USE 80 UM TOP SIDE STENCIL FOR SOC BYPASS CAPS
SMALL_NOR SMALL NOR IS 4X3 SINGLE SOURCE PACKAGE, LARGE NOR IS 4X4 PACKAGE WITH MULTIPLE ALTERNATES
PACK_OPTIONS TO INCLUDE IN NETLIST REF_SECDIS_SAK

JTAG_SECDIS:YES KEEP THE JTAG CONNECTOR AND DEBUG PULLS
PROTO_PULLDOWN_SECDIS PULL DOWN SEP OUTPUTS WHEN SYSTEM IS IN S2 OR BELOW
PROD_SECDIS ALL PRODUCTION SYSTEMS CALL OUT PROD_SECDIS
PACK_OPTIONS TO INCLUDE IN NETLIST REF_SECDIS_AMR

AMR_INTERPOSER_LEFT ON J293, THE LEFT AMR IS ON THE MLB, SO CALL OUT AMR_INTERPOSER_LEFT
NO_AMR_INTERPOSER_RIGHT 1M PULL DOWNS ON RIGHT SIDE ENABLED WITH NO_AMR_INTERPOSER_RIGHT, TO ENSURE
NET IS LOW WHEN NO FLEX IS INSTALLED FOR THE RIGHT SIDE
REF_WIRELESS_RASPUTIN
PACK_OPTIONS TO INCLUDE IN NETLIST
IPEX 3X_ANTENNA PACK OPTION IS FOR PROGRAMS WITH DEDICATED BT ANTENNA, WHICH www.teknisi-indonesia.com
WLBT_DBG_CONN J293 DOES NOT HAVE, SO THIS IS NOT CALLED OUT
J293 USES IPEX CONNECTOR (NOT SUNWAY) FOR ANTENNA CONNECTOR, SO CALL OUT IPEX
J293 USES THE DEBUG WIFI CONNECTOR, SO WLBT_DBG_CONN IS CALLED OUT
PACK_OPTIONS TO INCLUDE IN NETLIST REF_VR_3V3_TPS62135

3V3 S2 PBUS-D2 SETTING D2 CAP SIZE
PACK_OPTIONS TO INCLUDE IN NETLIST REF_VR_5V_LT8642S

5V_S2_PBUS-D2 SETTING D2 CAP SIZE
PACK_OPTIONS TO INCLUDE IN NETLIST REF_VR_ICEMAN

3V8_AON_PBUS-D2 SETTING D2 CAP SIZE
3V8_AON_I2C-DEV SHORT I2C TO GND FOR POR
3V8 EXT DIODE ENABLE EXTERNAL CHARGE PUMP DIODES
PAGE TITLE
PACK OPTIONS
CHECKPLUS WAIVES
8 85 82 BI I2C_KBD_SDA
89 85 82 BI I2C_KBD_SCL
24 BI I2C_P3V8AON_SDA
24 BI I2C_P3V8AON_SCL
CHECKPLUS SUPPORT

Apple MacBook Pro M1 A2338 - 820-02020 Schematic Diagram

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Apple MacBook Pro M1 A2338 - 820-02020 Schematic Diagram

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T668 MLB

3 4 PD PARTS T668_KSAITO_MLB_0.11.1 63 201 WIFI/BT: ANTENNA and GND REF_WIRELESS_RASPUTIN 02/01/2020

6 7 SOC: AP I/Os T585_REF_SOC_H13G_0.56.0 66 224 STORAGE: NON OCARINA SUPPORT REF_STORAGE_NON_OCARINA_SUPPORT

8 9 SOC: PCIE ANDREW_T668_MLB 10/09/2019 68 231 SECDIS: MIPI MUX T585_REF_SECDIS_MIPIMUX_0.7.0

9 10 SOC: AOP T585_REF_SOC_H13G_0.56.0 69 236 DISPLAY: CONNECTOR, PWR AITKEN_T668_MLB 10/02/2019

11 12 SOC: POWER (IO) T585_REF_SOC_H13G_0.56.0 71 238 BEN: CONTROLLER REF_BLC_BEN 11/21/2019

13 14 SOC: POWER (SRAM) T585_REF_SOC_H13G_0.56.0 73 242 SECDIS: AMR T585_REF_SECDIS_AMR_0.9.0

16 17 SOC: GND-2 T585_REF_SOC_H13G_0.56.0 76 245 AUDIO JACK CODEC REF_CODEC_CLIFDEN 04/13/2020

26 59 POWER: 3V8 AON SUPPORT T585_REF_VR_ICEMAN_0.36.0 86 256 TOUCHID SUPPORT T585_REF_MESA_SUPPORT_0.11.0

28 78 PMU: SLAVE LDO 88 258 DFR SUPPORT 2

36 123 POWER: 5V S2 REF_VR_5V_TPS62135 04/16/2020 96 294 DEBUG: VITAMIN-C MANAN_T668_MLB 02/03/2020

58 155 USB-C: Port Controller ATC1 REF_USBC_ACE2 02/01/2020

59 156 USB-C: Connector(s) KEI_T668_MLB 02/01/2020

60 157 USB-C: HS Level Shifters REF_USBC_ACE2 02/04/2020

T585 REF_VR_ICEMAN 57,58 1.14.0 2020/04/27

T585 REF_CHARGER_SUONA 52,53 0.36.0 2020/04/27

T585 REF_STORAGE_NON_OCARINA_SUPPORT 224 0.5.0 2020/04/27

T585 245 1.6.0 2020/04/27

T585 REF_SPKRAMP_TAS5770 244,246,247 0.8.0 2020/04/27

T585 REF_VR_3V3_TPS62135 127 0.8.0 2020/04/27

T585 REF_VR_5V_LT8642S 123 0.13.0 2020/04/27

T585 REF_SECDIS_MIPIMUX 231 0.7.0 2020/04/27

T585 REF_DFR_V3_SUPPORT 257,258 0.25.0 2020/04/27

T585 REF_SE_CERES 50 0.13.0 2020/04/27

T585 REF_PANELPWR_BNJ 237 0.9.0 2020/04/27

REF_SECD S_ AK 243 40.0 2 20/04/27

T585 REF_STORAGE_S5E 220,221 0.34.0 2020/04/27

REFERENCE DESIGNS NO LONGER SYNCS FROM

Z0403 CORNER NEAREST KEYBOARD

AJ FLEX COWLING BOSS

BOARD REVISION NOTE: STUFFING RESISTOR MEANS 0

board rev should start at 0b0000 and increment each rev.

1. SET GPIO AS INPUT

J293 BOARD_REV [3:0] = 0000 : PRE P1

0100 : P2 SOC: Support

100 90 89 74 33 9 IN PMU_RESET_L R2 LP4_IN_RESET_N

90 89 56 33 5 IN SOC_FORCE_DFU AA49 FORCE_DFU DFU_STATUS V51 SOC_DFU_STATUS OUT 19 56 89 94

19 5 SOC_REQUEST_DFU1 AK55 REQUEST_DFU1

89 55 33 IN PMU_ACTIVE_READY AL54 CFSB

4 IN SOC_HOLD_RESET AC1 HOLD_RESET IPD

18 BI EUSB_ATC0_P BB54 ATC0_USB_EDP

60 IN CIO_ATC0_LSRX_1V2 BE18 USB_C0_LSRX CLOCKS XI0 BE36 SOC_XTAL24M_IN

5 SOC_ATC0_USB_RESREF BB53 ATC0_USB_RESREF TST_CLKOUT P54 TP_TST_CLKOUT 18

53 BI USBC_ATC0_D2R_P<2> GND_VOID=TRUE BE48 ATCPHY0_RX1_P

54 BI USBC_ATC1_AUX_P BA52 ATCPHY1_AUX_P

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

197S0590 197S0591 Y0600 EPSON,24MHZ.XTAL

197S0588 197S0591 Y0600 TXC,24MHZ,XTAL

18 UT TDM_SPKRAMP_L_BCLK_R AK4 I2S0_BCLK IPD SPI0_MISO AL4 SPI_DFR_MISO IN 4

18 IN TDM_SPKRAMP_L_D2R AJ3 I2S0_DIN IPD SPI0_MOSI AK2 SPI_DFR_MOSI_R OUT 4

18 OUT TDM_SPKRAMP_L_R2D_R AJ5 I2S0_DOUT SPI0_SCLK AK1 SPI_DFR_CLK_R OUT 4

18 OUT TDM_SPKRAMP_L_FSYNC_R AJ4 I2S0_LRCK

SPI1_MOSI AE4 SPI_SOCROM_MOSI_R 17

1 IN TDM_SPKRAMP_R_D2R AF3 I2S1_DIN IPD SPI1_SSIN AE3 SPI_SOCROM_CS_L OUT 17

1 OUT TDM_SPKRAMP_R_R2D_R AG4 I2S1_DOUT

6 NC_SOC_I2S1_MCK AG2 I2S1_MCK SPI2_MOSI AF54 SPI_TOUCHID_MOSI_R OUT 18

18 OUT TDM_CODEC_BCLK_R AK5 I2S2_BCLK SPI2_SSIN AF52 NC_SOC_SPI2_SSIN 106

76 IN TDM_CODEC_D2R AL6 I2S2_DIN IPD

18 OUT TDM_CODEC_FSYNC_R AM4 I2S2_LRCK SPI3_MOSI W1 SPI_IPD_MOSI_R OUT 18

TP_SOC_I2S2_MCK AK6 I2S2_MCK SPI3_SCLK AB1 SPI_IPD_CLK_R OUT 18

SPI3_SSIN AA1 SPI_IPD_CS_L 84

6 NC_I2S3_R2D AG5 I2S3_DOUT SPI4_MOSI AB4 SPI_TCON_MOSI_R OUT 69

106 NC_I2S3_LRCLK AJ6 I2S3_LRCK SPI4_SCLK AA4 SPI_TCON_CLK_R OUT 69