Architecture Exploration

What is Electronic Design?

Given specifications, we want to develop a circuit by connecting
known electronic devices, such that the circuit meets given
specifications.

“Known” devices are those whose behaviour can be modelled by

known equations or algorithms, with known values of parameters.
“Specifications” refer to the description of the desired behaviour of
the circuit

Electronic Design is the process of converting

a behavioural description (What happens when ..) to
a structural description (What is connected to what and how ..)
 Logic Specification vs. Implementation
Logic Specification precedes Logic Implementation.
For a particular Logic Specification, there are many different possible
Logic Implementations.
These different Logic Implementations may widely differ in their
cost, speed of operation and power consumption.

Logic Specification is also called Behavioural Description of logic.

Logic Implementation is also called Structural Description of logic.
 Implementing Logic How do you efficiently implement
logic given the constraints on
Speed of Operation.
Power Consumption.
The strategic planning and
Design Time. selection of an optimal approach
for implementation of logic is
Design Cost. typically called architecting or
Product Cost. architecture design.

Upgradability.
 A
A
Z =A+ B + C + D + E B
C D Z
D
D
E

Fastest
A
B Large Area
C
Very Difficult
D Z to Change
E

4 adder delay (20 ns) ie output (Z) is available every

20 ns (~ 50 Mhz)
 A
B
C
D
Z
E

3 adder delay (15ns) ie output (Z) is available every 15 ns (~ 67 Mhz)

Any further reduction ?
Valid input should continue to remain valid till (until) valid output
is (required to be) produced.
In planar technology, the gate of the transistor keeps holding Intermediate
the applied voltage(input) until it is removed. storage
timing
 Register or memory circuits are very regular
structure and are compact, hence their design time
and cost are much less than processing elements
like adder, divider etc.

Since adder is costly, can we use only one adder, pay a

little time penalty and solve the problem?

Storage problem has to be taken care of— Sequential Circuit

Sequential

2:1 Mux

A B C D E R
Select

Control

Little extra hardware Z = A+B+C+D+E

4 adder delay Z=A+B+C+D

Flexibility in operation
Characteristics of Sequential Architectures:
They need storage elements besides combinational
logic.
They need a sequence of steps to implement the full
logic specification.
Next step should be taken only when the logic
function of the previous step has been completed
and its result saved.
Regenerative behaviour—mainly because of direct or
indirect feedback between output and input
Pipelining Cl1 Cl2 Cl3 Cl4 Cl5

I1
A I2 O
R
B

C R

D R
R

E R R

I1 I2 O
Cl1 A+B, C+D, E H H
Cl2 A1+B1,C1+D1,E1 A+B+C+D,E H
Cl3 A2+B2,C2+D2,E2 A1+B1+C1+D1,E1 A+B+C+D+E
Cl4 A3+B3,C3+D3,E3 A2+B2+C2+D2,E2 A1+B1+C1+D1+E1
Cl5 …………………… ………………….. ……………………
Characteristics of Pipelined
Architectures:
They increase the sustained throughput of logic
function computation (roughly by a factor of 2 for a
2-stage pipelined architecture)

They do not reduce the delay of computation of the

logic function.

Their cost is higher due to the need of pipeline

registers.
Control-Programmable; Sequential for Logic Implementation

2:1 Mux
A
A B C D E L R
Select U

Control Op-select

Z=A+B+C–D-E
R

Dependency of Hardware on logic to be implemented.

Characteristics of Control-Programmable
Sequential Architectures:

They have a fixed execution unit, but a

programmable controller.
By appropriately programming the controller, any
logic function can be implemented.
A popular choice for control programming is
through micro-programming via a Writable Control
Store (WCS).
(Instruction-set Based; Programmable; Sequential)
For Logic Implementation
The von Neumann architecture of a general-purpose stored-program
digital computer (CISC).

ADD A, B, Z

ADD Z, C, Z

ADD Z, D, Z

ADD Z, E, Z
Disadvantages of CISC:
Heavy Control
Variable clock cycle—pipelining is a difficult task
Variable instruction strength

Harvard Architecture:
Reduced clock cycle
Increased throughput
• RISC
• ASIP (Application Specific Instruction Processor)