A B C D E

MODEL NAME : DDK51 - Firestar MLK / DDK52 - Firestar-B / DDK53 - Armani MLK
PCB NO : LA-E993P
Vinafix.comArmani MLK:
BOM P/N : Firestar MLK/Firestar-B
1 1

451A9U31L01 451A9U31L51
451A9U31L02 451A9U31L52
451A9U31L03 451A9U31L53
451A9U31L04 451A9U31L54

2
Dell/Compal Confidential 2

Schematic Document
Coffee Lake-H
N17P
3
Firestar-B, Firestar/Armani MLK 3

2018-03-06
Rev: 1.0 (A00)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 1 of 78
A B C D E
 A B C D E

128M x32 *4 =2G

256M x32 *4 =4G
VRAM * 4 GB4-128
GDDR5 P28-29 GPU PEG 3.0 x16 DDR4 ChannelA DDRIV-DIMM X2
N17P-G0/G1 1.2V DDR4 2666 MHz
DDR4 ChannelB
HDMI 2.0
HDMI2.0
Retimer Vinafix.com
IFP
Intel
P14-15

Conn. P34 PS8409A P33 P23-31 32GB Max

1
CFL-Lake-H 1

Processor
45W
BGA eDP1.4 x4 15.6''
DP to VGA DP
DDI1 x4 HD / FHD / UHD
CRT RTD2166-CG DDI2 x4 P38
Conn. P35
P38 P6-12
Thunderbolt
CIO/USB3.1 Alpine Ridge-SP DMI x4
USB3.1 100MHz
5GB/s
TypeC USB2.0/CC TPS65982D I2C/USB2.0
P50 PCI-E x4 USB2.0 USB Powershare
P50 P36~37
Port 1 TPS2544 P31
Port 21-Port 24
USB 3.0 Left
Type-A
PCI-E x1 Port 15 USB3.0 USB 3.0 Re-driver
M.2 Slot A Key-E
(WLAN+BT4.0) Port 1 PS8713 P31 P51
P41 CNVi

USB2.0 Port 2
2
LOM PCI-E x1 USB3.0 Port 2 USB 3.0 Right 2

RJ45 Port 14 Type-A P52

P40 Killer E2400 P40 Intel
PCI-E x4 CNL-H-PCH USB2.0 Port 3
M.2 Slot C Key-M Port 9-Port 12 USB3.0 Port 3 USB 3.0 Right
(SATA/PCIe SSD)
SATA1A
BGA 874 Balls Type-A P52
P39

HM370 USB2.0 Port 5 Digital Camera

HDD SATA0B Conn. P35

Conn. P39

USB2.0 Port 7 M.2 Slot A Key-E

Main SPKR *2 (WLAN+BT4.0) P41
P43
HDA Codec HD Audio
ALC3246
P42 USB2.0 Port 8 Touch Panel
Universal
Audio Jack Conn. P35
P43

SPI Flash SPI USB2.0 Card Reader SD3.0 2 in 1

(BIOS 32MB) Port 6 RTS5144-GR P53 SD / MS
3 P53 3
P14

SMBus USB2.0 Port 9 Touch Finger Print w/ power button

TPM Conn. P48
NPCT750JAAYX I2C
P45
Power Button Board
P16-22

FFS eSPI
LNG2DMTR P39 PWM
Touch Pad PS2 FAN P47
MEC 1416
P47
KBC
P44 I2C Thermal Sensor
F75303M P45

P48
LED KB Conn.
P46
4 LED Board SMBus
4

Power Button Charger & AC Adaptor

P48
Battery P59/P60 P59

Power Button Board Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block diagram
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 2 of 78
A B C D E
 5 4 3 2 1

Refer Page 44 HSIO port Alloction

Board ID Resistor USB3 DESTINATION PCI EXPRESS DESTINATION USB3 DESTINATION
1 USB JUSB3 (Left Side) Lane 1 None 7 None
X00 10K 2 USB JUSB1 (Right Side) Lane 2 None 8 None
X01 17.8K 3 USB JUSB2 (Right Side) Lane 3 None 9 None
4 None
Vinafix.com Lane 4 None 10 None
D
X02 27K D
5 None Lane 5 None
X03 37.4K 6 None Lane 6 None
A00 49.9K Lane 7 None
Lane 8 None
Lane 9
USB2 DESTINATION Lane 10 SATA DESTINATION
1 USB JUSB3 (Left Side) Lane 11 NGFF - NVMe SSD 0a None (NVMe)
2 USB JUSB1 (Right Side) Lane 12 1a NGFF - SSD
3 USB JUSB2 (Right Side) Lane 13 None (HDD) 0b HDD
4 None Lane 14 LOM 1b None (LOM)
5 CAMERA Lane 15 NGFF - WLAN 2 None (WLAN)
6 Card Reader Lane 16 None 3 None
7 NGFF - WLAN + BT Lane 17 4 None
8 Touch screen Lane 18 5 None
C C

9 Finger Print Lane 19

10 None Lane 20
11 None Lane 21
12 None Lane 22
Alpine Ridge - SP
13 None Lane 23
14 None Lane 24

DDI DESTINATION CLK_PCIE DESTINATION CLK_REQ DESTINATION

1 Alpine Ridge 0 None 0 None
2 Alpine Ridge 1 None 1 None
3 None 2 LOM 2 LOM
B
3 NGFF - WLAN + BT 3 NGFF - WLAN + BT B

4 None 4 None
5 Alpine Ridge - SP 5 Alpine Ridge - SP
6 NGFF - SSD 6 NGFF - SSD
7 GPU 7 GPU
8 None 8 None
9 None 9 None
10 None 10 None
11 None 11 None
12 None 12 None
13 None 13 None
14 None 14 None Symbol Note :
15 None 15 None
: means Digital Ground
A A

: means Analog Ground

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/06 Title
2017/01/06 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 3 of 78
5 4 3 2 1
 5 4 3 2 1

P71-74
NCP81215MNTXG
PU5000
B+ CPU_B+ NCP302045MN x4
PL5100 (PU5101/PU5102/ +VCC_CORE
PU5103/PU5202)

CPU_B+ NCP302045MN x1
(PU5201) +VCCGT

CPU_B+ NCP302035MNTXG x1

Vinafix.com EN : VR_ON
PG : IMVP_VR_PG
(PU5203) +VCCSA

D D

P55 P33
B+ 1.2V_B+ +1.2VP
AON7408L/AON7506 APE8937GN2
PJP200 (PQ201/PQ202) +1.2V_DDR (UZ16) +1.2V_VCCPLL_OC RP31 +1.2V_RTM
PJP201/PJP202 P55
EN : SIO_SLP_S3#
RT8207PGQW
PU200 EN 0.6V : SM_PG_CTRL +0.6VSP
EN 1.2V : 1.2V_VDDQ_EN
PG : 1.2V_PGOOD
+0.6VS
P62 PJP203

P18

RH123 +1P05V_VCCUSB
P76
B+ B+_VCCIO SY8286RAC +VCCIOP
PJP400 (PU4000) +VCCIO
PJP4001 P18
EN : VCCIO_EN P33
PG : +VCCIO_PG RH597 +1P05V_VCCPRIM_MPHY
RP28 +3V_RTM
P64 P18
B+ +1V_B+ SY8286RAC +1VALWP
P35
PJP11 +1P05VALW RH598 +1P05V_VCCAMPHYPLL
(PU100) PJP12
RZ37 +3VS_CAM
EN : PCH_PRIM_EN
PG : 1V_PG
P18
P37
RH600 +1P05V_SRC
RT124 +3VS_TBT
P32
B+
SI3457BDV-T1-E3 +INV_PWR_SRC P18
(QV11) RH603 +1P05V_VCCAPLL P38
EN : SIO_SLP_S3#
RVGA1 +AVCC33
P18
P38
RH602 +1P05V_BCLK
RVGA2 +VDD_DAC_33
P18
P39
RH607 +1P05V_XTAL RZ36 +3.3VDX_SSD
RZ117
P20
P42
RH614 +1P05V_XDP
C RA5 +3V_DVDD C

P54
TPS22961DNYR P42
(UZ15) +VCCST
P54
P59 RW4 +3V_FPSW
EN : VCCST_EN
ACIN Adapter RZ119
P55
130W/180W
TPS22961DNYR P50
P61 +VCCSTG
TPS51285BRUKR (UZ9 Reserved) P55
RI59 +3V_USBRD
VIN PU300 EN : VCCSTG_EN
P63
+3VALWP VIN_2.5V +2.5V_MEMP
AON7380/AON6796 +3VALW PJP25V1 RT9059GSP +2.5V_MEM P53
P60
(PQ301/PQ302) PJP33/PJP34 (PU25V00) PJP25V2 P63
Charger IC B+ B+ PL300 3/5V_B+ RI52 +3VS_CR
EN : SIO_SLP_S4#
TI BQ24780SRUYR PL301 PG : 2.5V_PGOOD
(PU700) AON7380/AON6796 P54 P42
(PQ303/PQ304) EM5209VF +3VS G9090-180T11U +1.8V_DVDD
(UZ1) P54 (UA1)
BATT+
EN : 3V_5V_EN EN : SIO_SLP_S3# EN : +3VS RC delay
PG : POK
P55 P14
P59
TPS22967DSGR
Battery (UZ25) +3VALW_PCH RH121 +3V_ROM
P55
56W
EN : PCH_PRIM_EN
P40 P14
SY6288C20AAC
+LAN_IO RH604 +3V_PCH_SPI
(UL2) P40
EN : LAN_EN
P47 P14
SY6288D20AAC
(UE4) +3VS_TP RH605 +3V_PCH_DSW
P47
EN : TP_EN#
P54 P14
SY6288C20AAC
+EDPVDD LH1 +3V_HDA
(UZ8) P54
EN : ENVDD
P37 P41

RT97 +3.3V_TBT_SX RN2 +3VA_WLAN

P44
P34 P34
RE12 +3VALW_EC
B
AP2330W-7 B

(UV17) +VDISPLAY_VCC
P44
P35
RE130 +DEBUG_PWR
RZ26 +5VS_TS
P45
P38
RTPM10 +3V_TPM DVGA1 +CRT_5V_OUT
FVGA1
P50
P39
RT53 +3VALW_PD
RZ34 +5VS_HDD
P66
+5VALWP 1.0VS_VGAP_VIN RT8061AZQW +1.0VS_VGAP
P42
+5VALW PJP10V1 +1VS_GFX
PJP31/PJP32 (PU10V00) PJP10V3 P66 RA7
RA10 +5V_PVDD
EN : NVVDDS_EN
PG : 1VS_GFX_PG

P51 P42
TPS2544RTER +5V_CHGUSB_3 RA8 +5V_AVDD
(US1) P51
EN : USB_POWERSHARE_VBUS_EN
P51 P46
SY6288D20AAC
(US2) +5V_CHGUSB_1 F1 +5VS_KBL
P52
EN : USB_EN#
P54 P47
EM5209VF
(UZ1) +5VS RE104 +5VS_FAN1
P54
EN : SIO_SLP_S3#
P65 P31 P47
B+ 1.8V_B+ SY8286RAC +1.8VSP APE8937GN2
PJP18V1 (PU18V00) +1.8V_PRIM (UZ24) +1.8V_GFX_AON RE105 +5VS_FAN2
PJP18V2 P31
EN : PCH_PRIM_EN EN : DGPU_PWR_EN
PG : PRIM_PWRGD_R
P31
P67 APE8937GN2
(UZ17) +1.8V_GFX_RUN
P31
B+ GPU_B+ AON6992 x4
EN : 1V8_RUN_EN
PL6000 (PQ6000/PQ6001 +GPU_CORE
P44
PQ6002/PQ6003)
A
RT8816AGQW RE15 +1.8VALW_EC A

EN : NVVDD_EN
PU6000 PG : GPU_CORE_PG

P68

GPU_B+
AON6992 x1 +GPU_CORE_VDDS
(PQ6200)
RT8816AGQW
EN : NVVDDS_EN
PU6101 PG : NC

P69

GPU_B+ +1.35VS_B+ AON6962 x1 +1.35VS_VGAP

PJP800 (PQ800) +1.35VS_VGA
PJP801/PJP802

RT8812AGQW-GP
PU800 EN : FBVDD_EN
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2016/09/01 Title
PG : DGPU_PWROK 2015/09/01 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 4 of 78
5 4 3 2 1
 5 4 3 2 1

Vinafix.com 1K 1K
Slave
D
1K
+3VALW 1K
+3VS D
DIMMA Address: 0xA0/0xA1
PCH
Host +3VS Slave
AW44 SMBCLK DMN65D8L PCH_SMBCLK
SMBDATA PCH_SMBDATA DIMMB Address: 0xA4/0xA5
BB43 DMN65D8L
Slave
499
FFS Address: 0x52/0x53
499
+3VALW
Slave

SML0_SMBCLK RTD2166 Address: 0x64/0x65, 0x68/0x69

AY44
BB39 SML0_SMBDATA

2.2K 2.4K

2.2K
+3VS 2.4K
+3VS_TP

Host +3VS Slave

AR41 I2C1_SCK_TP DMN65D8L I2C1_SCK_TP_C
Touch Address: 0x2C/0x2D
C
AR44 I2C1_SDA_TP DMN65D8L I2C1_SDA_TP_C Pad C

5.1K(@) 2.2K 10K

2.2K
+3VALW_EC 10K
+3VS

Slave +3VS Slave

AW42 GPU_THM_SMBCLK GPU_THM_SMBCLK DMN65D8L THM_SML1_CLK
Thermal
AW45 GPU_THM_SMBDAT GPU_THM_SMBDAT DMN65D8L THM_SML1_DATA Sensor
1.8K Address: 0x9A/0x9B

Address: 0x88/0x89
1.8K
+1.8V_GFX_AON

ALL_GPWRGD Slave
GPU_THM_SMBCLK DMN65D8L VGA_SMB_CK2
GPU_THM_SMBDAT DMN65D8L VGA_SMB_DA2 GPU

Address: 0x9E/0x9F
4.7K
B B

4.7K
+3VALW_EC
Host
Slave
PBAT_CHG_SMBCLK

Host
MEC1416 PBAT_CHG_SMBDAT BATT Address: 0x16/0x17

Slave
Host
CHAGER Address: 0x12/0x13

2.2K

2.2K
+3VALW_EC

Slave
TYPEC_SMBCLK 0 Ohm PD_I2C_SCL_R
TYPEC_SMBDA PD_I2C_SDA_R TPS65982D
0 Ohm
Address: 0x70/0x71
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMBus Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 5 of 78
5 4 3 2 1
 5 4 3 2 1

CFL-H
UH1C @
PEG_CRX_GTX_P15 E25 B25 PEG_CTX_GRX_P15 CH5 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P15
PEG_CTX_C_GRX_P[0..15] PEG_CRX_GTX_N15 D25 PEG_RXP_0 PEG_TXP_0 A25 PEG_CTX_GRX_N15 CH6 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N15
<23> PEG_CTX_C_GRX_P[0..15] PEG_RXN_0 PEG_TXN_0

<23> PEG_CTX_C_GRX_N[0..15] Vinafix.com

PEG_CTX_C_GRX_N[0..15]

PEG_CRX_GTX_P[0..15]
PEG_CRX_GTX_P14
PEG_CRX_GTX_N14
E24
F24 PEG_RXP_1
PEG_RXN_1
PEG_TXP_1
PEG_TXN_1
B24
C24
PEG_CTX_GRX_P14
PEG_CTX_GRX_N14
CH7
CH8
1
1
2 0.22U_0201_6.3V6M
2 0.22U_0201_6.3V6M
PEG_CTX_C_GRX_P14
PEG_CTX_C_GRX_N14
<23> PEG_CRX_GTX_P[0..15] PEG_CRX_GTX_P13 PEG_CTX_GRX_P13 PEG_CTX_C_GRX_P13
E23 B23 CH9 1 2 0.22U_0201_6.3V6M
D PEG_CRX_GTX_N[0..15] PEG_CRX_GTX_N13 D23 PEG_RXP_2 PEG_TXP_2 A23 PEG_CTX_GRX_N13 CH10 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N13
D
<23> PEG_CRX_GTX_N[0..15] PEG_RXN_2 PEG_TXN_2
PEG_CRX_GTX_P12 E22 B22 PEG_CTX_GRX_P12 CH11 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P12
PEG_CRX_GTX_N12 F22 PEG_RXP_3 PEG_TXP_3 C22 PEG_CTX_GRX_N12 CH12 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N12
PEG_RXN_3 PEG_TXN_3
PEG_CRX_GTX_P11 E21 B21 PEG_CTX_GRX_P11 CH13 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P11
PEG_CRX_GTX_N11 D21 PEG_RXP_4 PEG_TXP_4 A21 PEG_CTX_GRX_N11 CH14 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N11
PEG_RXN_4 PEG_TXN_4
PEG_CRX_GTX_P10 E20 B20 PEG_CTX_GRX_P10 CH15 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P10
PEG_CRX_GTX_N10 F20 PEG_RXP_5 PEG_TXP_5 C20 PEG_CTX_GRX_N10 CH16 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N10
PEG_RXN_5 PEG_TXN_5
PEG_CRX_GTX_P9 E19 B19 PEG_CTX_GRX_P9 CH17 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P9
PEG_CRX_GTX_N9 D19 PEG_RXP_6 PEG_TXP_6 A19 PEG_CTX_GRX_N9 CH18 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N9
PEG_RXN_6 PEG_TXN_6
PEG_CRX_GTX_P8 E18 B18 PEG_CTX_GRX_P8 CH19 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P8
PEG_CRX_GTX_N8 F18 PEG_RXP_7 PEG_TXP_7 C18 PEG_CTX_GRX_N8 CH20 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N8
PEG_RXN_7 PEG_TXN_7
PEG_CRX_GTX_P7 D17 A17 PEG_CTX_GRX_P7 CH21 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P7
PEG_CRX_GTX_N7 E17 PEG_RXP_8 PEG_TXP_8 B17 PEG_CTX_GRX_N7 CH22 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N7
PEG_RXN_8 PEG_TXN_8
PEG_CRX_GTX_P6 F16 C16 PEG_CTX_GRX_P6 CH23 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P6
PEG_CRX_GTX_N6 E16 PEG_RXP_9 PEG_TXP_9 B16 PEG_CTX_GRX_N6 CH24 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N6
PEG_RXN_9 PEG_TXN_9
PEG_CRX_GTX_P5 D15 A15 PEG_CTX_GRX_P5 CH25 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P5
PEG_CRX_GTX_N5 E15 PEG_RXP_10 PEG_TXP_10 B15 PEG_CTX_GRX_N5 CH26 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N5
PEG_RXN_10 PEG_TXN_10
PEG_CRX_GTX_P4 F14 C14 PEG_CTX_GRX_P4 CH27 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P4
PEG_CRX_GTX_N4 E14 PEG_RXP_11 PEG_TXP_11 B14 PEG_CTX_GRX_N4 CH28 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N4
PEG_RXN_11 PEG_TXN_11
PEG_CRX_GTX_P3 D13 A13 PEG_CTX_GRX_P3 CH29 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P3
PEG_CRX_GTX_N3 E13 PEG_RXP_12 PEG_TXP_12 B13 PEG_CTX_GRX_N3 CH30 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N3
PEG_RXN_12 PEG_TXN_12
PEG_CRX_GTX_P2 F12 C12 PEG_CTX_GRX_P2 CH31 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P2
PEG_CRX_GTX_N2 E12 PEG_RXP_13 PEG_TXP_13 B12 PEG_CTX_GRX_N2 CH32 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N2
PEG_RXN_13 PEG_TXN_13
C PEG_CRX_GTX_P1 D11 A11 PEG_CTX_GRX_P1 CH33 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P1 C
PEG_CRX_GTX_N1 E11 PEG_RXP_14 PEG_TXP_14 B11 PEG_CTX_GRX_N1 CH34 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N1
PEG_RXN_14 PEG_TXN_14
PEG_CRX_GTX_P0 F10 C10 PEG_CTX_GRX_P0 CH35 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P0
PEG_CRX_GTX_N0 E10 PEG_RXP_15 PEG_TXP_15 B10 PEG_CTX_GRX_N0 CH36 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N0
+VCCIO PEG_RXN_15 PEG_TXN_15
RH24
1 2 PEG_RCOMP G2
24.9_0402_1% PEG_RCOMP

DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0
<16> DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 <16>
E8 A8
<16> DMI_CRX_PTX_N0 DMI_RXN_0 DMI_TXN_0 DMI_CTX_PRX_N0 <16>
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
<16> DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 DMI_RXP_1 DMI_TXP_1 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 <16>
F6 B6
<16> DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1 DMI_CTX_PRX_N1 <16>
To PCH <16> DMI_CRX_PTX_P2
DMI_CRX_PTX_P2 D5
DMI_RXP_2 DMI_TXP_2
B5 DMI_CTX_PRX_P2
DMI_CTX_PRX_P2 <16>
To PCH
DMI_CRX_PTX_N2 E5 A5 DMI_CTX_PRX_N2
<16> DMI_CRX_PTX_N2 DMI_RXN_2 DMI_TXN_2 DMI_CTX_PRX_N2 <16>
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
<16> DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_RXP_3 3 OF 13 DMI_TXP_3 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 <16>
J9 B4
<16> DMI_CRX_PTX_N3 DMI_RXN_3 DMI_TXN_3 DMI_CTX_PRX_N3 <16>
CFL-H_BGA1440

CFL-H
UH1D @

CPU_DP1_P0 K36 D29 EDP_TXP0

<36> CPU_DP1_P0 CPU_DP1_N0 DDI1_TXP_0 EDP_TXP_0 EDP_TXN0 EDP_TXP0 <35>
K37 E29
<36> CPU_DP1_N0 CPU_DP1_P1 DDI1_TXN_0 EDP_TXN_0 EDP_TXP1 EDP_TXN0 <35>
B J35 F28 B
<36> CPU_DP1_P1 CPU_DP1_N1 DDI1_TXP_1 EDP_TXP_1 EDP_TXN1 EDP_TXP1 <35>
J34 E28
<36> CPU_DP1_N1 CPU_DP1_P2 DDI1_TXN_1 EDP_TXN_1 EDP_TXP2 EDP_TXN1 <35>
H37 A29
<36> CPU_DP1_P2 CPU_DP1_N2 DDI1_TXP_2 EDP_TXP_2 EDP_TXN2 EDP_TXP2 <35>
H36 B29
TBT-AR <36>
<36>
CPU_DP1_N2
CPU_DP1_P3
CPU_DP1_P3 J37 DDI1_TXN_2
DDI1_TXP_3
EDP_TXN_2
EDP_TXP_3
C28 EDP_TXP3 EDP_TXN2
EDP_TXP3
<35>
<35>
CPU_DP1_N3 J38 B28 EDP_TXN3
<36> CPU_DP1_N3 DDI1_TXN_3 EDP_TXN_3 EDP_TXN3 <35>
CPU_DP1_AUXP D27 C26 EDP_AUXP
<36> CPU_DP1_AUXP CPU_DP1_AUXN E27 DDI1_AUXP EDP_AUXP B26 EDP_AUXN EDP_AUXP <35>
<36> CPU_DP1_AUXN DDI1_AUXN EDP_AUXN EDP_AUXN <35>
CPU_DP2_P0 H34
<36> CPU_DP2_P0 CPU_DP2_N0 DDI2_TXP_0
H33
<36> CPU_DP2_N0 CPU_DP2_P1 DDI2_TXN_0 EDP_DISP_UTIL BIA_PWM_PCH
F37 A33 RH20 1 @ 2
<36> CPU_DP2_P1 CPU_DP2_N1 DDI2_TXP_1 EDP_DISP_UTIL BIA_PWM_PCH <13,35> +VCCIO
G38 0_0402_5%
<36> CPU_DP2_N1 CPU_DP2_P2 DDI2_TXN_1
F34
<36> CPU_DP2_P2 CPU_DP2_N2 DDI2_TXP_2 EDP_COMP
F35 D37 RH30 1 2
TBT-AR <36>
<36>
CPU_DP2_N2
CPU_DP2_P3
CPU_DP2_P3 E37 DDI2_TXN_2
DDI2_TXP_3
DISP_RCOMP 24.9_0402_1%
CPU_DP2_N3 E36
<36> CPU_DP2_N3 DDI2_TXN_3 EDP_COMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
CPU_DP2_AUXP F26 Max length=100 mils.
<36> CPU_DP2_AUXP CPU_DP2_AUXN E26 DDI2_AUXP
<36> CPU_DP2_AUXN DDI2_AUXN
C34
D34 DDI3_TXP_0
B36 DDI3_TXN_0
B34 DDI3_TXP_1
F33 DDI3_TXN_1
E33 DDI3_TXP_2
C33 DDI3_TXN_2
B33 DDI3_TXP_3
DDI3_TXN_3 G27 AUD_AZA_CPU_SCLK
PROC_AUDIO_CLK AUD_AZA_CPU_SDO AUD_AZA_CPU_SCLK <15>
A27 G25
DDI3_AUXP PROC_AUDIO_SDI AUD_AZA_CPU_SDI AUD_AZA_CPU_SDI_R AUD_AZA_CPU_SDO <15>
B27 G29 RH145 1 2
DDI3_AUXN 4 ofPROC_AUDIO_SDO
13 AUD_AZA_CPU_SDI_R <15>
20_0402_5%
A A
CFL-H_BGA1440 Close to CPU

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(1/7) DMI,PEG,DDI,EDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 6 of 78
5 4 3 2 1
 5 4 3 2 1

Non-Interleave
<21> DDR_A_D[0..63]
<21> DDR_A_MA[0..13]
<21> DDR_A_DQS#[0..7]

Vinafix.com <21>

<22>
DDR_A_DQS[0..7]

DDR_B_D[0..63]
<22> DDR_B_MA[0..13]
D <22> DDR_B_DQS#[0..7] D
<22> DDR_B_DQS[0..7]

CFL-H
UH1A @ CFL-H
UH1B @
DDR CHANNEL A DDR CHANNEL B
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4 DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_A_CLK0 DDR_A_D16 BT11 AM9 DDR_B_CLK0
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK#0 DDR_A_CLK0 <21> DDR_A_D17 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK#0 DDR_B_CLK0 <22>
BT6 AG2 BR11 AN9
DDR_A_D2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR_A_CLK1 DDR_A_CLK#0 <21> DDR_A_D18 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 DDR_B_CLK1 DDR_B_CLK#0 <22>
BP3 AK2 BT9 AM7
DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR_A_CLK#1 DDR_A_CLK1 <21> DDR_A_D19 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 DDR_B_CLK#1 DDR_B_CLK1 <22>
BR3 AK1 BR8 AM8
DDR_A_D4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR_A_CLK#1 <21> DDR_A_D20 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 DDR_B_CLK#1 <22>
BN5 AL3 BP11 AM11
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3 DDR_A_D21 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
DDR_A_D6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2 DDR_A_D22 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1 DDR_A_D23 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR_A_D24 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_CKE0 DDR_A_D25 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8 DDR_B_CKE0
DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE1 DDR_A_CKE0 <21> DDR_A_D26 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE1 DDR_B_CKE0 <22>
BL2 AT2 BL8 AT10
DDR_A_D11 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 DDR_A_CKE1 <21> DDR_A_D27 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 DDR_B_CKE1 <22>
BM1 AT3 BJ8 AT7
DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5 DDR_A_D28 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
DDR_A_D13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR_A_D29 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_CS#0 DDR_A_D30 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11 DDR_B_CS#0
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#1 DDR_A_CS#0 <21> DDR_A_D31 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#1 DDR_B_CS#0 <22>
BK2 AE2 BJ7 AE7
DDR_A_D32 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 DDR_A_CS#1 <21> DDR_A_D48 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 DDR_B_CS#1 <22>
BG4 AD2 BG11 AF10
DDR_A_D33 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5 DDR_A_D49 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_A_D34 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR_A_D50 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_A_D35 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_ODT0 DDR_A_D51 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7 DDR_B_ODT0
DDR_A_D36 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT1 DDR_A_ODT0 <21> DDR_A_D52 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT1 DDR_B_ODT0 <22>
BG2 AE4 BF11 AE8
DDR_A_D37 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 DDR_A_ODT1 <21> DDR_A_D53 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 DDR_B_ODT1 <22>
BG1 AE1 BF10 AE9
DDR_A_D38 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4 DDR_A_D54 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_A_D39 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR_A_D55 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
C DDR_A_D40 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_BA0 DDR_A_D56 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10 DDR_B_MA16_RAS# C
DDR_A_D41 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA1 DDR_A_BA0 <21> DDR_A_D57 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA14_WE# DDR_B_MA16_RAS# <22>
BD1 AH1 BC11 AH11
DDR_A_D42 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR_A_BG0 DDR_A_BA1 <21> DDR_A_D58 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 DDR_B_MA15_CAS# DDR_B_MA14_WE# <22>
BC4 AU1 BB8 AF8
DDR_A_D43 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <21> DDR_A_D59 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15_CAS# <22>
BC5 BC8
DDR_A_D44 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_MA16_RAS# DDR_A_D60 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8 DDR_B_BA0
DDR_A_D45 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA14_WE# DDR_A_MA16_RAS# <21> DDR_A_D61 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA1 DDR_B_BA0 <22>
BD4 AG4 BB10 AH9
DDR_A_D46 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 DDR_A_MA15_CAS# DDR_A_MA14_WE# <21> DDR_A_D62 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 DDR_B_BG0 DDR_B_BA1 <22>
BC1 AD1 BC7 AR9
DDR_A_D47 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15_CAS# <21> DDR_A_D63 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <22>
BC2 BB7
DDR_B_D0 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0 DDR_B_D16 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR_B_D1 AB2 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 AP4 DDR_A_MA1 DDR_B_D17 AA10 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 AK6 DDR_B_MA1
DDR_B_D2 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2 DDR_B_D18 AC11 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 AK5 DDR_B_MA2
DDR_B_D3 AA5 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 AP5 DDR_A_MA3 DDR_B_D19 AC10 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_5/DDR1_MA_2 AL5 DDR_B_MA3
DDR_B_D4 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4 DDR_B_D20 AA7 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 AL6 DDR_B_MA4
DDR_B_D5 AB4 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 AP1 DDR_A_MA5 DDR_B_D21 AA8 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 AM6 DDR_B_MA5
DDR_B_D6 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6 DDR_B_D22 AC8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AN7 DDR_B_MA6
DDR_B_D7 AA1 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 AN1 DDR_A_MA7 DDR_B_D23 AC7 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 AN10 DDR_B_MA7
DDR_B_D8 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8 DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7
DDR_B_D9 V2 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 AT4 DDR_A_MA9 DDR_B_D24 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
DDR_B_D10 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10 DDR_B_D25 W7 DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 AR11 DDR_B_MA9
DDR_B_D11 U2 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 AN2 DDR_A_MA11 DDR_B_D26 V10 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AH7 DDR_B_MA10
DDR_B_D12 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12 DDR_B_D27 V11 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 AN11 DDR_B_MA11
DDR_B_D13 V4 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 AE3 DDR_A_MA13 DDR_B_D28 W11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AR10 DDR_B_MA12
DDR_B_D14 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_A_BG1 DDR_B_D29 W10 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 AF9 DDR_B_MA13
DDR_B_D15 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR_A_ACT# DDR_A_BG1 <21> DDR_B_D30 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 DDR_B_BG1
U4 AU3 V7 AR7
DDR_B_D32 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR_A_ACT# <21> DDR_B_D31 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_ACT# DDR_B_BG1 <22>
R2 V8 AT9
DDR_B_D33 DDR0_DQ_48/DDR1_DQ_32 DDR_A_PAR DDR_B_D48 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <22>
P5 AG3 R11
DDR_B_D34 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_ALERT# DDR_A_PAR <21> DDR_B_D49 DDR1_DQ_48/DDR1_DQ_48 DDR_B_PAR
R4 AU5 P11 AJ7
DDR_B_D35 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR_A_ALERT# <21> DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_ALERT# DDR_B_PAR <22>
P4 P7 AR8
DDR_B_D36 DDR0_DQ_51/DDR1_DQ_35 DDR_B_D51 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR_B_ALERT# <22>
R5 DDR4(IL)/LP3-DDR4(NIL) R8
DDR_B_D37 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0 DDR_B_D52 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_B_D38 R1 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 BL3 DDR_A_DQS#1 DDR_B_D53 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_A_DQS#2
DDR_B_D39 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#4 DDR_B_D54 R7 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 BL9 DDR_A_DQS#3
B DDR_B_D40 M4 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 BD3 DDR_A_DQS#5 DDR_B_D55 P8 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 BG9 DDR_A_DQS#6 B
DDR_B_D41 M1 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 AA3 DDR_B_DQS#0 DDR_B_D56 L11 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 BC9 DDR_A_DQS#7
DDR_B_D42 L4 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 U3 DDR_B_DQS#1 DDR_B_D57 M11 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 AC9 DDR_B_DQS#2
DDR_B_D43 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_B_DQS#4 DDR_B_D58 L7 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 W9 DDR_B_DQS#3
DDR_B_D44 M5 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 L3 DDR_B_DQS#5 DDR_B_D59 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 DDR_B_DQS#6
DDR_B_D45 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR_B_D60 L10 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 M9 DDR_B_DQS#7
DDR_B_D46 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0 DDR_B_D61 M10 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
DDR_B_D47 L1 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 BK3 DDR_A_DQS1 DDR_B_D62 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_A_DQS2
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 BF3 DDR_A_DQS4 DDR_B_D63 L8 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 BJ9 DDR_A_DQS3
LP3/DDR4 DDR0_DQSP_2/DDR0_DQSP_4 BC3 DDR_A_DQS5 DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 BF9 DDR_A_DQS6
BA2 DDR0_DQSP_3/DDR0_DQSP_5 AB3 DDR_B_DQS0 AW11 LP3/DDR4 DDR1_DQSP_2/DDR0_DQSP_6 BB9 DDR_A_DQS7
BA1 NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 V3 DDR_B_DQS1 AY11 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 AA9 DDR_B_DQS2
AY4 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 R3 DDR_B_DQS4 AY8 NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 V9 DDR_B_DQS3
AY5 NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 M3 DDR_B_DQS5 AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 DDR_B_DQS6
BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5 AY10 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 L9 DDR_B_DQS7
BA4 NC/DDR0_ECC_4 AY3 AW10 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3 AY7 NC/DDR1_ECC_5 AW9
AY2 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8
1 OF 13 AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9
NC/DDR0_ECC_7 NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8
CFL-H_BGA1440
+V_DDR_REFA_R +V_DDR_REFB_R

RH148 1 2 121_0402_1% DDR_RCOMP0 G1 BN13

RH149 1 2 75_0402_1% DDR_RCOMP1 H1 DDR_RCOMP_0 DDR_VREF_CA BP13
RH150 1 2 100_0402_1% DDR_RCOMP2 J2 DDR_RCOMP_1 2 OF 13 DDR0_VREF_DQ BR13
DDR_RCOMP_2 DDR1_VREF_DQ
CFL-H_BGA1440

A A

Security Classification Compal Secret Data

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(2/7) DDRIV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 7 of 78
5 4 3 2 1
 5 4 3 2 1

+VCCSTG

RH165 1 2 H_PROCHOT#
CFG[0..19] <20>
1K_0402_5%
CFL-H

CFG Straps for Processor +VCCST

UH1E @

Vinafix.com
Stall reset sequence after CPU PLL lock until de-asserted RH163

RH156
1
1K_0402_5%
1 @
2

2
H_THERMTRIP#_R

XDP_PREQ#
<14>
<14>
PCH_CPU_BCLK_P
PCH_CPU_BCLK_N
PCH_CPU_BCLK_P
PCH_CPU_BCLK_N
B31
A32 BCLKP
BCLKN
CFG_0
CFG_1
BN25
BN27
BN26
CFG0
CFG1
CFG2
51_0402_5% PCH_CPU_PCIBCLK_P D35 CFG_2 BN28 CFG3
1 = (Default) Normal Operation; No stall.
D
CFG0 * RH164 1
1K_0402_5%
2 H_VCCST_PWRGD

VR_SVID_DATA
<14>
<14>
PCH_CPU_PCIBCLK_P
PCH_CPU_PCIBCLK_N
PCH_CPU_PCIBCLK_N

CPU_24MHZ_P
C36 PCI_BCLKP
PCI_BCLKN
CFG_3
CFG_4
CFG_5
BR20
BM20
CFG4
CFG5
D

RH151 1 2 E31 BT20 CFG6

<14> CPU_24MHZ_P CPU_24MHZ_N CLK24P CFG_6
0 = Stall. 100_0402_5% D31 BP20 CFG7
VR_SVID_ALERT# <14> CPU_24MHZ_N CLK24N CFG_7
RH152 1 2 BR23 CFG8
56.2_0402_1% CFG_8 BR22 CFG9
RH144 1 @ 2 H_CATERR# CFG_9 BT23 CFG10
CFG0 RH183 1 @ 2 49.9_0402_1% CFG_10 BT22 CFG11
1K_0402_5% CFG_11 BM19 CFG12
CFG_12 BR19 CFG13
CFG_13 BP19 CFG14
VR_SVID_ALERT# RH153 1 2 220_0402_5% VR_SVID_ALERT#_R BH31 CFG_14 BT19 CFG15
<71> VR_SVID_ALERT# VR_SVID_CLK VIDALERT# CFG_15
BH32
<71> VR_SVID_CLK VR_SVID_DATA VIDSCK
BH29 BN23 CFG17
<71> VR_SVID_DATA H_PROCHOT# H_PROCHOT#_R VIDSOUT CFG_17
RH158 1 2 499_0402_1% BR30 BP23 CFG16
<44,59,60,71> H_PROCHOT# PROCHOT# CFG_16 BP22 CFG19
DDR_VTT_PG_CTRL BT13 CFG_19 BN22 CFG18
DDR_VTT_CNTL CFG_18
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
BR27 XDP_BPM#0
BPM#_0 BT27 XDP_BPM#1 XDP_BPM#0 <20>
BPM#_1 BM31 XDP_BPM#1 <20>
1: Normal Operation; Lane # definition matches BPM#_2
CFG2 H_VCCST_PWRGD RH154 1 2 60.4_0402_1% VCCST_PWRGD_CPU H13 BT30
socket pin map definition <15,20> H_VCCST_PWRGD VCCST_PWRGD BPM#_3
H_CPUPWRGD BT31
<15> H_CPUPWRGD PLTRST_CPU# PROCPWRGD CPU_XDP_TDO
0:Lane Reversed BP35 BT28
* <13,20>
<13>
<13>
PLTRST_CPU#
H_PM_SYNC_R
H_PM_DOWN
H_PM_DOWN
PECI_EC
RH155 1 2 20_0402_5%
H_PM_SYNC_R
H_PM_DOWN_R
PECI_EC_R
BM34
BP31
RESET#
PM_SYNC
PM_DOWN
PROC_TDO
PROC_TDI
PROC_TMS
BL32
BP28
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TCK
CPU_XDP_TDO <20>
CPU_XDP_TDI <20>
CPU_XDP_TMS <20>
RH190 1 @ 2 0_0402_5% BT34 BR28
<13,44> PECI_EC H_THERMTRIP#_R PECI PROC_TCK CPU_XDP_TCK <15,20>
CFG2 RH184 1 2 J31
<13> H_THERMTRIP#_R THERMTRIP# CPU_XDP_TRST#
1K_0402_5% BP30
PROC_DETECT# PROC_TRST# XDP_PREQ# CPU_XDP_TRST# <19,20>
RH89 1 @ 2 0_0402_5% BR33 BL30
C <17> PROC_DETECT# SKTOCC# PROC_PREQ# XDP_PRDY# XDP_PREQ# <19,20> C
BN1 BP27
PROC_SELECT# PROC_PRDY# XDP_PRDY# <19,20>
H_CATERR# BM30
CATERR# BT25 CFG_RCOMP
+1.2V_DDR AT13 CFG_RCOMP
ZVM#

1
AW13
MSM# RH59
Display Port Presence Strap 1 AU13
CH197 +3VS AY13 RSVD1 49.9_0402_1%
0.1U_0402_10V7K UC1 RSVD2

2
1 : Disabled; No Physical Display Port 5 1 5 OF 13
VCC NC

1
2
CFG4 attached to Embedded Display Port RH93 2 DDR_VTT_PG_CTRL CFL-H_BGA1440
220K_0402_5% 4 A
Y 3
0 : Enabled; An external Display Port device is
* connected to the Embedded Display Port
GND

2
SM_PG_CTRL 74AUP1G07SE-7_SOT353 CFL-H
<62> SM_PG_CTRL
SA00007WE00 UH1M @

CFG4 RH185 1 2 E2
1K_0402_5% E3 RSVD_TP5
E1 IST_TRIG
Reserve for ESD D1 RSVD_TP4
RSVD_TP3
H_VCCST_PWRGD CH210 1 2 BR1 BK28
@ESD@ 100P_0402_50V8J BT2 RSVD_TP1 RSVD11 BJ28
RSVD_TP2 RSVD10
PLTRST_CPU# CH233 1 2 BN35
@ESD@ 470P_0402_50V7K RSVD15
PCIE Port Bifurcation Straps J24
H24 RSVD28
B H_PROCHOT#_R CH211 1 2 BN33 RSVD27 B
100P_0402_50V8J BL34 RSVD14
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2
RSVD13
H_CPUPWRGD CH232 1 2 N29
100P_0402_50V8J R14 RSVD30
disabled AE29 RSVD31
Pilot. AA14 RSVD2
01: Reserved - (Device 1 function 1 disabled ; function Pop CH232 and change from 0.1u to 100p RSVD1
AP29
2 enabled) AP14 RSVD5
A36 RSVD4
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled VSS_A36
A37
VSS_A37
CFG5 RH186 1 @ 2 PCH_TRIGGER RH167 1 2 30_0402_5% PCH_TRIGGER_R H23
<19> PCH_TRIGGER CPU_TRIGGER CPU_TRIGGER_R PROC_TRIGIN
1K_0402_5% RH192 1 2 30_0402_5% J23
<19> CPU_TRIGGER PROC_TRIGOUT
CFG6 RH187 1 @ 2 F30
1K_0402_5% RSVD24

E30
RSVD23
If change to x8, need cheange setting.
B30 BL31
C30 RSVD7 RSVD12 AJ8
RSVD21 RSVD3 G13
PEG DEFER TRAINING RSVD25
G3
J3 RSVD26 C38
1: (Default) PEG Train immediately following xxRESETB
CFG7 * de assertion
RSVD29 RSVD22
RSVD20
RSVD17
C1
BR2
BR35 BP1
BR31 RSVD19 RSVD16 B38
A
0: PEG Wait for BIOS for training RSVD18 RSVD8 A
BH30 B2
RSVD9 RSVD6
13 OF 13
CFG7 RH188 1 @ 2
1K_0402_5% CFL-H_BGA1440

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(3/7) RSVD,CFG,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 8 of 78
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE CFL-H Vinafix.com

+VCC_CORE 96000mA(Hexa Core GT2)
+VCC_CORE
CFL-H
+VCC_CORE
UH1I @ UH1J @
D AA13 AH13 D
AA31 VCC1 VCC64 AH14 K14 W35
AA32 VCC2 VCC65 AH29 L13 VCC1 VCC64 W36
AA33 VCC3 VCC66 AH30 L14 VCC2 VCC65 W37
AA34 VCC4 VCC67 AH31 N13 VCC3 VCC66 W38
AA35 VCC5 VCC68 AH32 N14 VCC4 VCC67 Y29
AA36 VCC6 VCC69 AJ14 N30 VCC5 VCC68 Y30
AA37 VCC7 VCC70 AJ29 N31 VCC6 VCC69 Y31
AA38 VCC8 VCC71 AJ30 N32 VCC7 VCC70 Y32
AB29 VCC9 VCC72 AJ31 N35 VCC8 VCC71 Y33
AB30 VCC10 VCC73 AJ32 N36 VCC9 VCC72 Y34
AB31 VCC11 VCC74 AJ33 N37 VCC10 VCC73 Y35
AB32 VCC12 VCC75 AJ34 N38 VCC11 VCC74 Y36
AB35 VCC13 VCC76 AJ35 P13 VCC12 VCC75
AB36 VCC14 VCC77 AJ36 P14 VCC13
AB37 VCC15 VCC78 AK31 P29 VCC14
AB38 VCC16 VCC79 AK32 P30 VCC15
AC13 VCC17 VCC80 AK33 P31 VCC16
AC14 VCC18 VCC81 AK34 P32 VCC17
AC29 VCC19 VCC82 AK35 P33 VCC18
AC30 VCC20 VCC83 AK36 P34 VCC19
AC31 VCC21 VCC84 AK37 P35 VCC20
AC32 VCC22 VCC85 AK38 P36 VCC21
AC33 VCC23 VCC86 AL13 R13 VCC22
AC34 VCC24 VCC87 AL29 R31 VCC23
AC35 VCC25 VCC88 AL30 R32 VCC24
AC36 VCC26 VCC89 AL31 R33 VCC25
AD13 VCC27 VCC90 AL32 R34 VCC26
AD14 VCC28 VCC91 AL35 R35 VCC27
C AD31 VCC29 VCC92 AL36 R36 VCC28 C
AD32 VCC30 VCC93 AL37 R37 VCC29
AD33 VCC31 VCC94 AL38 R38 VCC30
AD34 VCC32 VCC95 AM13 T29 VCC31
AD35 VCC33 VCC96 AM14 T30 VCC32
AD36 VCC34 VCC97 AM29 T31 VCC33
AD37 VCC35 VCC98 AM30 T32 VCC34
AD38 VCC36 VCC99 AM31 T35 VCC35
AE13 VCC37 VCC100 AM32 T36 VCC36
AE14 VCC38 VCC101 AM33 T37 VCC37
AE30 VCC39 VCC102 AM34 T38 VCC38
AE31 VCC40 VCC103 AM35 U29 VCC39
AE32 VCC41 VCC104 AM36 U30 VCC40
AE35 VCC42 VCC105 AN13 U31 VCC41
AE36 VCC43 VCC106 AN14 U32 VCC42
AE37 VCC44 VCC107 AN31 U33 VCC43
AE38 VCC45 VCC108 AN32 U34 VCC44
AF29 VCC46 VCC109 AN33 U35 VCC45
AF30 VCC47 VCC110 AN34 U36 VCC46
AF31 VCC48 VCC111 AN35 V13 VCC47
AF32 VCC49 VCC112 AN36 V14 VCC48
AF33 VCC50 VCC113 AN37 V31 VCC49
AF34 VCC51 VCC114 AN38 V32 VCC50
AF35 VCC52 VCC115 AP13 V33 VCC51
AF36 VCC53 VCC116 AP30 V34 VCC52
AF37 VCC54 VCC117 AP31 V35 VCC53
AF38 VCC55 VCC118 AP32 V36 VCC54
AG14 VCC56 VCC119 AP35 V37 VCC55
AG31 VCC57 VCC120 AP36 V38 VCC56
B AG32 VCC58 VCC121 AP37 +VCC_CORE W13 VCC57 B
AG33 VCC59 VCC122 AP38 W14 VCC58
AG34 VCC60 VCC123 K13 W29 VCC59
VCC61 VCC124 VCC60
1

AG35 W30
AG36 VCC62 RH197 W31 VCC61
VCC63 W32 VCC62 10 OF 13
100_0402_1% VCC63
CFL-H_BGA1440
2

AG37 RH198 1 @ 2 0_0402_5% VCCSENSE

VCC_SENSE VCCSENSE <71>
9 OF 13 AG38 RH28 1 @ 2 0_0402_5% VSSSENSE
VSS_SENSE VSSSENSE <71>
1

CFL-H_BGA1440
RH29

100_0402_1%
2

A A

Security Classification Compal Secret Data

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(4/7) PWR,RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 9 of 78
5 4 3 2 1
 5 4 3 2 1

570805_CFL_EDS_Vol1_Rev0.7 570805_CFL_EDS_Vol1_Rev0.7
+VCC_SA CFL-H +1.2V_VDDQ_CPU
Max: 11100mA +VCCSA UH1L @ +1.2V_DDR Max: 3300mA

J30
K29 VCCSA1
VCCSA2
VDDQ1
VDDQ2
Vinafix.com AA6
AE12
K30 AF5
K31 VCCSA3 VDDQ3 AF6
D D
K32 VCCSA4 VDDQ4 AG5
K33 VCCSA5 VDDQ5 AG9
K34 VCCSA6 VDDQ6 AJ12
K35 VCCSA7 VDDQ7 AL11 +VCCSA
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12 CH111 CH112 CH113 CH114 CH115 CH116 CH117
L36 VCCSA11 VDDQ11 AR6
VCCSA12 VDDQ12 1 1 1 1 1 1 1
L37 AT12
VCCSA13 VDDQ13

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
L38 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5 2 2 2 2 2 2 2
M31 VCCSA16 VDDQ16 J6
M32 VCCSA17 VDDQ17 K12
M33 VCCSA18 VDDQ18 K6
570805_CFL_EDS_Vol1_Rev0.7 M34 VCCSA19 VDDQ19 L12
+VCC_IO M35 VCCSA20 VDDQ20 L6
Max: 6400mA M36 VCCSA21 VDDQ21 R6
VCCSA22 VDDQ22 T6
+VCCIO VDDQ23 W6
VDDQ24 Y12
AG12 VDDQ25
G15 VCCIO1 +1.2V_VCCPLL_OC +1.2V_DDR +VCCSA
G17 VCCIO2
G19 VCCIO3 BH13 RH107 1 @ 2
G21 VCCIO4 VCCPLL_OC1 BJ13 0_0402_5% CH133
H15 VCCIO5 VCCPLL_OC2 G11 +VCCST
VCCIO6 VCCPLL_OC3 1
H16
VCCIO7 +VCCSTG

1U_0402_6.3V6K
C H17 H30 Max: 60mA C
H19 VCCIO8 VCCST
H20 VCCIO9 H29 Max: 20mA 2
H21 VCCIO10 VCCSTG2
H26 VCCIO11 G30 +VCCST
H27 VCCIO12 VCCSTG1
J15 VCCIO13 H28 Max: 150mA
J16 VCCIO14 VCCPLL1 J28 +VCCSA
J17 VCCIO15 VCCPLL2
J19 VCCIO16 RH201 1 2 100_0402_1%
J20 VCCIO17 M38 RH202 1 @ 2 0_0402_5% VCCSA_SENSE
VCCIO18 VCCSA_SENSE VSSSA_SENSE VCCSA_SENSE <71>
J21 M37 RH31 1 @ 2 0_0402_5%
VCCIO19 VSSSA_SENSE VSSSA_SENSE <71>
J26 RH41 1 2 100_0402_1%
J27 VCCIO20 H14
VCCIO21 VCCIO_SENSE J14
12 OF 13 VSSIO_SENSE
+VCCIO
CFL-H_BGA1440
RH515 1 2 100_0402_1%
RH514 1 @ 2 0_0402_5% VCCIO_SENSE
VSSIO_SENSE VCCIO_SENSE <76>
RH513 1 @ 2 0_0402_5%
VSSIO_SENSE <76>
RH516 1 2 100_0402_1%

DVT2.
Add CH234 22uF 0603 cap
close to CPU Ball H30/J28
B +VCCIO +1.2V_DDR +1.2V_DDR +VCCST +VCCSTG +1.2V_VCCPLL_OC B

1U_0201_6.3V6M

1U_0201_6.3V6M
CH102 CH103 CH104 CH129 CH130 CH131 CH132 CH118 CH121 CH120 CH119 CH122 CH123 CH125 CH126 CH127 CH128 CH124 CH110 CH204 CH234 CH106
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M

1U_0402_6.3V6K

CC36

CC37
@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

571391_PDG V0.71
Back cap +1.2V_VDDQ_CPU: 10uF * 11 22uF * 4 Back cap
Back cap Back cap close CPU ball Back cap close CPU ball
close CPU ball close CPU ball close CPU ball 1uF * 1 close BJ13
+1.2V_DDR 1uF * 1 close H30 1uF * 1 close G11
1uF * 1 close J28
10U_0603_6.3V6M

10U_0603_6.3V6M

CH216 CH217
1 1

2 2
A A

Back cap
close CPU ball
TD team 12 * 10u
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(5/7) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 10 of 78
5 4 3 2 1
 5 4 3 2 1

GT
55000mA(Hexa Core GT2)
+VCCGT CFL-H +VCCGT
UH1K @
AT14 BD35
AT31 VCCGT1 VCCGT80 BD36
Vinafix.com
AT32
AT33
VCCGT2
VCCGT3
VCCGT4
VCCGT81
VCCGT82
VCCGT83
BE31
BE32
AT34 BE33
AT35 VCCGT5 VCCGT84 BE34
D D
AT36 VCCGT6 VCCGT85 BE35
AT37 VCCGT7 VCCGT86 BE36
AT38 VCCGT8 VCCGT87 BE37
AU14 VCCGT9 VCCGT88 BE38
AU29 VCCGT10 VCCGT89 BF13
AU30 VCCGT11 VCCGT90 BF14
AU31 VCCGT12 VCCGT91 BF29
AU32 VCCGT13 VCCGT92 BF30
AU35 VCCGT14 VCCGT93 BF31
AU36 VCCGT15 VCCGT94 BF32
AU37 VCCGT16 VCCGT95 BF35
AU38 VCCGT17 VCCGT96 BF36
AV29 VCCGT18 VCCGT97 BF37
AV30 VCCGT19 VCCGT98 BF38
AV31 VCCGT20 VCCGT99 BG29
AV32 VCCGT21 VCCGT100 BG30
AV33 VCCGT22 VCCGT101 BG31
AV34 VCCGT23 VCCGT102 BG32
AV35 VCCGT24 VCCGT103 BG33
AV36 VCCGT25 VCCGT104 BG34
AW14 VCCGT26 VCCGT105 BG35
AW31 VCCGT27 VCCGT106 BG36
AW32 VCCGT28 VCCGT107 BH33
AW33 VCCGT29 VCCGT108 BH34
AW34 VCCGT30 VCCGT109 BH35
AW35 VCCGT31 VCCGT110 BH36
AW36 VCCGT32 VCCGT111 BH37
AW37 VCCGT33 VCCGT112 BH38
C AW38 VCCGT34 VCCGT113 BJ16 C
AY29 VCCGT35 VCCGT114 BJ17
AY30 VCCGT36 VCCGT115 BJ19
AY31 VCCGT37 VCCGT116 BJ20
AY32 VCCGT38 VCCGT117 BJ21
AY35 VCCGT39 VCCGT118 BJ23
AY36 VCCGT40 VCCGT119 BJ24
AY37 VCCGT41 VCCGT120 BJ26
AY38 VCCGT42 VCCGT121 BJ27
BA13 VCCGT43 VCCGT122 BJ37
BA14 VCCGT44 VCCGT123 BJ38
BA29 VCCGT45 VCCGT124 BK16
BA30 VCCGT46 VCCGT125 BK17
BA31 VCCGT47 VCCGT126 BK19
BA32 VCCGT48 VCCGT127 BK20
BA33 VCCGT49 VCCGT128 BK21
BA34 VCCGT50 VCCGT129 BK23
BA35 VCCGT51 VCCGT130 BK24
BA36 VCCGT52 VCCGT131 BK26
BB13 VCCGT53 VCCGT132 BK27
BB14 VCCGT54 VCCGT133 BL15
BB31 VCCGT55 VCCGT134 BL16
BB32 VCCGT56 VCCGT135 BL17
BB33 VCCGT57 VCCGT136 BL23
BB34 VCCGT58 VCCGT137 BL24
BB35 VCCGT59 VCCGT138 BL25
BB36 VCCGT60 VCCGT139 BL26
BB37 VCCGT61 VCCGT140 BL27
BB38 VCCGT62 VCCGT141 BL28
B BC29 VCCGT63 VCCGT142 BL36 B
BC30 VCCGT64 VCCGT143 BL37
BC31 VCCGT65 VCCGT144 BM15
BC32 VCCGT66 VCCGT145 BM16
BC35 VCCGT67 VCCGT146 BM17
BC36 VCCGT68 VCCGT147 BM36
BC37 VCCGT69 VCCGT148 BM37
BC38 VCCGT70 VCCGT149 BN15
BD13 VCCGT71 VCCGT150 BN16
BD14 VCCGT72 VCCGT151 BN17
BD29 VCCGT73 VCCGT152 BN36
BD30 VCCGT74 VCCGT153 BN37
BD31 VCCGT75 VCCGT154 BN38
BD32 VCCGT76 VCCGT155 BP15
BD33 VCCGT77 VCCGT156 BP16
VCCGT78 VCCGT157 +VCCGT
BD34 BP17
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
1

BR15 VCCGT160 VCCGT165 BT16 RH203

BR16 VCCGT161 VCCGT166 BT17
BR17 VCCGT162 VCCGT167 BT37 100_0402_1%
VCCGT163 VCCGT168
2

AH37 RH204 1 @ 2 0_0402_5% VSSGT_SENSE

11 OFVSSGT_SENSE VCCGT_SENSE VSSGT_SENSE <71>
13 AH38 RH32 1 @ 2 0_0402_5%
VCCGT_SENSE VCCGT_SENSE <71>
CFL-H_BGA1440
1

RH33
A 1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils A
100_0402_1% 2. Maintain 25-mil separation distance away from any other dynamic signals.
3. RC12, RC13 should be placed within 2 inches (50.8 mm) of CPU
2

Security Classification Compal Secret Data

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 11 of 78
5 4 3 2 1
 5 4 3 2 1

CFL-H CFL-H CFL-H

UH1F @ UH1G @ UH1H @
A10 AK4 AW5 BJ15 BN4 F15
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BN7 VSS_325 VSS_409 F17
Vinafix.com
A16
A18
VSS_2
VSS_3
VSS_4
VSS_83
VSS_84
VSS_85
AL12
AL14
AY33
AY34
VSS_164 VSS_245
VSS_165 VSS_246
VSS_166 VSS_247
BJ22
BJ25
BP12
BP14
VSS_326 VSS_410
VSS_327 VSS_411
VSS_328 VSS_412
F19
F2
A20 AL33 B9 BJ29 BP18 F21
A22 VSS_5 VSS_86 AL34 BA10 VSS_167 VSS_248 BJ30 BP21 VSS_329 VSS_413 F23
D D
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 BP24 VSS_330 VSS_414 F25
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP25 VSS_331 VSS_415 F27
A28 VSS_8 VSS_89 AL8 BA37 VSS_170 VSS_251 BJ33 BP26 VSS_332 VSS_416 F29
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP29 VSS_333 VSS_417 F3
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP33 VSS_334 VSS_418 F31
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP34 VSS_335 VSS_419 F36
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BP7 VSS_336 VSS_420 F4
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR12 VSS_337 VSS_421 F5
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR14 VSS_338 VSS_422 F8
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR18 VSS_339 VSS_423 F9
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR21 VSS_340 VSS_424 G10
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR24 VSS_341 VSS_425 G12
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR25 VSS_342 VSS_426 G14
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR26 VSS_343 VSS_427 G16
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR29 VSS_344 VSS_428 G18
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR34 VSS_345 VSS_429 G20
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR36 VSS_346 VSS_430 G22
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BR7 VSS_347 VSS_431 G23
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT12 VSS_348 VSS_432 G24
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT14 VSS_349 VSS_433 G26
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT18 VSS_350 VSS_434 G28
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT21 VSS_351 VSS_435 G4
AD11 VSS_28 VSS_109 AP8 BC6 VSS_190 VSS_271 BL33 BT24 VSS_352 VSS_436 G5
AD12 VSS_29 VSS_110 AP9 BD10 VSS_191 VSS_272 BL35 BT26 VSS_353 VSS_437 G6
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT29 VSS_354 VSS_438 G8
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT32 VSS_355 VSS_439 G9
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 BT5 VSS_356 VSS_440 H11
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C11 VSS_357 VSS_441 H12
C AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C13 VSS_358 VSS_442 H18 C
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C15 VSS_359 VSS_443 H22
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C17 VSS_360 VSS_444 H25
AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C19 VSS_361 VSS_445 H32
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C21 VSS_362 VSS_446 H35
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C23 VSS_363 VSS_447 J10
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C25 VSS_364 VSS_448 J18
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C27 VSS_365 VSS_449 J22
AF2 VSS_42 VSS_123 AR36 BE4 VSS_204 VSS_285 BM25 C29 VSS_366 VSS_450 J25
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C31 VSS_367 VSS_451 J32
AF4 VSS_44 VSS_125 AR38 BE6 VSS_206 VSS_287 BM27 C37 VSS_368 VSS_452 J33
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C5 VSS_369 VSS_453 J36
AG11 VSS_46 VSS_127 AR5 BF33 VSS_208 VSS_289 BM29 C8 VSS_370 VSS_454 J4
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 C9 VSS_371 VSS_455 J7
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D10 VSS_372 VSS_456 K1
AG30 VSS_49 VSS_130 AT6 BG12 VSS_211 VSS_292 BM35 D12 VSS_373 VSS_457 K10
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D14 VSS_374 VSS_458 K11
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D16 VSS_375 VSS_459 K2
AG8 VSS_52 VSS_133 AU12 BG37 VSS_214 VSS_295 BM6 D18 VSS_376 VSS_460 K3
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D20 VSS_377 VSS_461 K38
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D22 VSS_378 VSS_462 K4
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D24 VSS_379 VSS_463 K5
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D26 VSS_380 VSS_464 K7
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D28 VSS_381 VSS_465 K8
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D3 VSS_382 VSS_466 K9
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D30 VSS_383 VSS_467 L29
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D33 VSS_384 VSS_468 L30
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D6 VSS_385 VSS_469 L33
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 D9 VSS_386 VSS_470 L34
B AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E34 VSS_387 VSS_471 M12 B
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E35 VSS_388 VSS_472 M13
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E38 VSS_389 VSS_473 N10
AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E4 VSS_390 VSS_474 N11
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 E9 VSS_391 VSS_475 N12
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N3 VSS_392 VSS_476 N2
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N33 VSS_393 VSS_477 BT8
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N34 VSS_394 VSS_478 BR9
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N4 VSS_395 VSS_479
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N5 VSS_396 A3
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N6 VSS_397 VSS_A3 A34
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N7 VSS_398 VSS_A34 A4
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N8 VSS_399 VSS_A4 B3
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 N9 VSS_400 VSS_B3 B37
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P12 VSS_401 VSS_B37 BR38
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 P37 VSS_402 VSS_BR38 BT3
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M14 VSS_403 VSS_BT3 BT35
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 M6 VSS_404 VSS_BT35 BT36
VSS_81 VSS_162 VSS_243 VSS_324 N1 VSS_405 VSS_BT36 BT4
CFL-H_BGA1440 CFL-H_BGA1440 F11 VSS_406 VSS_BT4 C2
F13 VSS_4078 OF 13
VSS_C2 D38
VSS_408 VSS_D38
CFL-H_BGA1440

A A

Security Classification Compal Secret Data

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 12 of 78
5 4 3 2 1
 5 4 3 2 1

CNP-H
UH2C @
AR2 G36 PCIE_PRX_DTX_N9
CL_CLK PCIE9_RXN PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 <39> +3VALW_PCH
AT5 F36
CL_DATA PCIE9_RXP PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 <39>
AU4 C34
CL_RST# PCIE9_TXN PCIE_PTX_DRX_P9 PCIE_PTX_DRX_N9 <39> mCARD_PCIE_SATA#
D34 RH68 1 2
PCIE9_TXP PCIE_PTX_DRX_P9 <39>
P48 10K_0402_5%
V47 GPP_K8
GPP_K9 PCIE_PRX_DTX_N10
SSD +3VS
V48 K37
GPP_K10 PCIE10_RXN PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 <39>
W47 J37
GPP_K11 PCIE10_RXP PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <39> CAM_CBL_DET#
C35 RH79 1 2

Vinafix.com PCIE10_TXN PCIE_PTX_DRX_P10 PCIE_PTX_DRX_N10 <39>

L47 B35 10K_0402_5%
GPP_K0 PCIE10_TXP PCIE_PTX_DRX_P10 <39> PCH_SATA_LED#
L46 RH80 1 2
U48 GPP_K1 F44 PCIE_PRX_DTX_N15 10K_0402_5%
GPP_K2 PCIE15_RXN/SATA2_RXN PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 <41>
U47 E45
D GPP_K3 PCIE15_RXP/SATA2_RXP PCIE_PTX_DRX_N15 PCIE_PRX_DTX_P15 <41> D
N48 B40 NGFF WLAN
GPP_K4 PCIE_15_SATA_2_TXN PCIE_PTX_DRX_P15 PCIE_PTX_DRX_N15 <41>
N47 C40
GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_DRX_P15 <41>
P47
R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN M40
PCIE_PTX_DRX_P11 C36 PCIE16_RXP/SATA3_RXP B41
<39> PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN
SSD B36 C41
<39> PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP
F39
<39> PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11 PCIE11_RXP/SATA0A_RXP
G38 K43
<39> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44
AR42 PCIE17_RXP/SATA4_RXP A42
AR48 GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN B42
AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP
AU46 GPP_F13/SATA_SDATAOUT0 P41
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN R40
PCIE_PTX_DRX_N14 C39 PCIE18_RXP/SATA5_RXP C42
<40> PCIE_PTX_DRX_N14 PCIE_PTX_DRX_P14 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN
LAN D39 D42
<40> PCIE_PTX_DRX_P14 PCIE_PRX_DTX_N14 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
D46
<40> PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 PCIE14_RXN/SATA1B_RXN PCH_SATA_LED#
C47 AK48
<40> PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED# PCH_SATA_LED# <48>
SATA_PTX_DRX_N0B B38 AH41
<39> SATA_PTX_DRX_N0B SATA_PTX_DRX_P0B PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 mCARD_PCIE_SATA#
HDD C38 AJ43
TPM ID <39> SATA_PTX_DRX_P0B SATA_PRX_DTX_N0B C45 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 AK47
mCARD_PCIE_SATA# <39>
TPM ID <39> SATA_PRX_DTX_N0B SATA_PRX_DTX_P0B C46 PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 AN47
(GPP_G7) <39> SATA_PRX_DTX_P0B PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3
GPP_F1/SATAXPCIE4/SATAGP4
AM46
SATA_PTX_DRX_P1A E37 AM43
SW TPM 0 SSD
<39> SATA_PTX_DRX_P1A
<39> SATA_PTX_DRX_N1A
SATA_PTX_DRX_N1A D38 PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5
PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6
AM47
SATA_PRX_DTX_P1A J41 AM48
HW TPM 1 <39> SATA_PRX_DTX_P1A
<39> SATA_PRX_DTX_N1A
SATA_PRX_DTX_N1A H42 PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7
PCIE12_RXN/SATA1A_RXN AU48 BIA_PWM_PCH
GPP_F21/EDP_BKLTCTL L_BKLT_EN_EC BIA_PWM_PCH <6,35>
B44 AV46
PROJECT ID1 PROJECT ID2 A44 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN AV44 ENVDD_PCH L_BKLT_EN_EC <44>
C PROJECT ID R37 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN ENVDD_PCH <54> C
(GPP_G3) (GPP_G4) R35 PCIE20_RXP/SATA7_RXP
PCIE20_RXN/SATA7_RXN THRMTRIP#
AD3 H_THERMTRIP# RH191 1 2 620_0402_5% H_THERMTRIP#_R
H_THERMTRIP#_R <8>
D43 AF2 PECI RH138 1 2 13_0402_5% PECI_EC
Firestar MLK C44 PCIE19_TXP/SATA6_TXP PECI AF3 H_PM_SYNC RH189 1 2 30_0402_5% H_PM_SYNC_R PECI_EC <8,44>
0 0 N42 PCIE19_TXN/SATA6_TXN PM_SYNC AG5 PLTRST_CPU# H_PM_SYNC_R <8>
Firestar B M44 PCIE19_RXP/SATA6_RXP 3 OF 13
PCIE19_RXN/SATA6_RXN
PLTRST_CPU#
PM_DOWN
AE2 H_PM_DOWN PLTRST_CPU# <8,20>
H_PM_DOWN <8>
Armani MLK 1 0 CNP-H_BGA874 Rev1.0
CNP-H
0 1 UH2M @
Not Used
1 1 CAM_CBL_DET# AW13
GPP_G0/SD_CMD CNV_WR_CLKN
BD4 CLK_CNV_PRX_DTX_N
CLK_CNV_PRX_DTX_N <41>
@ PAD T94 BE9 BE3 CLK_CNV_PRX_DTX_P
TBT_CIO_PLUG_EVENT# GPP_G1/SD_DATA0 CNV_WR_CLKP CLK_CNV_PRX_DTX_P <41>
BF8
<36> TBT_CIO_PLUG_EVENT# PROJECT_ID1 GPP_G2/SD_DATA1 CNV_PRX_DTX_N0
BF9 BB3
+3VS PROJECT_ID2 GPP_G3/SD_DATA2 CNV_WR_D0N CNV_PRX_DTX_P0 CNV_PRX_DTX_N0 <41>
BG8 BB4
LCD_DBC GPP_G4/SD_DATA3 CNV_WR_D0P CNV_PRX_DTX_N1 CNV_PRX_DTX_P0 <41>
BE8 BA3
KB_BL_DET GPP_G5/SD_CD# CNV_WR_D1N CNV_PRX_DTX_P1 CNV_PRX_DTX_N1 <41>
BD8 BA2
<46> KB_BL_DET TPM_ID GPP_G6/SD_CLK CNV_WR_D1P CNV_PRX_DTX_P1 <41>
AV13
GPP_G7/SD_WP
1

BC5 CLK_CNV_PTX_DRX_N
+3VS CNV_WT_CLKN CLK_CNV_PTX_DRX_P CLK_CNV_PTX_DRX_N <41>
@ @ TPM@ AP3 BB6
GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP CLK_CNV_PTX_DRX_P <41>
RH557 RH561 RH616 AP2
10K_0402_5% 10K_0402_5% 10K_0402_5% RH559 1 2 LCD_DBC AN4 GPP_I12/M2_SKT2_CFG1 BE6 CNV_PTX_DRX_N0
GPP_I13/M2_SKT2_CFG2 3.3V CNV_WT_D0N CNV_PTX_DRX_N0 <41>
10K_0402_5% AM7 BD7 CNV_PTX_DRX_P0
CNV_PTX_DRX_P0 <41>
2

PROJECT_ID1 GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P BG6 CNV_PTX_DRX_N1

PROJECT_ID2 CNV_WT_D1N CNV_PTX_DRX_P1 CNV_PTX_DRX_N1 <41>
AV6 BF6
TPM_ID CPU_VCCIO_PWR_GATE# GPP_J0/CNV_PA_BLANKING CNV_WT_D1P CNV_WT_RCOMP CNV_PTX_DRX_P1 <41>
TH135 @ AY3 BA1
AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP RH25 1 2 150_0402_1%
GPP_J11/A4WP_PRESENT
1

AV7 B12 PCIE_RCOMPN RH108 1 2 100_0402_1%

@ @ NON_TPM@ AW3 GPP_J10 PCIE_RCOMPN A13 PCIE_RCOMPP
RH558 RH562 RH617 AT10 GPP_J_2 1.8V PCIE_RCOMPP BE5 SD_RCOMP_1P8 RH586 1 2 200_0402_1%
10K_0402_5% 10K_0402_5% 10K_0402_5% CNV_BRI_PTX_DRX AV4 GPP_J_3 SD_1P8_RCOMP BE4 SD_RCOMP_3P3 RH23 1 2 200_0402_1%
B <41> CNV_BRI_PTX_DRX CNV_BRI_PRX_DTX GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP B
AY2 BD1
<41> CNV_BRI_PRX_DTX
2

CNV_RGI_PTX_DRX BA4 GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 BE1 GPPJ_RCOMP_1P8 RH587 1 2 200_0402_1%

<41> CNV_RGI_PTX_DRX CNV_RGI_PRX_DTX GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82
AV3 BE2
<41> CNV_RGI_PRX_DTX GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
AW2
GPP_J9 AU9 GPP_J8/CNV_MFUART2_RXD Y35
GPP_J9/CNV_MFUART2_TXD RSVD2 Y36 Add TH136 test point for CVNi check list
RH558 FSTR@ RH562 FSTR@ RSVD3
BC1 @ TH136
13 OF 13 RSVD1 AL35 @ TH101
TP
Rev1.0
#571483_CFL_H_RVP_CRB_TDK_Rev0p5
CNP-H_BGA874 Recommend external test point

10K_0402_5% 10K_0402_5%
The 30 HSIO lanes on PCH-H supports the following configurations:
SD028100280 SD028100280 1. Up to 24 PCIe* Lanes
STRAP —A maximum of 16 PCIe* Ports (or devices) can be enabled
RH557 AMN@ RH562 AMN@ For DDX03 R02
‧ When a GbE Port is enabled, the maximum number of PCIe* Ports (or
+1.8V_PRIM XTAL Frequency Select devices) that can be enabled reduces based off the following:
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
RH590 1 2 1K_0402_5% CNV_BRI_PTX_DRX 21-24 (PCIe* Controller #6) can be individually configured
10K_0402_5% 10K_0402_5% 2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
This signal has a weak internal pull-down. — SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
SD028100280 SD028100280 0 = 38.4/19.2MHz XTAL frequency selected. — SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19
1 = 24MHz XTAL frequency selected. (DDX03) 3. Up to 10 USB 3.1 Lanes
Notes: — A maximum of 10 USB 3.1 Ports (or devices) can be enabled
1. The internal pull-down is disabled after RSMRST# 4. Up to 4 GbE Lanes
de-asserts. — A maximum of 1 GbE Port (or device) can be enabled
2. This signal is in the primary well. 5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
+1.8V_PRIM M.2 CNV Mode Select STRAP — x2 and x4 PCIe* NVMe SSD
A — x2 IntelR Optane? Memory Device A
— See the “PCI Express* (PCIe*)” chapter for the PCH PCIe* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support
STRAP RH588 2 1 100K_0402_5% CNV_RGI_PTX_DRX
6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
+1.8V_PRIM the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
RH589 2 @ 1 10K_0402_5% Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.
RH591 2 @ 1 10K_0402_5% GPP_J9
An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
Security Classification Compal Secret Data Compal Electronics, Inc.
The signal has a weak internal pull-down 1 = Integrated CNVi disable. 2011/08/25 2012/07/25 Title
0 = VCCPSPI is connected to 3.3V rail Issued Date Deciphered Date
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin CNVi CRF have internal pull down 1K. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/7) SATA,PCIE,CNVi
CNV_RGI_DT strap pin have internal pull up 20K. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
strap must be a ‘1’ for the proper functionality
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
of the SPI (Flash) I/Os CNV_RGI_DT will detect low and enable CNVi when insert CNVi CRF.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 13 of 78
5 4 3 2 1
 5 4 3 2 1

CNP-H
+3VS UH2G @
RP3 @ PAD T92 BE33
4 5 CLKREQ_PCIE#2 GPP_A16/CLKOUT_48
3 6 CLKREQ_PCIE#7 CPU_24MHZ_P D7 Y3 PCH_XDP_CLK_N
2
1
7
8
CLKREQ_PCIE#3
CLKREQ_PCIE#6
<8>
<8>
CPU_24MHZ_P
CPU_24MHZ_N
CPU_24MHZ_N C6 CLKOUT_CPUNSSC_P
CLKOUT_CPUNSSC#
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
Y4 PCH_XDP_CLK_P PCH_XDP_CLK_N
PCH_XDP_CLK_P
<20>
<20> PCH_RTCX2
RTC CRYSTAL
10K_0804_8P4R_5% Vinafix.com <8>
<8>
PCH_CPU_BCLK_P
PCH_CPU_BCLK_N
PCH_CPU_BCLK_P
PCH_CPU_BCLK_N
B8
C8 CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK#
CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P
B6
A6
PCH_CPU_PCIBCLK_N
PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N
PCH_CPU_PCIBCLK_P
<8>
<8>
PCH_RTCX1 RH70 1 2
10M_0402_5%
XTAL24_OUT U9 AJ6
D XTAL24_IN U10 XTAL_OUT CLKOUT_PCIE_N0 AJ7 YH1 D
XCLK_BIASREF XTAL_IN CLKOUT_PCIE_P0
Trace Width/Space: 15mil /15 mil RH593 1 2 XCLK_BIASREF T3 AH9 2 1
Max Trace Length: 1000 mil 60.4_0402_1% XCLK_BIASREF CLKOUT_PCIE_N1 AH10
PCH_RTCX1 BA49 CLKOUT_PCIE_P1 32.768KHZ 9PF 20PPM 9H03280012
PCH_RTCX2 BA48 RTCX1 AE14 CLK_PCIE_N2
RTCX2 CLKOUT_PCIE_N2 CLK_PCIE_N2 <40> SJ10000Q400

1
AE15 CLK_PCIE_P2 LAN CH45 CH46
+3V_ROM CLKOUT_PCIE_P2 CLK_PCIE_P2 <40>
BF31 10P_0402_50V 10P_0402_50V
BE31 GPP_B5/SRCCLKREQ0# AE6 CLK_PCIE_N3
CLK_PCIE_N3 <41>

2
RH74 CLKREQ_PCIE#2 AR32 GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 AE7 CLK_PCIE_P3
<40> CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_P3 <41> NGFF - WLAN
1 @ 2 PCH_SPI_0_CS#0 CLKREQ_PCIE#3 BB30
<41> CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3#
4.7K_0402_5% BA30 AC2
CLKREQ_PCIE#5 AN29 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 AC3 Trace Space: 15 mil
+3VALW_PCH <36> CLKREQ_PCIE#5 CLKREQ_PCIE#6 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 Max Trace Length: 1000 mil
AE47 DVT1.
<39> CLKREQ_PCIE#6 CLKREQ_PCIE#7 GPP_H0/SRCCLKREQ6# CLK_PCIE_N5
AC48 AB2
RH568
<23> CLKREQ_PCIE#7
AE41 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 AB3 CLK_PCIE_P5 CLK_PCIE_N5 <36>
TBT-AR Change CH45, CH46 form 8pF 0402 to 10pF 0402.
TPM_PIRQ# GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5 CLK_PCIE_P5 <36>
1 2 AF48
10K_0402_5% AC41 GPP_H3/SRCCLKREQ9# W4 CLK_PCIE_N6
GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 CLK_PCIE_P6 CLK_PCIE_N6 <39>
AC39 W3 NGFF - SSD
GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6 CLK_PCIE_P6 <39>
AE39
AB48 GPP_H6/SRCCLKREQ12# W7 CLK_PEG_N7
GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 CLK_PEG_P7 CLK_PEG_N7 <23>
AC44 W6 GPU
GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7 CLK_PEG_P7 <23>
AC43
+3VALW_PCH GPP_H9/SRCCLKREQ15# AC14
V2 CLKOUT_PCIE_N8 AC15

1
RH601
@ 2 GPP_H12
V3 CLKOUT_PCIE_N15
CLKOUT_PCIE_P15
CLKOUT_PCIE_P8
U2 XTAL24_OUT RH570 1 EMI@ 2 XTAL_24M_PCH_OUT
PCH CRYSTAL
STRAP CLKOUT_PCIE_N9
4.7K_0402_5% T2 U3 33_0201_5%
This signal has a weak internal pull-down. T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9 XTAL24_IN RH569 1 EMI@ 2 XTAL_24M_PCH_IN RH72 1 2
0 = Master Attached Flash Sharing (MAFS) enabled (Default) CLKOUT_PCIE_P14 AC9 33_0201_5% 1M_0402_5%
1 = Slave Attached Flash Sharing (SAFS) enabled. AA1 CLKOUT_PCIE_N10 AC11
Notes: Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10 YH2
C 1. This signal is in the primary well. CLKOUT_PCIE_P13 AE9 C
Warning: This strap must be configured to ‘0’ if the 24MHZ_12PF_7V24000020
AC7 CLKOUT_PCIE_N11 AE11
eSPI or LPC strap is configured to ‘0’ CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
AC6
CLKOUT_PCIE_P12 7 OF 13 3 1
R6 REFCLK_CNV 3 1
CLKIN_XTAL REFCLK_CNV <41>
1 GND GND 1

1
CNP-H_BGA874 Rev1.0 CH47 CH48
RN36 4 2
CNVI@ DVT1. 15P_0402_50V8J
15P_0402_50V8J 2 2
10K_0402_5%
Move RN36 from page 41 to page 14 and

2
connnet to net REFCLK_CNV.
RH582 993@EMI@ RH582 994@EMI@
CNP-H
UH2A @ +3VS
@ PAD T17 BE36 AV29 PCH_PLTRST#
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# TOUCH_SCREEN_PD# RH69 1 2
10K_0402_5%
15_0402_5% 0_0402_5% R15 Y47 TBT_FORCE_PWR TOUCHPAD_INTR# RH179 1 2
RSVD2 GPP_K16/GSXCLK RTD3_CIO_PWR_EN TBT_FORCE_PWR <36>
R13 Y46 10K_0402_5%
RSVD1 GPP_K12/GSXDOUT RTD3_CIO_PWR_EN <36> GC6_THM_DIS#
SD028150A80 SD028000080 Y48 RH573 1 2
GPP_K13/GSXSLOAD W46 10K_0402_5%
@ PAD T4943 AL37 GPP_K14/GSXDIN AA45
@ PAD T4944 AN35 VSS GPP_K15/GSXSRESET#
TP
PCH_SPI_0_SI AU41 AL47
<20,45> PCH_SPI_0_SI PCH_SPI_0_SO SPI0_MOSI GPP_E3/CPU_GP0 TOUCH_SCREEN_PD#
BA45 AM45
<45> PCH_SPI_0_SO PCH_SPI_0_CS#0 SPI0_MISO GPP_E7/CPU_GP1 TOUCHPAD_INTR# TOUCH_SCREEN_PD# <35>
AY47 BF32
PCH_SPI_0_CLK_R RH582 1 @EMI@ 2 PCH_SPI_0_CLK AW47 SPI0_CS0# GPP_B3/CPU_GP2 BC33 GC6_THM_DIS# +RTCVCC_PCH
<45> PCH_SPI_0_CLK_R SPI0_CLK GPP_B4/CPU_GP3 GC6_THM_DIS# <44>
1 15_0402_5% AW48
CH215 SPI0_CS1# AE44 INTRUDER# RH143 1 2
@RF@ PCH_SPI_0_WP# AY48 GPP_H18/SML4ALERT# AJ46 1M_0402_5%
<20> PCH_SPI_0_WP# PCH_SPI_0_HOLD# SPI0_IO2 GPP_H17/SML4DATA
10P_0402_25V8J BA46 AE43
B RH610 1 2 PCH_SPI_0_CLK 2 PCH_SPI_0_CS#2 AT40 SPI0_IO3 GPP_H16/SML4CLK AC47 GPP_H15 B
<45> PCH_SPI_0_CS#2 SPI0_CS2# GPP_H15/SML3ALERT#
100K_0402_5% AD48 DH1
BE19 GPP_H14/SML3DATA AF47 TOUCHPAD_INTR# 2 1 PTP_INT#
Reserve for RF BF19 GPP_D1/SPI1_CLK/SBK1_BK1
GPP_D0/SPI1_CS#/SBK0_BK0
GPP_H13/SML3CLK
GPP_H12/SML2ALERT#
AB47 GPP_H12 PTP_INT# <44,47>
FFS_INT2 BF18 AD47 RB751S40_SOD523-2
<39> FFS_INT2 TPM_PIRQ# GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA
BE18 AE48 AZ5125-01HPR7G_SOD523-2
<45> TPM_PIRQ# GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
BC17
BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 INTRUDER#
GPP_D21/SPI1_IO2 INTRUDER#
CNP-H_BGA874 Rev1.0 Reserve for ESD
PCH_PLTRST# CH208 1 2
@ESD@ 100P_0402_50V8J

+3V_ROM

#571182_CNL_PCH_H_EDS_Rev0p7
RH3 2 1 100K_0402_5% PCH_SPI_0_WP# SPI ROM FOR ME ( 16MByte ) +3VALW_PCH

2
RH121
@ 1
+3V_ROM
1
RH1
@
0_0402_5%
2

RH4 2 1 100K_0402_5% PCH_SPI_0_HOLD#

0_0402_5%
RH5832 1 100K_0402_5% PCH_SPI_0_SI +3VS
UH8
PCH_SPI_0_CS#0 RH101 1 @ 2 0_0402_5% PCH_SPI_0_CS#_R 1 8
CS# VCC

5
+3VALW_PCH PCH_SPI_0_SO_R 2 7 PCH_SPI_0_HOLD#_R UH7
PCH_SPI_0_WP#_R 3 DO(IO1) IO 6 PCH_SPI_0_CLK_ROM

VCC
RH99 2 1 100K_0402_5% GPP_H15 STRAP 4 IO2 CLK 5 PCH_SPI_0_SI_R PCH_PLTRST# 1
GND DI(IO0) IN1 4 PCH_PLTRST#_EC
OUT PCH_PLTRST#_EC <23,36,39,40,41,44,45>

1
#571182_CNL_PCH_H_EDS_V1_Rev0.5 W25Q128JVSIQ_SO8 2

GND
IN2

1
External pull-up is required. Recommend 100K if pulled RH612
up to 3.3V or 75K if pulled up to 1.8V. SA00005VV20 RH77
100K_0402_5%

3
A MC74VHC1G08DFT2G_SC70-5 100K_0402_5% A
DVT2.

2
Change UH8 from SA00009RI10 W25Q256JVEIQ_WSON8_8X6 SA00000OH00

2
to SA00005VV20 W25Q128JVSIQ_SO8
PCH_SPI_0_CLK_R RE126 1 EMI@ 2 33_0402_5% PCH_SPI_0_CLK_ROM
PCH_SPI_0_SO RE127 1 2 33_0402_5% PCH_SPI_0_SO_R
PCH PCH_SPI_0_SI
PCH_SPI_0_WP#
RE128
RE129
1
1
2
2
33_0402_5%
33_0402_5%
PCH_SPI_0_SI_R
PCH_SPI_0_WP#_R
SPI ROM Security Classification Compal Secret Data Compal Electronics, Inc.
PCH_SPI_0_HOLD# RE71 1 2 33_0402_5% PCH_SPI_0_HOLD#_R 2011/08/25 2012/07/25 Title
Issued Date Deciphered Date
Close to UH8 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/7) CLK,SPI,PLTRST
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 14 of 78
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH
+3VALW_PCH
RP15 6/18: PCH_PCIE_WAKE# RH17 1 2 1K_0402_5%
RH21 1 2 1K_0402_5% SMBCLK HDA_SDOUT_R 1 8 HDA_SDOUT PCH_PCIE_WAKE#_XDP PCH_BATLOW# RH81 1 2 10K_0402_5%
<42> HDA_SDOUT_R LAN_WAKE#
RH22 1 2 1K_0402_5% SMBDATA 2 7 RH181 1 2 10K_0402_5%
HDA_SYNC_R HDA_SYNC
PCH_BATLOW# AC_PRESENT
3 6 RH125 1 2 100K_0402_5%
<42> HDA_SYNC_R
4 5 LAN_WAKE#
RH62 1 2 499_0402_1% SML0_SMBCLK AC_PRESENT are DSW rail
RH63 1 2 499_0402_1% SML0_SMBDATA 33_0804_8P4R_5% +3VALW_PCH

CH50 1 2 CNP-H SYS_RESET# RH193 1 @ 2 8.2K_0402_5%

@EMI@ 10P_0402_25V8J UH2D

Vinafix.com
+3VS 33_0402_5% 1 EMI@ 2 RH572 HDA_BIT_CLK BD11 BF36 +1.8V_PRIM
<42> HDA_BIT_CLK_R HDA_SDIN0 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
BE11 AV32
PCH_SMBCLK <42> HDA_SDIN0 HDA_SDOUT HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN# ME_SUS_PWR_ACK
RH27 1 2 1K_0402_5% BF12 RH67 1 @ 2 1M_0402_5%
RH26 1 2 1K_0402_5% PCH_SMBDATA HDA_SYNC BG13 HDA_SDO/I2S0_TXD BF41
RH86 1 2 10K_0402_5% DGPU_PWROK HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC SIO_SLP_S3# RH608 1 2 100K_0402_5%
D D
BE10 BD42 SIO_SLP_S4# RH609 1 2 100K_0402_5%
BF10 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN#
BE12 HDA_SDI1/I2S1_RXD BB46 H_DRAMRST#
I2S1_TXD/SNDW2_DATA DRAM_RESET# H_DRAMRST# <21>
BD12 BE32
RH13 1 2 100K_0402_5% PCH_RSMRST# I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
RH581 1 2 100K_0402_5% SYS_PWROK
Close to PCH GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29
RH613 1 2 100K_0402_5% HDA_BIT_CLK AUD_AZA_CPU_SDO RH146 1 2 AUD_AZA_CPU_SDO_R AM2 GPP_B0/GSPI0_CS1# R47
<6> AUD_AZA_CPU_SDO AUD_AZA_CPU_SDI_R HDACPU_SDO GPP_K17/ADR_COMPLETE
30_0402_5% AN3 AP29
<6> AUD_AZA_CPU_SDI_R AUD_AZA_CPU_SCLK AUD_AZA_CPU_SCLK_R HDACPU_SDI GPP_B11/I2S_MCLK SYS_PWROK
RH147 1 2 AM3 AU3
<6> AUD_AZA_CPU_SCLK HDACPU_SCLK SYS_PWROK SYS_PWROK <20,44>
30_0402_5%
GPU_ID2 AV18 BB47 PCH_PCIE_WAKE# RH114 1 @ 2 0_0402_5% PCIE_WAKE#
GPU_ID1 GPP_D8/I2S2_SCLK WAKE# SIO_SLP_A# PCIE_WAKE# <36,40,41,44>
AW18 BE40
CLKREQ_CNV# BA17 GPP_D7/I2S2_RXD GPD6/SLP_A# BF40 T4947 PAD
<41> CLKREQ_CNV# CNV_RF_RESET# GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# SIO_SLP_S0#
BE16 BC28 @
<41> CNV_RF_RESET# GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# SIO_SLP_S3# SIO_SLP_S0# <45>
BF15 BF42
GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# SIO_SLP_S4# SIO_SLP_S3# <31,33,35,36,54,55,62>
BD16 BE42
DGPU_PWROK GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# SIO_SLP_S5# SIO_SLP_S4# <54,55,63>
AV16 BC42
<23,69> DGPU_PWROK GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5#
AW15 T4938 PAD
GPP_D17/DMIC_CLK1/SNDW3_CLK BE45 SUSCLK @
GPD8/SUSCLK PCH_BATLOW# SUSCLK <39,41,44>
BF44
GPD0/BATLOW# BE35
PCH_RTCRST# BE47 GPP_A15/SUSACK# BC37 ME_SUS_PWR_ACK
PCH_SRTCRST# BD46 RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK
SRTCRST#
PCH_PWROK AY42 BG44 LAN_WAKE# RH11 1 @ 2 0_0402_5% LANWAKE#
PCH_RSMRST# PCH_RSMRST#_R PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT DV1 ACAV_IN LANWAKE# <44>
RH503 1 @ 2 BA47 BG42 2 1
<20,44> PCH_RSMRST# RSMRST# GPD1/ACPRESENT ACAV_IN <44,59,60>
0_0402_5% BD39 RB751S40_SOD523-2
SLP_SUS# BE46 SIO_PWRBTN# AZ5125-01HPR7G_SOD523-2
PCH_DPWROK GPD3/PWRBTN# SYS_RESET# SIO_PWRBTN# <20,44>
RH9 1 @ 2 AW41 AU2
DSW_PWROK SYS_RESET# SYS_RESET# <20>
0_0402_5% SMBALERT# BE25 AW29 SPKR
PCH_RTCRST# GPP_C2/SMBALERT# GPP_B14/SPKR H_CPUPWRGD SPKR <42>
SMBCLK BE26 AE3
GPP_C0/SMBCLK CPUPWRGD H_CPUPWRGD <8>
SMBDATA BF26
SML0ALERT# BF24 GPP_C1/SMBDATA AL3 PCH_ITP_PMODE
SML0_SMBCLK GPP_C5/SML0ALERT# ITP_PMODE PCH_JTAGX PCH_ITP_PMODE <20> CPU_XDP_TCK
BF25 AH4 RH38 1 @ 2
SML0_SMBDATA GPP_C3/SML0CLK PCH_JTAGX PCH_JTAG_TMS CPU_XDP_TCK <8,20>
BE24 AJ4 0_0402_5%
C GPP_C4/SML0DATA PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TMS <20> C
SML1ALERT# BD33 AH3
GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO PCH_JTAG_TDO <20>
1

D GPU_THM_SMBCLK BF27 AH2 PCH_JTAG_TDI

RTCRST_ON <23,44,45> GPU_THM_SMBCLK GPU_THM_SMBDAT GPP_C6/SML1CLK PCH_JTAG_TDI PCH_JTAG_TCK PCH_JTAG_TDI <20>
2 QH6 BE27 4 OF 13 AJ3
<44,47> RTCRST_ON <23,44,45> GPU_THM_SMBDAT GPP_C7/SML1DATA PCH_JTAG_TCK PCH_JTAG_TCK <20>
G 2N7002K_SOT23-3
1

S CNP-H_BGA874 Rev1.0
SB00000EN00
3

RH571 @
100K_0402_5% +3VS
2

1
RH180

+3VS 100K_0402_5%

2
PCH to DDR RH103 RH105

QH4A
<76> +VCCIO_PG
+VCCIO_PG 1
0_0402_5%
@ 2 1 @ 2 ALL_SYS_PWRGD
0_0402_5%
ALL_SYS_PWRGD <15,44,61> RTC Reset +3VALW_PCH
2

DMN65D8LDW-7_SOT363-6 +RTCVCC_PCH

SMBCLK 6 1 PCH_SMBCLK +3VS RH83 1 2 20K_0402_5% PCH_SRTCRST# RH66 1 @ 2 2.2K_0402_5% SMBALERT#

PCH_SMBCLK <20,21,22,38,39>
5

1
UH14 TLS CONFIDENTIALITY
SMBDATA 3 4 PCH_SMBDATA CH52

VCC
PCH_SMBDATA <20,21,22,38,39> IMVP_VR_PG 1
<71> IMVP_VR_PG 1U_0402_6.3V6K HIGH Enable

2
QH4B IN1 4 PCH_PWROK
DMN65D8LDW-7_SOT363-6 ALL_SYS_PWRGD 2 OUT LOW(DEFAULT) Disable

GND
<15,44,61> ALL_SYS_PWRGD IN2

1
RH94
MC74VHC1G08DFT2G_SC70-5 3 +RTCVCC_PCH
SA00000OH00 10K_0402_5%
RH84 1 2 20K_0402_5% PCH_RTCRST# +3VALW_PCH

2
B
Buffer with Open Drain Output For VTT power control B

1
CH53 CLRP1
+3VALW @ RH64 1 2 2.2K_0402_5% SML0ALERT#
+3VALW 1U_0402_6.3V6K SHORT PADS

2
CC298 2 1
0.1U_0402_16V7K EC interface
5

UC16 UZ21
1 5
HIGH ESPI*
VCC

NC VCC IMVP_VR_ON 1
VR_ON 2
<44> IMVP_VR_ON IN1 4 VR_ON LOW(DEFAULT) LPC
A H_VCCST_PWRGD SIO_SLP_S3# OUT VR_ON <71>
4 2
GND

Y H_VCCST_PWRGD <8,20> IN2

1

3
GND RZ71
74AUP1G07SE-7_SOT353 MC74VHC1G08DFT2G_SC70-5
3

100K_0402_5% +3VALW_PCH
SA00007WE00 SA00000OH00 Reserve for ESD
2

CH212 2 1 PCH_RSMRST#
ESD@ 100P_0402_50V8J RH65 1 2 150K_0402_5% SML1ALERT#

+3VS CH209 2 1 SYS_RESET#

GPU ID2 GPU ID1 @ESD@ 100P_0402_50V8J PCHHOT#
GPU ID
(GPP_D6) (GPP_D5) HIGH Enable
1

N/A 0 0 1
RH551 RH553 LOW(DEFAULT) Disable
@ @
Service Mode Switch: N17P-G0 0 1 10K_0402_5% 10K_0402_5%
Add a switch to ME_FWP signal to unlock the ME region and N17E-G1 1 0
2

GPU_ID1
allow the entire region of the SPI flash to be updated using FPT. GPU_ID2 +3VALW_PCH
N17P-G1 1 1
1

RH552 UMA@ RH551 N17P_G0@ RH552 N17E_G1@ RH551 N17P_G1@

RH552 RH554 Reserve for RF please close to UH1 RH82 1 @ 2 2.2K_0402_5% SPKR
A @ @ A
ME_FWP RH18 1 2 1K_0402_5% HDA_SDOUT 10K_0402_5% 10K_0402_5% CH51 1 2 HDA_SDOUT
<44> ME_FWP
@RF@ 10P_0402_25V8J Top Swap Override (internal PD)
2

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% HIGH ENABLE

ME_FWP PCH has internal 20K PD. LOW(DEFAULT) DISABLE
SD028100280 SD028100280 SD028100280 SD028100280
FLASH DESCRIPTOR SECURITY OVERRIDE RH554 UMA@ RH554 N17P_G0@ RH553 N17E_G1@ RH553 N17P_G1@
Disable ME Protect (ME can be updated) Security Classification Compal Secret Data Compal Electronics, Inc.
Enable ME Protect (ME cannot be updated)(Default position) 2011/08/25 2012/07/25 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/7) PM,HDA,SMB,JTAG
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
SD028100280 SD028100280 SD028100280 SD028100280 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 15 of 78
5 4 3 2 1
 5 4 3 2 1

CNP-H
UH2B @
DMI_CTX_PRX_N0 K34 J3 USB20_N1
<6> DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI0_RXN USB2N_1 USB20_P1 USB20_N1 <51>
J35 J2 Left USB Type-A
<6> DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 DMI0_RXP USB2P_1 USB20_N2 USB20_P1 <51>
C33 N13
<6> DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI0_TXN USB2N_2 USB20_P2 USB20_N2 <52>
B33 N15 Right USB Type-A
<6> DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 DMI0_TXP USB2P_2 USB20_N3 USB20_P2 <52>
G33 K4

Vinafix.com
<6> DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI1_RXN USB2N_3 USB20_P3 USB20_N3 <52>
F34 K3 Right USB Type-A
<6> DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 DMI1_RXP USB2P_3 USB20_P3 <52>
C32 M10
<6> DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI1_TXN USB2N_4
B32 L9
<6> DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI1_TXP USB2P_4 USB20_N5
K32 M1
D <6> DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI2_RXN USB2N_5 USB20_P5 USB20_N5 <35> D
J32 L2 Camera
<6> DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI2_RXP USB2P_5 USB20_N6 USB20_P5 <35>
C31 K7
<6> DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI2_TXN USB2N_6 USB20_P6 USB20_N6 <53>
B31 K6 Card Reader
<6> DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 DMI2_TXP USB2P_6 USB20_N7 USB20_P6 <53>
G30 L4
<6> DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI3_RXN USB2N_7 USB20_P7 USB20_N7 <41>
F30 L3 M.2-WLAN
<6> DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI3_RXP USB2P_7 USB20_N8 USB20_P7 <41>
C29 G4
<6> DMI_CRX_PTX_N3 DMI_CRX_PTX_P3 DMI3_TXN USB2N_8 USB20_P8 USB20_N8 <35>
B29 G5 Touch Screen
<6> DMI_CRX_PTX_P3 DMI3_TXP USB2P_8 USB20_N9 USB20_P8 <35> +3VALW_PCH
A25 M6
B25 DMI7_TXP USB2N_9 N8 USB20_P9 USB20_N9 <48> RP16
P24 DMI7_TXN USB2P_9 H3 USB20_P9 <48> Finger Print USB_OC0# 4 5
R24 DMI7_RXP USB2N_10 H2 USB_OC1# 3 6
C26 DMI7_RXN USB2P_10 R10 USB_OC3# 2 7
B26 DMI6_TXP USB2N_11 P9 USB_OC2# 1 8
F26 DMI6_TXN USB2P_11 G1
G26 DMI6_RXP USB2N_12 G2 10K_0804_8P4R_5%
B27 DMI6_RXN USB2P_12 N3
C27 DMI5_TXP USB2N_13 N2
L26 DMI5_TXN USB2P_13 E5
M26 DMI5_RXP USB2N_14 F6 +3VALW_PCH
D29 DMI5_RXN USB2P_14 RP8
E28 DMI4_TXP AH36 USB_OC0# USB_OC6# 4 5
K29 DMI4_TXN GPP_E9/USB2_OC0# AL40 USB_OC1# USB_OC0# <51> USB_OC7# 3 6
M29 DMI4_RXP GPP_E10/USB2_OC1# AJ44 USB_OC2# USB_OC1# <52> USB_OC5# 2 7
DMI4_RXN GPP_E11/USB2_OC2# AL41 USB_OC3# USB_OC4# 1 8
G17 GPP_E12/USB2_OC3# AV47 USB_OC4#
F16 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# AR35 USB_OC5# 10K_0804_8P4R_5%
A17 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR37 USB_OC6#
B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43 USB_OC7#
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
P21 PCIE2_RXN/USB31_8_RXN F4 USB2_COMP RH109 1 2 113_0402_1%
B18 PCIE2_RXP/USB31_8_RXP USB2_COMP F3 USB2_VBUSSENSE RH112 1 2 1K_0402_5%
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13
PCIE2_TXP/USB31_8_TXP RSVD1 +3VALW_PCH
C K18 G3 USB2_ID RH113 1 2 1K_0402_5% C
J18 PCIE3_RXN/USB31_9_RXN USB2_ID
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7
PCIE3_TXN/USB31_9_TXN GPD7

1
C19
N18 PCIE3_TXP/USB31_9_TXP G45 PCIE_PTX_TRX_P24 RH12
PCIE4_RXN/USB31_10_RXN PCIE24_TXP PCIE_PTX_TRX_N24 PCIE_PTX_TRX_P24 <36>
R18 G46
PCIE4_RXP/USB31_10_RXP PCIE24_TXN PCIE_PRX_TTX_P24 PCIE_PTX_TRX_N24 <36>
D20 Y41 100K_0402_5%
PCIE4_TXN/USB31_10_TXN PCIE24_RXP PCIE_PRX_TTX_N24 PCIE_PRX_TTX_P24 <36>
C20 Y40
PCIE_PRX_TTX_N24 <36>

2
F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48 PCIE_PTX_TRX_P23 GPD_7
PCIE5_RXN PCIE23_TXP PCIE_PTX_TRX_N23 PCIE_PTX_TRX_P23 <36> STRAP
G20 G49
PCIE5_RXP PCIE23_TXN PCIE_PRX_TTX_P23 PCIE_PTX_TRX_N23 <36>
B21 W44
PCIE5_TXN PCIE23_RXP PCIE_PRX_TTX_P23 <36>

1
A22 W43 PCIE_PRX_TTX_N23
K21 PCIE5_TXP PCIE23_RXN H48 PCIE_PTX_TRX_P22 PCIE_PRX_TTX_N23 <36> TBT-AR RH584
PCIE6_RXN PCIE22_TXP PCIE_PTX_TRX_N22 PCIE_PTX_TRX_P22 <36>
J21 H47 @
PCIE6_RXP PCIE22_TXN PCIE_PRX_TTX_P22 PCIE_PTX_TRX_N22 <36>
D21 U41 10K_0402_5%
PCIE6_TXN PCIE22_RXP PCIE_PRX_TTX_N22 PCIE_PRX_TTX_P22 <36>
C21 U40
PCIE_PRX_TTX_N22 <36>

2
B23 PCIE6_TXP PCIE22_RXN F46 PCIE_PTX_TRX_P21
PCIE7_TXP PCIE21_TXP PCIE_PTX_TRX_N21 PCIE_PTX_TRX_P21 <36>
C23 G47 X'tal Input:
PCIE7_TXN PCIE21_TXN PCIE_PRX_TTX_P21 PCIE_PTX_TRX_N21 <36> High: Differential
J24 R44
PCIE7_RXP PCIE21_RXP PCIE_PRX_TTX_N21 PCIE_PRX_TTX_P21 <36> Low: Single ended
L24 T43
PCIE7_RXN PCIE21_RXN PCIE_PRX_TTX_N21 <36>
F24
G24 PCIE8_RXN
PCIE8_RXP 6/18:
B24 GPD_7 is DSW rail
C24 PCIE8_TXN 2 OF 13
PCIE8_TXP
CNP-H_BGA874 Rev1.0

CNP-H
UH2F @
USB3_PTX_DRX_N1 F9 BB39 ESPI_IO0_R RH574 1 2 15_0402_5%
<51> USB3_PTX_DRX_N1 USB3_PTX_DRX_P1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 ESPI_IO1_R ESPI_IO0 <44>
F7 AW37 RH575 1 2 15_0402_5%
B <51> USB3_PTX_DRX_P1 USB3_PRX_DTX_N1 USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 ESPI_IO2_R ESPI_IO1 <44> B
Left USB Type-A D11 AV37 RH576 1 2 15_0402_5%
<51> USB3_PRX_DTX_N1 USB3_PRX_DTX_P1 USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 ESPI_IO3_R ESPI_IO2 <44>
C11 BA38 RH577 1 2 15_0402_5%
<51> USB3_PRX_DTX_P1 USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 <44>
USB3_PTX_DRX_N2 C3 +1.8V_PRIM
<52> USB3_PTX_DRX_N2 USB3_PTX_DRX_P2 USB31_2_TXN ESPI_CS#
D4 BE38
Right USB Type-A <52> USB3_PTX_DRX_P2 USB3_PRX_DTX_N2 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# ESPI_ALERT# ESPI_CS# <44>
B9 AW35 PIRQA# RH546 1 2 10K_0402_5%
<52> USB3_PRX_DTX_N2 USB3_PRX_DTX_P2 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# ESPI_ALERT# <44>
C9 BA36 PIRQA#
<52> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# ESPI_ALERT#
BE39 RH578 1 2 8.2K_0402_5%
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RESET#
USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <44>
C16
G14 USB31_6_TXP BB36 ESPI_CLK_R RH168 1 EMI@ 2 ESPI_CLK ESPI_RESET# RH611 1 2 100K_0402_5%
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK ESPI_CLK <44>
F14 BB34 33_0402_5%
C15 USB31_6_RXP GPP_A10/CLKOUT_LPC1
B15 USB31_5_TXN T48
J13 USB31_5_TXP GPP_K19/SMI# T47
K13 USB31_5_RXN GPP_K18/NMI#
USB31_5_RXP
USB3_PTX_DRX_P3 G12 AH40
<52> USB3_PTX_DRX_P3 USB3_PTX_DRX_N3 USB31_3_TXP GPP_E6/SATA_DEVSLP2 mSATA_DEVSLP
F11 AH35
<52> USB3_PTX_DRX_N3 USB3_PRX_DTX_P3 USB31_3_TXN GPP_E5/SATA_DEVSLP1 HDD_DEVSLP mSATA_DEVSLP <39>
Right USB Type-A C10 AL48
<52> USB3_PRX_DTX_P3 USB3_PRX_DTX_N3 USB31_3_RXP GPP_E4/SATA_DEVSLP0 HDD_DEVSLP <39>
B10 AP47
<52> USB3_PRX_DTX_N3 USB31_3_RXN GPP_F9/SATA_DEVSLP7 AN37
C14 GPP_F8/SATA_DEVSLP6 AN46
B14 USB31_4_TXP GPP_F7/SATA_DEVSLP5 AR47
J15 USB31_4_TXN GPP_F6/SATA_DEVSLP4 AP48
K16 USB31_4_RXP 6 OF 13GPP_F5/SATA_DEVSLP3
USB31_4_RXN
CNP-H_BGA874 Rev1.0

Reserve for EMI

ESPI_CLK CC4 2 1
A @EMI@ 12P_0402_50V8J A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/7) DMI,PCIE,USB,ESPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 16 of 78
5 4 3 2 1
 5 4 3 2 1

DVT1.
+3VS Un-pop RH159. CNP-H
UH2K @
RH10 1 2 10K_0402_5% SIO_EXT_SCI#
RH159 1 @ 2 49.9K_0402_1% UART_2_CTXD_DRXD BBS_BIT0 BA26 BA20
RH160 1 2 49.9K_0402_1% UART_2_CRXD_DTXD BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20 DGPU_HOLD_RST#
I2C_1_SCL SIO_EXT_SCI# GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK WLAN_WIGIG60GHZ_DIS# DGPU_HOLD_RST# <23>
RH119 1 2 2.2K_0402_5% AU26 BB16
I2C_1_SDA FFS_INT1 GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO DGPU_PWR_EN WLAN_WIGIG60GHZ_DIS# <41>
RH120 1 2 2.2K_0402_5% AW26 AN18
GPU_GC6_FB_EN_H <39> FFS_INT1 GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI DGPU_PWR_EN <31>
RH545 1 2 100K_0402_5%
NRB_BIT BE30 BF14 +3VS

Vinafix.com
<23> GPU_GC6_FB_EN_H
GPU_GC6_FB_EN_H
GPU_EVENT#
BD29
BF29
BB26
GPP_B18/GSPI0_MOSI
GPP_B17/GSPI0_MISO
GPP_B16/GSPI0_CLK
GPP_D16/ISH_UART0_CTS#/CNV_WCEN
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
GPP_D14/ISH_UART0_TXD/I2C2_SCL
AR18
BF17
BE17 DGPU_PWR_EN RH129 1 2 10K_0402_5%
+3VALW_PCH <23> GPU_EVENT# GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
D BB24 D
RH91 1 2 10K_0402_5% SIO_EXT_WAKE# BE23 GPP_C9/UART0A_TXD
RZ96 1 2 100K_0402_5% IR_CAM_DET# AP24 GPP_C8/UART0A_RXD
BT_RADIO_DIS# BA24 GPP_C11/UART0A_CTS#
<41> BT_RADIO_DIS# GPP_C10/UART0A_RTS# AG45
BD21 GPP_H20/ISH_I2C0_SCL AH46
HDMI_HPD_PCH AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
HDMI_HPD_PCH <33> HDMI_HPD_PCH PHASE_ID2 GPP_C14/UART1_RTS#/ISH_UART1_RTS#
RH567 1 2 100K_0402_5% AP21 AH47
PHASE_ID1 AU24 GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL AH48
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA +1.8V_PRIM
IR_CAM_DET# AV21
GPU HDMI HPD. <44> SIO_EXT_WAKE#
SIO_EXT_WAKE# AW21 GPP_C23/UART2_CTS#
GPP_C22/UART2_RTS#
KB_DET# RH128 1 2 10K_0402_5%
UART_2_CTXD_DRXD BE20 AV34
<41> UART_2_CTXD_DRXD UART_2_CRXD_DTXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5
BD20 AW32
<41> UART_2_CRXD_DTXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33
I2C_1_SCL BE21 GPP_A21/ISH_GP3 BE34 KB_DET#
<47> I2C_1_SCL I2C_1_SDA GPP_C19/I2C1_SCL GPP_A20/ISH_GP2 KB_DET# <46>
TP BF21 BD34
<47> I2C_1_SDA BC22 GPP_C18/I2C1_SDA GPP_A19/ISH_GP1 BF35
BF23 GPP_C17/I2C0_SCL GPP_A18/ISH_GP0 BD38
GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BE15
BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
11 OF 13
GPP_D23/ISH_I2C2_SCL/I2C3_SCL
CNP-H_BGA874 Rev1.0

PCH Strap PIN

+3VS
CNP-H
C UH2E @ CPU_DP1_CTRL_DATA RH580 1 2 C
AL13 2.2K_0402_5%
GPP_I5/DDPB_CTRLCLK AR8 CPU_DP1_CTRL_DATA
CPU_DP1_HPD AT6 GPP_I6/DDPB_CTRLDATA AN13 CPU_DP2_CTRL_DATA RH579 1 2
<36> CPU_DP1_HPD CPU_DP2_HPD GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK CPU_DP2_CTRL_DATA
AN10 AL10 2.2K_0402_5%
<36> CPU_DP2_HPD GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA
AP9 AL9
AL15 GPP_I2/DPPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3
GPP_I3/DPPE_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA AN40 T2 PAD@
GPP_F23/DDPF_CTRLDATA AT49
GPP_F22/DDPF_CTRLCLK
AP41 PROC_DETECT#
EDP_HPD GPP_F14/PS_ON# PROC_DETECT# <8>
AN6
<35> EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
M45
GPP_K23/IMGCLKOUT1 L48
GPP_K22/IMGCLKOUT0 T45
GPP_K21 T46
5 OF 13 GPP_K20 AJ47
GPP_H23/TIME_SYNC0
CNP-H_BGA874 Rev1.0
RV551 2 1 EDP_HPD
100K_0402_5%

RH548 EVT@ RH550 EVT@

B +3VS B

10K_0402_5% 10K_0402_5%
1

RH547 RH549 SD028100280 SD028100280

@ @
10K_0402_5% 10K_0402_5%
RH547 DVT1@ RH550 DVT1@
2

PHASE_ID1
PHASE_ID2
1

10K_0402_5% 10K_0402_5%
RH548 RH550
@ @ SD028100280 SD028100280
10K_0402_5% 10K_0402_5%
2

RH548 DVT2@ RH549 DVT2@

+3VALW_PCH +3VALW_PCH
10K_0402_5% 10K_0402_5%
RH130 1 @ 2 2.2K_0402_5% BBS_BIT0 RH92 1 @ 2 2.2K_0402_5% NRB_BIT

PHASE ID2 PHASE ID1 SD028100280 SD028100280

PHASE ID
(GPP_C13) (GPP_C12) RH547 PILOT@ RH549 PILOT@ Boot BIOS Strap Bit (internal PD) NO REBOOT mode (internal PD)
A EVT 0 0 HIGH LPC HIGH ENABLE A

DVT1 0 1 LOW(DEFAULT) SPI LOW(DEFAULT) DISABLE

DVT2 1 0 10K_0402_5% 10K_0402_5%
Pilot 1 1 SD028100280 SD028100280
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/7) I2C,GPIO,DDC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 17 of 78
5 4 3 2 1
 5 4 3 2 1

GPIO Group Voltage

GPPA eSPI: 1.8V
+1P05VALW +1P05V_VCCUSB +1P05VALW CNP-H +3VALW_PCH GPPB
UH2H @ +DCPRTC GPPC 3.3V
RH123 1 @ 2 4.174A AA22 AW9 0.318A+0.582A(CNVi)
AA23 VCCPRIM_1P051 VCCPRIM_3P32 GPPD 3.3V
0_0402_5% +1P05V_VCCPRIM_MPHY AB20 VCCPRIM_1P052 BF47
GPPE
RH597 1 @ 2 Vinafix.com AB22
AB23
VCCPRIM_1P053
VCCPRIM_1P054
VCCPRIM_1P055
DCPRTC1
DCPRTC2
BG47 +3VALW_PCH

+3V_PCH_SPI +3VALW_PCH
GPPF 3.3V
AB27 V23
0_0402_5% +1P05V_VCCAMPHYPLL AB28 VCCPRIM_1P056 VCCPRIM_3P35 GPPG 3.3V
D D
AB30 VCCPRIM_1P057 AN44 0.042A +RTCVCC_PCH +RTCVCC RH604 1 @ 2
RH598 1 @ 2 AD20 VCCPRIM_1P058 VCCSPI GPPH
AD23 VCCPRIM_1P059 BC49 1
RH615 2 0_0402_5%
GPPK 3.3V
0_0402_5% +1P05V_SRC AD27 VCCPRIM_1P0510 VCCRTC1 BD49 0.00031A 0_0402_5%
AD28 VCCPRIM_1P0511 VCCRTC2 +3VALW_PCH GEN8@ GPPI 3.3V Only
RH600 1 @ 2 AD30 VCCPRIM_1P0512 AN21 0.145A for VCCGPPG
AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8
GPPJ 1.8V Only
0_0402_5% +1P05V_VCCAPLL AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7 +3VALW_PCH
RF@ AF30 VCCPRIM_1P0517 VCCPRIM_3P34
LH2 1 2 VCCPRIM_1P0518 AC35 0.219A +3VALW_PCH
BLM15BD601SN1D_2P U26 VCCPGPPHK1 AC36
+1P05V_BCLK U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35 0.145A
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36 +3VALW_PCH
RH602 1 @ 2 V27 VCCPRIM_1P0525 VCCPGPPEF2 +3VALW_PCH
V28 VCCPRIM_1P0526 AN24 0.117A
0_0402_5% +1P05V_XTAL V30 VCCPRIM_1P0527 VCCPGPPD AN26 0.286A
V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 +1.8V_PRIM
RH607 2 @ 1 VCCPRIM_1P0529 VCCPGPPBC2 eSPI need use +1.8V_PRIM
AD31 AN32 0.085A +3VALW_PCH
0_0402_5% VCCPRIM_1P0514 VCCPGPPA +3V_PCH_DSW +3VALW_PCH
+1P05V_VCCUSB AE17 AT44
+3VALW_PCH +3V_HDA VCCPRIM_1P0515 VCCPRIM_3P31 BE48 0.094A +3V_PCH_DSW RH605 1 @ 2
0.33A W22 VCCDSW_3P31 BE49 +3V_HDA
LH1 1 2 W23 VCCDUSB_1P051 VCCDSW_3P32 +1.8V_PRIM 0_0402_5%
BLM15PX221SN1D_2P +1P05V_VCCDSW VCCDUSB_1P052 BB14 0.007A
+1P05V_VCCPRIM_MPHY 0.01A BG45 VCCHDA AG19 0.152A+0.582A(CNVi)
BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20
0.088A W31 VCCDSW_1P052 VCCPRIM_1P84 AN15
C +1P05VALW VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15 C
D1 VCCPRIM_1P86 BB11 +1.8V_PRIM +1P24V_VCCDPHY +1P24V_VCCLDOSRAM_IN
E1 VCCPRIM_1P0521 VCCPRIM_1P87
+1P05V_VCCAMPHYPLL C49 VCCPRIM_1P0522 AF19 0.882A +1.8V_PRIM_LDO RH606 1 @ 2 RH124 2 @ 1
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20 0_0402_5% 0_0603_5%
0.114A E49 VCCAMPHYPLL_1P052 VCCPRIM_1P82 +1P05VALW
+1P05V_XTAL VCCAMPHYPLL_1P053 AG31
P2 VCCPRIM_1P0520 AF31 +1P24V_VCCLDOSRAM_IN
+1P05V_SRC 0.005A P3 VCCA_XTAL_1P051 VCCPRIM_1P0519 AK22
W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23
0.141A W20 VCCA_SRC_1P051 VCCPRIM_1P242 +1P24V_VCCDPHY
+1P05V_VCCAPLL VCCA_SRC_1P052 AJ22 +1P24V_VCCDPHY_CAP
+1P05V_BCLK C1 VCCDPHY_1P241 AJ23
0.034A C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5
0.007A V19 VCCAPLL_1P055 VCCDPHY_1P243
VCCA_BCLK_1P05 K47 1P05V_VCCMPHY_SENSE T4945 PAD @
+1P05V_VCCAPLL B1 VCCMPHY_SENSE K46 1P05V_VSSMPHY_SENSE T4946 PAD @
B2 VCCAPLL_1P051 VSSMPHY_SENSE
B3 VCCAPLL_1P052 8 OF 13
VCCAPLL_1P053
CNP-H_BGA874 Rev1.0

+1P05V_VCCAPLL +1P05VALW +1P05V_VCCAMPHYPLL +1P05VALW +1P05VALW +1.8V_PRIM +RTCVCC_PCH +1P24V_VCCDPHY_CAP

CH221 1 CH230 1 CH177 1 CH180 1 CH222 1 CH223 1 CH224 1 CH225 1 CH80 1 CH173 1 CH220 1
B RF@ B
1U_0402_6.3V6K

0.5P_0402_50V8

22U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M

1U_0402_6.3V6K

4.7U_0402_6.3V6M
2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V6K
External Pin Name Cap Number
edge cap-5mm edge cap-3mm edge cap-3mm edge cap-3mm edge cap-3mm edge cap-3mm
VCCAPLL_1P05 1uF 0402 x1 close B1/B2/B3/C1/C2 close U26/U29 close C49/D49/E49 close AF31/AG31 close AD31/AA22/AA23 close AG19/AG20 edge cap-3mm edge cap-5mm
0.5P 0402 x1 V25/V27/V28/V30/V31 /AR15/AN15/BB11 close BC49/BD49 close BG5
VCCPRIM_1P05 22 uF 0603 x1
1u 0402 x3
+1P05V_XTAL +1P05V_VCCAMPHYPLL +3VALW_PCH +3VALW_PCH +3VALW_PCH +3V_PCH_DSW +1P05V_VCCDSW +DCPRTC +3V_HDA
VCCA_XTAL_1P05 47 uF 0805 x1
VCCAMPHYPLL_1P05 47 uF 0805 x1 CH226 CH227 CH200 CH70 CH188 CH203 CH228 CH229
1uF 0402 x1 1 1 1 1 1 1 1 1
@ @ CH231 1
VCCDSW_1P05 1uF 0402 x1 (@)
47U_0805_6.3V6M

47U_0805_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

1U_0402_6.3V6K

0.1U_0402_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
RF@
2 2 2 2 2 2 2 2

0.5P_0402_50V8
VCCPRIM_1P8 4.7 uF 0402 x1 2
VCCPGPPA
VCCPGPPBC 1uF 0402 x1
VCCPGPPD 0.1uF 0402 x2
A VCCPGPPEF A
VCCPGPPHK
VCCPSPI Back cap-3mm Back cap-3mm Back cap-3mm Back cap-3mm Back cap-3mm Back cap-3mm edge cap-5mm edge cap-5mm close BB14
VCCPRIM_3P3 close P2/P3 close C49/D49/E49 close AE35/AE36 close AC35/AC36 close AY8/BB7 close BE48/BE49 close BG45 close BG47
VCCPDSW_3P3 0.1uF 0402 x1
VCCHDA 0.5P 0402 x1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title
VCCRTC 1uF 0402 x1 PCH (6/7) PWR
0.1uF 0402 x1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
VCCDPHY_1P24 4.7 uF 0402 x1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 18 of 78
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

CNP-H CNP-H CNP-H

UH2I @ UH2L @ UH2J @
A2 AL12 Y14
A28 VSS VSS AL17 BG3 M24 RSVD7 Y15
A3 VSS VSS AL21 BG33 VSS VSS M32 RSVD8 U37
A33 VSS VSS AL24 BG37 VSS VSS M34 RSVD6 U35
A37 VSS VSS AL26 BG4 VSS VSS M49 RSVD5
A4 VSS VSS AL29 BG48 VSS VSS M5 N32
A45 VSS VSS AL33 C12 VSS VSS N12 RSVD3 R32
A46 VSS VSS AL38 C25 VSS VSS N16 RSVD4
A47 VSS VSS AM1 C30 VSS VSS N34 AH15
A48 VSS VSS AM18 C4 VSS VSS N35 RSVD2 AH14
A5 VSS VSS AM32 C48 VSS VSS N37 RSVD1
A8 VSS VSS AM49 C5 VSS VSS N38
AA19 VSS VSS AN12 D12 VSS VSS P26
AA20 VSS VSS AN16 D16 VSS VSS P29 AL2 XDP_PREQ#
VSS VSS VSS VSS PREQ# XDP_PRDY# XDP_PREQ# <8,20>
AA25 AN34 D17 P4 AM5
VSS VSS VSS VSS PRDY# CPU_XDP_TRST# XDP_PRDY# <8,20>
AA27 AN38 D30 P46 AM4
VSS VSS VSS VSS CPU_TRST# PCH_TRIGGER CPU_XDP_TRST# <8,20>
AA28 AP4 D33 R12 AK3
VSS VSS VSS VSS TRIGGER_OUT CPU_TRIGGER PCH_TRIGGER <8>
AA30 AP46 D8 R16 AK2
VSS VSS VSS VSS TRIGGER_IN CPU_TRIGGER <8>
AA31 AR12 E10 R26
AA49 VSS VSS AR16 E13 VSS VSS R29 10 OF 13
AA5 VSS VSS AR34 E15 VSS VSS R3 CNP-H_BGA874 Rev1.0
C AB19 VSS VSS AR38 E17 VSS VSS R34 C
AB25 VSS VSS AT1 E19 VSS VSS R38
AB31 VSS VSS AT16 E22 VSS VSS R4
AC12 VSS VSS AT18 E24 VSS VSS T17
AC17 VSS VSS AT21 E26 VSS VSS T18
AC33 VSS VSS AT24 E31 VSS VSS T32
AC38 VSS VSS AT26 E33 VSS VSS T4
AC4 VSS VSS AT29 E35 VSS VSS T49
AC46 VSS VSS AT32 E40 VSS VSS T5
AD1 VSS VSS AT34 E42 VSS VSS T7
AD19 VSS VSS AT45 E8 VSS VSS U12
AD2 VSS VSS AV11 F41 VSS VSS U15
AD22 VSS VSS AV39 F43 VSS VSS U17
AD25 VSS VSS AW10 F47 VSS VSS U21
AD49 VSS VSS AW4 G44 VSS VSS U24
AE12 VSS VSS AW40 G6 VSS VSS U33
AE33 VSS VSS AW46 H8 VSS VSS U38
AE38 VSS VSS B47 J10 VSS VSS V20
AE4 VSS VSS B48 J26 VSS VSS V22
AE46 VSS VSS B49 J29 VSS VSS V4
AF22 VSS VSS BA12 J4 VSS VSS V46
AF25 VSS VSS BA14 J40 VSS VSS W25
AF28 VSS VSS BA44 J46 VSS VSS W27
AG1 VSS VSS BA5 J47 VSS VSS W28
AG22 VSS VSS BA6 J48 VSS VSS W30
AG23 VSS VSS BB41 J9 VSS VSS Y10
AG25 VSS VSS BB43 K11 VSS VSS Y12
AG27 VSS VSS BB9 K39 VSS VSS Y17
AG28 VSS VSS BC10 M16 VSS VSS Y33
B AG30 VSS VSS BC13 M18 VSS VSS Y38 B
AG49 VSS VSS BC15 M21 VSS 12 OF 13 VSS Y9
AH12 VSS VSS BC19 VSS VSS
AH17 VSS VSS BC24 CNP-H_BGA874 Rev1.0
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
AJ27 VSS VSS BC8
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 19 of 78
5 4 3 2 1
 5 4 3 2 1

<8> CFG[0..19]

+VCCSTG

RH497 1 2 51_0402_5% CPU_XDP_TDO

Vinafix.com +1P05VALW +1P05V_XDP +1P05V_XDP +1P05V_XDP

RH496 1 2 51_0402_5% CPU_XDP_TMS RH614 1 @ 2 0_0402_5% 1

D CH205 0_0402_5% 2 XDP@ 1 RH522 D
CPU_XDP_TDI PCH_ITP_PMODE <15>
RH56 1 2 51_0402_5% XDP@
JXDP1 0.1U_0402_10V7K XDP_PLTRST# 1K_0402_5% 2 @ 1 RH523
2 PLTRST_CPU# <8,13>
CFG3 RH517 2 XDP@ 1 1K_0402_5% 1 2
RH95 1 @ 2 51_0402_5% PCH_JTAG_TCK XDP_PREQ# 3 1 2 4 CFG17 0_0402_5% 2 @ 1 RH524
<8,19> XDP_PREQ# XDP_PRDY# 3 4 SYS_PWROK <15,44>
5 6 CFG16
CPU_XDP_TCK <8,19> XDP_PRDY# 5 6 PCH_SYS_PWROK_XDP
RH61 1 2 51_0402_5% 7 8 1K_0402_5% 2 XDP@ 1 RH525
7 8 PCH_SPI_0_SI <14,45>
CFG0 9 10 CFG8
RH60 1 @ 2 51_0402_5% CPU_XDP_TRST# CFG1 11 9 10 12 CFG9 1K_0402_5% 2 XDP@ 1 RH541
11 12 PCH_RSMRST# <15,44>
13 14
CFG2 15 13 14 16 CFG10 XDP_PWRGOOD 1K_0402_5% 2 @ 1 RH542
15 16 H_VCCST_PWRGD <8,15>
CFG3 17 18 CFG11
19 17 18 20
+1P05V_XDP XDP_BPM#0 21 19 20 22 CFG19
<8> XDP_BPM#0 XDP_BPM#1 23 21 22 24 CFG18
RH520 1 2 2.2K_0402_5% XDP_PLTRST# <8> XDP_BPM#1 25 23 24 26
CFG4 27 25 26 28 CFG12
CFG5 29 27 28 30 CFG13
+VCCST 31 29 30 32
CFG6 33 31 32 34 CFG14
RH97 1 @ 2 51_0402_5% PCH_JTAG_TDO CFG7 35 33 34 36 CFG15
37 35 36 38
RH98 1 @ 2 51_0402_5% PCH_JTAG_TMS XDP_PWRGOOD 39 37 38 40 PCH_XDP_CLK_P
PWRBTN#_XDP 41 39 40 42 PCH_XDP_CLK_N PCH_XDP_CLK_P <14> Pin XDP Signal Name Target Signal I/O Device
PCH_JTAG_TDI 41 42 PCH_XDP_CLK_N <14>
RH100 1 @ 2 51_0402_5% 43 44 2 GND GND NA
PWR_DEBUG#_XDP 45 43 44 46 XDP_PLTRST#
PCH_SYS_PWROK_XDP 47 45 46 48 XDP_DBRESET#
+3VALW_PCH 49 47 48 50
4 OBSFN_C0 CFG(17) I Coffee Lake
PCH_SMBDATA 51 49 50 52 PCH_JTAG_TDO
C RH521 1 2 2.2K_0402_5% PCH_SYS_PWROK_XDP <15,21,22,38,39> PCH_SMBDATA PCH_SMBCLK 53 51 52 54 XDP_TRST# PCH_JTAG_TDO <15> 6 OBSFN_C1 CFG(16) I Coffee Lake C
<15,21,22,38,39> PCH_SMBCLK PCH_JTAG_TCK 53 54 PCH_JTAG_TDI
55 56
<15> PCH_JTAG_TCK CPU_XDP_TCK 57 55 56 58 PCH_JTAG_TMS PCH_JTAG_TDI <15> 8 GND GND NA
<8,15> CPU_XDP_TCK 57 58 XDP_PRESENT# PCH_JTAG_TMS <15>
59 60
59 60 10 OBSDATA_C0 CFG[8] I/O Coffee Lake

1
Pin XDP Signal Name Target Signal I/O Device RH518
@
CONN@
SAMTE_BSH-030-01-L-D-A-TR
PCH 12 OBSDATA_C1 CFG[9] I/O Coffee Lake
1 XDP Pin#1 Refer NA Coffee Lake 0_0402_5% SAMTE_BSH-030-01-LDA-TR_60P-NPM 14 GND GND NA
XDP_PRESENT# SP02000L900

2
routing guidelines 16 OBSDATA_C2 CFG[10] I/O Coffee Lake
3 OBSFN_A0 PROC_PREQ# O Coffee Lake 18 OBSDATA_C3 CFG[11] I/O Coffee Lake
5 OBSFN_A1 PROC_PRDY# I Coffee Lake 20 GND GND NA
7 GND GND NA 22 OBSFN_D0 CFG(19) I Coffee Lake
9 OBSDATA_A0 CFG[0] I/O Coffee Lake 24 OBSFN_D1 CFG(18) I Coffee Lake
11 OBSDATA_A1 CFG[1] I/O Coffee Lake
CPU 26 GND GND NA
PCH_JTAG_TDO RH533 1 @ 2 0_0402_5%
CPU_XDP_TDO <8>
13 GND GND NA PCH_JTAG_TDI RH534 1 @ 2 0_0402_5%
28 OBSDATA_D0 CFG[12] I/O Coffee Lake
CPU_XDP_TDI <8>
15 OBSDATA_A2 CFG[2] I/O Coffee Lake PCH_JTAG_TMS RH535 1 @ 2 0_0402_5%
30 OBSDATA_D1 CFG[13] I/O Coffee Lake
CPU_XDP_TMS <8>
17 OBSDATA_A3 CFG[3] I/O Coffee Lake XDP_TRST# RH536 1 @ 2 0_0402_5%
32 GND GND NA
CPU_XDP_TRST# <8,19>
19 GND GND NA 34 OBSDATA_D2 CFG[14] I/O Coffee Lake
B B
21 OBSFN_B0 BPM#[0] I/O Coffee Lake 36 OBSDATA_D3 CFG[15] I/O Coffee Lake
23 OBSFN_B1 BPM#[1] I/O Coffee Lake 38 GND GND NA
25 GND GND NA 40 ITPCLK/HOOK4 CLKOUT_ITPXDP_P I Coffee Lake
+VCCIO
27 OBSDATA_B0 CFG[4] I/O Coffee Lake 42 ITPCLK#/HOOK5 CLKOUT_ITPXDP_N I Coffee Lake
RH526 1 @ 2 150_0402_5% PWR_DEBUG#_XDP RH528 1 2 1K_0402_5% CFG0
29 OBSDATA_B1 CFG[5] I/O Coffee Lake 44 VCC_OBS_AB PCH V1.0A NA
31 GND GND NA 46 HOOK6/RESET# ITP_PMODE I Coffee Lake
+3VALW_PCH
33 OBSDATA_B2 CFG[6] I/O Coffee Lake 48 HOOK7/DBR# SYS_RESET# O Coffee Lake
RH540 1 XDP@ 2 1K_0402_5% XDP_PRESENT# RH519 1 XDP@ 2 1K_0402_5%
35 OBSDATA_B3 CFG[7] I/O Coffee Lake PCH_SPI_0_WP# <14> 50 GND GND NA
RH529 1 XDP@ 2 1K_0402_5% PWRBTN#_XDP RH530 1 XDP@ 2 0_0402_5%
37 GND GND NA SIO_PWRBTN# <15,44> 52 XDP_TDO PROC_TDO I Coffee Lake
+3VS PCH_JTAG_TDO
39 HOOK0 RSMRST# I Coffee Lake
RH531 1 2 1K_0402_5% XDP_DBRESET# RH532 1 @ 2 0_0402_5%
54 XDP_TRSTn PROC_TRST# O Coffee Lake
41 HOOK1 PWRBTN# O Coffee Lake SYS_RESET# <15> PCH_TRST#
43 VCC_OBS_AB PCH V1.0A NA CH206
1 1
CH207
56 XDP_TDI PROC_TDI O Coffee Lake
@ XDP@ PCH_JTAG_TDI
45 HOOK2 Open NA 0.1U_0402_10V7K 0.1U_0402_10V7K
2 2 58 XDP_TMS PROC_TMS O Coffee Lake
47 HOOK3 SPIO_MOSI O Coffee Lake PCH_JTAG_TMS
A 49 GND GND NA 60 GND Refer NA system A
(XDP_PRESENT#) XDP_PRESENT#
51 XDP_SDA SDA I/O system routing guidelines
53 XDP_SCL SCL I/O system
55 XDP_TCK1 PCH_JTAG_TCK O Coffee Lake Security Classification Compal Secret Data Compal Electronics, Inc.
57 XDP_TCK0 PROC_TCK O Coffee Lake Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title
JTAGX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
XDP CONN
59 GND GND NA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 20 of 78
5 4 3 2 1
 5 4 3 2 1

<7> DDR_A_D[0..63]
<7> DDR_A_MA[0..13] +1.2V_DDR +1.2V_DDR
<7> DDR_A_DQS#[0..7] JDIMM1
<7> DDR_A_DQS[0..7]
1 2
DDR_A_D4 3 VSS1 VSS2 4 DDR_A_D1
5 DQ5 DQ4 6
DDR_A_D0 7 VSS3 VSS4 8 DDR_A_D5
9 DQ1 DQ0 10
Layout Note: Layout Note: Layout Note: DDR_A_DQS#0 VSS5 VSS6
11 12
Place near JDIMM1.257,259 Place near JDIMM1.258 Place near JDIMM1.255
Vinafix.com DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_A_D6
DDR_A_D7 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_A_D2
DDR_A_D3 21 VSS10 DQ2 22
D 23 DQ3 VSS11 24 DDR_A_D9 D
DDR_A_D13 25 VSS12 DQ12 26
+2.5V_MEM +0.6VS +3VS 27 DQ13 VSS13 28 DDR_A_D8
DDR_A_D12 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_A_DQS#1
CD9 CD10 CD3 CD4 CD12 CD13 CD14 CD15 CD16 CD17 33 VSS16 DQS1_c 34 DDR_A_DQS1
35 DM1_n/DBI_n DQS1_t 36
1 1 1 1 1 1 1 1 1 1 VSS17 VSS18
DDR_A_D15 37 38 DDR_A_D10
DQ15 DQ14
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

2.2U_0402_6.3V6M
39 40
DDR_A_D14 41 VSS19 VSS20 42 DDR_A_D11
2 2 2 2 2 2 2 2 2 2 43 DQ10 DQ11 44
DDR_A_D37 45 VSS21 VSS22 46 DDR_A_D32
47 DQ21 DQ20 48
DDR_A_D36 49 VSS23 VSS24 50 DDR_A_D33
51 DQ17 DQ16 52
DDR_A_DQS#4 53 VSS25 VSS26 54
DDR_A_DQS4 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_A_D35
DDR_A_D38 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D39
DDR_A_D34 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_A_D40
DDR_A_D45 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_A_D41
DDR_A_D44 71 VSS34 DQ24 72
Layout Note: DQ25 VSS35 DDR_A_DQS#5
Layout Note: 73 74
PLACE THE CAP near 75 VSS36 DQS3_c 76 DDR_A_DQS5
Place near JDIMM1 JDIMM1. 164 77 DM3_n/DBI3_n DQS3_t 78
DDR_A_D43 79 VSS37 VSS38 80 DDR_A_D42
81 DQ30 DQ31 82
DDR_A_D46 83 VSS39 VSS40 84 DDR_A_D47
85 DQ26 DQ27 86
+1.2V_DDR +V_DDR_REFA 87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
2.2uF*1 VSS43 VSS44
91 92
CD1 CD2 CD75 CD74 CD77 CD76 CD79 CD78 CD11 CD98
0.1uF*1 93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
1 1 1 1 1 1 1 1 2 2 DQS8_c DM8_n/DBI_n/NC
@ @ 97 98
DQS8_t VSS47
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V6K

2.2U_0402_6.3V6M
99 100
101 VSS48 CB6/NC 102
2 2 2 2 2 2 2 2 1 1 103 CB2/NC VSS49 104
105 VSS50 CB7/NC 106
C CB3/NC VSS51 C
107 108 DDR4_DRAMRST#
DDR_A_CKE0 109 VSS52 RESET_n 110 DDR_A_CKE1
<7> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <7>
111 112
DDR_A_BG1 113 VDD1 VDD2 114 DDR_A_ACT#
<7> DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT# DDR_A_ACT# <7>
115 116
<7> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <7>
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124
+1.2V_DDR DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
DDR_A_MA6 127 A8 A5 128 DDR_A_MA4
DDR4_DRAMRST# 129 A6 A4 130
CD5 CD6 CD7 CD8 CD70 CD71 CD72 CD73 CD99 DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
@ DDR_A_MA1 133 A3 A2 134
1 1 1 1 1 1 1 1 2 A1 EVENT_n/NF
135 136
VDD9 VDD10
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K
DDR_A_CLK0 137 138 DDR_A_CLK1
<7> DDR_A_CLK0 DDR_A_CLK#0 CK0_t CK1_t/NF DDR_A_CLK#1 DDR_A_CLK1 <7>
139 140
2 2 2 2 2 2 2 2 1 <7> DDR_A_CLK#0 CK0_c CK1_c/NF DDR_A_CLK#1 <7>
141 142
DDR_A_PAR 143 VDD11 VDD12 144 DDR_A_MA0
<7> DDR_A_PAR DDR_A_BA1 PARITY A0 DDR_A_MA10
145 146
<7> DDR_A_BA1 BA1 A10/AP
147 148
DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BA0
<7> DDR_A_CS#0 DDR_A_MA14_WE# CS0_n BA0 DDR_A_MA16_RAS# DDR_A_BA0 <7>
151 152
<7> DDR_A_MA14_WE# WE_n/A14 RAS_n/A16 DDR_A_MA16_RAS# <7>
153 154
DDR_A_ODT0 155 VDD15 VDD16 156 DDR_A_MA15_CAS#
<7> DDR_A_ODT0 DDR_A_CS#1 ODT0 CAS_n/A15 DDR_A_MA13 DDR_A_MA15_CAS# <7>
157 158
<7> DDR_A_CS#1
PLACE NEAR TO SODIMM 159 CS1_n
VDD17
A13
VDD18
160
DDR_A_ODT1 161 162
<7> DDR_A_ODT1 ODT1 C0/CS2_n/NC +V_DDR_REFA
163 164
165 VDD19 VREFCA 166 DIMM_CHA_SA2
167 C1, CS3_n,NC SA2 168 CD96
VSS53 VSS54 1
DDR_A_D20 169 170 DDR_A_D17
DQ37 DQ36

0.1U_0402_10V6K
171 172 All VREF traces should
DDR_A_D21 173 VSS55 VSS56 174 DDR_A_D16
DQ33 DQ32 have 10 mil trace width
175 176 2
DDR_A_DQS#2 177 VSS57 VSS58 178
+1.2V_DDR DDR_A_DQS2 179 DQS4_c DM4_n/DBI4_n 180
+1.2V_DDR
181 DQS4_t VSS59 182 DDR_A_D22
DDR_A_D18 183 VSS60 DQ39 184
DQ38 VSS61
1

185 186 DDR_A_D23

RD35 DDR_A_D19 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D26
B B
470_0402_1% DDR_A_D25 191 VSS64 DQ45 192
RD31 193 DQ44 VSS65 194 DDR_A_D30
2

DDR4_DRAMRST# 1 @ 2 H_DRAMRST# DDR_A_D24 195 VSS66 DQ41 196

<22> DDR4_DRAMRST# H_DRAMRST# <15> DQ40 VSS67 DDR_A_DQS#3
1 1 1 197 198
CD97 0_0402_5% CD69 CD103 199 VSS68 DQS5_c 200 DDR_A_DQS3
@ESD@ @ESD@ @
+1.2V_DDR 201 DM5_n/DBI5_n DQS5_t 202
.1U_0402_16V7K .1U_0402_16V7K 1U_0402_6.3V6K DDR_A_D27 203 VSS69 VSS70 204 DDR_A_D31
2 2 2 205 DQ46 DQ47 206
DDR_A_D29 207 VSS71 VSS72 208 DDR_A_D28
209 DQ42 DQ43 210
DDR_A_D49 211 VSS73 VSS74 212 DDR_A_D50
213 DQ52 DQ53 214
DDR_A_D48 215 VSS75 VSS76 216 DDR_A_D54
217 DQ49 DQ48 218
DDR_A_DQS#6 219 VSS77 VSS78 220
DDR_A_DQS6 221 DQS6_c DM6_n/DBI6_n 222
+1.2V_DDR
223 DQS6_t VSS79 224 DDR_A_D52
DDR_A_D53 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_A_D55
DDR_A_D51 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_A_D59
DDR_A_D60 233 VSS84 DQ60 234
+V_DDR_REFA_R +1.2V_DDR 235 DQ61 VSS85 236 DDR_A_D62
DDR_A_D57 237 VSS86 DQ57 238
239 DQ56 VSS87 240 DDR_A_DQS#7
VSS88 DQS7_c
1

241 242 DDR_A_DQS7

+1.2V_DDR 243 DM7_n/DBI7_n DQS7_t 244
20mil RH206 DDR_A_D56 245 VSS89 VSS90 246 DDR_A_D63
1K_0402_1% DIMM_CHA_SA2 247 DQ62 DQ63 248
RH45 DDR_A_D61 249 VSS91 VSS92 250 DDR_A_D58
2

1 2 +V_DDR_REFA DIMM_CHA_SA1 251 DQ58 DQ59 252

2_0402_1% PCH_SMBCLK 253 VSS93 VSS94 254 PCH_SMBDATA
1 <15,20,22,38,39> PCH_SMBCLK SCL SDA PCH_SMBDATA <15,20,22,38,39>
1

DIMM_CHA_SA0 255 256 DIMM_CHA_SA0

+3VS VDDSPD SA0
CH101 257 258
+2.5V_MEM VPP1 VTT +0.6VS
0.022U_0402_16V7K RH209 259 260 DIMM_CHA_SA1
2 1K_0402_1% 261 VPP2 SA1 262
GND1 GND2
1

RH211
24.9_0402_1%
2

A A
DEREN_40-42271-26001RHF
CONN@
SP07001CW00

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 DIMMA
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 21 of 78
5 4 3 2 1
 5 4 3 2 1

<7> DDR_B_D[0..63]
<7> DDR_B_MA[0..13] +1.2V_DDR +1.2V_DDR
<7> DDR_B_DQS#[0..7] JDIMM2
<7> DDR_B_DQS[0..7]
1 2
DDR_B_D0 3 VSS1 VSS2 4 DDR_B_D5
5 DQ5 DQ4 6
DDR_B_D1 7 VSS3 VSS4 8 DDR_B_D4
9 DQ1 DQ0 10
Layout Note: Layout Note: Layout Note: DDR_B_DQS#0 VSS5 VSS6
11 12
Place near JDIMM2.257,259 Place near JDIMM2.258 Place near JDIMM2.255
Vinafix.com DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_B_D7
DDR_B_D3 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_B_D6
DDR_B_D2 21 VSS10 DQ2 22
D 23 DQ3 VSS11 24 DDR_B_D9 D
DDR_B_D8 25 VSS12 DQ12 26
+2.5V_MEM +0.6VS +3VS 27 DQ13 VSS13 28 DDR_B_D13
DDR_B_D12 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_B_DQS#1
CD30 CD31 CD27 CD28 CD32 CD90 CD89 CD88 CD34 CD35 33 VSS16 DQS1_c 34 DDR_B_DQS1
35 DM1_n/DBI_n DQS1_t 36
1 1 1 1 1 1 1 1 1 1 VSS17 VSS18
DDR_B_D14 37 38 DDR_B_D11
DQ15 DQ14
1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

2.2U_0402_6.3V6M
39 40
DDR_B_D15 41 VSS19 VSS20 42 DDR_B_D10
2 2 2 2 2 2 2 2 2 2 43 DQ10 DQ11 44
DDR_B_D22 45 VSS21 VSS22 46 DDR_B_D18
47 DQ21 DQ20 48
DDR_B_D23 49 VSS23 VSS24 50 DDR_B_D19
51 DQ17 DQ16 52
DDR_B_DQS#2 53 VSS25 VSS26 54
DDR_B_DQS2 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_B_D20
DDR_B_D21 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_B_D17
DDR_B_D16 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_B_D28
DDR_B_D25 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D29
DDR_B_D24 71 VSS34 DQ24 72
Layout Note: DQ25 VSS35 DDR_B_DQS#3
Layout Note: 73 74
PLACE THE CAP near 75 VSS36 DQS3_c 76 DDR_B_DQS3
Place near JDIMM2 JDIMM2. 164 77 DM3_n/DBI3_n DQS3_t 78
DDR_B_D31 79 VSS37 VSS38 80 DDR_B_D26
81 DQ30 DQ31 82
DDR_B_D27 83 VSS39 VSS40 84 DDR_B_D30
85 DQ26 DQ27 86
+1.2V_DDR +V_DDR_REFB 87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
2.2uF*1 VSS43 VSS44
91 92
CD19 CD20 CD21 CD22 CD83 CD81 CD80 CD82 CD101 CD100
0.1uF*1 93 CB1/NC CB0/NC 94
@ 95 VSS45 VSS46 96
1 1 1 1 1 1 1 1 2 @ 2 DQS8_c DM8_n/DBI_n/NC
97 98
DQS8_t VSS47
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V6K

2.2U_0402_6.3V6M
99 100
101 VSS48 CB6/NC 102
2 2 2 2 2 2 2 2 1 1 103 CB2/NC VSS49 104
105 VSS50 CB7/NC 106
C CB3/NC VSS51 C
107 108 DDR4_DRAMRST#
DDR_B_CKE0 VSS52 RESET_n DDR_B_CKE1 DDR4_DRAMRST# <21>
109 110
<7> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <7>
111 112
DDR_B_BG1 113 VDD1 VDD2 114 DDR_B_ACT#
<7> DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT# DDR_B_ACT# <7>
115 116
<7> DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT# <7>
117 118
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7
123 A9 A7 124
+1.2V_DDR DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
SF000003100 DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
DDR4_DRAMRST# 129 A6 A4 130
CD23 CD24 CD25 CD26 CD87 CD85 CD84 CD86 CD33 CD102 DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
1 A3 A2
1 1 1 1 1 1 1 1 @ 2 DDR_B_MA1 133 134
+ 135 A1 EVENT_n/NF 136
VDD9 VDD10
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_2.5V_M

0.1U_0402_10V6K
DDR_B_CLK0 137 138 DDR_B_CLK1
<7> DDR_B_CLK0 DDR_B_CLK#0 CK0_t CK1_t/NF DDR_B_CLK#1 DDR_B_CLK1 <7>
139 140
2 2 2 2 2 2 2 2 2 1 <7> DDR_B_CLK#0 CK0_c CK1_c/NF DDR_B_CLK#1 <7>
141 142
DDR_B_PAR 143 VDD11 VDD12 144 DDR_B_MA0
<7> DDR_B_PAR DDR_B_BA1 PARITY A0 DDR_B_MA10
145 146
<7> DDR_B_BA1 BA1 A10/AP
147 148
DDR_B_CS#0 149 VDD13 VDD14 150 DDR_B_BA0
<7> DDR_B_CS#0 DDR_B_MA14_WE# CS0_n BA0 DDR_B_MA16_RAS# DDR_B_BA0 <7>
151 152
<7> DDR_B_MA14_WE# WE_n/A14 RAS_n/A16 DDR_B_MA16_RAS# <7>
153 154
DDR_B_ODT0 155 VDD15 VDD16 156 DDR_B_MA15_CAS#
<7> DDR_B_ODT0 DDR_B_CS#1 ODT0 CAS_n/A15 DDR_B_MA13 DDR_B_MA15_CAS# <7>
157 158
<7> DDR_B_CS#1
PLACE NEAR TO SODIMM 159 CS1_n
VDD17
A13
VDD18
160
DDR_B_ODT1 161 162
<7> DDR_B_ODT1 ODT1 C0/CS2_n/NC +V_DDR_REFB
163 164
165 VDD19 VREFCA 166 DIMM_CHB_SA2
167 C1, CS3_n,NC SA2 168 CD29
VSS53 VSS54 1
DDR_B_D32 169 170 DDR_B_D34
DQ37 DQ36

0.1U_0402_10V6K
171 172 All VREF traces should
DDR_B_D38 173 VSS55 VSS56 174 DDR_B_D36
DQ33 DQ32 have 10 mil trace width
175 176 2
DDR_B_DQS#4 177 VSS57 VSS58 178
DDR_B_DQS4 179 DQS4_c DM4_n/DBI4_n 180
+1.2V_DDR
181 DQS4_t VSS59 182 DDR_B_D35
DDR_B_D37 183 VSS60 DQ39 184
185 DQ38 VSS61 186 DDR_B_D33
DDR_B_D39 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_B_D44
B B
DDR_B_D40 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_B_D41
DDR_B_D45 195 VSS66 DQ41 196
197 DQ40 VSS67 198 DDR_B_DQS#5
199 VSS68 DQS5_c 200 DDR_B_DQS5
+1.2V_DDR 201 DM5_n/DBI5_n DQS5_t 202
DDR_B_D47 203 VSS69 VSS70 204 DDR_B_D46
205 DQ46 DQ47 206
DDR_B_D42 207 VSS71 VSS72 208 DDR_B_D43
209 DQ42 DQ43 210
DDR_B_D52 211 VSS73 VSS74 212 DDR_B_D54
213 DQ52 DQ53 214
DDR_B_D51 215 VSS75 VSS76 216 DDR_B_D48
217 DQ49 DQ48 218
DDR_B_DQS#6 219 VSS77 VSS78 220
DDR_B_DQS6 221 DQS6_c DM6_n/DBI6_n 222
+1.2V_DDR
223 DQS6_t VSS79 224 DDR_B_D53
DDR_B_D55 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_B_D49
DDR_B_D50 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_B_D59
DDR_B_D61 233 VSS84 DQ60 234
+V_DDR_REFB_R +1.2V_DDR 235 DQ61 VSS85 236 DDR_B_D62
DDR_B_D57 237 VSS86 DQ57 238
239 DQ56 VSS87 240 DDR_B_DQS#7
VSS88 DQS7_c
1

241 242 DDR_B_DQS7

+3VS +1.2V_DDR 243 DM7_n/DBI7_n DQS7_t 244
20mil RH207 DDR_B_D63 245 VSS89 VSS90 246 DDR_B_D60
1K_0402_1% DIMM_CHB_SA1 247 DQ62 DQ63 248
RH46 DDR_B_D58 249 VSS91 VSS92 250 DDR_B_D56
2

1 2 +V_DDR_REFB DIMM_CHB_SA2 251 DQ58 DQ59 252

2_0402_1% PCH_SMBCLK 253 VSS93 VSS94 254 PCH_SMBDATA
1 <15,20,21,38,39> PCH_SMBCLK SCL SDA PCH_SMBDATA <15,20,21,38,39>
1

DIMM_CHB_SA0 255 256 DIMM_CHB_SA0

+3VS VDDSPD SA0
CH100 257 258
+2.5V_MEM VPP1 VTT +0.6VS
0.022U_0402_16V7K RH210 259 260 DIMM_CHB_SA1
2 1K_0402_1% 261 VPP2 SA1 262
GND1 GND2
1

RH212
24.9_0402_1%
2

A A
DEREN_40-42271-26001RHF
CONN@
SP07001CW00

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 DIMMB
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 22 of 78
5 4 3 2 1
 5 4 3 2 1

UV1A @ +1.8V_GFX_AON +1.8V_PLLVDD

<6> PEG_CTX_C_GRX_P[0..15]
PEG_CTX_C_GRX_P[0..15]
PEG_CTX_C_GRX_P0 GC6_EVENT#_D
RV583 Under +GPCPLL_AVDD
AN12 Part 1 of 7 RV42 1 N17P@ 2 10K_0402_5% 2 @ 1
PEG_CTX_C_GRX_N[0..15] PEG_CTX_C_GRX_N0 AM12 PEX_RX0 P6 NVVDD_PWM_VID GPU_PSI RV574 1 @ 2 10K_0402_5% CV833 1 CV939 1
<6> PEG_CTX_C_GRX_N[0..15] PEG_CTX_C_GRX_P1 AN14 PEX_RX0_N GPIO0 M3 GPU_GC6_FB_EN NVVDD_PWM_VID <67> THERMAL_ALERT# 1 2
RV526 N17P@ 10K_0402_5% 0_0402_5% N17P@ @
PEG_CRX_GTX_P[0..15] PEG_CTX_C_GRX_N1 AM14 PEX_RX1 GPIO1 L6 GC6_EVENT#_D GPU_LEVEL RV60 1 N17P@ 2 100K_0402_5%
<6> PEG_CRX_GTX_P[0..15] PEX_RX1_N GPIO2

0.1U_0402_10V7K

0.1U_0402_10V7K
PEG_CTX_C_GRX_P2 AP14 P5 NVVDDS_PWM_VID SYS_PEX_RST_MON# RV532 1 N17P@ 2 10K_0402_5%
PEG_CRX_GTX_N[0..15] PEG_CTX_C_GRX_N2 PEX_RX2 GPIO3 1V8_MAIN_EN NVVDDS_PWM_VID <68> 1V8_MAIN_EN 2 2
AP15 P7 RV55 1 N17P@ 2 10K_0402_5%
<6> PEG_CRX_GTX_N[0..15] PEG_CTX_C_GRX_P3 PEX_RX2_N GPIO4 FRM_LCK 1V8_MAIN_EN <31> GPU_PEX_RST_HOLD#
AN15 L7 RV41 1 N17P@ 2 10K_0402_5%
PEG_CTX_C_GRX_N3 AM15 PEX_RX3 GPIO5 M7 GPU_PSI FRM_LCK RV581 1 N17P@ 2 10K_0402_5%
PEG_CTX_C_GRX_P4 PEX_RX3_N GPIO6 GPU_PSI <67,68>
AN17 N8
N17P@ PEG_CTX_C_GRX_N4 AM17 PEX_RX4 GPIO7 L3 MEM_VDD_CTL GPU_GC6_FB_EN RV37 1 N17P@ 2 10K_0402_5%
PEG_CRX_GTX_P0 PEG_CRX_C_GTX_P0 PEG_CTX_C_GRX_P5 PEX_RX4_N GPIO8 THERMAL_ALERT# MEM_VDD_CTL <69> MEM_VREF
CV531 2 1 0.22U_0201_6.3V6M AP17 M2 RV27 1 N17P@ 2 100K_0402_5%
PEG_CRX_GTX_N0 CV532 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N0 PEG_CTX_C_GRX_N5 AP18 PEX_RX5 GPIO9 L1 MEM_VREF

PEG_CRX_GTX_P1
N17P@
CV533 2
N17P@
1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P1 Vinafix.com PEG_CTX_C_GRX_P6
PEG_CTX_C_GRX_N6
AN18
AM18
PEX_RX5_N
PEX_RX6
GPIO10
GPIO11
M5
N3 GPU_LEVEL
MEM_VREF <28,29>
+1.8V_GFX_AON

GPIO
PEG_CRX_GTX_N1 PEG_CRX_C_GTX_N1 PEG_CTX_C_GRX_P7 PEX_RX6_N GPIO12 GPU_LEVEL <59>
CV534 2 1 0.22U_0201_6.3V6M AN20 M4
N17P@ N17P@ PEG_CTX_C_GRX_N7 AM20 PEX_RX7 GPIO13 N4 VGA_SMB_CK2 RV191 1 N17P@ 2 1.8K_0402_5% 12/21 follow NV spec.
PEG_CRX_GTX_P2 CV535 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P2 PEG_CTX_C_GRX_P8 AP20 PEX_RX7_N GPIO14 P2 VGA_SMB_DA2 RV192 1 N17P@ 2 1.8K_0402_5%
D D
PEG_CRX_GTX_N2 CV536 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N2 PEG_CTX_C_GRX_N8 AP21 PEX_RX8 GPIO15 R8 SYS_PEX_RST_MON# +1.8V_PLLVDD

PEG_CRX_GTX_P3
N17P@ N17P@
PEG_CRX_C_GTX_P3
PEG_CTX_C_GRX_P9
PEG_CTX_C_GRX_N9
AN21 PEX_RX8_N
PEX_RX9
GPIO16
GPIO17
M6 I2CB_SCL
I2CB_SDA
RV512 1 N17P@ 2 1.8K_0402_5% RV584 Under +XS_PLLVDD
CV537 2 1 0.22U_0201_6.3V6M AM21 R1 RV513 1 N17P@ 2 1.8K_0402_5% 2 @ 1
PEG_CRX_GTX_N3 CV538 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N3 PEG_CTX_C_GRX_P10 AN23 PEX_RX9_N GPIO18 P3 CV72 1 CV940 1
N17P@ N17P@ PEG_CTX_C_GRX_N10 AM23 PEX_RX10 GPIO19 P4 VGA_EDID_CLK RV514 1 N17P@ 2 1.8K_0402_5% 0_0402_5% N17P@ @
PEG_CRX_GTX_P4 CV539 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P4 PEG_CTX_C_GRX_P11 AP23 PEX_RX10_N GPIO20 P1 VGA_EDID_DATA RV515 1 N17P@ 2 1.8K_0402_5%
PEX_RX11 GPIO21

0.1U_0402_10V7K

0.1U_0402_10V7K
PEG_CRX_GTX_N4 CV540 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N4 PEG_CTX_C_GRX_N11 AP24 P8 HPD_IFPC RV626 1 N17P@ 2 10K_0402_5%
N17P@ N17P@ PEG_CTX_C_GRX_P12 AN24 PEX_RX11_N GPIO22 T8 GPU_PEX_RST_HOLD# 2 2
PEG_CRX_GTX_P5 CV541 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P5 PEG_CTX_C_GRX_N12 AM24 PEX_RX12 GPIO23 L2
PEG_CRX_GTX_N5 CV542 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N5 PEG_CTX_C_GRX_P13 AN26 PEX_RX12_N GPIO24 R4
N17P@ N17P@ PEG_CTX_C_GRX_N13 AM26 PEX_RX13 GPIO25 R5
PEG_CRX_GTX_P6 CV543 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P6 PEG_CTX_C_GRX_P14 AP26 PEX_RX13_N GPIO26 U3 HPD_IFPC
PEG_CRX_GTX_N6 CV544 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N6 PEG_CTX_C_GRX_N14 AP27 PEX_RX14 GPIO27
N17P@ N17P@ PEG_CTX_C_GRX_P15 AN27 PEX_RX14_N DV13 N17P@
PEG_CRX_GTX_P7 CV545 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P7 PEG_CTX_C_GRX_N15 AM27 PEX_RX15 1VS_GFX_PG 2
PEG_CRX_GTX_N7 PEG_CRX_C_GTX_N7 PEX_RX15_N <66> 1VS_GFX_PG
CV546 2 1 0.22U_0201_6.3V6M
N17P@ 1 FBVDD_EN 12/21 follow NV spec.
PEG_CRX_C_GTX_P0 AK14 FBVDD_EN <31,69>
PEX_TX0

1
PEG_CRX_C_GTX_N0 AJ14 AK9 GPU_GC6_FB_EN 3 +1.8V_PLLVDD
PEG_CRX_C_GTX_P1
PEG_CRX_C_GTX_N1
AH14 PEX_TX0_N
PEX_TX1
RES
RES
AL10 RV209 RV585 Under+SP_PLLVDD
N17P@ AG14 AL9 BAT54CW_SOT323-3 N17P@ 2 @ 1
PEG_CRX_GTX_P8 CV547 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P8 PEG_CRX_C_GTX_P2 AK15 PEX_TX1_N RES BAT54CW-7-F_SOT323-3 100K_0402_5% CV52 1
PEG_CRX_GTX_N8 CV548 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N8 PEG_CRX_C_GTX_N2 AJ15 PEX_TX2 AM9 0_0402_5% N17P@
SCS00003800

RES

2
N17P@ N17P@ PEG_CRX_C_GTX_P3 AL16 PEX_TX2_N RES AN9
PEX_TX3 RES

PCI EXPRESS

0.1U_0402_10V7K
PEG_CRX_GTX_P9 CV550 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P9 PEG_CRX_C_GTX_N3 AK16
PEG_CRX_GTX_N9 CV551 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N9 PEG_CRX_C_GTX_P4 AK17 PEX_TX3_N AG10 2
N17P@ N17P@ PEG_CRX_C_GTX_N4 AJ17 PEX_TX4 RES AP9
PEG_CRX_GTX_P10 CV552 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P10 PEG_CRX_C_GTX_P5 AH17 PEX_TX4_N RES AP8 +1.8V_GFX_AON
PEG_CRX_GTX_N10 CV557 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N10 PEG_CRX_C_GTX_N5 AG17 PEX_TX5 RES
N17P@ N17P@ PEG_CRX_C_GTX_P6 AK18 PEX_TX5_N
PEX_TX6

2
G
PEG_CRX_GTX_P11 CV558 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P11 PEG_CRX_C_GTX_N6 AJ18 QV10 N17P@
PEG_CRX_GTX_N11 CV559 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N11 PEG_CRX_C_GTX_P7 AL19 PEX_TX6_N
N17P@ N17P@ PEG_CRX_C_GTX_N7 AK19 PEX_TX7 GPU_GC6_FB_EN 3 1 GPU_GC6_FB_EN_H
PEG_CRX_GTX_P12 PEG_CRX_C_GTX_P12 PEG_CRX_C_GTX_P8 PEX_TX7_N GPU_GC6_FB_EN_H <17>
CV560 2 1 0.22U_0201_6.3V6M AK20

D
PEG_CRX_GTX_N12 CV561 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N12 PEG_CRX_C_GTX_N8 AJ20 PEX_TX8
N17P@ N17P@ PEG_CRX_C_GTX_P9 AH20 PEX_TX8_N R7 I2CB_SCL BSS138W 1N SOT-323-3
PEG_CRX_GTX_P13 CV562 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P13 PEG_CRX_C_GTX_N9 AG20 PEX_TX9 I2CB_SCL R6 I2CB_SDA +1.8V_PLLVDD
C
PEG_CRX_GTX_N13 CV563 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N13 PEG_CRX_C_GTX_P10
PEG_CRX_C_GTX_N10
AK21 PEX_TX9_N
PEX_TX10
I2CB_SDA
VGA_EDID_CLK GC6_EVENT#_D
DV9 N17P@
GPU_EVENT#
RV586 Under +VID_PLLVDD C
N17P@ N17P@ AJ21 R2 2 1 2 @ 1

I2C
PEG_CRX_GTX_P14 PEG_CRX_C_GTX_P14 PEG_CRX_C_GTX_P11 PEX_TX10_N I2CC_SCL VGA_EDID_DATA GPU_EVENT# <17>
CV564 2 1 0.22U_0201_6.3V6M AL22 R3 CV53 1
PEG_CRX_GTX_N14 CV565 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N14 PEG_CRX_C_GTX_N11 AK22 PEX_TX11 I2CC_SDA RB751S40_SOD523-2 0_0402_5% N17P@
N17P@ N17P@ PEG_CRX_C_GTX_P12 AK23 PEX_TX11_N T4 VGA_SMB_CK2 AZ5125-01HPR7G_SOD523-2
PEX_TX12 I2CS_SCL

0.1U_0402_10V7K
PEG_CRX_GTX_P15 CV566 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_P15 PEG_CRX_C_GTX_N12 AJ23 T3 VGA_SMB_DA2
PEG_CRX_GTX_N15 CV567 2 1 0.22U_0201_6.3V6M PEG_CRX_C_GTX_N15 PEG_CRX_C_GTX_P13 AH23 PEX_TX12_N I2CS_SDA DV11 N17P@ 2
N17P@ PEG_CRX_C_GTX_N13 AG23 PEX_TX13 GPU_LEVEL 2 1 GPU_PWR_LEVEL
PEG_CRX_C_GTX_P14 PEX_TX13_N GPU_PWR_LEVEL <44>
AK24
PEG_CRX_C_GTX_N14 AJ24 PEX_TX14 RB751S40_SOD523-2
+1.8V_GFX_AON PEG_CRX_C_GTX_P15 AL25 PEX_TX14_N AZ5125-01HPR7G_SOD523-2
PEG_CRX_C_GTX_N15 AK25 PEX_TX15
PEX_TX15_N GPCPLL_AVDD
H26 +GPCPLL_AVDD W=40mils
W=40mils
1

AD8 +XS_PLLVDD
RV39 AJ11 XS_PLLVDD GPU_PWR_LEVEL
@ NC
SP_PLLVDD
AE8 +SP_PLLVDD W=40mils Low Low Performace
10K_0402_5% CLK_PEG_P7 AL13
RV40
<14>
<14>
CLK_PEG_P7
CLK_PEG_N7
CLK_PEG_N7 AK13 PEX_REFCLK AD7 +VID_PLLVDD W=40mils High High Performace
2

DGPU_PEX_RST# 1 @ 2 DGPU_PEX_RST#_R CLKREQ_PCIE#7_M AK12 PEX_REFCLK_N VID_PLLVDD +1.8V_PLLVDD +1.8V_GFX_RUN

PEX_CLKREQ_N Near LV7 N17P@

CLK
1

0_0402_5% AJ26 H3 XTALIN 1 2

RV573 AK26 NC XTAL_IN H2 XTAL_OUT CV51 1 CV50 1 BLM15AX300SN1D
N17P@ NC XTAL_OUT RV572 2 @ 1 ALL_GPWRGD N17P@ N17P@
100K_0402_5% DGPU_PEX_RST#_R AJ12 J4 XTALOUT 0_0402_5%
PEX_RST_N XTAL_OUTBUFF

4.7U_0603_6.3V6K

22U_0603_6.3V6M
PEX_TERMP AP29 H1 XTALSSIN
2

PEX_TERMP XTAL_SSIN RV571 2 @ 1 DGPU_PEX_RST# 2 2

2

1
0_0402_5%
RV50 RV49 RV51
N17P@ N17P@ N17P@

2
2.49K_0402_1% N17P-GT_BGA908 10K_0402_5% 10K_0402_5%
QV1A N17P@
1

2
GPU_THM_SMBCLK 6 1 VGA_SMB_CK2
<15,44,45> GPU_THM_SMBCLK

5
+1.8V_GFX_AON DMN63D8LDW-7 2N SOT363-6
QV1B N17P@
GPU_THM_SMBDAT 3 4 VGA_SMB_DA2
<15,44,45> GPU_THM_SMBDAT
5

UV19 N17P@
1VS_GFX_PG 1 DMN63D8LDW-7 2N SOT363-6
P

B 4 ALL_GPWRGD XTAL_OUT RV627 1 @ 2

DGPU_PWROK 2 O 0_0402_5%
B B
<15,69> DGPU_PWROK A
2
G

+1.8V_GFX_AON XTALIN RV52 1 @ 2 HPD_IFPC

TC7SZ08FU_SSOP5 RV56 10M_0402_5% +1.8V_GFX_AON
3

SA00001DG90 N17P@
2

10K_0402_5% YV1 N17P@ UV22

5
RV57 N17P@
2 1

1
N17P@ 1 3 QV94 D 1 GPU_HPD_RT

P
1 3 B GPU_HPD_RT <33>
QV3 N17P@ 10K_0402_5% N17P@ 2 4
G

CV70 GND GND CV71 G O 2 DGPU_PEX_RST#_R

BSS138W 1N SOT-323-3
1

G
CLKREQ_PCIE#7 1 3 CLKREQ_PCIE#7_M N17P@ N17P@ S
<14> CLKREQ_PCIE#7 2 4 3
10P_0402_50V8J 10P_0402_50V8J RV628 TC7SZ08FU_SSOP5
D

3
N17P@
BSS138W 1N SOT-323-3 27MHZ_10PF_7V27000050 100K_0402_5% P.P
SJ100009700

2
GC6 2.1 function +1.8V_GFX_AON +1.8V_GFX_AON DGPU_PEX_RST#

DGPU_HOLD_RST# 1
2

CV212
2

@ RV619 RV620
RV58 0.1U_0402_10V7K N17P@ @
N17P@ 2 10K_0402_5% 0_0402_5%
10K_0402_5%
1

2
1

CMP_VOUT0
+1.8V_GFX_AON CMP_VOUT0 <44,61>
5

UV14 N17P@ QV88B

DGPU_HOLD_RST# 1 RV587 N17P@
P

<17> DGPU_HOLD_RST# B SYS_PEX_RST_MON#

4 1 @ 2
PCH_PLTRST#_EC 2 O 0_0402_5% 5
<14,36,39,40,41,44,45> PCH_PLTRST#_EC A
G

DMN63D8LDW-7 2N SOT363-6
A A
TC7SZ08FU_SSOP5
3

SA00001DG90
1

QV88A
RV208 N17P@
@ 0_0402_5%
+1.8V_GFX_AON THERMATRIP_GPU# 2
<24> THERMATRIP_GPU#
DMN63D8LDW-7 2N SOT363-6
2

1
5

UV18 @
SYS_PEX_RST_MON# 1
P

B 4
GPU_PEX_RST_HOLD# 2
A
O DGPU_PEX_RST# <24> Security Classification Compal Secret Data Compal Electronics, Inc.
G

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

TC7SZ08FU_SSOP5
N17P_PCIE/DAC/GPIO
3

SA00001DG90 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 23 of 78
5 4 3 2 1
 5 4 3 2 1

UV1D @

Part 4 of 7
Vinafix.com AM6
AN6 IFPA_L3
IFPA_L3_N
AP3 AC6
AN3 IFPA_L2 NC AJ28
D D
AN5 IFPA_L2_N NC AJ4
AM5 IFPA_L1 NC AJ5
AL6 IFPA_L1_N NC AL11
AK6 IFPA_L0 NC C15
IFPA_L0_N NC

NC
AJ6 D19
AH6 IFPA_AUX_SCL NC D20
IFPA_AUX_SDA_N NC D23
NC D26
AJ9 NC
AH9 IFPB_L3
AP6 IFPB_L3_N V32
AP5 IFPB_L2 NC
AM7 IFPB_L2_N
IFPB_L1
trace width: 16mils
AL7
AN8 IFPB_L1_N
IFPB_L0
differential voltage sensing.
AM8
AK8 IFPB_L0_N
IFPB_AUX_SCL
differential signal routing.
AL8
IFPB_AUX_SDA_N L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA <67>
GPU_IFPC_P0 AK1
<33> GPU_IFPC_P0 GPU_IFPC_N0 IFPC_L0
AJ1
<33> GPU_IFPC_N0 GPU_IFPC_P1 IFPC_L0_N VSSSENSE_VGA
AJ3 L5
<33> GPU_IFPC_P1 GPU_IFPC_N1 IFPC_L1 GND_SENSE VSSSENSE_VGA <67>
AJ2
<33> GPU_IFPC_N1 GPU_IFPC_P2 IFPC_L1_N
AH3

TMDS
<33> GPU_IFPC_P2 GPU_IFPC_N2 IFPC_L2
AH4
<33> GPU_IFPC_N2 GPU_IFPC_P3 IFPC_L2_N
AG5
<33> GPU_IFPC_P3 GPU_IFPC_N3 IFPC_L3
AG4 TESTMODE
<33> GPU_IFPC_N3 IFPC_L3_N
C C
TEST

1
AM1 AK11 TESTMODE RV62
AM2 IFPD_L0 NVJTAG_SEL N17P@
AM3 IFPD_L0_N AM10 GPU_JTAG_TCK PAD T98 @ 10K_0402_5%
AM4 IFPD_L1 JTAG_TCK AM11 GPU_JTAG_TDI PAD T99 @

2
AL3 IFPD_L1_N JTAG_TDI AP12 GPU_JTAG_TDO PAD T100 @
AL4 IFPD_L2 JTAG_TDO AP11 GPU_JTAG_TMS PAD T101 @
AK4 IFPD_L2_N JTAG_TMS AN11 GPU_JTAG_TRST#
AK5 IFPD_L3 JTAG_TRST_N
IFPD_L3_N
GPU_JTAG_TRST#
+1.8V_GFX_AON AD2
IFPE_L0

1
AD3
AD1 IFPE_L0_N RV63
IFPE_L1 SERIAL
1

AC1 N17P@
RV630 AC2 IFPE_L1_N H6 ROM_CS PAD T97 @ 10K_0402_5%
@ 0_0402_5% AC3 IFPE_L2 ROM_CS_N H4 ROM_SCLK
ROM_SCLK <30>

2
AC4 IFPE_L2_N ROM_SCLK H5 ROM_SI
IFPE_L3 ROM_SI ROM_SO ROM_SI <30>
AC5 H7
ROM_SO <30>
2

IFPE_L3_N ROM_SO
+1.8V_GFX_AON +1.8V_GFX_AON
AE3
AE4 IFPF_L0
IFPF_L0_N

2
RV629 1 @ 2 0_0402_5% AF4
<23> DGPU_PEX_RST# IFPF_L1
AF5 RV34
IFPF_L1_N GENERAL
1

AD4 N17P@
RV621 RV622 AD5 IFPF_L2 E1 10K_0402_5%
N17P@ N17P@ AG1 IFPF_L2_N BUFRST_N
Vgs:0.5V~1V

1
B 10K_0402_5% 10K_0402_5% AF1 IFPF_L3 M1 THERMATRIP_GPU# THERMATRIP_GPU# B
IFPF_L3_N OVERT THERMATRIP_GPU# <23>
QV93A
2

2
2

N17P@

GPU_IFPC_CTRL_CLK_M 6 1 GPU_IFPC_CTRL_CLK AG3

GPU_IFPC_CTRL_DATA AG2 IFPC_AUX_SCL
DMN61D9UDW-7 2N SOT363-6 IFPC_AUX_SDA_N J2 STRAP0
STRAP0 STRAP0 <30>
QV93B J7 STRAP1
SB00001GW00 STRAP1 STRAP1 <30>
5

N17P@ AK3 J6 STRAP2

IFPD_AUX_SCL STRAP2 STRAP2 <30>
AK2 J5 STRAP3
GPU_IFPC_CTRL_DATA_M IFPD_AUX_SDA_N STRAP3 STRAP3 <30>
3 4 J3 STRAP4
STRAP4 STRAP4 <30>
J1 STRAP5
STRAP5 STRAP5 <30>
DMN61D9UDW-7 2N SOT363-6 AB3
AB4 IFPE_AUX_SCL
SB00001GW00 IFPE_AUX_SDA_N K3
THERMDP K4
HDMI_CTRL_CLK RV624 2 @ 1 GPU_IFPC_CTRL_CLK_M AF3 THERMDN
<33,34> HDMI_CTRL_CLK IFPF_AUX_SCL
0_0402_5% AF2
HDMI_CTRL_DAT RV623 2 @ 1 GPU_IFPC_CTRL_DATA_M IFPF_AUX_SDA_N
<33,34> HDMI_CTRL_DAT
0_0402_5%

N17P-GT_BGA908
IFPC_I2C_8409_DAT RP10 2 1
<33> IFPC_I2C_8409_DAT
0_0402_5%
@PS8409@
IFPC_I2C_8409_CLK RP9 2 1
<33> IFPC_I2C_8409_CLK
0_0402_5%
@PS8409@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17P_eDP/HDMI/mDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 24 of 78
5 4 3 2 1
 5 4 3 2 1

+1VS_GFX
Under GPU Near GPU 3A
CV87 1 CV88 1 CV89 1 CV90 1 CV91 1 CV92 1 CV93 2 CV96 1
N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

22U_0603_6.3V6M
UV1E @
2 2 2 2 2 2 1 2
+1.35VS_VGA Part 5 of 7
11A 12/21 follow NV spec. Near GPU
CV941 1 CV945 1 CV942 1 CV946 1 CV947 1 CV944 2 CV943 2 Vinafix.com
CV83 1 CV834 1 CV85 1 CV84 1 CV86 1 CV79 2 CV80 2
AA27
AA30 FBVDDQ_0
FBVDDQ_1
PEX_DVDD_0
PEX_DVDD_1
AG19
AG21
N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ AB27 AG22
AB33 FBVDDQ_2 PEX_DVDD_2 AG24
D D
FBVDDQ_3 PEX_DVDD_3
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
AC27 AH21
2 2 2 2 2 1 1 2 2 2 2 2 1 1 AD27 FBVDDQ_4 PEX_DVDD_4 AH25
AE27 FBVDDQ_5 PEX_DVDD_5 +1.8V_GFX_RUN
AF27 FBVDDQ_6
FBVDDQ_7
Under GPU Near GPU 1A
AG27 AG13
B13 FBVDDQ_8 PEX_HVDD_0 AG15 CV835 1 CV836 1 CV837 1 CV838 1 CV839 1 CV840 1 CV94 2 CV95 2 CV97 1
B19 FBVDDQ_9 PEX_HVDD_1 AG16 N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@
E13 FBVDDQ_11 PEX_HVDD_2 AG18
FBVDDQ_12 PEX_HVDD_3

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M
E19 AG25
H10 FBVDDQ_14 PEX_HVDD_4 AH15 2 2 2 2 2 2 1 1 2
H11 FBVDDQ_15 PEX_HVDD_5 AH18
H12 FBVDDQ_16 PEX_HVDD_6 AH26
+1.35VS_VGA H13 FBVDDQ_17 PEX_HVDD_7 AH27
FBVDDQ Under GPU(below 150mils) H14 FBVDDQ_18
FBVDDQ_19
PEX_HVDD_8
PEX_HVDD_9
AJ27
H18 AK27
Under GPU CV841 2 CV842 2 CV100 1 CV101 1 CV102 1 CV103 1 CV112 1 CV113 1 H19 FBVDDQ_22
FBVDDQ_23
PEX_HVDD_10
PEX_HVDD_11
AL27
N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ H20 AM28
1uF x 12

POWER
H21 FBVDDQ_24 PEX_HVDD_12 AN28
FBVDDQ_25 PEX_HVDD_13

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
H22
10uF x 4 1 1 2 2 2 2 2 2 H23 FBVDDQ_26 +1.8V_GFX_RUN
Near GPU H24 FBVDDQ_27
FBVDDQ_28 +PEX_PLL_HVDD
Near GPU RV590
H8 AH12 1 @ 2
10uF x 4 H9 FBVDDQ_29 PEX_PLL_HVDD CV114 1
L27 FBVDDQ_30 N17P@ 0_0402_5%
22uF x 10 M27 FBVDDQ_31 +1.8V_GFX_AON
FBVDDQ_32 Under GPU Near GPU

0.1U_0402_10V7K
N27 AG12
P27 FBVDDQ_33 NC 2
R27 FBVDDQ_34 CV843 1 CV202 1 CV214 1 CV213 1
C T27 FBVDDQ_35 N17P@ N17P@ N17P@ N17P@ C
+1.35VS_VGA T30 FBVDDQ_36 AG26
Under GPU(below 150mils) FBVDDQ_37 NC

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
T33
Y27 FBVDDQ_38 +1.8V_GFX_AON 2 2 2 2
CV844 2 CV845 2 CV211 1 CV210 1 CV209 1 CV206 1 CV207 1 CV208 1 FBVDDQ_43
1
220U_D2 SX_2VY_R9M

CV948 N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ J8

+ 1V8_AON K8 +1.8V_GFX_RUN
1V8_AON
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
L8
N17P@ 1 1 2 2 2 2 2 2 B16 VDD18 M8
2 E16 FBVDDQ VDD18
H15 FBVDDQ
H16 FBVDDQ
V27 FBVDDQ AH8
W27 FBVDDQ IFPAB_PLLVDD AJ8 +IFPX_PLLVDD +1.8V_GFX_RUN +1.8V_GFX_RUN
W30 FBVDDQ
FBVDDQ
IFPAB_RSET Under GPU Near GPU
W33 LV1
SGA20221D40 FBVDDQ AF7 1 N17P@ 2 CV117 1 CV118 1 CV119 1 CV120 1
IFPCD_PLLVDD AF8 IFPCD_RSET PBY160808T-300Y-N_2P N17P@ N17P@ N17P@ N17P@
IFPCD_RSET

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
1

1
AB8 RV625 CV961 2 2 2 2
IFPEF_PLVDD AD6 N17P@ N17P@
W=10mils IFPEF_RSET

0.1U_0402_10V7K
FBVDDQ_SENSE F1 1K_0402_1%
<69> FBVDDQ_SENSE FBVDDQ_SENSE 2

2
F2 AG8
+1.35VS_VGA PROBE_FB_GND IFP_IOVDD AG9
IFP_IOVDD

B
RV77 1 N17P@ 2 J27
FB_CAL_PD_VDDQ IFP_IOVDD
AF6 Under GPU B
40.2_0402_1% AG6
IFP_IOVDD +1VS_GFX
CALIBRATION PIN GDDR5 RV78 1 N17P@ 2 H27 AC7
40.2_0402_1% FB_CAL_PU_GND IFP_IOVDD AC8
FB_CAL_x_PD_VDDQ 40.2 ohm IFP_IOVDD
RV79 1 N17P@ 2 H25
FB_CAL_x_PU_GND 40.2 ohm 60.4_0402_1% FB_CAL_TERM_GND AG7
1
CV949
1
CV950
1
CV951
1
CV952
1
CV953
1
CV954
1
CV955
1
CV956
1
CV957
NC AN2 N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@
FB_CAL_xTERM_GND 60.4 ohm Place near balls NC

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2

N17P-GT_BGA908

+1VS_GFX

Under GPU Under GPU Under GPU CV995 near AG8/AG9

1 CV958 1 CV959 1 CV960 AG8/AG9 AF6/AG6 AC7/AC8 CV956 near AF6/AG6
N17P@ N17P@ N17P@
CV957 near AC7/AC8
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2 2 2 4.7U_0603_6.3V6K

CV958 near AG8/AG9

A
CV959 near AF6/AG6 A
CV960 near AC7/AC8

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17P_Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 25 of 78
5 4 3 2 1
 5 4 3 2 1

UV1F @

Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10

Vinafix.com AA22
AB12
AB14
GND_3
GND_4
GND_5
GND_103
GND_104
GND_105
E22
E25
E5
AB16 GND_6 GND_106 E7
D AB19 GND_7 GND_107 F28 D
AB2 GND_8 GND_108 F7
AB21 GND_9 GND_109 G10
A33 GND_10 GND_110 G13
AB23 GND_11 GND_111 G16
47A +GPU_CORE UV1G @ +GPU_CORE AB28 GND_12
GND_13
GND_112
GND_113
G19
AB30 G2
AB32 GND_14 GND_114 G22
AA14 Part 7 of 7 V17 AB5 GND_15 GND_115 G25
AA21 VDD_1 VDD_56 V20 AB7 GND_16 GND_116 G28
AB13 VDD_4 VDD_58 V22 AC13 GND_17 GND_117 G3
AB15 VDD_6 VDD_59 W12 AC15 GND_18 GND_118 G30
AB17 VDD_7 VDD_60 W16 AC17 GND_19 GND_119 G32
AB18 VDD_8 VDD_62 W19 AC18 GND_20 GND_120 G33
AB20 VDD_9 VDD_63 W23 AA13 GND_21 GND_121 G5
AB22 VDD_10 VDD_65 Y13 AC20 GND_22 GND_122 G7
AC12 VDD_11 VDD_66 Y15 AC22 GND_23 GND_123 K2
AC16 VDD_12 VDD_67 Y17 AE2 GND_24 GND_124 K28
AC19 VDD_14 VDD_68 Y18 AE28 GND_25 GND_125 K30
AC23 VDD_15 VDD_69 Y20 AE30 GND_26 GND_126 K32
M12 VDD_17 VDD_70 Y22 AE32 GND_27 GND_127 K33
M16 VDD_18 VDD_71 AE33 GND_28 GND_128 K5
M19 VDD_20 AE5 GND_29 GND_129 K7
M23 VDD_21
VDD_23 VDDS_SENSE_VGA
W=10mils AE7 GND_30
GND_31
GND_130
GND_131
M13
N13 U1 AH10 M15
VDD_24 VDDS_SENSE GNDS_SENSE_VGA VDDS_SENSE_VGA <68> GND_32 GND_132
N15 U2 AA15 M17
VDD_25 GNDS_SENSE GNDS_SENSE_VGA <68> GND_33 GND_133
N17 AH13 M18
N18 VDD_26 +GPU_CORE AH16 GND_34 GND_134 M20
N20 VDD_27 AH19 GND_35 GND_135 M22
N22 VDD_28 U4 AH2 GND_36 GND_136 N12

POWER
P14 VDD_29 XVDD_4 U5 AH22 GND_37 GND_137 N14
P21 VDD_31 XVDD_5 U6 AH24 GND_38 GND_138 N16
C R13 VDD_34 XVDD_6 U7 AH28 GND_39 GND_139 N19 C
R15 VDD_36 XVDD_7 U8 AH29 GND_40 GND_140 N2
R17 VDD_37 XVDD_8 AH30 GND_41 GND_141 N21
R18 VDD_38 AH32 GND_42 GND_142 N23
R20 VDD_39 V1 AH33 GND_43 GND_143 N28

GND
R22 VDD_40 XVDD_9 V2 AH5 GND_44 GND_144 N30
T12 VDD_41 XVDD_10 V3 AH7 GND_45 GND_145 N32
T16 VDD_42 XVDD_11 V4 AJ7 GND_46 GND_146 N33
T19 VDD_44 XVDD_12 V5 AK10 GND_47 GND_147 N5
T23 VDD_45 XVDD_13 V6 AK7 GND_48 GND_148 N7
U13 VDD_47 XVDD_14 V7 AL12 GND_49 GND_149 P13
U15 VDD_48 XVDD_15 V8 AL14 GND_50 GND_150 P15
U18 VDD_49 XVDD_16 AL15 GND_51 GND_151 P17
U20 VDD_51 AL17 GND_52 GND_152 P18
U22 VDD_52 W2 AL18 GND_53 GND_153 P20
V13 VDD_53 XVDD_17 W3 AL2 GND_54 GND_154 P22
V15 VDD_54 XVDD_18 W4 AL20 GND_55 GND_155 R12
VDD_55 XVDD_19 W5 AL21 GND_56 GND_156 R14
XVDD_20 W7 AL23 GND_57 GND_157 R16
+GPU_CORE_VDDS XVDD_21 W8 AL24 GND_58 GND_158 R19
XVDD_22 AL26 GND_59 GND_159 R21
19A AA12
VDDS
AL28 GND_60
GND_61
GND_160
GND_161
R23
AA16 Y1 AL30 T13
AA19 VDDS NC Y2 AL32 GND_62 GND_162 T15
AA23 VDDS NC Y3 AL33 GND_63 GND_163 T17
AC14 VDDS NC Y4 AL5 GND_64 GND_164 T18
AC21 VDDS XVDD_23 Y5 AM13 GND_65 GND_165 T2
M14 VDDS XVDD_24 Y6 AM16 GND_66 GND_166 T20
M21 VDDS XVDD_25 Y7 AM19 GND_67 GND_167 T22
P12 VDDS XVDD_26 Y8 AM22 GND_68 GND_168 AG11
P16 VDDS XVDD_27 AM25 GND_69 GND_169 T28
P19 VDDS AN1 GND_70 GND_170 T32
B P23 VDDS AA1 AN10 GND_71 GND_171 T5 B
T14 VDDS NC AA2 AN13 GND_72 GND_172 T7
T21 VDDS NC AA3 AN16 GND_73 GND_173 U12
U17 VDDS NC AA4 AN19 GND_74 GND_174 U14
V18 VDDS NC AA5 AN22 GND_75 GND_175 U16
W14 VDDS NC AA6 AN25 GND_76 GND_176 U19
W21 VDDS NC AA7 AN30 GND_77 GND_177 U21
VDDS NC AA8 AN34 GND_78 GND_178 U23
NC AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
N17P-GT_BGA908 AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W13
B25 GND_86 GND_186 W15
B28 GND_87 GND_187 W17
B31 GND_88 GND_188 W18
B34 GND_89 GND_189 W20
B4 GND_90 GND_190 W22
B7 GND_91 GND_191 W28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
C7 GND_98 GND_198 AH11
GND_99 GND_199 C16
GND_OPT W32
GND_OPT

A A
N17P-GT_BGA908

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17P_VGA CORE/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 26 of 78
5 4 3 2 1
 5 4 3 2 1

FB_A_D[0..63] FB_B_D[0..63]
<28> FB_A_D[0..63] <29> FB_B_D[0..63]

<28> FB_A_EDC[7..0] <29> FB_B_EDC[7..0]

UV1B @ UV1C @

FB_A_D0 L28
Part 2 of 7 Vinafix.comU30 FB_A_CMD0 FB_B_D0 G9
Part 3 of 7
D13 FB_B_CMD0
FB_A_D1 FBA_D0 FBA_CMD0 FB_A_CMD1 FB_A_CMD0 <28> FB_B_D1 FBB_D0 FBB_CMD0 FB_B_CMD1 FB_B_CMD0 <29>
M29 T31 E9 E14
D FB_A_D2 FBA_D1 FBA_CMD1 FB_A_CMD2 FB_A_CMD1 <28> FB_B_D2 FBB_D1 FBB_CMD1 FB_B_CMD2 FB_B_CMD1 <29> D
L29 U29 G8 F14
FB_A_D3 FBA_D2 FBA_CMD2 FB_A_CMD3 FB_A_CMD2 <28> FB_B_D3 FBB_D2 FBB_CMD2 FB_B_CMD3 FB_B_CMD2 <29>
M28 R34 F9 A12
FB_A_D4 FBA_D3 FBA_CMD3 FB_A_CMD4 FB_A_CMD3 <28> FB_B_D4 FBB_D3 FBB_CMD3 FB_B_CMD4 FB_B_CMD3 <29>
N31 R33 F11 B12
FB_A_D5 FBA_D4 FBA_CMD4 FB_A_CMD5 FB_A_CMD4 <28> FB_B_D5 FBB_D4 FBB_CMD4 FB_B_CMD5 FB_B_CMD4 <29>
P29 U32 G11 C14
FB_A_D6 FBA_D5 FBA_CMD5 FB_A_CMD6 FB_A_CMD5 <28> FB_B_D6 FBB_D5 FBB_CMD5 FB_B_CMD6 FB_B_CMD5 <29>
R29 U33 F12 B14
FB_A_D7 FBA_D6 FBA_CMD6 FB_A_CMD7 FB_A_CMD6 <28> FB_B_D7 FBB_D6 FBB_CMD6 FB_B_CMD7 FB_B_CMD6 <29>
P28 U28 G12 G15
FB_A_D8 FBA_D7 FBA_CMD7 FB_A_CMD8 FB_A_CMD7 <28> FB_B_D8 FBB_D7 FBB_CMD7 FB_B_CMD8 FB_B_CMD7 <29>
J28 V28 G6 F15
FB_A_D9 FBA_D8 FBA_CMD8 FB_A_CMD9 FB_A_CMD8 <28> FB_B_D9 FBB_D8 FBB_CMD8 FB_B_CMD9 FB_B_CMD8 <29>
H29 V29 F5 E15
FB_A_D10 FBA_D9 FBA_CMD9 FB_A_CMD10 FB_A_CMD9 <28> FB_B_D10 FBB_D9 FBB_CMD9 FB_B_CMD10 FB_B_CMD9 <29>
J29 V30 E6 D15
FB_A_D11 FBA_D10 FBA_CMD10 FB_A_CMD11 FB_A_CMD10 <28> FB_B_D11 FBB_D10 FBB_CMD10 FB_B_CMD11 FB_B_CMD10 <29>
H28 U34 F6 A14
FB_A_D12 FBA_D11 FBA_CMD11 FB_A_CMD12 FB_A_CMD11 <28> FB_B_D12 FBB_D11 FBB_CMD11 FB_B_CMD12 FB_B_CMD11 <29>
G29 U31 F4 D14
FB_A_D13 FBA_D12 FBA_CMD12 FB_A_CMD13 FB_A_CMD12 <28> FB_B_D13 FBB_D12 FBB_CMD12 FB_B_CMD13 FB_B_CMD12 <29>
E31 V34 G4 A15
FB_A_D14 FBA_D13 FBA_CMD13 FB_A_CMD14 FB_A_CMD13 <28> FB_B_D14 FBB_D13 FBB_CMD13 FB_B_CMD14 FB_B_CMD13 <29>
E32 V33 E2 B15
FB_A_D15 FBA_D14 FBA_CMD14 FB_A_CMD15 FB_A_CMD14 <28> FB_B_D15 FBB_D14 FBB_CMD14 FB_B_CMD15 FB_B_CMD14 <29>
F30 Y32 F3 C17
FB_A_D16 FBA_D15 FBA_CMD15 FB_A_CMD16 FB_A_CMD15 <28> FB_B_D16 FBB_D15 FBB_CMD15 FB_B_CMD16 FB_B_CMD15 <29>
C34 AA31 C2 D18
FB_A_D17 FBA_D16 FBA_CMD16 FB_A_CMD17 FB_A_CMD16 <28> FB_B_D17 FBB_D16 FBB_CMD16 FB_B_CMD17 FB_B_CMD16 <29>
D32 AA29 D4 E18
FB_A_D18 FBA_D17 FBA_CMD17 FB_A_CMD18 FB_A_CMD17 <28> FB_B_D18 FBB_D17 FBB_CMD17 FB_B_CMD18 FB_B_CMD17 <29>
B33 AA28 D3 F18
FB_A_D19 FBA_D18 FBA_CMD18 FB_A_CMD19 FB_A_CMD18 <28> FB_B_D19 FBB_D18 FBB_CMD18 FB_B_CMD19 FB_B_CMD18 <29>
C33 AC34 C1 A20
FB_A_D20 FBA_D19 FBA_CMD19 FB_A_CMD20 FB_A_CMD19 <28> FB_B_D20 FBB_D19 FBB_CMD19 FB_B_CMD20 FB_B_CMD19 <29>
F33 AC33 B3 B20
FB_A_D21 FBA_D20 FBA_CMD20 FB_A_CMD21 FB_A_CMD20 <28> FB_B_D21 FBB_D20 FBB_CMD20 FB_B_CMD21 FB_B_CMD20 <29>
F32 AA32 C4 C18
FB_A_D22 FBA_D21 FBA_CMD21 FB_A_CMD22 FB_A_CMD21 <28> FB_B_D22 FBB_D21 FBB_CMD21 FB_B_CMD22 FB_B_CMD21 <29>
H33 AA33 B5 B18
FB_A_D23 FBA_D22 FBA_CMD22 FB_A_CMD23 FB_A_CMD22 <28> FB_B_D23 FBB_D22 FBB_CMD22 FB_B_CMD23 FB_B_CMD22 <29>
H32 Y28 C5 G18
FB_A_D24 FBA_D23 FBA_CMD23 FB_A_CMD24 FB_A_CMD23 <28> FB_B_D24 FBB_D23 FBB_CMD23 FB_B_CMD24 FB_B_CMD23 <29>
P34 Y29 A11 G17
FB_A_D25 FBA_D24 FBA_CMD24 FB_A_CMD25 FB_A_CMD24 <28> FB_B_D25 FBB_D24 FBB_CMD24 FB_B_CMD25 FB_B_CMD24 <29>
P32 W31 C11 F17
FB_A_D26 FBA_D25 FBA_CMD25 FB_A_CMD26 FB_A_CMD25 <28> FB_B_D26 FBB_D25 FBB_CMD25 FB_B_CMD26 FB_B_CMD25 <29>
P31 Y30 D11 D16
FB_A_D27 FBA_D26 FBA_CMD26 FB_A_CMD27 FB_A_CMD26 <28> FB_B_D27 FBB_D26 FBB_CMD26 FB_B_CMD27 FB_B_CMD26 <29>
P33 AA34 B11 A18

MEMORY INTERFACE B
FB_A_D28 FBA_D27 FBA_CMD27 FB_A_CMD28 FB_A_CMD27 <28> FB_B_D28 FBB_D27 FBB_CMD27 FB_B_CMD28 FB_B_CMD27 <29>
L31 Y31 D8 D17
FB_A_D29 FBA_D28 FBA_CMD28 FB_A_CMD29 FB_A_CMD28 <28> FB_B_D29 FBB_D28 FBB_CMD28 FB_B_CMD29 FB_B_CMD28 <29>
L34 Y34 A8 A17
FB_A_D30 FBA_D29 FBA_CMD29 FB_A_CMD30 FB_A_CMD29 <28> FB_B_D30 FBB_D29 FBB_CMD29 FB_B_CMD30 FB_B_CMD29 <29>
L32 Y33 C8 B17
FB_A_D31 FBA_D30 FBA_CMD30 FB_A_CMD31 FB_A_CMD30 <28> FB_B_D31 FBB_D30 FBB_CMD30 FB_B_CMD31 FB_B_CMD30 <29>
L33 V31 B8 E17
FB_A_D32 FBA_D31 FBA_CMD31 FB_A_CMD31 <28> FB_B_D32 FBB_D31 FBB_CMD31 FB_B_CMD31 <29>
AG28 R28 F24 G14
FB_A_D33 AF29 FBA_D32 FBA_CMD32 AC28 FB_B_D33 G23 FBB_D32 FBB_CMD32 G20
MEMORY INTERFACE

C FB_A_D34 AG29 FBA_D33 FBA_CMD33 R32 RV602 1 @ 2 60.4_0402_1% FB_B_D34 E24 FBB_D33 FBB_CMD33 C12 RV604 1 @ 2 60.4_0402_1% C
FBA_D34 FBA_CMD34 +1.35VS_VGA FBB_D34 FBB_CMD34 +1.35VS_VGA
FB_A_D35 AF28 AC32 RV603 1 @ 2 60.4_0402_1% FB_B_D35 G24 C20 RV605 1 @ 2 60.4_0402_1%
FB_A_D36
FB_A_D37
AD30 FBA_D35
FBA_D36
FBA_CMD35 PU for X32 mode FB_B_D36
FB_B_D37
D21 FBB_D35
FBB_D36
FBB_CMD35 PU for X32 mode
AD29 E21
FB_A_D38 AC29 FBA_D37 FB_B_D38 G21 FBB_D37
FB_A_D39 AD28 FBA_D38 +1.35VS_VGA FB_B_D39 F21 FBB_D38 +1.35VS_VGA
FB_A_D40 AJ29 FBA_D39 FB_B_D40 G27 FBB_D39
FB_A_D41 AK29 FBA_D40 FB_B_D41 D27 FBB_D40
FB_A_D42 AJ30 FBA_D41 FB_B_D42 G26 FBB_D41
FBA_D42 FBB_D42

1
1

1
1
FB_A_D43 AK28 FB_B_D43 E27 N17P@
FB_A_D44 AM29 FBA_D43 RV98 RV95 FB_B_D44 E29 FBB_D43 RV99 RV96
FB_A_D45 AM31 FBA_D44 R30 FB_A_CLK0 N17P@ N17P@ FB_B_D45 F29 FBB_D44 D12 FB_B_CLK0 N17P@
FB_A_D46 FBA_D45 FBA_CLK0 FB_A_CLK#0 FB_A_CLK0 <28> FB_B_D46 FBB_D45 FBB_CLK0 FB_B_CLK#0 FB_B_CLK0 <29>
AN29 R31 10K_0402_5% 10K_0402_5% E30 E12 10K_0402_5% 10K_0402_5%
FB_A_D47 FBA_D46 FBA_CLK0_N FB_A_CLK1 FB_A_CLK#0 <28> FB_B_D47 FBB_D46 FBB_CLK0_N FB_B_CLK1 FB_B_CLK#0 <29>
AM30 AB31 D30 E20
FB_A_CLK1 <28> FB_B_CLK1 <29>

2
2

2
2
FB_A_D48 AN31 FBA_D47 FBA_CLK1 AC31 FB_A_CLK#1 FB_A_CMD14 FB_B_D48 A32 FBB_D47 FBB_CLK1 F20 FB_B_CLK#1 FB_B_CMD14
FB_A_D49 FBA_D48 FBA_CLK1_N FB_A_CLK#1 <28> FB_A_CMD30 FB_B_D49 FBB_D48 FBB_CLK1_N FB_B_CLK#1 <29> FB_B_CMD30
AN32 C31
A

FB_A_D50 AP30 FBA_D49 FB_B_D50 C32 FBB_D49

FB_A_D51 AP32 FBA_D50 FB_B_D51 B32 FBB_D50
FB_A_D52 AM33 FBA_D51 K31 FB_A_WCK0 FB_B_D52 D29 FBB_D51 F8 FB_B_WCK0
FB_A_D53 FBA_D52 FBA_WCK01 FB_A_WCK#0 FB_A_WCK0 <28> FB_B_D53 FBB_D52 FBB_WCK01 FB_B_WCK#0 FB_B_WCK0 <29>
AL31 L30 A29 E8
FB_A_D54 FBA_D53 FBA_WCK01_N FB_A_WCK1 FB_A_WCK#0 <28> FB_A_CMD13 FB_B_D54 FBB_D53 FBB_WCK01_N FB_B_WCK1 FB_B_WCK#0 <29> FB_B_CMD13
AK33 H34 C29 A5
FB_A_D55 FBA_D54 FBA_WCK23 FB_A_WCK#1 FB_A_WCK1 <28> FB_A_CMD29 FB_B_D55 FBB_D54 FBB_WCK23 FB_B_WCK#1 FB_B_WCK1 <29> FB_B_CMD29
AK32 J34 B29 A6
FB_A_D56 FBA_D55 FBA_WCK23_N FB_A_WCK2 FB_A_WCK#1 <28> FB_B_D56 FBB_D55 FBB_WCK23_N FB_B_WCK2 FB_B_WCK#1 <29>
AD34 AG30 B21 D24
FBA_D56 FBA_WCK45 FB_A_WCK2 <28> FBB_D56 FBB_WCK45 FB_B_WCK2 <29>

1
1

1
1
FB_A_D57 AD32 AG31 FB_A_WCK#2 FB_B_D57 C23 D25 FB_B_WCK#2
FB_A_D58 FBA_D57 FBA_WCK45_N FB_A_WCK3 FB_A_WCK#2 <28> FB_B_D58 FBB_D57 FBB_WCK45_N FB_B_WCK3 FB_B_WCK#2 <29>
AC30 AJ34 RV107 RV108 A21 B27 RV110 RV111
FB_A_D59 FBA_D58 FBA_WCK67 FB_A_WCK#3 FB_A_WCK3 <28> FB_B_D59 FBB_D58 FBB_WCK67 FB_B_WCK#3 FB_B_WCK3 <29>
AD33 AK34 N17P@ N17P@ C21 C27 N17P@ N17P@
FB_A_D60 FBA_D59 FBA_WCK67_N FB_A_WCK#3 <28> FB_B_D60 FBB_D59 FBB_WCK67_N FB_B_WCK#3 <29>
AF31 10K_0402_5% 10K_0402_5% B24 10K_0402_5% 10K_0402_5%
FB_A_D61 AG34 FBA_D60 FB_B_D61 C24 FBB_D60

2
2

2
2
FB_A_D62 AG32 FBA_D61 FB_B_D62 B26 FBB_D61
FB_A_D63 AG33 FBA_D62 J30 FB_B_D63 C26 FBB_D62 D6
FBA_D63 FBA_WCKB01 J31 +FB_PLLAVDD FBB_D63 FBB_WCKB01 D7

B <28> FB_A_DBI0
FB_A_DBI0
FB_A_DBI1
P30
FBA_DQM0
FBA_WCKB01_N
FBA_WCKB23
J32 50mA <29> FB_B_DBI0
FB_B_DBI0
FB_B_DBI1
E11
FBB_DQM0
FBB_WCKB01_N
FBB_WCKB23
C6
B
F31 J33 E3 B6
<28> FB_A_DBI1 FB_A_DBI2 FBA_DQM1 FBA_WCKB23_N <29> FB_B_DBI1 FB_B_DBI2 FBB_DQM1 FBB_WCKB23_N
F34 AH31 CV152 1 CV938 1 A3 F26
<28> FB_A_DBI2 FB_A_DBI3 FBA_DQM2 FBA_WCKB45 <29> FB_B_DBI2 FB_B_DBI3 FBB_DQM2 FBB_WCKB45
M32 AJ31 N17P@ @ C9 E26
<28> FB_A_DBI3 FB_A_DBI4 FBA_DQM3 FBA_WCKB45_N <29> FB_B_DBI3 FB_B_DBI4 FBB_DQM3 FBB_WCKB45_N
AD31 AJ32 F23 A26
<28> FB_A_DBI4 FBA_DQM4 FBA_WCKB67 <29> FB_B_DBI4 FBB_DQM4 FBB_WCKB67
0.1U_0402_10V7K

0.1U_0402_10V7K

FB_A_DBI5 AL29 AJ33 FB_B_DBI5 F27 A27

<28> FB_A_DBI5 FB_A_DBI6 FBA_DQM5 FBA_WCKB67_N 2 2 <29> FB_B_DBI5 FB_B_DBI6 FBB_DQM5 FBB_WCKB67_N
AM32 C30
<28> FB_A_DBI6 FB_A_DBI7 FBA_DQM6 <29> FB_B_DBI6 FB_B_DBI7 FBB_DQM6
AF34 A24
<28> FB_A_DBI7 FBA_DQM7 <29> FB_B_DBI7 FBB_DQM7
FB_A_EDC0 M31 FB_B_EDC0 D10
FB_A_EDC1 G31 FBA_DQS_WP0 12/21 follow NV spec. FB_B_EDC1 D5 FBB_DQS_WP0
FB_A_EDC2 E33 FBA_DQS_WP1 FB_B_EDC2 C3 FBB_DQS_WP1 +FB_PLLAVDD
FB_A_EDC3
FB_A_EDC4
M33 FBA_DQS_WP2
FBA_DQS_WP3
FB_B_EDC3
FB_B_EDC4
B9 FBB_DQS_WP2
FBB_DQS_WP3
120mA
AE31 K27 E23 H17
FB_A_EDC5 AK30 FBA_DQS_WP4 FB_REFPLL_AVDD FB_B_EDC5 E28 FBB_DQS_WP4 FBB_PLL_AVDD CV153 1
FB_A_EDC6
FB_A_EDC7
AN33 FBA_DQS_WP5
FBA_DQS_WP6
Place close to ball +FB_PLLAVDD +1.8V_GFX_RUN FB_B_EDC6
FB_B_EDC7
B30 FBB_DQS_WP5
FBB_DQS_WP6
N17P@
AF33 LV13 N17P@ A23
FBA_DQS_WP7 120mA 300mA FBB_DQS_WP7

0.1U_0402_10V7K
U27 1 2
M30 FBA_PLL_AVDD CV937 1 CV154 1 CV156 1 BLM15AX300SN1D D9 2
H30 FBA_DQS_RN0 N17P@ N17P@ N17P@ E4 FBB_DQS_RN0
E34 FBA_DQS_RN1 B2 FBB_DQS_RN1
FBA_DQS_RN2 FBB_DQS_RN2
0.1U_0402_10V7K

0.1U_0402_10V7K

22U_0603_6.3V6M

M34 H31 A9
AF30 FBA_DQS_RN3 FB_VREF 2 2 2 D22 FBB_DQS_RN3
AK31 FBA_DQS_RN4 D28 FBB_DQS_RN4
AM34 FBA_DQS_RN5 A30 FBB_DQS_RN5
AF32 FBA_DQS_RN6 B23 FBB_DQS_RN6
FBA_DQS_RN7 FBB_DQS_RN7
Place close to ball
N17P-GT_BGA908 N17P-GT_BGA908

Place close to ball

A
Place close to BGA A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17P_MEM Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 27 of 78
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits

FB_A_D[0..63]
UV6 MF=0 @ UV7 MF=1 @
<27> FB_A_D[0..63] MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0
FB_A_EDC[7..0]
<27> FB_A_EDC[7..0] A4 FB_A_D0 A4 FB_A_D56
FB_A_EDC0 C2 DQ24 DQ0 A2 FB_A_D1 FB_A_EDC7 C2 DQ24 DQ0 A2 FB_A_D57
FB_A_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FB_A_D2 FB_A_EDC6 C13 EDC0 EDC3 DQ25 DQ1 B4 FB_A_D58
FB_A_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FB_A_D3 FB_A_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FB_A_D59

Vinafix.com
FB_A_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FB_A_D4 FB_A_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 FB_A_D60
EDC3 EDC0 DQ28 DQ4 FB_A_D5
BYTE0 EDC3 EDC0 DQ28 DQ4 FB_A_D61
BYTE7
E2 E2
DQ29 DQ5 F4 FB_A_D6 DQ29 DQ5 F4 FB_A_D62
FB_A_DBI0 D2 DQ30 DQ6 F2 FB_A_D7 FB_A_DBI7 D2 DQ30 DQ6 F2 FB_A_D63
<27> FB_A_DBI0 FB_A_DBI1 DBI0# DBI3# DQ31 DQ7 FB_A_D8 <27> FB_A_DBI7 FB_A_DBI6 DBI0# DBI3# DQ31 DQ7 FB_A_D48
D13 A11 D13 A11
D <27> FB_A_DBI1 FB_A_DBI2 DBI1# DBI2# DQ16 DQ8 FB_A_D9 <27> FB_A_DBI6 FB_A_DBI5 DBI1# DBI2# DQ16 DQ8 FB_A_D49 D
P13 A13 P13 A13
<27> FB_A_DBI2 FB_A_DBI3 DBI2# DBI1# DQ17 DQ9 FB_A_D10 <27> FB_A_DBI5 FB_A_DBI4 DBI2# DBI1# DQ17 DQ9 FB_A_D50
P2 B11 P2 B11
<27> FB_A_DBI3 DBI3# DBI0# DQ18 DQ10 FB_A_D11 <27> FB_A_DBI4 DBI3# DBI0# DQ18 DQ10 FB_A_D51
B13 B13
FB_A_CLK0 J12 DQ19 DQ11 E11 FB_A_D12 FB_A_CLK1 J12 DQ19 DQ11 E11 FB_A_D52
<27> FB_A_CLK0 FB_A_CLK#0 CK DQ20 DQ12 FB_A_D13
BYTE1 <27> FB_A_CLK1 FB_A_CLK#1 CK DQ20 DQ12 FB_A_D53
BYTE6
J11 E13 J11 E13
<27> FB_A_CLK#0 FB_A_CMD14 CK# DQ21 DQ13 FB_A_D14 <27> FB_A_CLK#1 FB_A_CMD30 CK# DQ21 DQ13 FB_A_D54
J3 F11 J3 F11
<27> FB_A_CMD14 CKE# DQ22 DQ14 FB_A_D15 <27> FB_A_CMD30 CKE# DQ22 DQ14 FB_A_D55
F13 F13
DQ23 DQ15 U11 FB_A_D16 DQ23 DQ15 U11 FB_A_D40
FB_A_CMD2 H11 DQ8 DQ16 U13 FB_A_D17 FB_A_CMD19 H11 DQ8 DQ16 U13 FB_A_D41
<27> FB_A_CMD2 FB_A_CMD4 BA0/A2 BA2/A4 DQ9 DQ17 FB_A_D18 <27> FB_A_CMD19 FB_A_CMD17 BA0/A2 BA2/A4 DQ9 DQ17 FB_A_D42
K10 T11 K10 T11
<27> FB_A_CMD4 FB_A_CMD3 BA1/A5 BA3/A3 DQ10 DQ18 FB_A_D19 <27> FB_A_CMD17 FB_A_CMD18 BA1/A5 BA3/A3 DQ10 DQ18 FB_A_D43
K11 T13 K11 T13
<27> FB_A_CMD3 FB_A_CMD1 BA2/A4 BA0/A2 DQ11 DQ19 FB_A_D20 <27> FB_A_CMD18 FB_A_CMD20 BA2/A4 BA0/A2 DQ11 DQ19 FB_A_D44
H10 N11 BYTE2 H10 N11 BYTE5
<27> FB_A_CMD1 BA3/A3 BA1/A5 DQ12 DQ20 FB_A_D21 <27> FB_A_CMD20 BA3/A3 BA1/A5 DQ12 DQ20 FB_A_D45
N13 N13
DQ13 DQ21 M11 FB_A_D22 DQ13 DQ21 M11 FB_A_D46
FB_A_CMD6 K4 DQ14 DQ22 M13 FB_A_D23 FB_A_CMD26 K4 DQ14 DQ22 M13 FB_A_D47
<27> FB_A_CMD6 FB_A_CMD11 A8/A7 A10/A0 DQ15 DQ23 FB_A_D24 <27> FB_A_CMD26 FB_A_CMD23 A8/A7 A10/A0 DQ15 DQ23 FB_A_D32
H5 U4 H5 U4
<27> FB_A_CMD11 FB_A_CMD10 A9/A1 A11/A6 DQ0 DQ24 FB_A_D25 <27> FB_A_CMD23 FB_A_CMD22 A9/A1 A11/A6 DQ0 DQ24 FB_A_D33
H4 U2 H4 U2
<27> FB_A_CMD10 FB_A_CMD7 A10/A0 A8/A7 DQ1 DQ25 FB_A_D26 <27> FB_A_CMD22 FB_A_CMD27 A10/A0 A8/A7 DQ1 DQ25 FB_A_D34
K5 T4 K5 T4
<27> FB_A_CMD7 FB_A_CMD9 A11/A6 A9/A1 DQ2 DQ26 FB_A_D27 <27> FB_A_CMD27 FB_A_CMD25 A11/A6 A9/A1 DQ2 DQ26 FB_A_D35
J5 T2 J5 T2
<27> FB_A_CMD9 A12/RFU/NC DQ3 DQ27 FB_A_D28 <27> FB_A_CMD25 A12/RFU/NC DQ3 DQ27 FB_A_D36
N4 BYTE3 N4 BYTE4
A5 DQ4 DQ28 N2 FB_A_D29 A5 DQ4 DQ28 N2 FB_A_D37
U5 VPP/NC DQ5 DQ29 M4 FB_A_D30 U5 VPP/NC DQ5 DQ29 M4 FB_A_D38
VPP/NC DQ6 DQ30 M2 FB_A_D31 +1.35VS_VGA VPP/NC DQ6 DQ30 M2 FB_A_D39
DQ7 DQ31 DQ7 DQ31
RV116 2 N17P@ 1 J1 +1.35VS_VGA RV117 2 N17P@ 1 J1 +1.35VS_VGA
1K_0402_1% J10 MF 1K_0402_1% J10 MF
RV120 2 N17P@ 1 J13 SEN B1 RV121 2 N17P@ 1 J13 SEN B1
121_0402_1% ZQ VDDQ D1 121_0402_1% ZQ VDDQ D1
VDDQ F1 VDDQ F1
FB_A_CMD8 J4 VDDQ M1 FB_A_CMD24 J4 VDDQ M1
<27> FB_A_CMD8 FB_A_CMD12 ABI# VDDQ <27> FB_A_CMD24 FB_A_CMD31 ABI# VDDQ
G3 P1 G3 P1
<27> FB_A_CMD12 FB_A_CMD0 RAS# CAS# VDDQ <27> FB_A_CMD31 FB_A_CMD21 RAS# CAS# VDDQ
G12 T1 G12 T1
<27> FB_A_CMD0 FB_A_CMD15 CS# WE# VDDQ <27> FB_A_CMD21 FB_A_CMD28 CS# WE# VDDQ
L3 G2 L3 G2
<27> FB_A_CMD15 FB_A_CMD5 CAS# RAS# VDDQ <27> FB_A_CMD28 FB_A_CMD16 CAS# RAS# VDDQ
L12 L2 L12 L2
<27> FB_A_CMD5 WE# CS# VDDQ <27> FB_A_CMD16 WE# CS# VDDQ
B3 B3
VDDQ D3 VDDQ D3
VDDQ F3 VDDQ F3
FB_A_WCK#0 D5 VDDQ H3 FB_A_WCK#3 D5 VDDQ H3
<27> FB_A_WCK#0 FB_A_WCK0 WCK01# WCK23# VDDQ <27> FB_A_WCK#3 FB_A_WCK3 WCK01# WCK23# VDDQ
D4 K3 D4 K3
<27> FB_A_WCK0 WCK01 WCK23 VDDQ <27> FB_A_WCK3 WCK01 WCK23 VDDQ
M3 M3
FB_A_WCK#1 P5 VDDQ P3 FB_A_WCK#2 P5 VDDQ P3
<27> FB_A_WCK#1 FB_A_WCK1 WCK23# WCK01# VDDQ <27> FB_A_WCK#2 FB_A_WCK2 WCK23# WCK01# VDDQ
P4 T3 P4 T3
C <27> FB_A_WCK1 WCK23 WCK01 VDDQ <27> FB_A_WCK2 WCK23 WCK01 VDDQ C
E5 E5
+FBA_VREFC0 VDDQ N5 +FBA_VREFC0 VDDQ N5
A10 VDDQ E10 A10 VDDQ E10
1 VREFD VDDQ 1 VREFD VDDQ
CV158 U10 N10 CV200 U10 N10
N17P@ +FBA_VREFC0 J14 VREFD VDDQ B12 N17P@ +FBA_VREFC0 J14 VREFD VDDQ B12
820P_0402_25V7 VREFC VDDQ D12 820P_0402_25V7 VREFC VDDQ D12
2 VDDQ F12 2 VDDQ F12
VDDQ H12 VDDQ H12
FB_A_CMD13 J2 VDDQ K12 FB_A_CMD29 J2 VDDQ K12
<27> FB_A_CMD13 RESET# VDDQ <27> FB_A_CMD29 RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
FB_A_CLK0 K1 VSS VDDQ B14 FB_A_CLK1 K1 VSS VDDQ B14
FB_A_CLK#0 B5 VSS VDDQ D14 FB_A_CLK#1 B5 VSS VDDQ D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
VSS VDDQ VSS VDDQ
1
1

1
1
L5 M14 L5 M14
RV594 RV595 T5 VSS VDDQ P14 RV596 RV597 T5 VSS VDDQ P14
N17P@ N17P@ B10 VSS VDDQ T14 N17P@ N17P@ B10 VSS VDDQ T14
40.2_0402_1% 40.2_0402_1% D10 VSS VDDQ 40.2_0402_1% 40.2_0402_1% D10 VSS VDDQ
G10 VSS G10 VSS
2
2

2
2
L10 VSS A1 L10 VSS A1
P10 VSS VSSQ C1 P10 VSS VSSQ C1
1 VSS VSSQ 1 VSS VSSQ
CV903 T10 E1 CV904 T10 E1
N17P@ H14 VSS VSSQ N1 N17P@ H14 VSS VSSQ N1
0.01U_0402_16V7K K14 VSS VSSQ R1 0.01U_0402_16V7K K14 VSS VSSQ R1
2 +1.35VS_VGA VSS VSSQ U1 2 +1.35VS_VGA VSS VSSQ U1
VSSQ H2 VSSQ H2
G1 VSSQ K2 G1 VSSQ K2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
MEM_VREF levels G4 VDD VSSQ C3 G4 VDD VSSQ C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
70% of rail Termination Enable C5 VDD VSSQ N3 C5 VDD VSSQ N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
50% of rail Termination Disable C10 VDD VSSQ U3 C10 VDD VSSQ U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
L11 VDD VSSQ M5 L11 VDD VSSQ M5
+1.35VS_VGA P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
B B
L14 VDD VSSQ C11 L14 VDD VSSQ C11
VDD VSSQ VDD VSSQ
1

R11 R11
RV125 VSSQ A12 VSSQ A12
N17P@ VSSQ C12 VSSQ C12
549_0402_1% VSSQ E12 VSSQ E12
W=16mils VSSQ N12 VSSQ N12
2

RV126 1 N17P@ 2 +FBA_VREFC0 VSSQ R12 VSSQ R12

931_0402_1% 170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ VSSQ
1

H13 H13
RV127 SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
QV20 N17P@ VSSQ A14 VSSQ A14
VSSQ VSSQ
1

D 1.33K_0402_1% C14 C14

MEM_VREF 2 N17P@ VSSQ E14 VSSQ E14
<23,29> MEM_VREF
2

G VSSQ N14 VSSQ N14

BSS138W 1N SOT-323-3 VSSQ R14 VSSQ R14
S
3

VSSQ U14 VSSQ U14

VSSQ VSSQ
H5GC4H24MFR-T2C H5GC4H24MFR-T2C

+1.35VS_VGA +1.35VS_VGA
Around DRAM Close to DRAM Around DRAM Close to DRAM
CV863 1 CV859 1 CV860 1 CV861 1 CV862 1 CV373 1 CV160 1 CV161 1 CV162 1 CV163 1 CV164 1 CV165 1 CV166 1 CV167 1 CV375 1 CV374 1 CV376 1 CV378 1 CV377 1 CV379 1 CV380 1 CV868 1 CV865 1 CV864 1 CV867 1 CV866 1 CV381 1 CV168 1 CV169 1 CV170 1 CV171 1 CV172 1 CV173 1 CV174 1 CV175 1 CV384 1 CV383 1 CV382 1 CV387 1 CV386 1 CV385 1 CV388 1
N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

+1.35VS_VGA +1.35VS_VGA
Under DRAM Under DRAM
CV869 1 CV870 1 CV871 1 CV872 1 CV873 1 CV874 1 CV875 1 CV876 1 VDDQ CV851 1 CV852 1 CV853 1 CV854 1 CV855 1 CV856 1 CV857 1 CV858 1 VDDQ
A
N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ Under GPU N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ Under GPU A
1uF x 18 1uF x 18
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10uF x 4 10uF x 4
Near GPU Near GPU
10uF x 2 10uF x 2
22uF x 5 22uF x 5

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17P_GDDR5_A
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 28 of 78
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits

FB_B_D[0..63]
UV8 MF=0 @ UV9 MF=1 @
<27> FB_B_D[0..63] MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0
FB_B_EDC[7..0]
<27> FB_B_EDC[7..0] A4 FB_B_D0 A4 FB_B_D56
FB_B_EDC0 C2 DQ24 DQ0 A2 FB_B_D1 FB_B_EDC7 C2 DQ24 DQ0 A2 FB_B_D57
FB_B_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FB_B_D2 FB_B_EDC6 C13 EDC0 EDC3 DQ25 DQ1 B4 FB_B_D58
FB_B_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FB_B_D3 FB_B_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FB_B_D59

Vinafix.com
FB_B_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FB_B_D4 FB_B_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 FB_B_D60
EDC3 EDC0 DQ28 DQ4 FB_B_D5
BYTE0 EDC3 EDC0 DQ28 DQ4 FB_B_D61
BYTE7
E2 E2
DQ29 DQ5 F4 FB_B_D6 DQ29 DQ5 F4 FB_B_D62
FB_B_DBI0 D2 DQ30 DQ6 F2 FB_B_D7 FB_B_DBI7 D2 DQ30 DQ6 F2 FB_B_D63
<27> FB_B_DBI0 FB_B_DBI1 DBI0# DBI3# DQ31 DQ7 FB_B_D8 <27> FB_B_DBI7 FB_B_DBI6 DBI0# DBI3# DQ31 DQ7 FB_B_D48
D13 A11 D13 A11
D <27> FB_B_DBI1 FB_B_DBI2 DBI1# DBI2# DQ16 DQ8 FB_B_D9 <27> FB_B_DBI6 FB_B_DBI5 DBI1# DBI2# DQ16 DQ8 FB_B_D49 D
P13 A13 P13 A13
<27> FB_B_DBI2 FB_B_DBI3 DBI2# DBI1# DQ17 DQ9 FB_B_D10 <27> FB_B_DBI5 FB_B_DBI4 DBI2# DBI1# DQ17 DQ9 FB_B_D50
P2 B11 P2 B11
<27> FB_B_DBI3 DBI3# DBI0# DQ18 DQ10 FB_B_D11 <27> FB_B_DBI4 DBI3# DBI0# DQ18 DQ10 FB_B_D51
B13 B13
FB_B_CLK0 J12 DQ19 DQ11 E11 FB_B_D12 FB_B_CLK1 J12 DQ19 DQ11 E11 FB_B_D52
<27> FB_B_CLK0 FB_B_CLK#0 CK DQ20 DQ12 FB_B_D13
BYTE1 <27> FB_B_CLK1 FB_B_CLK#1 CK DQ20 DQ12 FB_B_D53
BYTE6
J11 E13 J11 E13
<27> FB_B_CLK#0 FB_B_CMD14 CK# DQ21 DQ13 FB_B_D14 <27> FB_B_CLK#1 FB_B_CMD30 CK# DQ21 DQ13 FB_B_D54
J3 F11 J3 F11
<27> FB_B_CMD14 CKE# DQ22 DQ14 FB_B_D15 <27> FB_B_CMD30 CKE# DQ22 DQ14 FB_B_D55
F13 F13
DQ23 DQ15 U11 FB_B_D16 DQ23 DQ15 U11 FB_B_D40
FB_B_CMD2 H11 DQ8 DQ16 U13 FB_B_D17 FB_B_CMD19 H11 DQ8 DQ16 U13 FB_B_D41
<27> FB_B_CMD2 FB_B_CMD4 BA0/A2 BA2/A4 DQ9 DQ17 FB_B_D18 <27> FB_B_CMD19 FB_B_CMD17 BA0/A2 BA2/A4 DQ9 DQ17 FB_B_D42
K10 T11 K10 T11
<27> FB_B_CMD4 FB_B_CMD3 BA1/A5 BA3/A3 DQ10 DQ18 FB_B_D19 <27> FB_B_CMD17 FB_B_CMD18 BA1/A5 BA3/A3 DQ10 DQ18 FB_B_D43
K11 T13 K11 T13
<27> FB_B_CMD3 FB_B_CMD1 BA2/A4 BA0/A2 DQ11 DQ19 FB_B_D20 <27> FB_B_CMD18 FB_B_CMD20 BA2/A4 BA0/A2 DQ11 DQ19 FB_B_D44
H10 N11 BYTE2 H10 N11 BYTE5
<27> FB_B_CMD1 BA3/A3 BA1/A5 DQ12 DQ20 FB_B_D21 <27> FB_B_CMD20 BA3/A3 BA1/A5 DQ12 DQ20 FB_B_D45
N13 N13
DQ13 DQ21 M11 FB_B_D22 DQ13 DQ21 M11 FB_B_D46
FB_B_CMD6 K4 DQ14 DQ22 M13 FB_B_D23 FB_B_CMD26 K4 DQ14 DQ22 M13 FB_B_D47
<27> FB_B_CMD6 FB_B_CMD11 A8/A7 A10/A0 DQ15 DQ23 FB_B_D24 <27> FB_B_CMD26 FB_B_CMD23 A8/A7 A10/A0 DQ15 DQ23 FB_B_D32
H5 U4 H5 U4
<27> FB_B_CMD11 FB_B_CMD10 A9/A1 A11/A6 DQ0 DQ24 FB_B_D25 <27> FB_B_CMD23 FB_B_CMD22 A9/A1 A11/A6 DQ0 DQ24 FB_B_D33
H4 U2 H4 U2
<27> FB_B_CMD10 FB_B_CMD7 A10/A0 A8/A7 DQ1 DQ25 FB_B_D26 <27> FB_B_CMD22 FB_B_CMD27 A10/A0 A8/A7 DQ1 DQ25 FB_B_D34
K5 T4 K5 T4
<27> FB_B_CMD7 FB_B_CMD9 A11/A6 A9/A1 DQ2 DQ26 FB_B_D27 <27> FB_B_CMD27 FB_B_CMD25 A11/A6 A9/A1 DQ2 DQ26 FB_B_D35
J5 T2 J5 T2
<27> FB_B_CMD9 A12/RFU/NC DQ3 DQ27 FB_B_D28 <27> FB_B_CMD25 A12/RFU/NC DQ3 DQ27 FB_B_D36
N4 BYTE3 N4 BYTE4
A5 DQ4 DQ28 N2 FB_B_D29 A5 DQ4 DQ28 N2 FB_B_D37
U5 VPP/NC DQ5 DQ29 M4 FB_B_D30 U5 VPP/NC DQ5 DQ29 M4 FB_B_D38
VPP/NC DQ6 DQ30 M2 FB_B_D31 +1.35VS_VGA VPP/NC DQ6 DQ30 M2 FB_B_D39
DQ7 DQ31 DQ7 DQ31
RV132 2 N17P@ 1 J1 +1.35VS_VGA RV131 2 N17P@ 1 J1 +1.35VS_VGA
1K_0402_1% J10 MF 1K_0402_1% J10 MF
RV136 2 N17P@ 1 J13 SEN B1 RV135 2 N17P@ 1 J13 SEN B1
121_0402_1% ZQ VDDQ D1 121_0402_1% ZQ VDDQ D1
VDDQ F1 VDDQ F1
FB_B_CMD8 J4 VDDQ M1 FB_B_CMD24 J4 VDDQ M1
<27> FB_B_CMD8 FB_B_CMD12 ABI# VDDQ <27> FB_B_CMD24 FB_B_CMD31 ABI# VDDQ
G3 P1 G3 P1
<27> FB_B_CMD12 FB_B_CMD0 RAS# CAS# VDDQ <27> FB_B_CMD31 FB_B_CMD21 RAS# CAS# VDDQ
G12 T1 G12 T1
<27> FB_B_CMD0 FB_B_CMD15 CS# WE# VDDQ <27> FB_B_CMD21 FB_B_CMD28 CS# WE# VDDQ
L3 G2 L3 G2
<27> FB_B_CMD15 FB_B_CMD5 CAS# RAS# VDDQ <27> FB_B_CMD28 FB_B_CMD16 CAS# RAS# VDDQ
L12 L2 L12 L2
<27> FB_B_CMD5 WE# CS# VDDQ <27> FB_B_CMD16 WE# CS# VDDQ
B3 B3
VDDQ D3 VDDQ D3
VDDQ F3 VDDQ F3
FB_B_WCK#0 D5 VDDQ H3 FB_B_WCK#3 D5 VDDQ H3
<27> FB_B_WCK#0 FB_B_WCK0 WCK01# WCK23# VDDQ <27> FB_B_WCK#3 FB_B_WCK3 WCK01# WCK23# VDDQ
D4 K3 D4 K3
<27> FB_B_WCK0 WCK01 WCK23 VDDQ <27> FB_B_WCK3 WCK01 WCK23 VDDQ
M3 M3
FB_B_WCK#1 P5 VDDQ P3 FB_B_WCK#2 P5 VDDQ P3
<27> FB_B_WCK#1 FB_B_WCK1 WCK23# WCK01# VDDQ <27> FB_B_WCK#2 FB_B_WCK2 WCK23# WCK01# VDDQ
P4 T3 P4 T3
C <27> FB_B_WCK1 WCK23 WCK01 VDDQ <27> FB_B_WCK2 WCK23 WCK01 VDDQ C
E5 E5
+FBC_VREFC1 VDDQ N5 +FBC_VREFC1 VDDQ N5
A10 VDDQ E10 A10 VDDQ E10
1 VREFD VDDQ 1 VREFD VDDQ
CV177 U10 N10 CV199 U10 N10
N17P@ +FBC_VREFC1 J14 VREFD VDDQ B12 N17P@ +FBC_VREFC1 J14 VREFD VDDQ B12
820P_0402_25V7 VREFC VDDQ D12 820P_0402_25V7 VREFC VDDQ D12
2 VDDQ F12 2 VDDQ F12
VDDQ H12 VDDQ H12
FB_B_CMD13 J2 VDDQ K12 FB_B_CMD29 J2 VDDQ K12
<27> FB_B_CMD13 RESET# VDDQ <27> FB_B_CMD29 RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
FB_B_CLK0 K1 VSS VDDQ B14 FB_B_CLK1 K1 VSS VDDQ B14
FB_B_CLK#0 B5 VSS VDDQ D14 FB_B_CLK#1 B5 VSS VDDQ D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
VSS VDDQ VSS VDDQ
1
1

1
1
L5 M14 L5 M14
RV598 RV599 T5 VSS VDDQ P14 RV600 RV601 T5 VSS VDDQ P14
N17P@ N17P@ B10 VSS VDDQ T14 N17P@ N17P@ B10 VSS VDDQ T14
40.2_0402_1% 40.2_0402_1% D10 VSS VDDQ 40.2_0402_1% 40.2_0402_1% D10 VSS VDDQ
G10 VSS G10 VSS
2
2

2
2
L10 VSS A1 L10 VSS A1
P10 VSS VSSQ C1 P10 VSS VSSQ C1
1 VSS VSSQ 1 VSS VSSQ
CV905 T10 E1 CV906 T10 E1
N17P@ H14 VSS VSSQ N1 N17P@ H14 VSS VSSQ N1
0.01U_0402_16V7K K14 VSS VSSQ R1 0.01U_0402_16V7K K14 VSS VSSQ R1
2 +1.35VS_VGA VSS VSSQ U1 2 +1.35VS_VGA VSS VSSQ U1
VSSQ H2 VSSQ H2
G1 VSSQ K2 G1 VSSQ K2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
MEM_VREF levels G4 VDD VSSQ C3 G4 VDD VSSQ C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
70% of rail Termination Enable C5 VDD VSSQ N3 C5 VDD VSSQ N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
50% of rail Termination Disable C10 VDD VSSQ U3 C10 VDD VSSQ U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
L11 VDD VSSQ M5 L11 VDD VSSQ M5
+1.35VS_VGA P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
B B
L14 VDD VSSQ C11 L14 VDD VSSQ C11
VDD VSSQ VDD VSSQ
1

R11 R11
RV140 VSSQ A12 VSSQ A12
N17P@ VSSQ C12 VSSQ C12
549_0402_1% VSSQ E12 VSSQ E12
W=16mils VSSQ N12 VSSQ N12
2

RV141 1 N17P@ 2 +FBC_VREFC1 VSSQ R12 VSSQ R12

931_0402_1% 170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ VSSQ
1

H13 H13
RV142 SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
QV21 N17P@ VSSQ A14 VSSQ A14
VSSQ VSSQ
1

D 1.33K_0402_1% C14 C14

MEM_VREF 2 N17P@ VSSQ E14 VSSQ E14
<23,28> MEM_VREF
2

G VSSQ N14 VSSQ N14

BSS138W 1N SOT-323-3 VSSQ R14 VSSQ R14
S
3

VSSQ U14 VSSQ U14

VSSQ VSSQ
H5GC4H24MFR-T2C H5GC4H24MFR-T2C

+1.35VS_VGA +1.35VS_VGA
Around DRAM Close to DRAM Around DRAM Close to DRAM
CV889 1 CV886 1 CV885 1 CV888 1 CV887 1 CV182 1 CV183 1 CV389 1 CV179 1 CV180 1 CV181 1 CV184 1 CV185 1 CV186 1 CV392 1 CV390 1 CV391 1 CV395 1 CV393 1 CV394 1 CV396 1 CV894 1 CV891 1 CV890 1 CV893 1 CV892 1 CV187 1 CV397 1 CV188 1 CV189 1 CV190 1 CV191 1 CV192 1 CV193 1 CV194 1 CV399 1 CV400 1 CV398 1 CV402 1 CV403 1 CV401 1 CV404 1
N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

+1.35VS_VGA +1.35VS_VGA
Under DRAM Under DRAM
CV895 1 CV896 1 CV897 1 CV898 1 CV899 1 CV900 1 CV901 1 CV902 1 VDDQ CV877 1 CV878 1 CV879 1 CV880 1 CV881 1 CV882 1 CV883 1 CV884 1 VDDQ
A
N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ Under GPU N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ Under GPU A
1uF x 18 1uF x 18
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10uF x 4 10uF x 4
Near GPU Near GPU
10uF x 2 10uF x 2
22uF x 5 22uF x 5

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17P_GDDR5_B
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 29 of 78
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

+1.8V_GFX_AON

2
RV146 RV147 RV148 RV149 RV150 RV593
@ @ @ @ @ @
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%

1
STRAP0
<24> STRAP0
STRAP1
<24> STRAP1
STRAP2
C <24> STRAP2 C
STRAP3
<24> STRAP3
STRAP4
<24> STRAP4
STRAP5
<24> STRAP5

2
RV152 RV153 RV154 RV155 RV156 RV66
@ @ @ N17P@ N17P@ N17P@
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%

1
B B

+1.8V_GFX_AON

2
RV157 RV158 RV159
N17P@ N17P@ N17P@
100K_0402_5% 100K_0402_5% 100K_0402_5%
1

1
ROM_SI
<24> ROM_SI ROM_SO
<24> ROM_SO ROM_SCLK
<24> ROM_SCLK
2

2
SMB_ALT_ADDR RV160 RV161 RV162
@ @ @
Low Single GPU 100K_0402_5% 100K_0402_5% 100K_0402_5%
High Dual GPU
1

1
DEVID_SEL
Low Original Device ID
A
High Re-brand Device ID A

VGA_DEVICE
Low 3D Device
High VGA Device

PCIE_CFG
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title
Low Normal signal swing N17P_MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
High Reduce the signal amplitude AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 30 of 78
5 4 3 2 1
 5 4 3 2 1

+3VALW +1.35VS_VGA +5VALW +1.8V_GFX_AON

+1.8V_GFX_RUN Discharge

1
RZ12 RZ8 RV534 RZ11
N17P@ N17P@ N17P@ N17P@
100K_0402_5% 10_0402_1% 100K_0402_5% 100_0402_5%
+1.8V_PRIM UZ17 N17P@ +1.8V_GFX_RUN

2
1 8
2 VIN VOUT 7
VIN VOUT

3
1 1 QZ12A QZ12B

6
Vinafix.com
CV573 1V8_RUN_EN 3 6 CZ95 1 2 CZ98 QZ6B QZ6A
N17P@ EN CT @ 2200P_0402_25V7K N17P@ RV399
0.1U_0402_10V7K 4 5 0.1U_0402_10V6K DGPU_PWR_EN_R 2 DGPU_PWR_EN# 1 @ 2 DGPU_PWR_EN#_R 5
2 +5VALW VBIAS GND 2
9 FBVDD_EN 5 2 N17P@ 0_0402_5% 1 N17P@
GND <23,69> FBVDD_EN
N17P@ N17P@ DMN63D8LDW-7 2N SOT363-6 CV499 DMN63D8LDW-7 2N SOT363-6

4
D D
FA7607OTR_DFN_8P DMN63D8LDW-7 2N SOT363-6 @

1
APE8937GN2_DFN8_2X2 DMN63D8LDW-7 2N SOT363-6 0.1U_0402_10V7K
2
SA00009PI00
DV14 N17P@
1V8_MAIN_EN 1 @ 2 1V8_RUN_EN 2 1 DGPU_PWR_EN_R
<23> 1V8_MAIN_EN
RZ106 0_0402_5%
RB751S40_SOD523-2
AZ5125-01HPR7G_SOD523-2

+3VALW
DVT1.
Add UV23 AND Gate for GPU power sequence. N17P@

5
UV23

VCC
DGPU_PWR_EN 1 +3VALW +GPU_CORE_VDDS +1VS_GFX +3VALW +GPU_CORE +3VALW +1.8V_GFX_RUN
<17> DGPU_PWR_EN IN1 DGPU_PWR_EN_R
4
SIO_SLP_S3# 2 OUT

GND
<15,33,35,36,54,55,62> SIO_SLP_S3# IN2

1
RZ103 RZ9 RZ73 RZ104 RZ10 RZ105 RZ100
MC74VHC1G08DFT2G_SC70-5 N17P@ N17P@ N17P@ N17P@ N17P@ N17P@ N17P@

3
SA00000OH00 100K_0402_5% 10_0402_1% 10_0402_1% 100K_0402_5% 10_0402_1% 100K_0402_5% 10_0402_1%

2
DMN63D8LDW-7 2N SOT363-6
CV923 1 CV924 1 CV925 1
+1.8V_GFX_AON @ @ @

3
N17P@

3
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
QZ8A QZ8B QZ11

1
2 D QZ7A 2 QZ7B QZ10A 2 QZ10B
5 2
NVVDDS_EN 2 G NVVDD_EN 2 5 1V8_MAIN_EN 2 5
+1.8V_PRIM +5VALW UZ24 N17P@ +1.8V_GFX_AON N17P@ N17P@ S N17P@ N17P@ N17P@ N17P@

3
1

4
1 8 DMN63D8LDW-7 2N SOT363-6 L2N7002WT1G_SC-70-3 DMN63D8LDW-7 2N SOT363-6 DMN63D8LDW-7 2N SOT363-6
C CV920 2 VIN VOUT 7 DMN63D8LDW-7 2N SOT363-6 DMN63D8LDW-7 2N SOT363-6 C
1 VIN VOUT
N17P@ 1
3 6 CZ104 1 2 CZ103
EN CT
0.1U_0402_10V7K

@ 2200P_0402_25V7K N17P@
2 4 5 0.1U_0402_10V6K
VBIAS GND 9 2
GND
FA7607OTR_DFN_8P
APE8937GN2_DFN8_2X2
SA00009PI00
2 @ 1 DGPU_PWR_EN_R
0_0402_5% RV617
GPU Power Up Sequence GPU GC6 Entry Sequence GPU GC6 Exit Sequence
1

1
CV921 RV618
@ N17P@
0.1U_0402_10V7K 1M_0402_5%
2
2

+3VS +3VS
1

RZ109 RZ110
N17P@ N17P@
100K_0402_5% 100K_0402_5%
2

1V8_EN_LS3V3

B N17P@ N17P@ B
6

QV92A QV92B

2 5 1V8_MAIN_EN
DMN63D8LDW-7 2N SOT363-6
DMN63D8LDW-7 2N SOT363-6
1

GPU Power Down Sequence

+3VS

NVVDDS Enable CV917 1 2

N17P@ 0.1U_0402_25V6
5

UV21 N17P@
VCC

1 RV606 1 @ 2 1V8_EN_LS3V3
NVVDDS_EN 4 IN1 0_0402_5%
<66,68> NVVDDS_EN OUT GPU_CORE_PG
2
GND

IN2 GPU_CORE_PG <67>

1
1

CV918 RV607
@ N17P@ MC74VHC1G08DFT2G_SC70-5
3

0.01UF_0402_25V7K 1M_0402_5% SA00000OH00

2

Enable 1.2V
Disable 0.55V

A A
NVVDD Enable
N17P@
RV608
10K_0402_5%
NVVDD_EN 1 2 1V8_MAIN_EN
<67> NVVDD_EN
1

CV919
N17P@ Security Classification Compal Secret Data Compal Electronics, Inc.
0.01UF_0402_25V7K Enable 1.2V Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title
2

Disable 0.55V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GPU DC/DC interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 31 of 78
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

Reserved
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/06 Title
2017/01/06 Deciphered Date Reserve
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 32 of 78
5 4 3 2 1
 5 4 3 2 1

+1.2V_RTM +3VS +3V_RTM +3V_RTM +3V_RTM +3V_RTM

DVT1. RP28 1 @ 2 IFPC_I2C_8409_DAT RP24 1 2

+1.2V_VCCPLL_OC
Remove QZ2.
+1.2V_RTM Vinafix.com 1 1 0_0402_5%
CP24 1 CP25
PS8409@ PS8409@
1 CP26
PS8409@
1
IFPC_I2C_8409_CLK
@PS8409@ 47K_0402_5%
RP25 1 2

@PS8409@
@PS8409@
22U_0603_6.3V6M
CP28

22U_0603_6.3V6M
CP29
@PS8409@ 47K_0402_5%

0.1U_0402_10V6K

0.01U_0402_16V7K

0.1U_0402_10V6K
D 2 2 2 D
2 2 12/12 Add
RTM_CSCL RP48 1 2
@PS8409@ 10K_0402_5%
RTM_CSDA RP49 1 2
@PS8409@ 10K_0402_5%
RP31 1 @ 2
Close Pin 24 Close Pin 1
0_0402_5%

+1.2V_RTM +1.2V_RTM +3V_RTM

UP2 PS8409@
30 1
CP3 6 VDD12 VDD33 24
1 CP4 1 VDD12 VDD33
PS8409@ PS8409@ 11
43 VDDA12
VDDRX12
0.01U_0402_16V7K

0.1U_0402_10V6K

46 23 HDMI_RT_TX_P2
2 2 VDDRX12 OUT_D2p HDMI_RT_TX_N2 HDMI_RT_TX_P2 <34>
15 22
VDDTX12 OUT_D2n HDMI_RT_TX_N2 <34>
18
37 VDDTX12 20 HDMI_RT_TX_P1
POWERSWITCH OUT_D1p HDMI_RT_TX_N1 HDMI_RT_TX_P1 <34>
PS8409@ 19
GPU_IFPC_P0 HDMI_TX_P2 OUT_D1n HDMI_RT_TX_N1 <34> HDMI_RT_CLKP
CP17 1 2 0.1U_0402_10V6K 38
<24> GPU_IFPC_P0 GPU_IFPC_N0 HDMI_TX_N2 IN_D2p HDMI_RT_TX_P0
CP18 1 2 0.1U_0402_10V6K 39 17 1
<24> GPU_IFPC_N0 IN_D2n OUT_D0p HDMI_RT_TX_N0 HDMI_RT_TX_P0 <34>
PS8409@ PS8409@ 16 CP23
GPU_IFPC_P1 HDMI_TX_P1 OUT_D0n HDMI_RT_TX_N0 <34>
Close Pin 30 CP19 1 2 0.1U_0402_10V6K 41 @PS8409@
<24> GPU_IFPC_P1 GPU_IFPC_N1 HDMI_TX_N1 IN_D1p HDMI_RT_CLKP
CP20 1 2 0.1U_0402_10V6K 42 14 0.1U_0402_10V6K
C <24> GPU_IFPC_N1 IN_D1n OUT_CKp HDMI_RT_CLKN HDMI_RT_CLKP <34> HDMI_RT_CLKN 2 C
PS8409@ PS8409@ 13
GPU_IFPC_P2 HDMI_TX_P0 OUT_CKn HDMI_RT_CLKN <34>
CP22 1 2 0.1U_0402_10V6K 44
+1.2V_RTM <24> GPU_IFPC_P2 GPU_IFPC_N2 HDMI_TX_N0 IN_D0p IFPC_I2C_8409_DAT
CP21 1 2 0.1U_0402_10V6K 45 33
<24> GPU_IFPC_N2 IN_D0n SDA_SRC/AUXN IFPC_I2C_8409_CLK IFPC_I2C_8409_DAT <24>
PS8409@ PS8409@ 34
GPU_IFPC_P3 HDMI_CLKP SCL_SRC/AUXP HDMI_CTRL_DAT IFPC_I2C_8409_CLK <24>
CP16 1 2 0.1U_0402_10V6K 47 8
<24> GPU_IFPC_P3 GPU_IFPC_N3 HDMI_CLKN IN_CKp SDA_SNK HDMI_CTRL_CLK HDMI_CTRL_DAT <24,34>
CP5 1 CP6 1 CP7 1 CP15 1 2 0.1U_0402_10V6K 48 7
<24> GPU_IFPC_N3 IN_CKn SCL_SNK HDMI_CTRL_CLK <24,34>
PS8409@ PS8409@ PS8409@ PS8409@
0.1U_0402_10V6K

0.1U_0402_10V6K

0.01U_0402_16V7K

RTM_DCIN_ENB 3 40 PS8409@ RP45 1 2 1K_0402_5% GPU_HPD_RT

2 2 2 RTM_EQ DCIN_EN HPD_SRC HDMI_HPD GPU_HPD_RT <23>
5 21
RTM_I2C_ADDR EQ HPD_SNK HDMI_HPD <34>
@ T4951 31
I2C_ADDR
10
25 RSV1 32 RTM_HDMI_ID T4952@
26 NC HDMI_ID 9 @PS8409@ RP11 1 2 0_0402_5% HDMI_CEC
RSV2 HDMI_CEC HDMI_CEC <34>
12
CEC_EN
Close Pin 6,11
36 29 RTM_CSCL
RTM_PDB 4 REXT CSCL 28 RTM_CSDA
RTM_RST# 35 PDB CSDA
+1.2V_RTM RESETB

10K_0402_5%

4.99K_0402_1%
RTM_PRE 27
PRE

1
1 2 49
TESTMODEB EPAD

PS8409@
RP39

PS8409@
RP32
CP27
CP8 1 CP9 1 CP11 1 CP10 1 PS8409@
PS8409@ PS8409@ PS8409@ PS8409@ 1U_0402_6.3V6K PS8409AQFN48GTR2-A2 QFN48P
+3V_RTM 2
SA0000AC320

2
4.7U_0603_6.3V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.01U_0402_16V7K

2 2 2 2 RP35 1 2 RTM_RST#
PS8409@ 10K_0402_5%

RP44 1 2 RTM_PDB
B @PS8409@ 10K_0402_5% B

Close Pin 43,46

+1.2V_RTM
+3V_RTM

CP13 1 CP12 1 CP14 1

PS8409@ PS8409@ PS8409@ +3VS
1

1
0.1U_0402_10V6K

0.1U_0402_10V6K

0.01U_0402_16V7K

RP34 RP37

1
2 2 2 @PS8409@ @PS8409@ QP1 C RP46
10K_0402_5% 10K_0402_5% 2 1 2 HDMI_HPD
B 150K_0402_5%
2

RTM_EQ S TR METR3904W-G NPN SOT323-3 E CP30 1

3
RTM_PRE
2

0.1U_0402_16V7K
HDMI_HPD_PCH
<17> HDMI_HPD_PCH 2
Close Pin 15,18 RP40 RP42
@PS8409@ @PS8409@
10K_0402_5% 10K_0402_5%
1

A A

Title

HDMI Retimer-PS8409
Size Document Number Rev
Custom 1.0(A00)
LA-E993P
Date: Tuesday, March 06, 2018 Sheet 33 of 78
5 4 3 2 1
 5 4 3 2 1

Vinafix.com DVT1.
Move RV554, RV557, RV562, RV565
D
Place close to JHDMI1 close to HDMI onnector. +5VS UV17 +VDISPLAY_VCC D

3
W=40mils
HDMI_RT_CLKP RV609 1 EMI@ 2 HDMI_L_CLKP OUT CV598 1 CV597 1
<33> HDMI_RT_CLKP
2.2_0402_1% 1
PANAS_EXC24CG900U_4P-NPM IN

0.1U_0402_10V6K

10U_0603_6.3V6M
LV23 @EMI@ 2
GND

1
4 3 2 2
4 3 RV554
SM070002R00 @EMI@ AP2330W-7_SC59-3
1 2 300_0402_5%
1 2 SA00004ZA00

2
EXC24CG900U_4P

HDMI_RT_CLKN RV610 1 EMI@ 2 HDMI_L_CLKN

<33> HDMI_RT_CLKN
2.2_0402_1%

HDMI_RT_TX_P0 RV611 1 EMI@ 2 HDMI_L_TX_P0

<33> HDMI_RT_TX_P0
2.2_0402_1%
PANAS_EXC24CG900U_4P-NPM
LV24 @EMI@

1
4 3
4 3 RV557
SM070002R00 @EMI@
1 2 300_0402_5%
1 2
HDMI conn

2
EXC24CG900U_4P

C HDMI_RT_TX_N0 RV612 1 EMI@ 2 HDMI_L_TX_N0 +VDISPLAY_VCC C

<33> HDMI_RT_TX_N0
2.2_0402_1% JHDMI1
HDMI_HPD 19
<33> HDMI_HPD HP_DET
18
HDMI_RT_TX_P1 RV613 1 EMI@ 2 HDMI_L_TX_P1 17 +5V
<33> HDMI_RT_TX_P1 HDMI_CTRL_DAT DDC/CEC_GND
2.2_0402_1% 16
PANAS_EXC24CG900U_4P-NPM <24,33> HDMI_CTRL_DAT HDMI_CTRL_CLK 15 SDA
<24,33> HDMI_CTRL_CLK HDMI_Reserved SCL
LV25 @EMI@ 14
Reserved

1
4 3 HDMI_CEC 13
4 3 <33> HDMI_CEC HDMI_L_CLKN CEC
RV562 12
@EMI@ 11 CK-
SM070002R00 CK_shield
1 2 300_0402_5% HDMI_L_CLKP 10
1 2 HDMI_L_TX_N0 9 CK+

2
EXC24CG900U_4P 8 D0-
HDMI_L_TX_P0 7 D0_shield
HDMI_RT_TX_N1 RV614 1 EMI@ 2 HDMI_L_TX_N1 HDMI_L_TX_N1 6 D0+
<33> HDMI_RT_TX_N1 D1-
2.2_0402_1% 5
HDMI_L_TX_P1 4 D1_shield 20
HDMI_L_TX_N2 3 D1+ GND1 21
HDMI_RT_TX_P2 RV615 1 EMI@ 2 HDMI_L_TX_P2 2 D2- GND2 22
<33> HDMI_RT_TX_P2 HDMI_L_TX_P2 D2_shield GND3
2.2_0402_1% 1 23
PANAS_EXC24CG900U_4P-NPM D2+ GND4
LV26 @EMI@ CONCR_099A3AC19JBLCNF

1
4 3 CONN@
4 3 RV565
@EMI@
DC232003400
SM070002R00
1 2 300_0402_5%
1 2

2
EXC24CG900U_4P
B B
HDMI_RT_TX_N2 RV616 1 EMI@ 2 HDMI_L_TX_N2
<33> HDMI_RT_TX_N2
2.2_0402_1%
For EMI Reserve
CV599 1 2 HDMI_HPD
@ 0.1U_0402_25V6
CV600 1 2 HDMI_Reserved
@ 0.1U_0402_25V6
CV601 1 2 HDMI_CEC
@ 0.1U_0402_25V6
Close to JHDMI
+VDISPLAY_VCC

RM3 1 2 HDMI_CTRL_CLK
2.2K_0402_5%
RM4 1 2 HDMI_CTRL_DAT
2.2K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 34 of 78
5 4 3 2 1
 5 4 3 2 1

LCD backlight PWR CTRL +INV_PWR_SRC

eDP & TS Conn.
1
CV922 W=60mils JEDP1
QV11 @RF@
B+ +INV_PWR_SRC B+ +INV_PWR_SRC 10P_0402_25V8J 1

D
F2 @ 6 2 2 GND
60mil 60mil

S
1 2
Vinafix.com
4 5
2 1 RV538
3
4
BATT_WHITE_LED
BATT_YELLOW_LED
BREATH_WHITE_LED

1
SMD1812P150TF/24 1.5A UL/CSA/TUV 1 CV579 LCD_TST 1 @ 2 LCD_TST_R 5
VR_SRC

G
CV578 RV535 0_0402_5% 6
D SI3457BDV-T1-E3_TSOP6 0.1U_0402_25V6 7 VR_SRC D

3
1U_0603_25V6K 1M_0402_5% 2 8 VR_SRC
SB934570010

2
USB20_P8_R 9 NC
SE000006900

2
USB20_N8_R 10 DISP_ON/OFF#
11 PWM
CONNTST_GND

2
DI3 TS_EN 12
RV570 TS@ESD@ 13 VR_GND
AZC199-02SPR7G_SOT23-3 14 VR_GND
120K_0402_5% SC600001600 15 VR_GND
PESD5V0U2BT_SOT23-3 INV_PWM 16 LCD_B_CLK+

1 2
DISPOFF# 17 LCD_B_CLK-

1
D QV2 EDP_HPD 18 GND
SIO_SLP_S3# <17> EDP_HPD LVDS_B2+
2 +5VS_TS 19
<15,31,33,36,54,55,62> SIO_SLP_S3# +EDPVDD LVDS_B2-
G L2N7002WT1G_SC-70-3 20
21 LVDS_B1+
S W=60mils

3
22 LVDS_B1-
23 LVDS_B0+
24 LVDS_B0-
DVT1. CV577 EDP_AUXP_C 25 GND
Pop CV577 1 1 CV576 LVDS_A_CLK+
EDP_AUXN_C 26
27 LVDS_A_CLK-
GND

10U_0603_6.3V6M

8.2P_0402_50V8D
EDP_TXP0_C 28
2 2 EDP_TXN0_C 29 LVDS_A2+
30 LVDS_A2-
EDP_TXP1_C 31 LVDS_A1+
EDP_TXN1_C 32 LVDS_A1-

CCD +DMIC Circuit EDP_TXP2_C

EDP_TXN2_C
33
34
35
LVDS_A0+
LVDS_A0-
EDID_DATA 46
36 EDID_CLK MGND6 45
EDP_TXP3_C 37 BIST MGND5 44
EDP_TXN3_C 38 V_EDID MGND4 43
C +3VS +3VS_CAM 39 LCD_VDD MGND3 42 C
RZ37 40 LCD_VDD MGND2 41
1 @ 2 CONNTST MGND1
CV582 1 CV583 1 CV584 1
0_0603_5% @ ACES_59003-04006-001
CONN@
0.1U_0402_10V6K

8.2P_0402_50V8D

10U_0603_6.3V6M

2 2 2 SP01001BT00

DV2
<44> LCD_TST LCD_TST 3

1 INV_PWM

BIA_PWM_PCH 2
<6,13> BIA_PWM_PCH DVT1.

1
BAT54CW_SOT323-3 Change RV537 from 100K to 4.7K. +5VS +5VS_TS
RV545 1 2 @EMI@ BAT54CW-7-F_SOT323-3 RV537 RZ26
0_0201_5% SCS00003800 4.7K_0402_5% 1 @ 2
R_0201-NPM

2
0_0402_5%
LV22 EMI@
USB20_P5 4 3 USB20_P5_R
<16> USB20_P5 4 3 RI1 1 2 @TS@EMI@
RV566 0_0201_5%
USB20_N5 1 2 USB20_N5_R PANEL_BKEN_EC 1 @ 2 DISPOFF# R_0201-NPM
<16> USB20_N5 1 2 <44> PANEL_BKEN_EC
0_0402_5%

1
DLM0NSN900HY2D_4P LI1 TS@EMI@
RV536 USB20_P8 1 2 USB20_P8_R
SM070005U00 <16> USB20_P8 1 2
100K_0402_5%
B RV547 1 2 @EMI@ USB20_N8 4 3 USB20_N8_R B

2
0_0201_5% <16> USB20_N8 4 3
R_0201-NPM DLM0NSN900HY2D_4P
SM070005U00
RI2 1 2 @TS@EMI@
0_0201_5%
R_0201-NPM
CCD +DMIC Connector <6> EDP_TXN0
EDP_TXN0 CV581 1 2
0.1U_0402_10V6K
EDP_TXN0_C

+3VS_CAM EDP_TXP0 CV580 1 2 EDP_TXP0_C DI1 TS@

<6> EDP_TXP0 TOUCH_SCREEN_PD# TS_EN
0.1U_0402_10V6K 1 2
<14> TOUCH_SCREEN_PD#
1 EDP_TXN1 CV586 1 2 EDP_TXN1_C RB751S40_SOD523-2
<6> EDP_TXN1
CZ44 JCAM1 0.1U_0402_10V6K AZ5125-01HPR7G_SOD523-2
8 EDP_TXP1 CV585 1 2 EDP_TXP1_C
GND <6> EDP_TXP1
1U_0402_6.3V6K 7 0.1U_0402_10V6K
2 GND
6 EDP_TXN2 CV588 1 2 EDP_TXN2_C
USB20_P5_R 6 <6> EDP_TXN2
5 0.1U_0402_10V6K
USB20_N5_R 4 5 EDP_TXP2 CV587 1 2 EDP_TXP2_C
DMIC_DAT 4 <6> EDP_TXP2
3 0.1U_0402_10V6K
<42> DMIC_DAT DMIC_CLK 3
2
<42> DMIC_CLK 2 EDP_TXN3 EDP_TXN3_C
DV12 DA1 1 CV590 1 2
1 <6> EDP_TXN3
2

EC5206 1 EC5205 1 ESD@ ESD@ 0.1U_0402_10V6K

@ @ ACES_50228-0067N-P01 EDP_TXP3 CV589 1 2 EDP_TXP3_C
2

<6> EDP_TXP3
PESD5V0U2BT_SOT23-3
SC600001600
AZC199-02SPR7G_SOT23-3

SC600001600
AZC199-02SPR7G_SOT23-3

ACES_50228-0067N-001_6P 0.1U_0402_10V6K
6.8P_0402_50V8C

6.8P_0402_50V8C

CONN@
2 2
1

EDP_AUXP CV592 1 2 EDP_AUXP_C

SP02000WS00 <6> EDP_AUXP 0.1U_0402_10V6K
1

EDP_AUXN CV591 1 2 EDP_AUXN_C

A <6> EDP_AUXN 0.1U_0402_10V6K A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP /TS conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 35 of 78
5 4 3 2 1
 5 4 3 2 1

UT1 TBT@

S IC JHL6340 SLLSP C1 THUNDERBOLT A31!

SA00009YL3L TBT@ UT1A TBT@
PCIE_PTX_TRX_P21 CT3 1 2 0.22U_0201_6.3V PCIE_PTX_C_TRX_P21 Y23 V23 PCIE_PRX_C_TTX_P21 CT14 2 1 0.22U_0201_6.3V PCIE_PRX_TTX_P21
<16> PCIE_PTX_TRX_P21 PCIE_PTX_TRX_N21 PCIE_PTX_C_TRX_N21 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_TTX_P21 <16>
CT15 1 2 0.22U_0201_6.3V Y22 V22 PCIE_PRX_C_TTX_N21 CT16 2 1 0.22U_0201_6.3V PCIE_PRX_TTX_N21
<16> PCIE_PTX_TRX_N21 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_TTX_N21 <16>
TBT@ TBT@ TBT@ TBT@
PCIE_PTX_TRX_P22 CT1 1 2 0.22U_0201_6.3V PCIE_PTX_C_TRX_P22 T23 P23 PCIE_PRX_C_TTX_P22 CT12 2 1 0.22U_0201_6.3V PCIE_PRX_TTX_P22
<16> PCIE_PTX_TRX_P22 PCIE_RX1_P PCIE_TX1_P PCIE_PRX_TTX_P22 <16>

Vinafix.com

PCIe GEN3
PCIE_PTX_TRX_N22 CT13 1 2 0.22U_0201_6.3V PCIE_PTX_C_TRX_N22 T22 P22 PCIE_PRX_C_TTX_N22 CT2 2 1 0.22U_0201_6.3V PCIE_PRX_TTX_N22
<16> PCIE_PTX_TRX_N22 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_TTX_N22 <16>
PCIE X4 Bus TBT@ TBT@ TBT@ TBT@
PCIE_PTX_TRX_P23 CT4 1 2 0.22U_0201_6.3V PCIE_PTX_C_TRX_P23 M23 K23 PCIE_PRX_C_TTX_P23 CT109 2 1 0.22U_0201_6.3V PCIE_PRX_TTX_P23
<16> PCIE_PTX_TRX_P23 PCIE_PTX_TRX_N23 PCIE_PTX_C_TRX_N23 PCIE_RX2_P PCIE_TX2_P PCIE_PRX_TTX_P23 <16>
CT18 1 2 0.22U_0201_6.3V M22 K22 PCIE_PRX_C_TTX_N23 CT108 2 1 0.22U_0201_6.3V PCIE_PRX_TTX_N23
<16> PCIE_PTX_TRX_N23 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_TTX_N23 <16>
TBT@ TBT@ TBT@ TBT@
D D
PCIE_PTX_TRX_P24 CT5 1 2 0.22U_0201_6.3V PCIE_PTX_C_TRX_P24 H23 F23 PCIE_PRX_C_TTX_P24 CT111 2 1 0.22U_0201_6.3V PCIE_PRX_TTX_P24
<16> PCIE_PTX_TRX_P24 PCIE_PTX_TRX_N24 PCIE_PTX_C_TRX_N24 PCIE_RX3_P PCIE_TX3_P PCIE_PRX_C_TTX_N24 PCIE_PRX_TTX_N24 PCIE_PRX_TTX_P24 <16>
CT21 1 2 0.22U_0201_6.3V H22 F22 CT110 2 1 0.22U_0201_6.3V
<16> PCIE_PTX_TRX_N24 PCIE_RX3_N PCIE_TX3_N PCIE_PRX_TTX_N24 <16>
TBT@ TBT@
CLK_PCIE_P5 V19 L4 TBT_RST#_R RT1 1 @ 2 0_0201_5% PCH_PLTRST#_EC
<14> CLK_PCIE_P5 CLK_PCIE_N5 PCIE_REFCLK_100_IN_P PERST_N PCH_PLTRST#_EC <14,23,39,40,41,44,45>
PCIE CLK T19
<14> CLK_PCIE_N5 CLKREQ_PCIE#5 CLKREQ_PCIE#5_R PCIE_REFCLK_100_IN_N
RT2 1 @ 2 0_0201_5% AC5 N16 PCIE_RBIAS RT3 1 TBT@ 2 3.01K_0201_1%
<14> CLKREQ_PCIE#5 PCIE_CLKREQ_N PCIE_RBIAS
TBT@
<6> CPU_DP1_P0
CPU_DP1_P0 CT6 1 2 0.1U_0201_6.3V6K CPU_DP1_P0_C AB7
DPSNK0_ML0_P DPSRC_ML0_P
R2 TBT_DP1_P0
TBT_DP1_P0 <38>
Closed to UT1 +3.3V_TBT_SX
CPU_DP1_N0 CT7 1 2 0.1U_0201_6.3V6K CPU_DP1_N0_C AC7 R1 TBT_DP1_N0
<6> CPU_DP1_N0 DPSNK0_ML0_N DPSRC_ML0_N TBT_DP1_N0 <38> TBT_I2C_SDA
TBT@ TBT@ RT26 2 TBT@ 1 3.3K_0201_5%
CPU_DP1_P1 CT8 1 2 0.1U_0201_6.3V6K CPU_DP1_P1_C AB9 N2 TBT_DP1_P1 TBT_I2C_SCL RT27 2 TBT@ 1 3.3K_0201_5%
<6> CPU_DP1_P1 CPU_DP1_N1 DPSNK0_ML1_P DPSRC_ML1_P TBT_DP1_P1 <38>
CT9 1 2 0.1U_0201_6.3V6K CPU_DP1_N1_C AC9 N1 TBT_DP1_N1 SIO_SLP_S3#_AR RT30 2 @ 1 10K_0201_5%

SOURCE PORT 0
<6> CPU_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N TBT_DP1_N1 <38>
TBT@ TBT@ BATLOW# RT31 2 TBT@ 1 10K_0201_5%

SINK PORT 0
CPU_DP1_P2 CT10 1 2 0.1U_0201_6.3V6K CPU_DP1_P2_C AB11 L2 TBTA_I2C_INT RT32 2 TBT@ 1 10K_0201_5%
<6> CPU_DP1_P2 CPU_DP1_N2 DPSNK0_ML2_P DPSRC_ML2_P
CT23 1 2 0.1U_0201_6.3V6K CPU_DP1_N2_C AC11 L1 TBTB_I2C_INT RT33 2 TBT@ 1 10K_0201_5%
<6> CPU_DP1_N2 DPSNK0_ML2_N DPSRC_ML2_N
TBT@ TBT@
CPU DDI1 CPU_DP1_P3 CT11 1 2 0.1U_0201_6.3V6K CPU_DP1_P3_C AB13 J2 TBT_RST#_R CT118 2 1 470P_0402_50V7K
<6> CPU_DP1_P3 CPU_DP1_N3 DPSNK0_ML3_P DPSRC_ML3_P
CT24 1 2 0.1U_0201_6.3V6K CPU_DP1_N3_C AC13 J1
<6> CPU_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N
TBT@ TBT@ @TBT@ESD@
CPU_DP1_AUXP CT25 1 2 0.1U_0201_6.3V6K CPU_DP1_AUXP_C Y11 W19 TBT_SRC_AUX_P
<6> CPU_DP1_AUXP CPU_DP1_AUXN DPSNK0_AUX_P DPSRC_AUX_P TBT_SRC_AUX_P <38>
Reserve for common DP design CT26 1 2 0.1U_0201_6.3V6K CPU_DP1_AUXN_C W11 Y19 TBT_SRC_AUX_N
+3VS_TBT <6> CPU_DP1_AUXN DPSNK0_AUX_N DPSRC_AUX_N TBT_SRC_AUX_N <38>
TBT@
CPU_DP1_HPD AA2 G1 TBT_SRC_HPD
CPU_DP1_AUXN <17> CPU_DP1_HPD DPSNK0_HPD DPSRC_HPD TBT_SRC_HPD <38> +3VALW_PCH
RT76 2 @ 1 100K_0201_5%
RT77 2 @ 1 100K_0201_5% CPU_DP2_AUXN DPSNK1_DDC_CLK Y5 N6 DPSRC_RBIAS RT5 1 TBT@ 2 14K_0402_1%
RT78 2 @ 1 100K_0201_5% CPU_DP1_AUXP DPSNK1_DDC_DATA R4 DPSNK0_DDC_CLK DPSRC_RBIAS TBT_CIO_PLUG_EVENT# RT29 2 TBT@ 1 10K_0201_5%
RT79 2 @ 1 100K_0201_5% CPU_DP2_AUXP TBT@ DPSNK0_DDC_DATA U1 TBT_I2C_SDA
CPU_DP2_P0 CT27 1 2 0.1U_0201_6.3V6K CPU_DP2_P0_C AB15 GPIO_0 U2 TBT_I2C_SCL TBT_I2C_SDA <50>
<6> CPU_DP2_P0 CPU_DP2_N0 CPU_DP2_N0_C DPSNK1_ML0_P GPIO_1 TBT_EE_WP_N TBT_I2C_SCL <50>
CT28 1 2 0.1U_0201_6.3V6K AC15 V1 DVT1. Change pull high RT29 form +3.3V_TBT_SX to +3VLAW_PCH

LC GPIO
<6> CPU_DP2_N0 DPSNK1_ML0_N GPIO_2 TBT_TMU_CLK_OUT
TBT@ TBT@ V2
CPU_DP2_P1 CT29 1 2 0.1U_0201_6.3V6K CPU_DP2_P1_C AB17 GPIO_3 W1 TBT_PCIE_WAKE_N RT10 1 @ 2 0_0201_5% PCIE_WAKE#
<6> CPU_DP2_P1 CPU_DP2_N1 CPU_DP2_N1_C DPSNK1_ML1_P GPIO_4 TBT_CIO_PLUG_EVENT# PCIE_WAKE# <15,40,41,44>
CT30 1 2 0.1U_0201_6.3V6K AC17 W2
<6> CPU_DP2_N1 DPSNK1_ML1_N GPIO_5 TBT_HDMI_DDC_DATA TBT_CIO_PLUG_EVENT# <13>
TBT@ TBT@ Y1 @ T7
CPU_DP2_P2 CT31 1 2 0.1U_0201_6.3V6K CPU_DP2_P2_C AB19 GPIO_6 Y2 TBT_HDMI_DDC_CLK

SINK PORT 1
<6> CPU_DP2_P2 DPSNK1_ML2_P GPIO_7 @ T9
CPU_DP2_N2 CT32 1 2 0.1U_0201_6.3V6K CPU_DP2_N2_C AC19 AA1 TBT_SRC_CFG1 RT11 1 TBT@ 2 1M_0201_1%
C <6> CPU_DP2_N2 DPSNK1_ML2_N GPIO_8 TBTA_I2C_INT C
CPU DDI2 TBT@ TBT@ J4
CPU_DP2_P3 CPU_DP2_P3_C POC_GPIO_0 TBTB_I2C_INT TBTA_I2C_INT <50>
CT33 1 2 0.1U_0201_6.3V6K AB21 E2

POC GPIO
<6> CPU_DP2_P3 CPU_DP2_N3 CPU_DP2_N3_C DPSNK1_ML3_P POC_GPIO_1 RTD3_USB_PWR_EN_R
CT34 1 2 0.1U_0201_6.3V6K AC21 D4
<6> CPU_DP2_N3 DPSNK1_ML3_N POC_GPIO_2 TBT_FORCE_PWR_R TBT_FORCE_PWR
TBT@ TBT@ H4 RT13 1 @ 2 0_0201_5%
CPU_DP2_AUXP CPU_DP2_AUXP_C POC_GPIO_3 TBT_FORCE_PWR <14>
CT35 1 2 0.1U_0201_6.3V6K Y12 F2 BATLOW#
<6> CPU_DP2_AUXP CPU_DP2_AUXN CT36 1 2 0.1U_0201_6.3V6K CPU_DP2_AUXN_C W12 DPSNK1_AUX_P POC_GPIO_4 D2 SIO_SLP_S3#_AR RT110 1 @ 2 0_0201_5% SIO_SLP_S3#
<6> CPU_DP2_AUXN DPSNK1_AUX_N POC_GPIO_5 RTD3_CIO_PWR_EN_R RTD3_CIO_PWR_EN SIO_SLP_S3# <15,31,33,35,54,55,62>
TBT@ F1 RT16 1 @ 2 0_0201_5%
CPU_DP2_HPD POC_GPIO_6 RTD3_CIO_PWR_EN <14>
Y6
<17> CPU_DP2_HPD DPSNK1_HPD TBT_TEST_EN
E1 RT17 1 TBT@ 2 100_0201_5%
DPSNK2_DDC_CLK Y8 TEST_EN

Misc
+3.3V_LC DPSNK2_DDC_DATA N4 DPSNK1_DDC_CLK AB5 TBT_TEST_PWG RT18 1 TBT@ 2 100_0201_5%
DPSNK1_DDC_DATA TEST_PWR_GOOD
RT9 1 TBT@ 2 10K_0201_5% TBT_TDI RT19 2 TBT@ 1 14K_0402_1% DPSNK_RBIAS Y18 F4 TBT_RESET_N
TBT_TMS DPSNK_RBIAS RESET_N TBT_RESET_N_EC# TBT_RESET_N <50>
RT8 1 TBT@ 2 10K_0201_5% RT121 1 @ 2 0_0201_5%
TBT_TCK TBT_TDI TBT_RESET_N_EC# <44,50>
RT7 1 TBT@ 2 10K_0201_5% Y4 D22 TBT_XTAL_25_IN
RT6 1 TBT@ 2 10K_0201_5% TBT_TDO TBT_TMS V4 TDI XTAL_25_IN D23 TBT_XTAL_25_OUT
TBT_TCK T4 TMS XTAL_25_OUT
TBT_TDO W4 TCK AB3 TBT_EE_DI
TDO MISC EE_DI AC4 TBT_EE_DO
RT25 2 TBT@ 1 4.75K_0402_0.5%TBT_RBIAS H6 EE_DO AC3 TBT_EE_CS_N
TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_EE_CLK RT101 1 2 15_0201_1% TBT_EE_CLK_R
RSENSE EE_CLK TBT@EMI@
+3VS_TBT TBT_A_TRX_DTX_P1 A15 B7 Close to UT1
<50> TBT_A_TRX_DTX_P1 TBT_A_TRX_DTX_N1 PA_RX1_P PB_RX1_P
B15 A7
<50> TBT_A_TRX_DTX_N1 PA_RX1_N PB_RX1_N
TBT@
RT20 1 TBT@ 2 10K_0201_5% CLKREQ_PCIE#5_R TBT_A_TTX_C_DRX_P1 CT39 1 2 0.22U_0201_6.3V TBT_A_TTX_DRX_P1 A17 A9
<50> TBT_A_TTX_C_DRX_P1 TBT_A_TTX_C_DRX_N1 CT40 TBT_A_TTX_DRX_N1 PA_TX1_P PB_TX1_P
1 2 0.22U_0201_6.3V B17 B9
<50> TBT_A_TTX_C_DRX_N1 PA_TX1_N PB_TX1_N TBT_TMU_CLK_OUT
TBT@ TBT@ RT34 1 TBT@ 2 100K_0201_5%
TBT@ TBT_A_TTX_C_DRX_P0 CT41 1 2 0.22U_0201_6.3V TBT_A_TTX_DRX_P0 A19 A11 TBT_FORCE_PWR_R RT35 1 TBT@ 2 100K_0201_5%
DPSNK2_DDC_CLK <50> TBT_A_TTX_C_DRX_P0 TBT_A_TTX_C_DRX_N0 CT42 TBT_A_TTX_DRX_N0 PA_TX0_P PB_TX0_P RTD3_CIO_PWR_EN_R
RPT1 8 1 1 2 0.22U_0201_6.3V B19 B11 RT36 1 TBT@ 2 100K_0201_5%
DPSNK2_DDC_DATA <50> TBT_A_TTX_C_DRX_N0 PA_TX0_N PB_TX0_N RTD3_USB_PWR_EN_R
7 2 TBT@ RT37 1 TBT@ 2 100K_0201_5%

TBT PORTS
6 3 DPSNK1_DDC_DATA TBT_A_TRX_DTX_P0 B21 A13
DPSNK1_DDC_CLK <50> TBT_A_TRX_DTX_P0 TBT_A_TRX_DTX_N0 PA_RX0_P PB_RX0_P NC_B4
5 4 A21 B13 RT45 1 TBT@ 2 100K_0201_5%

Port A

PORT B
<50> TBT_A_TRX_DTX_N0 PA_RX0_N PB_RX0_N NC_B5
TBT@ RT46 1 TBT@ 2 100K_0201_5%
100K_0804_8P4R_5% TBT_A_AUX_P_C CT43 1 2 0.1U_0201_6.3V6K TBT_A_AUX_P Y15 Y16 NC_G2 RT47 1 TBT@ 2 100K_0201_5%
B
<50> TBT_A_AUX_P_C TBT_A_AUX_N_C CT44 1 2 0.1U_0201_6.3V6K TBT_A_AUX_N W15 PA_DPSRC_AUX_P PB_DPSRC_AUX_P W16 B
RT38 2 TBT@ 1 100K_0201_5% CPU_DP1_HPD <50> TBT_A_AUX_N_C TBT@ PA_DPSRC_AUX_N PB_DPSRC_AUX_N
RT39 2 TBT@ 1 100K_0201_5% CPU_DP2_HPD TBT_A_USB20_P E20 E19
RT40 2 TBT@ 1 1M_0201_1% TBTA_LSTX <50> TBT_A_USB20_P TBT_A_USB20_N D20 PA_USB2_D_P PB_USB2_D_P D19
RT41 2 TBT@ 1 100K_0201_5% TBTA_HPD <50> TBT_A_USB20_N PA_USB2_D_N PB_USB2_D_N
RT42 2 TBT@ 1 1M_0201_1% TBTA_LSRX TBTA_LSTX A5 B4 NC_B4
<50> TBTA_LSTX PA_LS_G1 PB_LS_G1

POC
POC
TBTA_LSRX A4 B5 NC_B5
<50> TBTA_LSRX TBTA_HPD PA_LS_G2 PB_LS_G2 NC_G2
M4 G2
<50> TBTA_HPD PA_LS_G3 PB_LS_G3
RT43 2 TBT@ 1 499_0201_1% PA_USB2_RBIAS H19 F19 PB_USB2_RBIAS RT44 1 TBT@ 2 499_0201_1%
PA_USB2_RBIAS PB_USB2_RBIAS
AC23
AB23 THERMDA
THERMDA
MONDC_SVR
D6

A23
S1
V18 ATEST_P B23
CONN@
PCIE_ATEST ATEST_N
AC1 DEBUG E18
TEST_EDM USB2_ATEST
L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W18 TBT@EMI@ CT38 TBT@
C23 MONDC_DPSNK_1 TBT_XTAL_25_IN RT116 1 2 TBT_XTAL_25_IN_R 1 2
+3.3V_FLASH C22 MONDC_CIO_0 AB2 33_0201_5% 27P_0402_50V8J
MONDC_CIO_1 MONDC_DPSRC 3
YT1
RT49 2 TBT@ 1 2.2K_0402_5% TBT_EE_CS_N @ ALPINE-RIDGE_BGA337 TBT@EMI@ TBT@
RT50 2 TBT@ 1 2.2K_0402_5% TBT_EE_DO TBT_XTAL_25_OUT RT117 1 2 TBT_XTAL_25_OUT_R 3 SJ10000TZ00
RT48 1 TBT@ 2 3.3K_0402_5% TBT_EE_WP_N 33_0201_5% 4
RT51 1 TBT@ 2 3.3K_0402_5% TBT_HOLD_N GND

25MHZ 20PF +-10PPM 7M25000153

+3.3V_FLASH +3.3V_FLASH 2
UT2 TBT@ GND
TBT_EE_CS_N 1 8 1
TBT_EE_DO 2 CS# VCC 7 TBT_HOLD_N CT45 1
TBT_EE_WP_N 3 DO(IO1) HOLD#(IO3) 6 TBT_EE_CLK_R TBT@ CT37 TBT@
4 WP#(IO2) CLK 5 TBT_EE_DI 0.1U_0201_6.3V6K 1 1 2
A A
GND DI(IO0) 2 27P_0402_50V8J
W25Q80DVSSIG_SO8
SA00003EW10 EMI Shielding Can

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Thunderbolt (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 36 of 78
5 4 3 2 1
 5 4 3 2 1

+3VALW +3.3V_TBT_SX +3VALW +3VS_TBT +3.3V_TBT_S0 +3VS_TBT

RT97 RT95 LT4 TBT@
1 @ 2 1 @ 2 1 2
0_0402_5% CT116 1 CT115 1 CT48 1 LQM18PN1R0MFHD_2P CT50 1 CT51 1 CT52 1 CT53 1
0_0402_5% @ TBT@ TBT@ +3.3V_LC +3.3V_TBT_SX TBT@ TBT@ TBT@ TBT@
+3VS

Vinafix.com

47U_0603_6.3V6M

47U_0603_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
RT124
1 TBT@ 2 2 2 2 CT46 1 CT47 1 CT49 1 2 2 2 2
0_0402_5% TBT@ TBT@ TBT@

0.1U_0201_6.3V6K

1U_0201_6.3V6M

1U_0201_6.3V6M
D Follow Berlineta 2 2 2 D

+0.9V_DP

R13
R6

H9
F8
CT54 1 CT57 1 CT58 1 CT59 1 CT60 1 CT61 1 CT62 1 UT1B
TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ L8 A2

VCC3P3_LC

VCC3P3_S0
VCC3P3_SX

VCC3P3A
L11 VCC0P9_DP VCC3P3_SVR A3
VCC0P9_DP VCC3P3_SVR

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
L12 B3 +0.9V_SVR
2 2 2 2 2 2 2 M8 VCC0P9_DP VCC3P3_SVR CT63 1 CT64 1 CT65 1 CT66 1 CT67 1 CT68 1 CT69 1
T11 VCC0P9_DP TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@
T12 VCC0P9_DP L9
VCC0P9_DP VCC0P9_SVR

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
L6 M9
M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12 2 2 2 2 2 2 2
V11 VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA E13
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12
+0.9V_PCIE VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA
CT55 1 CT70 1 CT71 1 CT72 1 F13
TBT@ TBT@ TBT@ TBT@ M13 VCC0P9_SVR_ANA F15
M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9
VCC0P9_PCIE VCC0P9_SVR_SENSE

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
M16 LT1 TBT@
2 2 2 2 L19 VCC0P9_PCIE TBT_SVR_IND 1 2
N19 VCC0P9_ANA_PCIE_1 C1 0.6UH_MND-04ABIR60M-XGL_20%
CT73 1 CT74 1 CT75 1
L18 VCC0P9_ANA_PCIE_1 SVR_IND C2 TBT@ TBT@ TBT@
M18 VCC0P9_ANA_PCIE_2 SVR_IND D1
+0.9V_USB VCC0P9_ANA_PCIE_2 SVR_IND

47U_0603_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
N18

VCC
VCC0P9_ANA_PCIE_2 2 2 2
R15 A1
CT77 1 CT56 1 R16 VCC0P9_USB SVR_VSS B1
TBT@ TBT@ +0.9V_CIO VCC0P9_USB SVR_VSS B2
R8 SVR_VSS
VCC0P9_CIO
1U_0201_6.3V6M

1U_0201_6.3V6M

R9
2 2 R11 VCC0P9_CIO
CT78 1 CT79 1 CT80 1 R12 VCC0P9_CIO F18
C TBT@ TBT@ TBT@ VCC0P9_CIO VCC0P9_LVR H18 C
+3.3V_ANA_PCIE L16 VCC0P9_LVR J11
VCC3P3_ANA_PCIE VCC0P9_LVR
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
+3.3V_ANA_USB2 J16 H11 +0.9V_LVR_OUT
2 2 2 CT85 1 CT86 1 VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE CT81 1 CT82 1 CT83 1 CT84 1
TBT@ TBT@ A6 V5 TBT@ TBT@ TBT@ TBT@
A8 VSS_ANA VSS_ANA V6
VSS_ANA VSS_ANA

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
A10 V8
2 2 A12 VSS_ANA ALPINE-RIDGE_BGA337 VSS_ANA V9 2 2 2 2
A14 VSS_ANA VSS_ANA V15
A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
B10 VSS_ANA VSS_ANA W20
B12 VSS_ANA VSS_ANA W22
B14 VSS_ANA VSS_ANA W23
B16 VSS_ANA VSS_ANA Y9
B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
D11 VSS_ANA VSS_ANA AB8
D12 VSS_ANA VSS_ANA AB10
D13 VSS_ANA VSS_ANA AB12
D15 VSS_ANA VSS_ANA AB14
D16 VSS_ANA VSS_ANA AB16

GND
D18 VSS_ANA VSS_ANA AB18
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
E15 VSS_ANA VSS_ANA AC8
E16 VSS_ANA VSS_ANA AC10
B E22 VSS_ANA VSS_ANA AC12 B
E23 VSS_ANA VSS_ANA AC14
F9 VSS_ANA VSS_ANA AC16
F16 VSS_ANA VSS_ANA AC18
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
H12 VSS_ANA VSS E6
H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
H16 VSS_ANA VSS H5
H20 VSS_ANA VSS H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

N20 VSS_ANA VSS T18

N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
A A
@
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Thunderbolt (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 37 of 78
5 4 3 2 1
 5 4 3 2 1

Main Func = DP to VGA Converter

+3VS +AVCC33 +3VS +VDD_DAC_33
RVGA1 RVGA2
1 @ 2 1 @ 2
2 2
0_0402_5% CVGA1 0_0402_5% CVGA2

1
VGA@
10U_0603_6.3V6M Vinafix.com
1
VGA@
10U_0603_6.3V6M

D D

+AVCC33 +3VS +VDD_DAC_33

CVGA3 1 2
+3VS VGA@ 0.1U_0402_16V4Z
UVGA1 VGA@
RVGA3 2 @ 1 TBT_SRC_AUX_N_C +3VS 1 20 CVGA5 1 2
100K_0402_5% CVGA6 VGA@1 2 0.1U_0402_16V4Z +1.2V_VCCK 4 AVC33 VDD_DAC_33 VGA@ 2.2U_0402_6.3V6M
RVGA4 2 @ 1 TBT_SRC_AUX_P_C 14 AVCC_12 25 +1.2V_VCCK CVGA7 1 2
100K_0402_5% VCC_33 VCCK_12 VGA@ 0.1U_0402_16V4Z
TBT_SRC_AUX_P CVGA4 VGA@1 2 0.1U_0402_16V4Z TBT_SRC_AUX_P_C 2 26 CVGA8 1 2
<36> TBT_SRC_AUX_P TBT_SRC_AUX_N CVGA9 VGA@1 2 0.1U_0402_16V4Z TBT_SRC_AUX_N_C 3 AUX_P PVCC_33 VGA@ 0.1U_0402_16V4Z +5VS
<36> TBT_SRC_AUX_N AUX_N
TBT_DP1_P0 CVGA10 VGA@1 2 0.1U_0402_16V4Z TBT_DP1_P0_C 5 17
<36> TBT_DP1_P0 TBT_DP1_N0 TBT_DP1_N0_C LANE0_P HVSYNC_PWR DP_CRT_VSYNC_CON
CVGA11 VGA@1 2 0.1U_0402_16V4Z 6 18
<36> TBT_DP1_N0
<36>
<36>
TBT_DP1_P1
TBT_DP1_N1
TBT_DP1_P1
TBT_DP1_N1
+AVCC33
CVGA12
CVGA13
VGA@1
VGA@1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
TBT_DP1_P1_C
TBT_DP1_N1_C
7
8
LANE0_N
LANE1_P
LANE1_N
RTD2166 VSYNC
HSYNC
19 DP_CRT_HSYNC_CON CVGA15 1
VGA@
CVGA14 1
VGA@

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
RVGA5 2 VGA@ 1 4.7K_0402_5% POL1_SDA 10 21 DP_CRT_B
+3VS RVGA6 2 VGA@ 1 4.7K_0402_5% POL1_SCL 9 POL1/SPI_CEB BLUE_P 2 2
POL2 22 DP_CRT_G
RVGA16 2 @ 1 4.7K_0402_5% 11 GREEN_P
12 GPI1/SPI_CLK 23 DP_CRT_R
+CRT_5V_OUT 13 GPI2/SPI_SI RED_P
GPI3/SPI_SO
C CRT_DDCCLK_CON 15 C
CRT_DDCDATA_CON 16 VGA_SCL
VGA_SDA
2

27
RVGA7 RVGA8 PCH_SMBCLK 30 LDO_RSTB 28
<15,20,21,22,39> PCH_SMBCLK PCH_SMBDATA SMB_SCL EXT_CLK_IN
VGA@ VGA@ 29 31
2.2K_0402_5% 2.2K_0402_5% <15,20,21,22,39> PCH_SMBDATA SMB_SDA EXT1.2V_CTRL
TBT_SRC_HPD RVGA9 1 @ 2 CRT_PCH_HPD 32 24
<36> TBT_SRC_HPD
1

CRT_DDCDATA_CON 0_0402_5% HPD GND 33

EPAD_GND

2
CRT_DDCCLK_CON
RVGA10 RTD2166-CG_QFN32_4X4

100K_0402_5%
SA000098Q00

1
+5VS +CRT_5V_OUT
DVGA1 VGA@ FVGA1 VGA@
DP_CRT_R LVGA1 1 2 CRT_R 2 1 +CRT_5V_OUT_M 2 1
B VGA@EMI@ BLM15BB220SN1D B
DP_CRT_G LVGA2 1 2 CRT_G LRB551V-30T1G_SOD323-2 1.1A_6V_SPR-P110
VGA@EMI@ BLM15BB220SN1D
DP_CRT_B LVGA3 1 2 CRT_B
VGA@EMI@ BLM15BB220SN1D
1

1
75_0402_1%

CVGA16 1 CVGA17 1 CVGA18 1 CVGA19 1 CVGA20 1 CVGA21 1

75_0402_1%

75_0402_1%

RVGA11 RVGA12 RVGA13 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

VGA@ VGA@ VGA@ +CRT_5V_OUT
2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

JCRT1
2 2 2 2 2 2 6
2

11
CRT_R 1
7
CRT_DDCDATA_CON 12
CRT_G 2
8 G 16
CRT_HSYNC_CON 13 17
CRT_B 3 G
9
CRT_VSYNC_CON 14
4
DP_CRT_HSYNC_CON RVGA14 2 VGA@ 1 CRT_HSYNC_CON 10
47_0402_5% CRT_DDCCLK_CON 15
DP_CRT_VSYNC_CON RVGA15 2 VGA@ 1 CRT_VSYNC_CON 1 5
47_0402_5% CVGA22
@ C-K_80454-5K1-152
1

CVGA23 CVGA24 0.01U_0402_16V7K CONN@

VGA@EMI@ VGA@EMI@ 2
A
10P_0402_50V 10P_0402_50V
DC060004S10 A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/06 Title
2017/01/06 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DP to VGA Converter
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 38 of 78
5 4 3 2 1
 5 4 3 2 1

M.2 Key-M (SSD) +3VS

1
RZ36
@ 2
+3.3VDX_SSD

0_0603_5%
RZ117
1 @ 2

0_0603_5% +3.3VDX_SSD
JNGFF2 RF Reserved.
Vinafix.com PCIE_PRX_DTX_N9
1
3
5
GND
GND
3P3VAUX
3P3VAUX
2
4
6
CD36 1 CD38 1 CD39 1 CD40
RF@
1 CD41
RF@
1
<13> PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 PERn3 NC
7 8
<13> PCIE_PRX_DTX_P9 PERp3 NC

4.7U_0603_6.3V6K

0.1U_0402_10V6K

0.01U_0402_16V7K

47P_0402_50V8J

15P_0402_50V8J
D 9 10 SSD_LED# D
PCIE_PTX_DRX_N9 PCIE_PTX_C_DRX_N9 GND DAS/DSS# SSD_LED# <48> 2 2 2 2 2
CD37 1 2 0.22U_0402_10V6K 11 12
<13> PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9 PCIE_PTX_C_DRX_P9 PETn3 3P3VAUX
CD42 1 2 0.22U_0402_10V6K 13 14
<13> PCIE_PTX_DRX_P9 PETp3 3P3VAUX
15 16
PCIE_PRX_DTX_N10 17 GND 3P3VAUX 18
<13> PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 PERn2 3P3VAUX
19 20
<13> PCIE_PRX_DTX_P10 PERp2 NC
PCIe SSD 21 22
PCIE_PTX_DRX_N10 CD43 1 2 0.22U_0402_10V6K PCIE_PTX_C_DRX_N10 23 GND NC 24
<13> PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10 PCIE_PTX_C_DRX_P10 PETn2 NC
CD44 1 2 0.22U_0402_10V6K 25 26
<13> PCIE_PTX_DRX_P10 PETp2 NC
27 28
PCIE_PRX_DTX_N11 29 GND NC 30 +3.3VDX_SSD
<13> PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 PERn1 NC
31 32
<13> PCIE_PRX_DTX_P11 PERp1 NC
33 34 RD7 2 @ 1 10K_0402_5%
PCIE_PTX_DRX_N11 CD45 1 2 0.22U_0402_10V6K PCIE_PTX_C_DRX_N11 35 GND NC 36
<13> PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 PCIE_PTX_C_DRX_P11 PETn1 NC mSATA_DEVSLP
CD46 1 2 0.22U_0402_10V6K 37 38 RD59 1 @ 2 0_0402_5%
<13> PCIE_PTX_DRX_P11 PETp1 DEVSLP mSATA_DEVSLP <16>
39 40
SATA_PRX_DTX_P1A 41 GND NC 42
<13> SATA_PRX_DTX_P1A SATA_PRX_DTX_N1A PERn0/SATA-B+ NC
43 44
<13> SATA_PRX_DTX_N1A PERp0/SATA-B- NC
SATA SSD 45 46
SATA_PTX_DRX_N1A CD53 1 2 0.22U_0402_10V6K SATA_PTX_C_DRX_N1A 47 GND NC 48
<13> SATA_PTX_DRX_N1A SATA_PTX_DRX_P1A SATA_PTX_C_DRX_P1A PETn0/SATA-A- NC PCH_PLTRST#_EC
CD51 1 2 0.22U_0402_10V6K 49 50
<13> SATA_PTX_DRX_P1A PETp0/SATA-A+ PERST# CLKREQ_PCIE#6 PCH_PLTRST#_EC <14,23,36,40,41,44,45>
51 52
CLK_PCIE_N6 GND CLKREQ# SSD_PCIE_WAKE# CLKREQ_PCIE#6 <14>
53 54 RD8 1 2 10K_0402_5% +3.3VDX_SSD
<14> CLK_PCIE_N6 CLK_PCIE_P6 REFCLKN PEWake#
55 56
<14> CLK_PCIE_P6 REFCLKP NC
57 58
GND NC

59 60 RD9 1 @ 2 0_0402_5% SUSCLK

mCARD_PCIE_SATA# NC SUSCLK(32kHz) SUSCLK <15,41,44>
RD58 1 @ 2 0_0402_5% 61 62
<13> mCARD_PCIE_SATA# PEDET(NC-PCIE/GND-SATA) 3P3VAUX
63 64
C 65 GND 3P3VAUX 66 C
67 GND 3P3VAUX
GND 68
GND1 69
GND2
BELLW_SD-80159-4221
CONN@
SP07001D300

+3VS

CN19 1 CN22 1
FFS@ @ +3VS

Free Fall Sensor

0.1U_0402_16V7K

10U_0603_6.3V6M

2 2
1
1

U5603 FFS@ RS40 RS41

LNG2DM 100K_0402_5% 100K_0402_5% +5VS +5VS_HDD
10 5
2
2

9 VDD_IO RES 1 @ 2
VDD 12 FFS_INT1 RZ34 0_0805_5%
INT 1 FFS_INT2 FFS_INT1 <17>
3 11
PCH_SMBDATA SDO/SA0 INT 2 FFS_INT2 <14>
4
<15,20,21,22,38> PCH_SMBDATA PCH_SMBCLK 1 SDA/SDI/SDO 6
B <15,20,21,22,38> PCH_SMBCLK SCL/SPC GND B
7
2 GND 8
CS GND

LNG2DMTR_LGA12_2X2
SA000089W00
HDD CONN
JHDD1
1
<13> SATA_PTX_DRX_P0B
SATA_PTX_DRX_P0B CS28 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0B 2 1
2
Place near HDD CONN (JHDD1)
+5VS_HDD SATA_PTX_DRX_N0B CS27 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0B 3
<13> SATA_PTX_DRX_N0B 3 +5VS_HDD
4
SATA_PRX_DTX_N0B CS25 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0B 5 4
<13> SATA_PRX_DTX_N0B 5
1

SATA_PRX_DTX_P0B CS26 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0B 6

<13> SATA_PRX_DTX_P0B 6
RS1 7 CS12 1 CS13 1 CS14 1 CS15 1
FFS@ HDD_DEVSLP RD62 1 @ 2 0_0402_5% HDD_DEVSLP_R 8 7
<16> HDD_DEVSLP FFS_INT2_Q 8
100K_0402_5% 9
+3VS 9

1000P_0402_50V7K

0.1U_0402_10V6K

1U_0402_6.3V6K

10U_0603_6.3V6M
10
2

FFS_INT2_Q 11 10 2 2 2 2
12 11
+5VS_HDD 12
1

RS39 13
GND
6

FFS@ QC5A 14
100K_0402_5% FFS@ GND
ACES_51625-01201-001
2

2 CONN@
DMN65D8LDW-7_SOT363-6 SP010028W00
1
3

QC5B
A FFS@ A

FFS_INT2 5
DMN65D8LDW-7_SOT363-6
4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SSD/HDD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 39 of 78
5 4 3 2 1
 1 2 3 4 5

LOM + RJ45 +3VALW

2
+3VALW
W=40mils RL41
1
CL39 +3VALW 100K_0402_5% +LAN_IO 1A
UL2 +DVDDL +AVDDH
W=40 mils

1
1U_0402_6.3V6K 5 1 CL93 CL97 CL95 CL94 CL96
2 IN OUT

GND
2 Vinafix.com
CL11 1 CL12 1 CL13 1 CL14 1 CL15 1 CL16 1 CL17 1
1 1 1 1 1

1U_0402_6.3V6K

0.1U_0402_16V7K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K
2 2 2 2 2

1000P_0402_50V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V7K

1U_0402_6.3V6K
A LAN_EN 4 3 A
<44> LAN_EN EN OC 2 2 2 2 2 2 2

2
SY6288C20AAC_SOT23-5
RL27 SA000079400
100K_0402_5%

+LAN_IO rising time : >1ms and <100ms close to UL1 pin1 close to UL1 pin16 close to UL1 pin37 close to UL1 pin9 close to UL1 pin22
UL1 +LAN_IO
+V_DAC
PCIE_PRX_DTX_P14 CL30 2 1 PCIE_PRX_C_DTX_P14 30 1 TL2
<13> PCIE_PRX_DTX_P14 TX_P VDD33
0.1U_0402_16V7K 16 1 24 MCT0
PCIE_PRX_DTX_N14 CL31 2 1 PCIE_PRX_C_DTX_N14 29 AVDD33 TCT1 MCT1
<13> PCIE_PRX_DTX_N14 TX_N LAN_MDIN3 RJ45_MDIN3
0.1U_0402_16V7K 2 23
PCIE_PTX_DRX_P14 CL47 2 1 PCIE_PTX_C_DRX_P14 35 13 +AVDDL TD1+ MX1+
<13> PCIE_PTX_DRX_P14 RX_P AVDDL LAN_MDIP3 RJ45_MDIP3
0.1U_0402_16V7K 19 3 22
PCIE_PTX_DRX_N14 CL48 2 1 PCIE_PTX_C_DRX_N14 36 AVDDL 31 TD1- MX1-
<13> PCIE_PTX_DRX_N14 RX_N AVDDL
0.1U_0402_16V7K 34 4 21 MCT1
CLK_PCIE_P2 33 AVDDL 6 TCT2 MCT2
<14> CLK_PCIE_P2 REFCLK_P AVDDL_REG LAN_MDIN2 RJ45_MDIN2
5 20
CLK_PCIE_N2 32 TD2 MX2+
<14> CLK_PCIE_N2 REFCLK_N LAN_MDIP2 RJ45_MDIP2
22 +AVDDH 6 19
CLKREQ_PCIE#2 4 AVDDH 9 TD2- MX2-
<14> CLKREQ_PCIE#2 CLKREQ# AVDDH_REG 7 18 MCT2
B PCH_PLTRST#_EC 2 TCT3 MCT3 B
<14,23,36,39,41,44,45> PCH_PLTRST#_EC PERST# LAN_MDIN1 RJ45_MDIN1
37 +DVDDL 8 17
PCIE_WAKE# RL58 1 @ 2 0_0402_5% LAN_WAKE#_R 3 DVDDL_REG TD3+ MX3+
<15,36,41,44> PCIE_WAKE# WAKE# LAN_MDIP1 RJ45_MDIP1
9 16
11 LAN_MDIP0 TD3- MX3-
25 TRXP0 12 LAN_MDIN0 10 15 MCT3
26 SMCLK TRXN0 14 LAN_MDIP1 TCT4 MCT4
SMDATA TRXP1 15 LAN_MDIN1 LAN_MDIN0 11 14 RJ45_MDIN0
28 TRXN1 17 LAN_MDIP2 TD4+ MX4+
27 NC TRXP2 18 LAN_MDIN2 LAN_MDIP0 12 13 RJ45_MDIP0
41 TESTMODE TRXN2 20 LAN_MDIP3 TD4- MX4-
GND TRXP3 21 LAN_MDIN3
XTLI 8 TRXN3 MHPC_NS892407
+LAN_IO XTLO 7 XTLI
XTLO 40
SP050006800
RL51 1 2 30K_0402_5% 5 LX
ISOLAT# 24
PPS +V_DAC
RL60 1 2 4.7K_0402_5% LAN_ACTIVITY# 38 10 +RBIAS
RL52 1 2 5.1K_0402_1% LAN_LINK#_R 39 LED_0 RBIAS
LED_1

1
RL59 1 2 4.7K_0402_5% LAN_LED2#_R 23 CL49 1 CL41 1 CL53 1 CL52 1 CL55 1 CL54 1 CL57 1 CL56 1
LED_2 RL50 EMI@ EMI@ EMI@ EMI@ EMI@ EMI@ EMI@ EMI@ MCT0 RL19 1 2 75_0402_5%
MCT1 RL20 1 2 75_0402_5%

0.1U_0402_25V6

1000P_0402_50V7K

0.1U_0402_25V6

1000P_0402_50V7K

0.1U_0402_25V6

1000P_0402_50V7K

0.1U_0402_25V6

1000P_0402_50V7K
S IC E2400-BL3A-R QFN 40P E-LAN CTRL 2.37K_0402_1% MCT2 RL39 1 2 75_0402_5%
XTLI_R RL56 1 EMI@ 2 33_0402_5% XTLI 2 2 2 2 2 2 2 2 MCT3 RL40 1 2 75_0402_5%
SA00008TH00

2
XTLO_R RL57 1 EMI@ 2 33_0402_5% XTLO 1
CL33

C
1
YL2
OSC GND
2 Killer E2500 SA0000A6L00 Place close
EMI@
10P_1206_2KV8J
2 C
3
OSC GND
4 to MCT pin
25MHZ_10PF_+-10PPM_7M25000013

2
2

JLAN
CL36 CL37
12P_0402_50V8J 15P_0402_50V8J
1

1 RJ45_MDIN3 8
DVT1. PR4-
Change CL36 form 18pF 0402 to 12pF. RJ45_MDIP3 7
Change CL37 from 22pF 0402 to 15pF. PR4+
RJ45_MDIN1 6
PR2-
RJ45_MDIN2 5
+AVDDL PR3-
CL92 1 CL89 1 CL90 1 CL87 1 CL91 1 CL86 1 CL85 1 CL88 1 RJ45_MDIP2 4
PR3+
RJ45_MDIP1 3
PR2+
1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

2 2 2 2 2 2 2 2 RJ45_MDIN0 2
PR1-
RJ45_MDIP0 1
PR1+ 9
GND 10
GND 11
GND 12
GND
D D
SANTA_130460-N
CONN@
close to UL1 pin6 close to UL1 pin34 close to UL1 pin31 close to UL1 pin13 close to UL1 pin19 DC23400DT00

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN E2400
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 40 of 78
1 2 3 4 5
 5 4 3 2 1

M.2 Key-E (WLAN + BT) Close to JNGFF1.2&4 Close to JNGFF1.64&66

+3VA_WLAN +3VA_WLAN

+3VS +3VA_WLAN
RN37 CN1 1 CN2 1 CN9 1 CN23 1 CN6 1 CN7 1 CN24 1
1 @ 2 @RF@

Vinafix.com

22U_0603_6.3V6M

.1U_0402_16V7K

10P_0402_25V8J

0.01U_0402_16V7K

22U_0603_6.3V6M

.1U_0402_16V7K

0.01U_0402_16V7K
0_0805_5%
+3VALW_PCH 2 2 2 2 2 2 2

D 1 @ 2 D
RN2 0_0805_5%

6/18:
+3VALW_PCH is the same with +3VALW_DSW

+1.8V_PRIM +3VALW +1.8V_PRIM +3VALW

DVT1. DVT1.
Add level shift for CLKREQ_CNV# Add level shift for CNV_RF_RESET#

1
Debug Crad Port80: RN43 RN41 RN42 RN40
If need to use Debug card to check port80 code, please pop RN8 and un-pop RN32!!! 4.7K_0402_5% 100K_0402_5% 4.7K_0402_5% 100K_0402_5%

2
CLKREQ_CNV#_R CNV_RF_RESET#_R

Reserve for NGFF Debug Card CNVI@ CNVI@ CNVI@ CNVI@

6
QN2B QN2A QN1B QN1A
DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6
CNV_RGI_PTX_R_DRX 0_0402_5% 2 @ 1 RN8
E51_TX2 0_0402_5% 2 @ 1 RN5 HOST_DEBUG_TX 5 2 5 2
HOST_DEBUG_TX <44> CLKREQ_CNV# <15> CNV_RF_RESET# <15>
DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6
1

1
4

1
RN4 CNVI@ CNVI@
@ RN10 RN9
C 100K_0402_5% 75K_0402_1% 75K_0402_1% C
2

2
+3VA_WLAN
JNGFF1
1 2
USB20_P7 3 GND 3.3VAUX 4
<16> USB20_P7 USB20_N7 5 USB_D+ 3.3VAUX 6 +1.8V_PRIM
<16> USB20_N7 7 USB_D- LED1# 8
CNV_PRX_DTX_N1 RN21 1 @ 2 0_0402_5% CNV_PRX_R_DTX_N1 9 GND PCM_CLK 10 CNV_RF_RESET#_R CNV_RGI_PRX_DTX 20K_0402_5% 2 @ 1 RN14
<13> CNV_PRX_DTX_N1 CNV_PRX_DTX_P1 CNV_PRX_R_DTX_P1 SIDO_CLK PCM_SYNC
RN22 1 @ 2 0_0402_5% 11 12
<13> CNV_PRX_DTX_P1 SDIO_CMD PCM_IN CLKREQ_CNV#_R CNV_BRI_PRX_DTX
13 14 DVT2 20K_0402_5% 2 @ 1 RN12
CNV_PRX_DTX_N0 RN19 1 @ 2 0_0402_5% CNV_PRX_R_DTX_N0 15 SDO_DAT0 PCM_OUT 16
<13> CNV_PRX_DTX_N0 SDO_DAT1 LED2#
Change RN29, RN32 to 22ohm.
CNV_PRX_DTX_P0 RN20 1 @ 2 0_0402_5% CNV_PRX_R_DTX_P0 17 18
<13> CNV_PRX_DTX_P0 SDO_DAT2 GND
19 20
CLK_CNV_PRX_DTX_N RN17 1 @ 2 0_0402_5% CLK_CNV_PRX_R_DTX_N 21 SDO_DAT3 UART_WAKE# 22 CNV_BRI_PRX_R_DTX 22_0402_5% 1 CNVI@ 2 RN29 CNV_BRI_PRX_DTX
<13> CLK_CNV_PRX_DTX_N CLK_CNV_PRX_DTX_P RN18 CLK_CNV_PRX_R_DTX_P SDIO_WAKE# UART_RX UART_2_CRXD_DTXD CNV_BRI_PRX_DTX <13>
1 @ 2 0_0402_5% 23 0_0402_5% 1 @ 2 RN6
<13> CLK_CNV_PRX_DTX_P SDIO_RESET# UART_2_CRXD_DTXD <17>

E-Key 24 CNV_RGI_PTX_R_DRX
0_0402_5%
22_0402_5%
1 @ 2 RN7
1 CNVI@ 2 RN32
UART_2_CTXD_DRXD
CNV_RGI_PTX_DRX UART_2_CTXD_DRXD <17>
UART_TX CNV_RGI_PRX_R_DTX CNV_RGI_PRX_DTX CNV_RGI_PTX_DRX <13>
CN21 0.1U_0402_10V7K 25 26 22_0402_5% 1 CNVI@ 2 RN34
PCIE_PTX_DRX_P15 GND UART_CTS CNV_RGI_PRX_DTX <13>
1 2 PCIE_PTX_C_DRX_P15 27 28 CNV_BRI_PTX_R_DRX 22_0402_5% 1 CNVI@ 2 RN33 CNV_BRI_PTX_DRX
<13> PCIE_PTX_DRX_P15 PCIE_PTX_DRX_N15 PETP0 UART_RTS CNV_BRI_PTX_DRX <13>
1 2 PCIE_PTX_C_DRX_N15 29 30 E51_TX2
<13> PCIE_PTX_DRX_N15 PETN0 RESERVED
CN20 0.1U_0402_10V7K 31 32
PCIE_PRX_DTX_P15 33 GND RESERVED 34
<13> PCIE_PRX_DTX_P15 PERP0 RESERVED
DVT2
B PCIE_PRX_DTX_N15 35 36 Add RN33, RN34 22ohm. B
<13> PCIE_PRX_DTX_N15 PERN0 COEX3
37 38
CLK_PCIE_P3 39 GND COEX2 40
<14> CLK_PCIE_P3 CLK_PCIE_N3 REFCLKP0 COEX1 SUSCLK_R
41 42 0_0402_5% 1 @ 2 RN1 SUSCLK
<14> CLK_PCIE_N3 REFCLKN0 SUSCLK PCH_PLTRST#_EC SUSCLK <15,39,44>
43 44
CLKREQ_PCIE#3 GND PERST0# BT_RADIO_DIS#_R PCH_PLTRST#_EC <14,23,36,39,40,44,45>
45 46 DN2
<14> CLKREQ_PCIE#3 PCIE_WAKE# CLKEQ0# W_DISABLE2# WLAN_WIGIG60GHZ_DIS#_R
47 48 AZ5125-01HPR7G_SOD523-2 2 1
<15,36,40,44> PCIE_WAKE# PEWAKE0# W_DISABLE1# BT_RADIO_DIS# <17>
49 50 RB751S40_SOD523-2 DN1
CNV_PTX_DRX_N1 RN27 1 @ 2 0_0402_5% CNV_PTX_R_DRX_N1 51 GND I2C_DATA 52 AZ5125-01HPR7G_SOD523-2 2 1
<13> CNV_PTX_DRX_N1 CNV_PTX_DRX_P1 CNV_PTX_R_DRX_P1 RSRVD/PETP1 I2C_CLK WLAN_WIGIG60GHZ_DIS# <17>
RN28 1 @ 2 0_0402_5% 53 54 RB751S40_SOD523-2
<13> CNV_PTX_DRX_P1 RSRVD/PETN1 ALERT REFCLK_CNV_R
55 56
CNV_PTX_DRX_N0 RN25 1 @ 2 0_0402_5% CNV_PTX_R_DRX_N0 57 GND RESERVED 58
<13> CNV_PTX_DRX_N0 CNV_PTX_DRX_P0 CNV_PTX_R_DRX_P0 RSRVD/PERP1 RESERVED REFCLK_CNV
RN26 1 @ 2 0_0402_5% 59 60 0_0402_5% 1 @ 2 RN35
<13> CNV_PTX_DRX_P0 RSRVD/PERN1 RESERVED REFCLK_CNV <14>
61 62
CLK_CNV_PTX_DRX_N RN23 1 @ 2 0_0402_5% CLK_CNV_PTX_R_DRX_N 63 GND RESERVED 64
<13> CLK_CNV_PTX_DRX_N CLK_CNV_PTX_DRX_P RN24 CLK_CNV_PTX_R_DRX_P RESERVED 3.3VAUX
1 @ 2 0_0402_5% 65 66
<13> CLK_CNV_PTX_DRX_P RESERVED 3.3VAUX +3VA_WLAN
67
GND
WLAN_WIGIG60GHZ_DIS#_R 10K_0402_5% 2 @ 1 RN38
69 68
MTG77 MTG76 BT_RADIO_DIS#_R 10K_0402_5% 2 @ 1 RN39

CONCR_213EAAA32FA
Key-E Debug Card Socket CONN@
SP070011I00 +1.8V_PRIM +5VS

EMI@ CN25 1 2 .1U_0402_16V7K

A
DVT2 A
Place CN25 close to REFCLK_CNV signal
where cross +1.8V_PRIM and +5VS
power plane.
LA-E993P only.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF-WLAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 41 of 78
5 4 3 2 1
 5 4 3 2 1

Main Func = Audio

DVT1.
Add CA68 0.1uF 0402 Cap for EMI.
+3VS Add CA67 10uF 0603 Cap for EMI. +5VS +5V_PVDD
2A
UA1 RA7 0_0805_5% 5V_PVDD trace width > 40mil.
1 +1.8V_DVDD 1 @ 2
VIN

1
1 RA57 CA67 1 CA68 1 CA11 1 CA12 1 CA13 1 CA14 1
CA4 RA2 5 +1.8VS 1 @ 2 EMI@ EMI@ RA10 0_0805_5%
2
GND
VOUT
Vinafix.com 1 @ 2

10U_0603_6.3V6M

0.1U_0402_10V6K

10U_0603_6.3V6M

0.1U_0402_10V6K

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V6K 10K_0402_5% 0_0603_5%
2 4 2 2 2 2 2 2
1

2
3 NC CA7
D EN D
2
CA10 1U_0402_6.3V6K
G9090-180T11U_SOT23-5 2
0.68U_0603_16V6K
1 SA00004Z400

LINE1_VREFO_R MIC2_VREFO Close pin41 Close pin46

<43> LINE1_VREFO_R LINE1_VREFO_L MIC2_VREFO <43>
<43> LINE1_VREFO_L
+1.8V_DVDD moat +1.8V_AVDD moat +5V_AVDD
AUD_AGND
CA16 1 CA19 1

1
RA1 1 2 2 1 RA8
CA3 1 CA1 1 CA2 1 AUD_HP1_JACK_L RA11 CA18 1 CA17 1
<43> AUD_HP1_JACK_L

2.2U_0402_6.3V6M

4.7U_0603_6.3V6K
0_0402_5% AUD_HP1_JACK_R 0_0402_5%
<43> AUD_HP1_JACK_R 2 2

4.7U_0603_6.3V6K
100K_0402_5%
0.1U_0402_10V6K

0.1U_0402_10V6K

4.7U_0603_6.3V6K

0.1U_0402_10V6K
2
2 2 2 2 2

CA15 1 2 CPVEE
1U_0603_10V6K
LDO1_CAP
AUD_AGND CBN Place close to Pin 26
Close pin36 2
+1.8V_DVDD +5V_AVDD
CA20 AUD_AGND

1U_0603_10V6K
1
+3VS +3V_DVDD AUD_AGND

36

35

34

33

32

31

30

29

28

27

26

25
RA5 HDA1
C 1 @ 2 C

CPVEE

LDO1-CAP
CPVDD

CBN

HPOUT-R/PORT-I-R

LINE1-VREFO-R
HPOUT-L/PORT-I-L

LINE1-VREFO-L

MIC2-VREFO

AVDD1

AVSS1
VREF
CA8 1 CA9 1
0_0402_5%

25mA +1.8V_AVDD
4.7U_0603_6.3V6K

0.1U_0402_10V6K

CBP 37 24
2 2 CBP LINE2_L

AUD_AGND 38 23
AVSS2 LINE2_R
CA22 1 2 LDO2_CAP 39 22 LINE1_L moat
AUD_AGND LDO2-CAP LINE1_L LINE1_L <43>
10U_0603_6.3V6M
CA63 1 2 40 21 LINE1_R RA17 1 @ 2 0_0402_5%
AUD_AGND AVDD2 LINE1_R LINE1_R <43> +3VALW
10U_0603_6.3V6M Pop RA18 to prevent "zizi"
41 20 RA18 1 2 0_0402_5%
+5V_PVDD PVDD1 5/3D3VSTB +RTCVCC noise on G3 or DC S5/S4.
Close pin9
AUD_SPK_L+ 42 19 CA23 1 2
<43> AUD_SPK_L+ SPK-OUT-L+ MIC-CAP AUD_AGND
ALC3246-CG-GP 10U_0402_6.3V6M
AUD_SPK_L- 43 18 SLEEVE Width>40mil, to improve Headpohone Crosstalk noise
<43> AUD_SPK_L- SPK-OUT-L- SA00008GJ00 MIC2_R/SLEEVE SLEEVE <43>
Layout Note: <43> AUD_SPK_R-
AUD_SPK_R- 44 17 RING2
RING2 <43>
Layout Note: Change it to sharp will be better.
SPK-OUT-R- MIC2_L/RING2 Add 2 vias (>0.5A) when trace layer change.
Speaker trace width >40mil @ 2W4ohm speaker power
AUD_SPK_R+ 45 16 RA19 1 @ 2 AUD_PC_BEEP
<43> AUD_SPK_R+ SPK-OUT-R+ MONO-OUT
RA23 +5V_PVDD 46 15 0_0402_5%
1 @ 2 PVDD2 SPDIFO/FRONT_JD/JD3/GPIO3

GPIO0/DMIC-DATA
+3V_DVDD
100K_0402_5% EC_MUTE# 47 14

GPIO1/DMIC-CLK
<44> EC_MUTE# PDB MIC2/LINE2_JD/JD2

EAPD/DC DET
48 13 AUD_SENSE_A RA22 1 2 AUD_SENSE

SDATA-OUT
SPDIF-OUT/GPIO2 HP/LINE1_JD/JD1 AUD_SENSE <43>

LDO3-CAP
200K_0402_5%

SDATA-IN

DVDD-IO

I2C_SCL
I2C_SDA
49
GND

DVDD

SYNC
BCLK
Place close to Pin 13 +3V_DVDD
RA24
B
1
moat AUD_SENSE_A 2 1 B
2

10

11

12
+3V_DVDD 100K_0402_5%
1
CA24

DMIC_CLK DMIC_DAT moat

LDO3_CAP
CA25 1 CA26 1 0.1U_0402_10V6K
2
1 1
CA30 CA62 +3V_DVDD
4.7U_0603_6.3V6K

0.1U_0402_10V6K

@RF@ @ AUD_AGND
47P_0402_50V8J 10P_0402_25V8J 2 2
2 2
CA27 1 CA28 1 D1
SPKR 3
Reserve for RF <15> SPKR
RA30 CA29
4.7U_0603_6.3V6K

0.1U_0402_10V6K
Close pin3 1 AUD_PC_BEEP_C 1 2 1 2 AUD_PC_BEEP
2 2 1K_0402_5%
BEEP 2 0.1U_0402_10V6K
<44> BEEP

1
BAT54C_SOT23-3 RA33
DMIC_DAT RA27 1 2 33_0402_5% DMIC_DATA_R
<35> DMIC_DAT SCSBAT5407L 10K_0402_5%
DMIC_CLK LA1 1 2 DMIC_CLK_R
<35> DMIC_CLK

2
EMI@ BLM15PX471SN1D_2P

HDA_SDOUT_R
<15> HDA_SDOUT_R HDA_BITCLK_R
<15> HDA_BIT_CLK_R HDA_SDIN0 RA32 1 2 HDA_SDIN0_R
moat
<15> HDA_SDIN0
33_0402_5% HDA_SYNC_R EMI@ RA9 1 2 0.1U_0402_10V6K
<15> HDA_SYNC_R
1 DVT1. EMI@ RA12 1 2 0.1U_0402_10V6K
CA66 EMI@ RA13 1 2 0.1U_0402_10V6K
@RF@ Change RA9, RA12, RA13, RA15 from 0ohm to 0.1uF 0402 Cap.
10P_0402_25V8J RA14 1 2 0_0402_5%
2 moat
A EMI@ RA15 1 2 0.1U_0402_10V6K A
RA16 1 2 0_0805_5%
Reserve for RF
AUD_AGND AUD_AGND

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CODEC ALC3246
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 42 of 78
5 4 3 2 1
 5 4 3 2 1

Main Func = Audio

Layout Note:
Speaker trace width >40mil @ 2W4ohm speaker power Speaker
JSPK1 CONN Pin Net name
<42>
<42>
Vinafix.com
AUD_SPK_R+
AUD_SPK_R-
AUD_SPK_R+
AUD_SPK_R-
LA23
LA24
EMI@
EMI@
1
1
2
2
BLM15PX181SN1D_2P
BLM15PX181SN1D_2P
AUD_SPK_R+_C
AUD_SPK_R-_C
1
2 1
2 Pin1 SPK_R+
AUD_SPK_L+ LA25 EMI@ 1 2 BLM15PX181SN1D_2P AUD_SPK_L+_C 3
<42> AUD_SPK_L+ AUD_SPK_L- AUD_SPK_L-_C 3
D LA26 EMI@ 1 2 BLM15PX181SN1D_2P 4 Pin2 SPK_R- D
<42> AUD_SPK_L- 4
CA36 CA37 CA38 CA39

3
EMI@ 1 EMI@ 1 EMI@ 1 EMI@ 1 DA2 DA3 5
ESD@ ESD@ 6 GND Pin3 SPK_L+
GND
Pin4 SPK_L-

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

AZ5125-02S.R7G_SOT23-3

AZ5125-02S.R7G_SOT23-3
ACES_50278-0040N-001
2 2 2 2 CONN@
SP02001CE00

1
C C

MIC2_VREFO RA42 1 2 2.2K_0402_5%

<42> MIC2_VREFO
RA43 1 2 2.2K_0402_5%
SLEEVE LA22 ESD@ 1 2 BLM15PX330SN1D 0402 SLEEVE_R
<42> SLEEVE RING2_R
RING2 LA19 ESD@ 1 2 BLM15PX330SN1D 0402
<42> RING2
AUD_HP1_JACK_L RA44 1 2 10_0402_1%
<42> AUD_HP1_JACK_L LINE1_L LINE1-L_C
CA64 1 2 RA48 1 2 1K_0402_5%
<42> LINE1_L LINE1_VREFO_L AUD_HP1_JACK_L1 AUD_PORTA_L_R_B
10U_0603_6.3V6M RA46 1 2 4.7K_0402_5% LA20 EMI@ 1 2 BLM15AX700SN1D_2P
<42> LINE1_VREFO_L AUD_HP1_JACK_R AUD_HP1_JACK_R1 AUD_PORTA_R_R_B
RA49 1 2 10_0402_1% LA21 EMI@ 1 2 BLM15AX700SN1D_2P
<42> AUD_HP1_JACK_R LINE1_R LINE1-L_R
CA65 1 2 RA51 1 2 1K_0402_5% 1 1
<42> LINE1_R LINE1_VREFO_R 10U_0603_6.3V6M RA53 1 2 4.7K_0402_5%
<42> LINE1_VREFO_R
CA40 CA41

680P_0402_50V7K

680P_0402_50V7K
Close to HDA1 EMI@ EMI@
2 2 JHP1
SLEEVE_R 3
AUD_PORTA_R_R_B 2 #3 M/G
#2 R
JACK_PLUG 6
#6 AGND

5
#5
AUD_AGND
AUD_PORTA_L_R_B 1
RING2_R 4 #1 L
B 7 #4 G/M B
Universal Jack GND
SINGA_2SJ3095-106111F
AUD_PORTA_L_R_B AUD_PORTA_L_R_B AUD_AGND CONN@
AUD_PORTA_R_R_B AUD_PORTA_R_R_B
DC23000FV00
RA56
AUD_SENSE 1 @ 2 JACK_PLUG
<42> AUD_SENSE
0_0402_5%
RING2_R RING2_R
SLEEVE_R SLEEVE_R
SINGA_2SJ3095-106111F
3

DA5 DA4
3

DA6 ESD@ ESD@

CA42 1 CA43 1 CA60 1 CA61 1 ESD@
ESD@ ESD@ @EMI@ @EMI@
moat
TVNST52302AB0_SOT523-3

L03ESDL5V0CC3-2_SOT23-3
AZ5125-02S.R7G_SOT23-3
680P_0402_50V7K

680P_0402_50V7K

33P_0402_50V8J

33P_0402_50V8J

AZ5123-02S.R7G_SOT23-3
2 2 2 2
1

1
SCA00001A00

AUD_AGND AUD_AGND AUD_AGND AUD_AGND

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SPKR/JACK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 43 of 78
5 4 3 2 1
 5 4 3 2 1

+3VALW +3VALW_EC SD034100280 10K_0402_1% +3VALW_EC

RE125 For RE125 UMA@ MODEL_ID SD034137280 13.7K_0402_1%
RE13 For RE13 EVT@ Board ID
RPE2 5 4 KSI0 +3VALW +3VALW_EC SKU ID Select SD034178280 17.8K_0402_1% Board ID Select
RE12

1
6 3 KSI1 UMA 10K SD034221280 22.1K_0402_1% EVT X00 10K
7 2 KSI2 1 @ 2 N17P_G0 17.8K RE125 SD034270280 27K_0402_1% DVT1 X01 17.8K RE13
8 1 KSI3 CE89 1 CE62 1 CE63 2 CE64 2 CE65 1 CE66 1 CE67 1 CE68 1 CE69 1 N17P_G1 27K Ra @ SD034324280 32.4K_0402_1% DVT2 X02 27K Ra @ 10K_0402_1%
0_0402_5% @ @ N17E_G1 37.4K 10K_0402_1% SD034374280 37.4K_0402_1% X03 37.4K
10K_0804_8P4R_5% 10K_0402_1% SD034499280 49.9K_0402_1% Pilot A00 49.9K 10K_0402_1%

2
10U_0603_6.3V6M

0.1U_0402_10V6K

1000P_0402_50V7K

1000P_0402_50V7K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
RPE3 5 4 KSI4 MODEL_ID SD034576280 57.6K_0402_1% BOARD_ID
6 3 KSI5 2 2 1 1 2 2 2 2 2 SD034100280 SD034649280 64.9K_0402_1%
SD034100280

2
7 2 KSI6 1 SD00000B180 73.2K_0402_1% 1
8 1 KSI7 RE125 N17E_G1@ RE125 N17P_G1@ RE125 N17P_G0@ CE104 SD000002780 82.5K_0402_1% RE13 PILOT@ RE13 DVT2@ RE13 DVT1@ CE98
Rb RE124 SD034931280 93.1K_0402_1% Rb RE14
10K_0804_8P4R_5% 0.1U_0402_10V6K 100K_0402_1% SD034107380 107K_0402_1% 0.1U_0402_10V6K 100K_0402_1%
RPE4 1 8 KSO0 2 SD034120380 120K_0402_1% 2

Vinafix.com

1
2 7 KSO1 SD034137380 137K_0402_1%
3 6 KSO2 SD034154380 154K_0402_1%
4 5 KSO3 37.4K_0402_1% 27K_0402_1% 17.8K_0402_1% SD034200380 200K_0402_1% 49.9K_0402_1% 27K_0402_1% 17.8K_0402_1%
SD034374280 SD034270280 SD034178280 EC_AGND SD034232380 232K_0402_1% SD034499280 SD034270280 SD034178280 EC_AGND
100K_0804_8P4R_5% +3VS SD034100380 100K_0402_1%
D RPE5 1 8 KSO4 D
2 7 KSO5
<46> KSI[0..7]
3 6 KSO6 1
4 5 KSO7 CE85 +3VALW_EC
<46> KSO[0..16]
100K_0804_8P4R_5% 0.1U_0402_10V6K PBAT_CHG_SMBDAT RE43 1 2
RPE6 1 8 KSO10 2 4.7K_0402_5%

5
2 7 KSO11 UE6 PBAT_CHG_SMBCLK RE44 1 2
3 6 KSO12
SA00004H300 4.7K_0402_5%

P
4 5 KSO13 H_PROCHOT# 4 2 PROCHOT TP_WAKE_KBC# RE53 1 2
<8,59,60,71> H_PROCHOT# Y A RE16
100K_0402_5%

NC

2
100K_0804_8P4R_5% 1 @ 2 +RTC_CELL_VBAT +3VALW_EC BREATH_LED# RE119 1 2
1 +RTCVCC
RPE7 1 8 KSO8 CE86 RE27 100K_0402_5%
1 For eSPI Power +1.8V_PRIM

3
2 7 KSO15 0_0402_5% CE73 TYPEC_SMBDA RE139 1 2
3 6 KSO14 47P_0402_50V8J SN74LVC1G06DCKR_SC70-5 100K_0402_5% +1.8V_PRIM +1.8VALW_EC 2.2K_0402_5%
2 RE15 TYPEC_SMBCLK
4 5 KSO16 0.1U_0402_10V6K RE140 1 2

1
2 1 @ 2 2.2K_0402_5%

122

103
100K_0804_8P4R_5% UPD1_ALERT RE141 1 2

43
82

19
65
5
RE30 2 1 KSO9 UE1 0_0402_5% 10K_0402_5%
100K_0402_5% 1V_PG RE149 2 @ 1 0_0402_5% PRIM_PWRGD 54 CE71 1 2

VBAT

VTR
VTR
VTR
VTR
VTR
VTR
USB_EN# <64> 1V_PG VTR_33_18
RE29 2 1 0.1U_0402_10V6K
100K_0402_5% +3VALW_PCH
RE39 2 1 BAT1_LED# +3VALW KSO0 2
100K_0402_5% KSO1 14 GPIO027/KSO00/PVT_IO1 8 PBAT_CHG_SMBDAT GPU_THM_SMBDAT RE45 1 2
RE113 2 1 BAT2_LED# KSO2 15 GPIO015/KSO01/PVT_nCS GPIO007/SMB01_DATA/SMB01_DATA18 9 PBAT_CHG_SMBCLK PBAT_CHG_SMBDAT <59,60> 2.2K_0402_5%
GPIO016/KSO02/PVT_SCLK GPIO010/SMB01_CLK/SMB01_CLK18 PBAT_CHG_SMBCLK <59,60>

1
100K_0402_5% KSO3 16 11 GPU_THM_SMBDAT GPU_THM_SMBCLK RE46 1 2
RE150 2 1 PRIM_PWRGD RE25 KSO4 37 GPIO017/KSO03/PVT_IO0 GPIO012/SMB02_DATA/SMB02_DATA18 12 GPU_THM_SMBCLK GPU_THM_SMBDAT <15,23,45> 2.2K_0402_5%
GPIO045/BCM_nINT1/KSO04 GPIO013/SMB02_CLK/SMB02_CLK18 TYPEC_SMBDA GPU_THM_SMBCLK <15,23,45>
100K_0402_5% KSO5 38 89
100K_0402_5% KSO6 39 GPIO046/BCM_DAT1/KSO05 GPIO130/SMB03_DATA/SMB03_DATA18 91 TYPEC_SMBCLK TYPEC_SMBDA <50>
KSO7 50 GPIO047/BCM_CLK1/KSO06 GPIO131/SMB03_CLK/SMB03_CLK18 96 TBTA_HRESET_EC RE148 2 @ 1 0_0402_5% TBTA_HRESET TYPEC_SMBCLK <50> DVT1.
TBTA_HRESET <50> Change pull high RE45, RE46 form +3VLAW_EC to +3VLAW_PCH

2
RE68 KSO8 46 GPIO025/KSO07/PVT_IO2 GPIO141/SMB04_DATA/SMB04_DATA18 97 TBT_RESET_N_EC#
+3VS_TP LID_CLOSE# 1 LID_CL_SIO# GPIO055/PWM2/KSO08/PVT_IO3 GPIO142/SMB04_CLK/SMB04_CLK18 TBT_RESET_N_EC# <36,50>
@ 2 KSO9 68
<46> LID_CLOSE# GPIO102/KSO09/CR_STRAP FAN1_TACH
0_0402_5% KSO10 72 40
CLK_TP_SIO GPIO106/KSO10 GPIO050/TACH0 FAN2_TACH FAN1_TACH <47> +3VS
RE24 1 2 KSO11 74 41
GPIO110/KSO11 GPIO051/TACH1 FAN2_TACH <47>

1
4.7K_0402_5% CE8 KSO12 75
RE55 1 2 DAT_TP_SIO KSO13 76 GPIO111/KSO12 44 KB_LED_PWM FPR_SCAN# RE143 1 2
4.7K_0402_5% 0.047U_0402_16V4Z KSO14 77 GPIO112/PS2_CLK1A/KSO13 MEC1416 GPIO053/PWM0 45 BEEP
KB_LED_PWM <46>
100K_0402_5%
BEEP <42>
2
KSO15 86 GPIO113/PS2_DAT1A/KSO14 GPIO054/PWM1
KSO16 92 GPIO125/KSO15 47 FAN1_PWM
PBAT_PRES# CAP_LED# GPIO132/KSO16 GPIO056/PWM3 FAN2_PWM FAN1_PWM <47>
93 34
<46> CAP_LED# GPIO140/KSO17 GPIO030/BCM_nINT0/PWM4 FAN2_PWM <47> IMVP_VR_ON
35 LANWAKE# RE23 1 @ 2
GPIO031/BCM_DAT0/PWM5 PS_ID LANWAKE# <15>
1 KSI0 98 36 10K_0402_5%
C GPIO143/KSI0/nDTR GPIO032/BCM_CLK0/PWM6 PCIE_WAKE# PS_ID <59> ME_FWP
C
CE76 KSI1 99 4 RE21 1 @ 2
GPIO144/KSI1/nDCD GPIO002/PWM7 PCIE_WAKE# <15,36,40,41>
KSI2 6 1K_0402_5%
100P_0402_50V8J KSI3 7 GPIO005/SMB00_DATA/SMB00_DATA18/KSI2 1 BAT2_LED# BKLT_IN_EC RE114 2 1
2 GPIO006/SMB00_CLK/SMB00_CLK18/KSI3 GPIO157/LED0/TST_CLK_OUT BAT1_LED# BAT2_LED# <48>
KSI4 104 106 100K_0402_5%
GPIO147/KSI4/nDSR GPIO156/LED1 BREATH_LED# BAT1_LED# <48> TBT_RESET_N_EC#
KSI5 105 70 RE151 2 1
GPIO150/KSI5/nRI GPIO104/LED2 BREATH_LED# <48>
KSI6 107 100K_0402_5%
KSI7 108 GPIO151/KSI6/nRTS 80 ME_FWP
GPIO152/KSI7/nCTS GPIO116/TFDP_DATA/UART_RX HOST_DEBUG_TX ME_FWP <15>
81
CLK_TP_SIO GPIO117/TFDP_CLK/UART_TX HOST_DEBUG_TX <41>
78
<47> CLK_TP_SIO DAT_TP_SIO GPIO114/PS2_CLK0 PTP_DIS# PTP_DIS#_R
79 90 RE57 1 @ 2 0_0402_5%
<47> DAT_TP_SIO SIO_PWRBTN# GPIO115/PS2_DAT0 GPIO035/SB-TSI_CLK H_PECI PECI_EC PTP_DIS#_R <47>
52 94 RE17 1 2 43_0402_5%
<15,20> SIO_PWRBTN# VCCDSW_ON_R GPIO026/PS2_CLK1B GPIO033/PECI_DAT/SB_TSI_DAT PECI_EC <8,13> +3VLP
RE153 2 @ 1 0_0402_5% 88
<55> VCCDSW_ON GPIO127/PS2_DAT1B VREF_CPU
95
ESPI_IO0 59 VREF_CPU
<16> ESPI_IO0 GPIO040/LAD0/ESPI_IO0

2
ESPI_IO1 60 101 ICSP_CLK
<16> ESPI_IO1 ESPI_IO2 61 GPIO041/LAD1/ESPI_IO1 GPIO145/ICSP_CLOCK 102 ICSP_DAT RE20
<16> ESPI_IO2 ESPI_IO3 62 GPIO042/LAD2/ESPI_IO2 GPIO146/ICSP_DATA 87 ICSP_CLR
<16> ESPI_IO3 ESPI_CS# 58 GPIO043/LAD3/ESPI_IO3 ICSP_MCLR 1K_0402_5%
<16> ESPI_CS# SATA_LED_EN RE132 2 1 10K_0402_5% MASK_SATA_LED# 56 GPIO044/LFRAME#/ESPI_CS# 119 NB_MUTE# RE58 1 @ 2 0_0402_5% EC_MUTE#
<48> SATA_LED_EN EC_MUTE# <42>

1
ESPI_CLK 57 GPIO064/nLRESET BGPO/GPIO004 120 SYSPWR_PRES SYSPWR_PRES
<16> ESPI_CLK GPIO034/PCI_CLK/ESPI_CLK SYSPWR_PRES/GPIO003
63 121 ALWON
T4942 @ GPIO067/nCLKRUN VCI_OUT/GPIO036 ALWON <61>

1
ESPI_ALERT# 55 126 RE52 1 2 100K_0402_5%
<16> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# nVCI_IN1/GPIO162 +RTCVCC
GPU_PWR_LEVEL 10 127 POWER_SW_IN# RE22
<23> GPU_PWR_LEVEL TP_EN# GPIO011/nSMI/nEMI_INT nVCI_IN0/GPIO163 HW_ACAV_IN ACAV_IN
49 128 RE138 1 @ 2 0_0402_5%
<47> TP_EN# ESPI_RESET# GPIO060/KBRST VCI_OVRD_IN/GPIO164 ACAV_IN <15,59,60>
53 100K_0402_5%
<16> ESPI_RESET# LID_CL_SIO# GPIO061/LPCPD#/ESPI_RESET# GC6_THM_DIS# +3VALW_EC
66 23
GC6_THM_DIS# <14>

2
GPIO100/nEC_SCI GPIO160/DAC_0 24 @ T4940
UPD1_ALERT 32 GPIO161/DAC_1 22 CE79 1 2
<50> UPD1_ALERT SYS_PWROK GPIO126/SHD_SCLK DAC_VREF
28 0.1U_0402_10V6K
<15,20> SYS_PWROK PBAT_PRES# GPIO133/SHD_IO0 CMP_VOUT0
29 85
<59,60> PBAT_PRES# PRIM_PWRGD_R RE133 PRIM_PWRGD GPIO134/SHD_IO1 GPIO124/CMP_VOUT0 CMP_VIN0 VCIN0_PH CMP_VOUT0 <23,61> +3VALW
1 @ 2 0_0402_5% 30 20 RE73 1 @ 2 0_0402_5%
<65> PRIM_PWRGD_R RTCRST_ON GPIO135/SHD_IO2 GPIO020/CMP_VIN0 VCIN0_PH <45>
31 25 VCREF0
<15,47> RTCRST_ON PCH_RSMRST# GPIO136/SHD_IO3 GPIO165/CMP_VREF0
27
<15,20> PCH_RSMRST# GPIO123/SHD_CS# [BSS_STRAP]

1
83 PROCHOT
L_BKLT_EN_EC RE134 1 @ 2 0_0402_5% BKLT_IN_EC 67 GPIO120/CMP_VOUT1 21 @ T4939 RE38
<13> L_BKLT_EN_EC AC_DIS GPIO101/SPI_CLK GPIO021/CMP_VIN1 LCD_TST
69 26
<60> AC_DIS USB_POWERSHARE_VBUS_EN71 GPIO103/SPI_IO0 GPIO166/CMP_VREF1/UART_CLK LCD_TST <35>
100K_0402_5%
<51> USB_POWERSHARE_VBUS_EN FPR_SCAN# GPIO105/SPI_IO1 USB_PWR_SHR_EN_L#
42 118
<48> FPR_SCAN# USB_PWR_SHR_EN_L# <51>

2
PTP_INT# RE61 1 @ 2 0_0402_5% TP_WAKE_KBC# 33 GPIO052/SPI_IO2 GPIO024/ADC7 117 PANEL_BKEN_EC RE33
<14,47> PTP_INT# LAN_EN AUX_ON GPIO062/SPI_IO3 GPIO023/ADC6/A20M SIO_EXT_WAKE# PANEL_BKEN_EC <35> CMP_VIN0
RE131 1 @ 2 0_0402_5% 3 116 1 @ 2 CMP_VOUT0
<40> LAN_EN GPIO001/SPI_nCS/32KHZ_OUT GPIO022/ADC5 MODEL_ID SIO_EXT_WAKE# <17>
109 100K_0402_5%
USB_EN# 13 GPIO153/ADC4 110 I_ADP
B <52> USB_EN# B
ALL_SYS_PWRGD RE62 1 @ 2 0_0402_5% RUNPWROK 48 nRESET_IN/GPIO014 GPIO154/ADC3 111 BOARD_ID
<15,61> ALL_SYS_PWRGD GPIO057/VCC_PWRGD GPIO155/ADC2

VSS_VBAT
IMVP_VR_ON RE135 1 @ 2 0_0402_5% RESET_OUT# 73 113 LCD_VCC_TEST_EN
<15> IMVP_VR_ON GPIO107/nRESET_OUT GPIO122/ADC1 LCD_VCC_TEST_EN <54>

VR_CAP
114 I_BATT
Note: MEC_XTAL2 GPIO121/ADC0

AVSS
SUSCLK RE106 2 @ 1 0_0402_5% 125 115
<15,39,41> SUSCLK +3VALW_EC

VSS
VSS
VSS
VSS
VSS
MEC_XTAL1 RE66 1 @ 2 0_0402_5% MEC_XTAL1_R 123 XTAL2 ADC_VREF
XTAL1 1
CE81
The LPC Interface signals require the VTR_33_18 power SA0000A8L00
124 MEC1416-NU-D0 VTQFP 128P_14X14
84
51
17
64
100

112

18
MEC1404-NU-TR_VTQFP128_14X14 0.1U_0402_10V6K
pin to be connected to the 3.3V VTR rail.

EC_AGND
2

The eSPI Interface signals require the VTR_33_18 power 32 KHz Clock 20ppm / 9pF
@ T4931
EC_AGND
pin to be connected to the 1.8V rail. The GPIO signals on Y1 ESR <50kohm (MAX)
MEC_XTAL1 1 2 MEC_XTAL2 RE67
VR_CAP CE103 1 2

these pins may operate at either 1.8V or 3.3V. 2 @ 1 1U_0603_25V6K +RTCVCC

32.768KHZ 9PF 20PPM 9H03280012 SE000006900
Y_X1A000141000200_2P 0_0603_5% ESR <100m ohms
‧ GPIO061/LPCPD#/ESPI_RESET#

1
SJ10000Q400 Close UE1 EC_AGND
Close UE1 RE31
‧ VTR_33_18
1

‧ GPIO063/SER_IRQ/ESPI_ALERT# CE102 CE101 100K_0402_5%

2
‧ GPIO064/LRESET# 12P_0402_50V8J 12P_0402_50V8J RE47
2

POWER_SW_IN# 1 2 POWER_SW#_MB
‧ GPIO034/PCI_CLK/ESPI_CLK 1K_0402_5%
POWER_SW#_MB <48>

‧ GPIO044/LFRAME#/ESPI_CS# 1
CE12
‧ GPIO040/LAD0/ESPI_IO0 2.2U_0402_6.3V6M
‧ GPIO041/LAD1/ESPI_IO1 2

‧ GPIO042/LAD2/ESPI_IO2 RE36
‧ GPIO043/LAD3/ESPI_IO3 I_ADP 1 2
300_0402_5%
I_ADP_R
I_ADP_R <59,60>
‧ GPIO067/CLKRUN# 1
CE87 +1P05VALW +3VALW

Debug Connector 2200P_0402_25V7K

1
2
RE116 RE34
+3VALW_EC EC_AGND 0_0402_5% @
10K_0402_1%
A RE147 A

2
+3VALW_EC +DEBUG_PWR I_BATT 1 2 I_BATT_R VREF_CPU VCREF0
RE130 I_BATT_R <60>
2

300_0402_5%

1
RE60 RE154 1 @ 2 1 1 1 IMVP_VR_ON CE82 1 2
10K_0402_5% CE107 CE77 CE91 RE35 @ 1000P_0402_50V7K
CONN@ 49.9_0402_1% 0_0402_5%
JDEG1 CONN@ JESPI1 2200P_0402_25V7K 0.1U_0402_10V6K 0.1U_0402_10V6K 10K_0402_1% ACAV_IN CE84 2 1
1

1 1 2 2 2 100P_0402_50V8J

2
1 2 JTAG_TDI RE109 1 @ 2 0_0402_5% ICSP_CLK 1 2
2 3 JTAG_TMS RE110 1 @ 2 0_0402_5% ICSP_CLR 2 3 ESPI_IO0 EC_AGND
3 4 JTAG_CLK 1 2 3 4 ESPI_IO1
Close to UE1 each pin
RE111 @ 0_0402_5% @ T3 PAD
4 5 JTAG_TDO RE112 1 @ 2 0_0402_5% ICSP_DAT 4 5 ESPI_IO2
5 6 MSCLK RE63 2 1 10K_0402_5% 5 6 ESPI_IO3
6 7
7 8
MSDATA
HOST_DEBUG_TX
RE65
RE64
2
2
@ 1
1
100K_0402_5%
10K_0402_5%
+3VALW_EC 6 7
7 8
ESPI_CS# RE144 1 @
0_0402_5%
2 ESPI_RESET# Security Classification Compal Secret Data Compal Electronics, Inc.
8 9 8 9 Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title
11 RE118 2 @ 1 10K_0402_5% 11 RE145 1 @ 2 PCH_PLTRST#_EC
12 GND
GND
9 10
10
12 GND
GND
9 10
10
ESPI_CLK 0_0402_5%
PCH_PLTRST#_EC <14,23,36,39,40,41,45>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC MEC1404
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
JXT_FP241AH-010GAAM JXT_FP241AH-010GAAM DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
JXT_FP241AH-010GAAM_10P-NPM JXT_FP241AH-010GAAM_10P-NPM MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 44 of 78
5 4 3 2 1
 5 4 3 2 1

Thermal Sensor
OTP Thermistor +3VALW

Fintek thermal sensor

1
+3VS RTH1

Vinafix.com Placed BOT near between DIMM 7.87K_0402_1%

CTH1 1

2
VCIN0_PH
<44> VCIN0_PH
D D

1
0.1U_0201_10V6K
2 1
HT1 CTh2

100K +-1% 0402 B25/50 4250K 0.01U_0402_16V7K

TOP VCORE REMOTE1+ Close UTH1 UTH1 SL200002H00
2

2
+3VS
1
C 1
CPU TOP side

1
QTH1 2 CTH3 CTH4 1 10 THM_SML1_CLK
VCC SCL

1
B @
MMBT3904WH_SOT323-3 E 2200P_0402_25V7K 2200P_0402_25V7K REMOTE1+ 2 9 THM_SML1_DATA RTH2 Common P/N :
3

2
2 DP1 SDA @
REMOTE1- REMOTE1- 3 8 10K_0402_5% SL200002H00 S THERM_ 100K +-1% 0402 B25/50 4250K
DN1 ALERT#
Main SL200000U00 S THERM_ 100K +-1% TSM0B104F4251RZ 0402 Thinking

2
REMOTE2+ REMOTE2+ 4 7 MAINPWON MAINPWON
BOTTOM GPU DP2 THERM# 2nd SL200001J00 S THERM_ 100K +-1% ERTJ0ER104F 0402 Panasonic
1

C 1 REMOTE2- 5
DN2 GND
6 3rd SL200000V00 S THERM_ 100K +-1% NCP15WF104F03RC 0402 MURATA
1

QTH2 2 CTH5 CT114

B @
MMBT3904WH_SOT323-3 E 2200P_0402_25V7K 2200P_0402_25V7K F75303M_MSOP10 +3VS +3VS
3

2
REMOTE2-
SA000046C00
Address 1001_101xb

1
1
REMOTE1,2 (+/-) : RTH3 RTH4
Trace width/space:10/10 mil

2
10K_0402_5% 10K_0402_5% QTH3A
Trace length:<8"

2
2
THM_SML1_DATA 1 6 GPU_THM_SMBDAT
C
GPU_THM_SMBDAT <15,23,44> C

5
DMN65D8LDW-7_SOT363-6 QTH3B

THM_SML1_CLK 4 3 GPU_THM_SMBCLK
GPU_THM_SMBCLK <15,23,44>
DMN65D8LDW-7_SOT363-6

RTH5 1 @ 2
0_0402_5%
RTH6 1 @ 2
0_0402_5%

TPM
UTPM1 650TPM@
+3VALW
Place CZ95,CZ96 as close as UTPM.1 RTPM1 1 @ 2
1 1
CTPM1 CTPM2 0_0402_5%
B TPM@ TPM@ B
NPCT650VBCYX QFN_TPM2.0 FW 1.3.2.8
SA00008ELD0 0.1U_0402_16V7K 10U_0402_6.3V6M DVT1.
2 2
UTPM1 @ Change RTPM10 connect from +3VALW to +3VALW_PCH.
1 +3VS
UTPM1 750TPM@ SIO_SLP_S0# RTPM3 1 2 0_0402_5% SIO_SLP_S0#_R 29 VSB
<15> SIO_SLP_S0# GPIO0/SDA/XOR_OUT
750TPM@ 30 8
RTPM11 1 2 0_0402_5% TPM_LPM# 3 GPIO1/SCL VDD 14
650TPM@ 6 GPIO2/GPX VDD 22 +3VALW_PCH CTPM3 1 CTPM4 1
GPIO3/BADD VDD +3V_TPM TPM@ TPM@
PCH_SPI_0_SO RTPM2 1 TPM@ 2 33_0402_5% PCH_SPI_0_MISO 24 2
<14> PCH_SPI_0_SO LAD0/MISO NC

10U_0402_6.3V6M

0.1U_0201_10V6K
NPCT750JAAYX QFN 32P PCH_SPI_0_SI RTPM4 1 TPM@ 2 33_0402_5% PCH_SPI_0_MOSI 21 7 RTPM10 1 2
<14,20> PCH_SPI_0_SI TPM_PIRQ# TPM_PIRQ#_R LAD1/MOSI NC 2 2
SA0000AQ220 RTPM12 1 @ 2 0_0402_5% 18 10 650TPM@ 0_0402_5%
<14> TPM_PIRQ# LAD2/SPI_IRQ# NC
15 11
LAD3 NC 25 RTPM15 1 2
PCH_SPI_0_CLK_R RTPM5 1 TPM@ 2 27_0402_5% PCH_SPI_0_CLK_TPM 19 NC 26 CTPM5 1 CTPM6 1 CTPM7
<14> PCH_SPI_0_CLK_R LCKL/SCLK NC 1 750TPM@ 0_0402_5%
PCH_SPI_0_CS#2 RTPM6 1 @ 2 0_0402_5% PCH_SPI_0_CS#2_R 20 31 TPM@ TPM@ TPM@
<14> PCH_SPI_0_CS#2 PCH_PLTRST#_EC LFRAME#/SCS# NC
17
<14,23,36,39,40,41,44> PCH_PLTRST#_EC LRESET#/SPI_RST#/SRESET#

10U_0402_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K
27 9
13 SERIRQ GND 16 2 2 2
CLKRUN#/GPIO4/SINT# GND
1

28 23
RTPM7 LPCPD# GND 32
650TPM@ 4 GND 33
10K_0402_5% 5 PP PGND 12
TEST Reserved
2

NPCT650VBBYX_QFN32_5X5
SA00008EL90
A
TPM Model NPCT650VBCYX NPCT750JAAYX A

RTPM11
RTPM3
Pop RTPM10
RTPM15
RTPM7 Security Classification Compal Secret Data Compal Electronics, Inc.
2017/01/06 2018/01/06 Title
RTPM11 Issued Date Deciphered Date
RTPM3 Thermal Sensor
Un-pop RTPM10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
RTPM15 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
RTPM7 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 45 of 78
5 4 3 2 1
 5 4 3 2 1

Fuse for KB Backlight Connector for Keyboard Backlight Lid Switch

Vinafix.com +5VS_KBL

+3VALW
1
D CE4 D

1
1U_0402_6.3V6K CE18
+5VS +5VS_KBL 2 JBL1 UE3
20mil
RE3 1 2 .1U_0402_16V7K
F1 2 1 KB_BL_DET 1 2 2 1 VCC 2
<13> KB_BL_DET 2
47K_0402_5% 3 5 1
3 G1 GND

2
SMD1206P050TF/15_0.5A_15V ULCSATU KB_LED_PWM# 4 6
RE4 4 G2 3 LID_CLOSE#
SP040002500 ACES_51575-00401-001 VOUT LID_CLOSE# <44>
100K_0402_1% 1
1 1 CONN@ YB8251PST23_PSOT23_3P CE17
CE5 CE6 SP01002BY00 TCS40DLR_SOT23F3

1
SA0000AO500 10P_0402_25V8J
1U_0402_6.3V6K 10U_0603_6.3V6M~D LED Maximum Current is 273mA 2

1
2 2 D QE5
KB_LED_PWM 2
<44> KB_LED_PWM
G
S L2N7002WT1G_SC-70-3

3
Current limited 20mA

C C

Connector for Keyboard

KSI[0..7] <44>
KSO[0..16] <44>
JKB1
32 30 KB_DET#
GND 30 KB_DET# <17>
31 29 KSI7
GND 29 28 KSI6
28 27 KSI4
27 26 KSI2
26 25 KSI5
25 24 KSI1
24 23 KSI3
23 22 KSI0
22 21 KSO5
21 20 KSO4
20 19 KSO7
19 18 KSO6
18 17 KSO8
17 16 KSO3
B 16 15 KSO1 +5VS +5VS +3VS +3VS B
15 14 KSO2 QE4
14 13 KSO0 DMG2301U-7_SOT23-3
13
2

12 KSO12
12 11 KSO16 CAP_LED_R 1 3 RE1 RE120
D

11 10 KSO15
10
1

9 KSO13 100K_0402_5% QE3 100K_0402_5%

G

9 8 KSO14 RE2
G
2

8 7 KSO9 1 3 CAP_LED#
7 CAP_LED# <44>
6 KSO11 240_0402_1%
D

6 1
5 KSO10 CE1
2

5 4 CAP_LED @ L2N7002WT1G_SC-70-3
4 3 0.1U_0402_10V7K~D
3 2 2
2 1
1
ACES_50699-03001-P01
ACES_50699-03001-P01_30P
CONN@
SP01001LM00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/KBBL/Lid
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 46 of 78
5 4 3 2 1
 5 4 3 2 1

Touch pad RTC GEN 9

+3VALW

2
+3VS_TP_OUT +3VS_TP
RZ32 UE4 RE93 +RTCVCC_PCH Q23 GEN9@ +RTCVCC

100K_0402_5% 5 Vinafix.com
OUT
1 1 @ 2
1 3

S
IN 1
2 0_0402_5% CE2

1
GND

1
1U_0402_6.3V6K
D TP_EN# 4 RZ33 PJ2301_SOT23-3 D
<44> TP_EN# EN

1
3 2 @ 1 0.1U_0402_10V6K C59 R73 SB00000T900

G
+3VALW

2
OCB 100K_0402_5% 2 GEN9@ GEN9@ D7 GEN9@
SY6288D20AAC_SOT23-5 10K_0402_5% 2 1

2
SA00007AO00

2
RB751S40_SOD523-2
AZ5125-01HPR7G_SOD523-2

GEN9@

1
D R78
2 1 2 RTCRST_ON
+3VS_TP RTCRST_ON <15,44>
G 1M_0402_5%

22P_0402_50V8J
Q24 S

2
GEN9@ R79

1
+3VS L2N7002WT1G_SC-70-3 C60 GEN9@ @

2
2
GEN9@ 100K_0402_5% C61
RE9 RE7 0.1U_0402_25V6

2
1
1.5K_0402_5% 1.5K_0402_5%
SD028150180 SD028150180

1
1
2
QE19A

I2C_1_SDA 1 6 I2C_1_SDA_C
<17> I2C_1_SDA
5

QE19B DMN65D8LDW-7_SOT363-6

I2C_1_SCL 4 3 I2C_1_SCL_C

C
<17> I2C_1_SCL
DMN65D8LDW-7_SOT363-6
RTC Battery C
+RTCBATT
+RTCBATT
W=20mils JRTC
DC2 1
+3VS_TP +RTCVCC 2 +RTCBATT_R 1 2 RC11 2 1
+3VS_TP 1K_0402_5% 2
W=20mils +3VLP
1 3
4 GND
1 W=20mils GND
1

3
RE87 RE123 CC27 ACES_50273-0020N-001
1U_0402_6.3V6K BAT54CW_SOT323-3 CONN@
2

QE13 100K_0402_5% 100K_0402_5% 2 BAT54CW-7-F_SOT323-3

G

SP02000SJ00
SCS00003800
2

PTP_INT# 1 3 PTP_INT#_R PTP_DIS#_R

<14,44> PTP_INT#
D

L2N7002WT1G_SC-70-3

I2C_1_SDA_C 3
DE4
I/O2
ESD@
I/O4
6 DAT_TP_SIO PWM FAN +3VS +5VS

+3VS
+5VS

1
1
2 5 +3VS_TP RE121 RE100 RE82 RE104
B GND VDD @ @ RE81 @ B
0_0402_5%

2
G
10K_0402_5% Q12 10K_0402_5% 10K_0402_5%
100K_0402_5% JFAN1

2
I2C_1_SCL_C 1 4 CLK_TP_SIO FAN1_PWM 3 1 FAN1_PWM_OUT DE7 +5VS_FAN1 1
<44> FAN1_PWM

2
I/O1 I/O3 FAN1_TACH 2 1 FAN1_TACH_D 2 1

D
<44> FAN1_TACH FAN1_PWM_OUT 2
AZC099-04S.R7G_SOT23-6 2N7002K_SOT23-3 1 3
CE99 RB751S40_SOD523-2 4 3
SB00000EN00 AZ5125-01HPR7G_SOD523-2 4
+3VS +5VS 0.01U_0402_16V7K 5
2 6 GND
GND
ACES_50278-0040N-001

1
+5VS CONN@
+3VS_TP RE122 RE101
JTP @ @
SP02001CE00

2
+3VS

G
8 10K_0402_5% Q13 10K_0402_5%
8

1
I2C_1_SDA_C 7 10
2

2
I2C_1_SCL_C 6 7 G2 9 FAN2_PWM 3 1 FAN2_PWM_OUT RE84 RE105
6 G1 <44> FAN2_PWM

1
5 S @

D
5 0_0402_5%
PTP_INT#_R 4 2N7002K_SOT23-3 RE83 10K_0402_5%
PTP_DIS#_R 3 4
<44> PTP_DIS#_R SB00000EN00

2
DAT_TP_SIO 2 3 100K_0402_5% JFAN2
<44> DAT_TP_SIO CLK_TP_SIO 1 2 DE9 +5VS_FAN2 1
<44> CLK_TP_SIO

2
1 FAN2_TACH 2 1 FAN2_TACH_D 2 1
<44> FAN2_TACH FAN2_PWM_OUT 2
CE9 1 1 CE10 CE80 1 1 CE105 ACES_51524-0080N-001 1 3
@ @ CONN@ CE100 RB751S40_SOD523-2 4 3
AZ5125-01HPR7G_SOD523-2 4
SP01001A900
22P_0402_50V8J

22P_0402_50V8J

SE074271K80
270P_0402_50V7K

270P_0402_50V7K
SE074271K80

0.01U_0402_16V7K 5
2 2 2 2 2 6 GND
A GND A

ACES_50278-0040N-001
CONN@
SP02001CE00
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN/TP/KB/PWR SW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 47 of 78
5 4 3 2 1
 5 4 3 2 1

LED Board Connector Screw Hole - Base on 0505 ME Drawing

+5VALW - Trace width : 20mil
+5VALW
JLED
CPU x 4 GPU x 2
4 6
LED1 3 4 G2 5 @ HCPU1 @ HCPU2 @ HGPU1 @ HGPU2
Vinafix.com
LED2 2
1
3
2
1
G1

1
D ACES_51575-00401-001 D
CONN@
SP01002BY00 H_4P0-G H_4P0-G H_4P0-G H_4P0-G

+5VALW +5VALW @ HCPU3 @ HCPU4

LED1 LED2

1
RH504 RH505

3
QE20A QE23B
100K_0402_5% 100K_0402_5% H_3P7-G H_3P7-G
2

2
2 5
DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6
GND Pad Hole x 16 Non-GND Pad Hole x 5
1

4
3

6
QE20B QE23A

@ H1 @ H2 @ H3 @ H4 @ H5 @ H20 @ H21 @ H22

5 2
<44> BAT1_LED#
DMN65D8LDW-7_SOT363-6
<44> BAT2_LED#
DMN65D8LDW-7_SOT363-6
Remove H6
12/21
4

1
H_2P8-G H_2P8-G H_2P8-G H_2P8-G H_3P3 H_2P8X3P4N H_2P8N H_2P8X3P4N

@ H7 @ H8 @ H10 @ H11 @ H9 @ H23

C
Remove H12 C
12/21

1
LED2

H_2P8-G H_2P8-G H_2P8-G H_2P8-G H_2P8N H_4P5N

3
QE21B @ H13 @ H14 @ H15 @ H16 @ H17 @ H18

SATA_LED_EN 5
<44> SATA_LED_EN

1
DMN63D8LDW-7_SOT363-6
1

VGS(th) = 0.8V -1.5V FD5 FD6

4

RE152 H_3P3 H_2P8X3P4-G H_2P8-G H_2P8-G H_2P8-G H_3P0-G Add FD5, FD6 @ FIDUCIAL @ FIDUCAL
For DFB
6

QE21A 1M_0402_5% @ H19

2/12
2

1
PCH_SATA_LED# 2
<13> PCH_SATA_LED#

1
DMN63D8LDW-7_SOT363-6 FD1 FD2 FD3 FD4
RH502 VGS(th) = 0.8V -1.5V @ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
1

SSD_LED# 1 @ 2 H_3P0-G
<39> SSD_LED#
0_0402_5%

1
PWR BOARD Connector Touch Finger Print module. Power Button & LED (Reserve)
B B
+5VALW +5VALW
BREATH_LED_MB +3VS +3V_FPSW JPW
RW4 +3V_FPSW +5VALW
1
1
1

1 @ 2 2 LED3 @ RW3
RH506 3 2 C5235 BREATH_LED_MB 1 2 BREATH_LED_R2 1 DEBUG@2
3
3

1
QE24B POWER_SW#_MB 0_0402_5% 4 300_0402_5%
100K_0402_5% BREATH_LED_MB 5 4 HT-F196BP5_WHITE
5

1U_0402_10V6K
6
2

2
5 USB20_P9_R 7 6
DMN65D8LDW-7_SOT363-6 USB20_N9_R 8 7
9 8 11
4

FPR_SCAN# 10 9 G11 12
<44> FPR_SCAN# 10 G12
6

QE24A
ACES_51530-01001-P01
2

2
D5225 D5226 D5223 CONN@
BREATH_LED# 2 @ESD@ FP1@ESD@ FP1@ESD@ SW5 DEBUG@
<44> BREATH_LED#
DMN65D8LDW-7_SOT363-6
SP010025K00 Close to JPW POWER_SW#_MB 1 2
<44> POWER_SW#_MB
TVNST52302AB0_SOT523-3

TVNST52302AB0_SOT523-3

SCA00001A00
L03ESDL5V0CC3-2_SOT23-3
AZ5125-02S.R7G_SOT23-3
1

3 4
1

SKRBAAE010_4P

R126 1 2 @
SN111005800
0_0201_5%
R_0201-NPM
A A

TR5807 FP1@EMI@
USB20_P9 2 1 USB20_P9_R
<16> USB20_P9 2 1

USB20_N9 3 4 USB20_N9_R
<16> USB20_N9 3 4 Security Classification Compal Secret Data Compal Electronics, Inc.
DLM0NSN900HY2D_4P 2017/01/06 2018/01/06 Title
Issued Date Deciphered Date
SM070005U00 CONN/LED/Screws/PW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R127 1 2 @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0_0201_5% DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
R_0201-NPM MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 48 of 78
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

Reserved
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserved
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 49 of 78
5 4 3 2 1
 5 4 3 2 1

+5VALW

60mil 3A
+3VALW +3VALW_PD CT90 1 CT91 1 CT92 1 CT93
RT53 PD@ PD@ PD@ PD@
1
TBT_A_TTX_C_DRX_P0 DT2 1 2
SC40000AT00
1 @ 2 TBT@ESD@ PESD5V0H1BSF_SOD962-2-2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 ESD8011MUT5G_X3DFN2-2
0_0402_5% CT88 2 2 2 2
PD@ TBTA_LDO_BMC TBT_A_TTX_C_DRX_N0 DT3 1 2
SC40000AT00
0.1U_0402_10V6K TBT@ESD@ PESD5V0H1BSF_SOD962-2-2
2 +1.8VD_TBTA_LDO ESD8011MUT5G_X3DFN2-2

+3VS +1.8VA_TBTA_LDO TBT_A_TRX_DTX_P0 DT4 1 2

SC40000AT00

Vinafix.com CT98 CT99 1 CT100 1 TBT@ESD@ PESD5V0H1BSF_SOD962-2-2

1
PD@ PD@ PD@ +TBTA_VBUS ESD8011MUT5G_X3DFN2-2

60mil 3A SC40000AT00

1
1

2.2U_0603_16V6K

4.7U_0603_10V6K

4.7U_0603_10V6K
TBT_A_TRX_DTX_N0 DT5 1 2

2
D RT57 RT58 2 2 TBT@ESD@ PESD5V0H1BSF_SOD962-2-2 D
@ @ CT106 ESD8011MUT5G_X3DFN2-2

3
10K_0201_5% 10K_0201_5% PD@ SC40000AT00
DT1 DT15 TBT_A_TTX_C_DRX_P1 DT6 1 2

2
2

1U_0603_25V6K
PD@ESD@ PD@ESD@ TBT@ESD@ PESD5V0H1BSF_SOD962-2-2

2
ESD8011MUT5G_X3DFN2-2

AZ5125-01HPR7G_SOD523-2
RB751S40_SOD523-2
TYPEC_SMBDA RT59 1 @ 2 PD_I2C_SDA_R PESD24VS2UT_SOT23-3 SC40000AT00

2
<44> TYPEC_SMBDA 0_0201_5% TBT_A_TTX_C_DRX_N1 DT7 1 2

1
TYPEC_SMBCLK RT60 1 @ 2 PD_I2C_SCL_R TBT@ESD@ PESD5V0H1BSF_SOD962-2-2
<44> TYPEC_SMBCLK +3VALW_PD
0_0201_5% ESD8011MUT5G_X3DFN2-2
UPD1_ALERT RT120 1 @ 2 PD_I2C_INT#
<44> UPD1_ALERT
0_0402_5% TBT_A_TRX_DTX_P1 DT8 1 2
SC40000AT00
1 Close TBT@ESD@ PESD5V0H1BSF_SOD962-2-2
CT101 ESD8011MUT5G_X3DFN2-2
PD@
to UT4
TBT_A_TRX_DTX_N1 1 2
SC40000AT00
Master0: 0 ohm 1U_0402_6.3V6K
2
DT9
TBT@ESD@ PESD5V0H1BSF_SOD962-2-2
Slave1:93.1K ohm

H10

C11
D11
A11
B11

B10

A10
H1
ESD8011MUT5G_X3DFN2-2

B1

K1

A2

E1

A6
A7
A8
B7

B9

A9
UT4 Change DT1 and add DT15 SC40000AT00
RT83 1 @ 2 F1 TBT_A_SBU1 DT13 1 2

VDDIO

PP_FCM
PP_FCM
PP_FCM
PP_FCM
LDO_1V8A

LDO_1V8D

LDO_BMC

PP_CABLE

SENSEP

SENSEN
VIN_3V3

PP_5V0
PP_5V0
PP_5V0
PP_5V0

HV_GATE1

HV_GATE2
0_0201_5% I2C_ADDR follow E-team's design for DELL dat.04/07 TBT@ESD@ PESD5V0H1BSF_SOD962-2-2
TBT_I2C_SDA D1 ESD8011MUT5G_X3DFN2-2
<36> TBT_I2C_SDA TBT_I2C_SCL D2 I2C_SDA1
<36> TBT_I2C_SCL TBTA_I2C_INT C1 I2C_SCL1 TBT_A_SBU2 DT14 1 2
SC40000AT00
<36> TBTA_I2C_INT I2C_IRQ1_N TBT@ESD@ PESD5V0H1BSF_SOD962-2-2
ESD8011MUT5G_X3DFN2-2
PD_I2C_SDA_R A5
PD_I2C_SCL_R B5 I2C_SDA2 H11
PD_I2C_INT# B6 I2C_SCL2 VBUS J10
I2C_IRQ2_N VBUS J11 RT129 1 2 @TBT@EMI@
B2 VBUS K11 0_0201_5%
T65 @ C2 GPIO0 VBUS R_0201-NPM
RT111 2 PD@ 1 D10 GPIO1
1M_0201_1% T4936 @ G11 GPIO2 +3.3V_TBT_SX_R +3.3V_TBT_SX LT2 TBT@EMI@
+3.3V_FLASH TBTA_HPD C10 GPIO3 RT61 TBT_A_USB20_TP 4 3 TBT_A_USB20_TP_R
<36> TBTA_HPD GPIO4 4 3
T121 @ E10 H2 1 @ 2
G10 GPIO5 VOUT_3V3 0_0201_5%
GPIO6 1
1

D7 +3.3V_FLASH CT102 TBT_A_USB20_TN 1 2 TBT_A_USB20_TN_R

RT112 RT123 TBT_CONFIG H6 GPIO7 PD@ 1 2
C
PD@ TBT@EMI@ GPIO8 G1 1U_0201_6.3V6M DLM0NSN900HY2D_4P
C

10K_0201_5% PD_EE_CLK_R 2 1 PD_EE_CLK A3 LDO_3V3 2

15_0201_1% PD_EE_DI B4 SPI_CLK 1
CT103
SM070005U00
2

TBT_CONFIG PD_EE_DO A4 SPI_MOSI PD@ 1 2

PD_EE_CS_N B3 SPI_MISO K6 TBT_A_USB20_TP 10U_0402_6.3V6M RT130 0_0201_5% @TBT@EMI@
SPI_SS_N C_USB_TP
1

SN1610042ZQZR BGA 96P_BGA96 L6 TBT_A_USB20_TN 2 R_0201-NPM

RT113 TBT_A_USB20_P L5 C_USB_TN
PD@ <36> TBT_A_USB20_P TBT_A_USB20_N K5 USB_RP_P
100K_0201_5% <36> TBT_A_USB20_N USB_RP_N RT131 1 2 @TBT@EMI@
PD_UART E2 K7 TBT_A_USB20_BP 0_0201_5%
2

RT62 2 PD@ 1 F2 UART_TX C_USB_BP L7 TBT_A_USB20_BN R_0201-NPM

100K_0201_5% UART_RX C_USB_BN
F4 LT3 TBT@EMI@
T62 @ SWD_DATA
TI's Request G4 PD@ TBT_A_USB20_BN 4 3 TBT_A_USB20_BN_R
T63 @ SWD_CLK 4 3
L9 TBT_A_CC1 CT112 1 2 220P_0201_25V7K
TBT_RESET_N_EC# RT122 2 @ 1 C_CC1 L10 TBT_A_CC2 CT113 1 2 220P_0201_25V7K +3.3V_FLASH
<36,44> TBT_RESET_N_EC# C_CC2 TI's Requirement TBT_A_USB20_BP TBT_A_USB20_BP_R
0_0201_5% 1 2
RT63 2 PD@ 1 TBTA_MRESET E11 PD@ 1 2
100K_0201_5% MRESET DLM0NSN900HY2D_4P

1
K9
TBTA_LSTX L4 RPD_G1 K10 RT66 RT67
SM070005U00
TBTA_DIG_AUD_P <36> TBTA_LSTX TBTA_LSRX TBT_LSTX/R2P RPD_G2
RT68 2 PD@ 1 100K_0201_5% K4 PD@ PD@ 1 2
TBTA_DIG_AUD_N <36> TBTA_LSRX TBT_LSRX/P2R
RT69 2 PD@ 1 100K_0201_5% 10K_0201_5% 10K_0201_5% RT132 0_0201_5% @TBT@EMI@
RT71 2 PD@ 1 100K_0201_5% TBTA_DEBUG1 R_0201-NPM

2
RT72 2 PD@ 1 100K_0201_5% TBTA_DEBUG2 TBTA_DIG_AUD_P L3 E4 DEBUG_CTL1 DEBUG_CTL1
TBTA_DIG_AUD_N K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 DEBUG_CTL2 DEBUG_CTL2
DIG_AUD_N/DEBUG4 DEBUG_CTL2 DT10 TBT@ESD@
TBT_A_USB20_TP_R 1 9 TBT_A_USB20_TP_R
TBTA_DEBUG1 L2
TBTA_LSTX RT114 1 @ 2 0_0201_5% TBTA_DIG_AUD_P TBTA_DEBUG2 K2 DEBUG1 TBT_A_USB20_TN_R 2 8 TBT_A_USB20_TN_R
TBTA_LSRX RT115 1 @ 2 0_0201_5% TBTA_DIG_AUD_N DEBUG2
K8 TBT_A_SBU1 TBT_A_USB20_BN_R 4 7 TBT_A_USB20_BN_R
TBT_A_AUX_P_C J1 C_SBU1
PD_I2C_SCL_R RT118 2 @ 1 0_0201_5% TBTA_DEBUG1 +3.3V_FLASH TBT_A_AUX_N_C J2 AUX_P L8 TBT_A_SBU2
Differential Signal TBT_A_USB20_BP_R 5 6 TBT_A_USB20_BP_R
PD_I2C_SDA_R RT119 2 @ 1 0_0201_5% TBTA_DEBUG2 AUX_N C_SBU2

RT74 1 @ 2 BUSPOWER# F10 RT102

BUSPOWER_N F11 RESET_N 1 @ 2 TBT_RESET_N 3
+3.3V_TBT_SX RESET_N TBT_RESET_N <36>
B 0_0201_5% 0_0201_5% B
TBTA_ROSC G2 TVWDF1004AD0_DFN9
R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1

TBTA_HRESET D6 L11
<44> TBTA_HRESET HRESET NC
RT70
1

PD@ PD@ TBT_A_CC2

A1
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
100K_0201_5% RT108 RT75 TBT_A_CC1
0_0201_5% @ PD@
SA0000AK400
2

2
TBT_A_AUX_P_C 15K_0402_0.1% DT11
<36> TBT_A_AUX_P_C TBT_A_AUX_N_C TBT@ESD@
1
2

<36> TBT_A_AUX_N_C PD@

1

CT104
RT73 0.22U_0402_10V6K
PD@
TBTA_HRESET might be connected to EC 2 TVNST52302AB0_SOT523-3
or PCH to allow TPS65982 FW load

1
100K_0201_5% +TBTA_VBUS +TBTA_VBUS
Active high hardware reset input. Will re-load settings JUSBC1
2

6 5
from optional external flash memory. Ground pin when 3 GND10 GND9 2
HRESET functionality will not be used. GND7 GND6
4 1
BUSPOWERZ GND8 GND5
Sampled by ADC at boot. Tie pin to LDO_3V3
through a 100-kohm resistor to disable PP_EXT B1
GND4 GND2
A12
power path during dead-battery or no-battery boot TBT_A_TTX_C_DRX_P0 TBT_A_TRX_DTX_P0
B2 A11

Bottom
conditions. <36> TBT_A_TTX_C_DRX_P0 TBT_A_TTX_C_DRX_N0 B3 SSTXP2 SSRXP2 A10 TBT_A_TRX_DTX_N0 TBT_A_TRX_DTX_P0 <36>
<36> TBT_A_TTX_C_DRX_N0 SSTXN2 SSRXN2 TBT_A_TRX_DTX_N0 <36>

TOP
CT94 1 2 B4 A9 CT96 1 2
TBT@ 0.01U_0402_50V7K VBUS4 VBUS2 TBT@ 0.01U_0402_50V7K
TBT_A_CC1 B5 A8 TBT_A_SBU2
CC2 SBU1
TBT_A_USB20_TP_R B6 A7 TBT_A_USB20_BN_R
+3.3V_FLASH TBT_A_USB20_TN_R B7 DP2 DN1 A6 TBT_A_USB20_BP_R
DN2 DP1
RT125 2 PD@ 1 3.3K_0201_5% PD_EE_DO TBT_A_SBU1 B8 A5 TBT_A_CC2
RT126 2 PD@ 1 3.3K_0201_5% PD_EE_CS_N SBU2 CC1
RT127 2 PD@ 1 3.3K_0201_5% PD_EE_WP# CT95 1 2 B9 A4 CT97 1 2
RT128 2 PD@ 1 3.3K_0201_5% PD_EE_HOLD# TBT@ 0.01U_0402_50V7K VBUS3 VBUS1 TBT@ 0.01U_0402_50V7K
TBT_A_TRX_DTX_N1 B10 A3 TBT_A_TTX_C_DRX_N1
A <36> TBT_A_TRX_DTX_N1 TBT_A_TRX_DTX_P1 SSRXN1 SSTXN1 TBT_A_TTX_C_DRX_P1 TBT_A_TTX_C_DRX_N1 <36> A
B11 A2
+3.3V_FLASH +3.3V_FLASH <36> TBT_A_TRX_DTX_P1 SSRXP1 SSTXP1 TBT_A_TTX_C_DRX_P1 <36>
UT5 PD@ B12 A1
PD_EE_CS_N 1 8 GND3 GND1
CS# VCC 1
PD_EE_DO 2 7 PD_EE_HOLD# CT117 JAE_DX07S024JJ7R1200
PD_EE_WP# 3 DO HOLD# 6 PD_EE_CLK_R PD@ JAE_DX07S024JJ7R1200_24P-T
4 WP# CLK 5 PD_EE_DI 0.1U_0201_6.3V6K CONN@
GND DI 2
W25X20CLSNIG_SO8
LTCX0074A1L
SA00003GM30
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PD+USB3.1 type C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 50 of 78
5 4 3 2 1
 5 4 3 2 1

USB Powershare
RI65 1 2 @EMI@
0_0201_5%
Device Control Pins CTL1 = 0 : Enable Power Share DCP mode in Suspend mode R_0201-NPM
Flow Line
Condition Suspend mode LI8 EMI@
CTL1 CTL2 CTL3 ILIM_SEL CHR_USB20_P1 4 3 CHR_USB20_P1_R
CTL1 = 1 : Disable Power Share in Suspend mode (For Support USB wake) 4 3

0 1 1 X DCP AUTO Vinafix.com CHR_USB20_N1 1

1 2
2 CHR_USB20_N1_R

ILIM_SEL = 0 : SDP mode (0.9A by ILIM_LO setting) DLM0NSN900HY2D_4P

D 1 1 1 0 SDP SM070005U00
D
S0 mode
RI66 1 2 @EMI@
1 1 1 1 CDP ILIM_SEL = 1 : CDP mode (STATUS# trigger by ILIM_HI =2.2A) 0_0201_5%
R_0201-NPM

DI12 ESD@
USB3_PTX_RD_DRX_P1 CI28 1 2 USB3_PTX_C_DRX_P1 1 9 USB3_PTX_C_DRX_P1
0.1U_0402_10V7K
USB3_PTX_RD_DRX_N1 CI29 1 2 USB3_PTX_C_DRX_N1 2 8 USB3_PTX_C_DRX_N1

USB3.0 / USB2.0 Port1 0.1U_0402_10V7K

USB3_PRX_RD_DTX_P1 4 7 USB3_PRX_RD_DTX_P1

USB3_PRX_RD_DTX_N1 5 6 USB3_PRX_RD_DTX_N1

+3VALW
+5VALW +5V_CHGUSB_3
ILIM_SEL_R US1
RI30 1 2 3
100K_0402_5% CI23 2 1 1 12
RI9 1 2 USB_R_CTL 0.1U_0402_10V6K IN OUT TVWDF1004AD0_DFN9
100K_0402_5% USB20_N1 2
RI10 1 2
100K_0402_5%
USB_PWR_SHR_EN_L# <16>
<16>
USB20_N1
USB20_P1
USB20_P1 3 DM_OUT
DP_OUT 10 CHR_USB20_P1
Place close to JUSB3
RI51 1 2 USB_POWERSHARE_VBUS_EN USB_OC0# 13 DP_IN 11 CHR_USB20_N1 CHR_USB20_P1_R
<16> USB_OC0# FAULT# DM_IN CHR_USB20_N1_R
1M_0402_5%
ILIM_SEL_R 4
ILIM_SEL DI11

2
USB_POWERSHARE_VBUS_EN 5 15 ILIM_LO1 RI49 1 2 22.1K_0402_1% ESD@
<44> USB_POWERSHARE_VBUS_EN EN ILIM_LO ILIM_HI1
16 RI45 1 2 22.1K_0402_1%

2
ILIM_HI

AZC199-02SPR7G_SOT23-3
USB_PWR_SHR_EN_L# 6
<44> USB_PWR_SHR_EN_L# CTL1

1
7 9
USB_R_CTL 8 CTL2 NC 14

1
CTL3 GND 17
C GNDP C
TPS2544RTER_WQFN16_3X3
SA000070N00

USB3.0 Re-driver
Setting Status
USB3.0 / USB2.0 Left Side
B_EQ A_EQ B_DE A_DE From PCH +5V_CHGUSB_3
+5V_CHGUSB_3
JUSB3
NC 6.0dB NC 6.0dB NC -3.5dB NC -3.5dB PERICOM: RXA, PS8713: B_In 1 CI21 1 CI27 1 CI26 1 CI25 1
CHR_USB20_N1_R 2 VBUS @
PI3EQX7502AI 0 3.0dB 0 3.0dB 0 0.0dB 0 0.0dB D-

0.1U_0402_10V6K
CHR_USB20_P1_R 3
PERICOM: TXB, PS8713: A_Out D+

100U_1206_6.3V6K

47U_0805_6.3V6M

10U_0603_6.3V6M
4
1 9dB 1 9dB 1 -6.0dB 1 -6.0dB USB3_PRX_RD_DTX_N1 5 GND 2 2 2 2
USB3_PRX_RD_DTX_P1 6 SSRX- 10
A B A B 7 SSRX+ GND 11
A_EQ B_EQ A_DE B_DE USB3_PTX_C_DRX_N1 8 GND GND 12
EQ0 EQ1 EQ0EQ1 DE0DE1 DE0DE1 USB3_PTX_C_DRX_P1 9 SSTX- GND 13
To USB3 CONN SSTX+ GND
ACON_TCRA2-9R1394
PS8713
0 0 9.5dB 0 0 9.5dB 0 0 -3.5dB 0 0 -3.5dB ACON_TCRA2-9R1394_9P
0 1 4.5dB 0 1 4.5dB 0 1 -2.7dB 0 1 -2.7dB PERICOM: TXA, PS8713:B_Out CONN@
DC23300ES00
1 0 13 dB 1 0 13 dB 1 0 0.0dB 1 0 0.0dB PERICOM: RXB, PS8713:A_In
1 1 7.5dB 1 1 7.5dB 1 1 -5.0dB 1 1 -5.0dB
B
* red color is current setting B

+3V_USBRD UI3 PARADE@

PS8713
13
1 VCC<1> +3V_USBRD +3V_USBRD
VCC<0>
USB3_PTX_DRX_P1 CI5 1 2 0.1U_0402_10V7K USB3_PTX_C_RD_DRX_P1 9 22 USB3_PTX_RD_DRX_P1
<16> USB3_PTX_DRX_P1 USB3_PTX_DRX_N1 USB3_PTX_C_RD_DRX_N1 RX1P TX1P USB3_PTX_RD_DRX_N1
CI6 1 2 0.1U_0402_10V7K 8 23
<16> USB3_PTX_DRX_N1 RX1N TX1N

2
USB3_PRX_DTX_P1 CI7 1 2 0.1U_0402_10V7K USB3_PRX_C_RD_DTX_P1 12 19 USB3_PRX_RD_DTX_P1 RI22 RI21 RI20 RI19 RI18 RI17 RI16 RI15
<16> USB3_PRX_DTX_P1 USB3_PRX_DTX_N1 USB3_PRX_C_RD_DTX_N1 TX2P RX2P USB3_PRX_RD_DTX_N1
CI8 1 2 0.1U_0402_10V7K 11 20 @ @ @ @ @ @ @ @
<16> USB3_PRX_DTX_N1 TX2N RX2N 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 10K_0402_5% 4.7K_0402_5% 10K_0402_5%
A_EQ0 2 7 REXT_8713

1
A_DE0 3 EQ1 NC<0> 24 I2C_EN8713 A_DE0 A_EQ0
PS8713 CH_B A_OS0 4 DE1 NC<1> A_DE1 A_OS0
OS1 14 USB8713_test
B_EQ0 17 RSVD 6 A_DE1 B_DE0 B_EQ0
PS8713 CH_A B_DE0 16 EQ2 GND<0> 18 B_DE1 B_DE1 B_OS0
B_OS0 15 DE2 GND<2>
OS2

2
21
5 GND<3> 10 RI58 RI56 RI57 RI54 RI48 RI47 RI46 RI55
EN_RXD GND<1> 25 @ @ @ @ @ @ @ @
THPAD 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
+3VALW PS8713BTQFN24GTR2-A1 TQFN

1
RI67 SA00005OR30
1 @ 2
0_0402_5%

+3VS +3V_USBRD
RI59
1 2
A 0_0402_5% A
CI3 1 CI4 1
+3V_USBRD
PS8713: I2C_EN8713 RI25 2 @ 1 0_0402_5%
Pin8,9=B_In, P22,23=B_Out
0.1U_0402_10V7K

0.01U_0402_16V7K

REXT_8713 RI23 2 1 4.99K_0402_1% USB8713_test RI24 1 @ 2

2 2 4.7K_0402_5%
Pin11,12=A_Out, Pin19,20=A_In
UI3 PERICOM@ Pin 17=A_EQ0, Pin 15=A_EQ1
Pin 16=A_DE0, Pin 18=A_DE1
Pin 2=B_EQ0, Pin 4=B_EQ1 Security Classification Compal Secret Data Compal Electronics, Inc.
Pin 3=B_DE0, Pin 6=B_DE1 Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

PI3EQX7502AIZDEX TQFN24 USB3.0 REDR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB Powershare
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
SA00006WV00 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 51 of 78
5 4 3 2 1
 5 4 3 2 1

USB Power Switch

+5VALW

1
CI24 +5V_CHGUSB_1_OUT +5V_CHGUSB_1
Vinafix.com 1U_0402_6.3V6K
2
US2
OUT
1 1 @ 2
5 RE115 0_0805_5%
IN 2
D D
USB_EN# 4 GND
<44> USB_EN# EN USB_OC1#
3
Active Low OCB USB_OC1# <16>
SY6288D20AAC_SOT23-5
SA00007AO00

+5VALW
+5V_CHGUSB_1
+5V_CHGUSB_1_OUT
Trace width : 100mil

RI68 1
0_0201_5%
2 @EMI@ USB3.0 / USB2.0 Right Side
R_0201-NPM

LI2 EMI@
USB20_N2 1 2 USB20_N2_R
<16> USB20_N2 1 2
+5V_CHGUSB_1
C USB20_P2 4 3 USB20_P2_R +5V_CHGUSB_1 C
<16> USB20_P2 4 3 JUSB1
DLM0NSN900HY2D_4P 1 CI30 1 CI17 1 CI18 1 CI19 1
USB20_N2_R USB20_N2_R 2 VBUS
SM070005U00 USB20_P2_R USB20_P2_R 3 D-
D+

100U_1206_6.3V6K

47U_0805_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K
RI69 1 2 @EMI@ 4
GND

3
0_0201_5% DI10 USB3_PRX_DTX_N2 5 2 2 2 2
R_0201-NPM ESD@ USB3_PRX_DTX_P2 6 SSRX- 10

3
7 SSRX+ GND 11
DI9 GND GND

AZC199-02SPR7G_SOT23-3
ESD@ USB3_PTX_C_DRX_N2 8 12
SSTX- GND

1
USB3_PRX_DTX_N2 1 9 USB3_PRX_DTX_N2 USB3_PTX_C_DRX_P2 9 13
<16> USB3_PRX_DTX_N2 SSTX+ GND

1
USB3_PRX_DTX_P2 2 8 USB3_PRX_DTX_P2 ACON_TCRA2-9R1394
<16> USB3_PRX_DTX_P2
ACON_TCRA2-9R1394_9P
USB3_PTX_DRX_N2 CI16 1 2 USB3_PTX_C_DRX_N2 4 7 USB3_PTX_C_DRX_N2 CONN@
<16> USB3_PTX_DRX_N2
0.1U_0402_10V6K DC23300ES00
USB3_PTX_DRX_P2 CI20 1 2 USB3_PTX_C_DRX_P2 5 6 USB3_PTX_C_DRX_P2
<16> USB3_PTX_DRX_P2
0.1U_0402_10V6K

TVWDF1004AD0_DFN9

Place close to JUSB1

B RI70 1
0_0201_5%
2 @EMI@ USB3.0 / USB2.0 Right Side B

R_0201-NPM

LI5 EMI@
USB20_N3 1 2 USB20_N3_R
<16> USB20_N3 1 2
+5V_CHGUSB_1
USB20_P3 4 3 USB20_P3_R +5V_CHGUSB_1
<16> USB20_P3 4 3 JUSB2
DLM0NSN900HY2D_4P 1 CI31 1 CI11 1 CI12 1 CI13 1
USB20_N3_R USB20_N3_R 2 VBUS @
SM070005U00 USB20_P3_R USB20_P3_R 3 D-
D+

47U_0805_6.3V6M

47U_0805_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K
RI71 1 2 @EMI@ 4
GND

3
0_0201_5% DI8 USB3_PRX_DTX_N3 5 2 2 2 2
R_0201-NPM ESD@ USB3_PRX_DTX_P3 6 SSRX- 10

3
7 SSRX+ GND 11
DI7 GND GND

AZC199-02SPR7G_SOT23-3
ESD@ USB3_PTX_C_DRX_N3 8 12
SSTX- GND

1
USB3_PRX_DTX_N3 1 9 USB3_PRX_DTX_N3 USB3_PTX_C_DRX_P3 9 13
<16> USB3_PRX_DTX_N3 SSTX+ GND

1
USB3_PRX_DTX_P3 2 8 USB3_PRX_DTX_P3 ACON_TCRA2-9R1394
<16> USB3_PRX_DTX_P3
ACON_TCRA2-9R1394_9P
USB3_PTX_DRX_N3 CI9 1 2 USB3_PTX_C_DRX_N3 4 7 USB3_PTX_C_DRX_N3 CONN@
<16> USB3_PTX_DRX_N3
0.1U_0402_10V6K DC23300ES00
USB3_PTX_DRX_P3 CI10 1 2 USB3_PTX_C_DRX_P3 5 6 USB3_PTX_C_DRX_P3
<16> USB3_PTX_DRX_P3
0.1U_0402_10V6K

3
A A

TVWDF1004AD0_DFN9

Place close to JUSB2

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 52 of 78
5 4 3 2 1
 5 4 3 2 1

Card Reader
+3VS& +3VS_CR Trace width:40mil
+3VS +3VS_CR
RI52
1 @ 2
Vinafix.com 0_0402_5%
CR9 1 CR10 1

0.1U_0402_10V7K

4.7U_0603_6.3V6K
D D
2 2

Close to UR1

Pin 5,6,8 Trace width : 40mil

+3VS_CR +VCC_3IN1

UR1
Close to UR1 chip side
USB20_N6 3 1 V18
Pin 7 +VCC_3IN1 Trace width : 40mil RI53
<16> USB20_N6 USB20_P6 4 DM AV18 7 SD_CLK_R 1 EMI@ 2 SD_CLK
<16> USB20_P6 DP CARD_3V3 22_0402_5% 1
SD_CD# 10 16 SDREG CR4
C 15 SD_CD# SDREG CR7 CR8 @EMI@ C
MS_INS# 2 2
11 SD_WP 6.8P_0402_50V8C
9 SP1 13 SD_D0 2
GPIO SP2

1U_0402_6.3V6K

1U_0402_6.3V6K
SD_D1 12 14
SD_DAT1 SP3 17 1 1
RI3 2 1 RREF 2 SP4 18 SD_CLK_R
6.19K_0402_1% 5 RREF SP5 19
6 3V3_IN1 SP6 20 SD_CMD
Pin 2 Trace width : 15mil 8 3V3_IN2 SP7 21
Close to UR1 3V3_IN3 SP8 22 SD_D3
24 SP9 23 SD_D2
48MHz_In SP10
25
GND
RTS5144-GR_QFN24_4X4
Pin1,16 Trace width : 15mil
RTS5176E-GR_QFN24_4X4-S Close to UR1
SA00009UJ00
Pin 11,12,13,18,20,22,23
Trace length mismatchinh within 100 mils.

+VCC_3IN1 JREAD1

4
CR5 CR6 SD_CMD 2 VDD
B
1 1 CMD B
SD_CLK 5
3 CLK
VSS1
4.7U_0603_6.3V6K

0.1U_0402_10V7K

6
2 2 VSS2
SD_D0 7
SD_D1 8 DAT0
SD_D2 9 DAT1
SD_D3 1 DAT2
CD/DAT3
12
GND 13
SD_WP 11 GND 14
Close to JREAD1 SD_CD# 10 W/P
CD
GND
GND
15

T-SOL_156-1001902607
CONN@
SP07001AC00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/01/06 Title
2017/01/06 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crad Reader RTS5144
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 53 of 78
5 4 3 2 1
 A B C D E

+5VALW to +5VS +VCCST Load Switch

+3VALW to +3VS Vinafix.com +1P05VALW
UZ15
1 UZ1 1 1
1 14 2 VIN1 +VCCST_OUT +VCCST
+5VALW VIN1 VOUT1 +5VS_OUT VIN2
2 13
VIN1 VOUT1 +5VALW 7 6 RZ66 1 @ 2 0_0402_5%
SIO_SLP_S3# 3 12 CZ4 1 2 VIN thermal VOUT
<15,31,33,35,36,55,62> SIO_SLP_S3# ON1 CT1 470P_0402_50V7K 3
4 11 CZ96 CZ97 VBIAS
+5VALW VBIAS GND 1 1

1
@ VCCST_EN 4 5 CZ28
SIO_SLP_S3# 5 10 CZ6 1 2 0.01U_0402_16V7K ON GND 0.1U_0402_10V6K
ON2 CT2

1U_0402_6.3V6K

0.1U_0402_25V6
2
6 9 2 TPS22961DNYR_WSON8 2
7 VIN2 VOUT2 8
+3VALW VIN2 VOUT2 +3VS_OUT SA00007XR00
15 4.4mohm/6A
GPAD
EM5209VF_DFN14_3X2 TR=12.5us@Vin=1.05V
SA00007PM00

Close UZ1 SIO_SLP_S4# RZ111 1 @ 2 VCCST_EN

+5VALW +3VALW +5VS_OUT +3VS_OUT <15,55,63> SIO_SLP_S4#
JPZ1 @ 0_0402_5%
+5VS_OUT 1 2 +5VS
CZ11 1 CZ12 1 CZ8 1 CZ9 1 SIO_SLP_S3# RZ112 1 2
@ @ PAD-OPEN1x3m 0_0402_5%
1U_0603_10V6K

1U_0603_10V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

2 2 2 2 JPZ2 @
2 1 2
DVT1. 2
+3VS_OUT +3VS Pop RZ112, un-pop RZ111.
PAD-OPEN1x3m

eDP Load Switch B+ Discharge

B+ B+

+3VALW +EDPVDD_OUT +EDPVDD

2
UZ8 RZ35
3 5 1 1 @ 2 R2 3
R1
IN OUT
1
2 0_0805_5% CZ41 1M_0402_5% 4.7K_0805_5%
GND

1
ENVDD 4 3 0.1U_0402_10V6K
EN OC 2
SY6288C20AAC_SOT23-5
SA000079400

6
QZ13B QZ13A

R3
VCC_CHG 1 2 5 2
<60> VCC_CHG
1M_0402_5% DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6

1
4

1
R4 R5
DV3
LCD_VCC_TEST_EN 2 1M_0402_5% 1M_0402_5%
<44> LCD_VCC_TEST_EN

2
1 ENVDD
1

ENVDD_PCH 3
<13> ENVDD_PCH
RZ40
BAT54CW_SOT323-3
BAT54CW-7-F_SOT323-3 100K_0402_5%
SCS00003800
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SYS DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 54 of 78
A B C D E
 5 4 3 2 1

+1.2V_DDR Enable

DVT1. DZ1
1 2
Vinafix.com
Add RZ119 bypass +VCCST_OUT to +VCCSTG_OUT
+VCCSTG_OUT +VCCST_OUT
RB751S40_SOD523-2
AZ5125-01HPR7G_SOD523-2
D D

+VCCSTG Load Switch RZ119

<15,54,63> SIO_SLP_S4#
SIO_SLP_S4# RZ102 1 2
100K_0402_5% 1
1.2V_VDDQ_EN

CZ102
1.2V_VDDQ_EN <62>

1 2
0_0402_5% 0.1U_0402_10V6K
2
+1P05VALW @
UZ9
1 +VCCSTG
2 VIN1
CZ88 VIN2 RZ48
1
@ +5VALW 7 6 1 @ 2
VIN thermal VOUT
1U_0402_6.3V6K

3 0_0402_5% 1
2 CZ86 VBIAS
+VCCIO Enable
1

@ VCCSTG_EN 4 5 CZ47
ON GND 0.1U_0402_10V6K
2
0.1U_0402_10V7K
2

TPS22961DNYR_WSON8
SA00007XR00
4.4mohm/6A DZ2
1 2
TR=12.5us@Vin=1.05V
RB751S40_SOD523-2
AZ5125-01HPR7G_SOD523-2

C SIO_SLP_S3# RZ118 1 @ 2 10K_0402_1% VCCSTG_EN SIO_SLP_S3# RZ108 1 2 VCCIO_EN C

<15,31,33,35,36,54,62> SIO_SLP_S3# VCCIO_EN <76>
1 150K_0402_5% 1
@
DVT1. CZ114 CZ108
0.1U_0402_10V6K 0.22U_0402_10V6K
Add RZ118 10K, CZ114 0.1uF for +VCCSTG timing tuning. 2 2

RTC GEN 9 +3VALW

1
RZ115
GEN9@
100K_0402_5%

2
RZ113 2 GEN9@ 1 0_0402_5%
<44> VCCDSW_ON PCH_PRIM_EN <64,65>
1 2
<61> POK
DZ3
GEN9@
B +VCCPLL_OC Load Switch RB751S40_SOD523-2
AZ5125-01HPR7G_SOD523-2
RZ116 2 GEN8@ 1 0_0402_5%
B

H-Processor Line - Quad Core GT2

Max : 130 mA
+3VALW @ JPZ3 +3VALW_PCH

1 2
+1.2V_VCCPLL_OC_OUT +1.2V_VCCPLL_OC 1 2

+1.2V_DDR RZ67 JUMP_43X79 JPZ3 for RTC GEN8

UZ16 1 @ 2
JPZ4 for RTC GEN9
1 8 0_0402_5% UZ25 GEN9@ @ JPZ4
2 VIN VOUT 7
VIN VOUT 1 7 +3VALW_PCH_SW 1 2
1 VIN VOUT 1 2
+5VALW SIO_SLP_S3# 3 6 CZ57 1 2 CZ49 CZ109 2 8
EN CT 1 VIN VOUT
@ GEN9@
4 5 2200P_0402_25V7K 0.1U_0402_10V6K PCH_PRIM_EN 3 6 JUMP_43X79
VBIAS GND 2 ON CT
1U_0402_6.3V6K
9
GND 2 +5VALW
1 1
FA7607OTR_DFN_8P 4 CZ111 CZ112
APE8937GN2_DFN8_2X2 VBIAS 5 GEN9@ GEN9@
GND 9 100P_0402_50V8J 0.1U_0402_10V6K
SA00009PI00 GND 2 2
1 CZ113 1 CZ110
@ GEN9@
FA7607OTR_DFN_8P

0.1U_0402_10V6K

0.1U_0402_10V6K
TPS22967DSGR_SON8_2X2
2 2
SA00009PI00
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC/S0iX/CS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 55 of 78
5 4 3 2 1
 5 4 3 2 1

MODEL NAME : DDK51/ DDK52/ DDK53 Bom Structure

PCB NO : LA-E993P X76 : S4G@X7673331L54 X76 : M4G@ X7673331L56 X76 : H4G@X7673331L55

CPU PCH GPU Samsung 4G Micron 4G Hynix 4G

UV6 S4G@ UV7 S4G@ UV8 S4G@ UV9 S4G@ UV6 M4G@ UV7 M4G@ UV8 M4G@ UV9 M4G@ UV6 H4G@ UV7 H4G@ UV8 H4G@ UV9 H4G@
UH1 QNCT@ UH2 QNDQ@ UV1 N17P_G0@

R1 ES R1 ES R3 Vinafix.com R3

K4G80325FB-HC28
R3

K4G80325FB-HC28
R3

K4G80325FB-HC28
R3

K4G80325FB-HC28
R3 R3 R3

MT51J256M32HF-70:A MT51J256M32HF-70:A MT51J256M32HF-70:A MT51J256M32HF-70:A

R3 R3

H5GC8H24MJR-R0C
R3

H5GC8H24MJR-R0C
R3

H5GC8H24MJR-R0C
R3

H5GC8H24MJR-R0C
D
CFL-H_CL8068403359717 QNCT U0 2.4G CNL-H PCH FHSSKU04 QNDQ A1 N17P-G0-A1 D
SA0000B7U0L SA0000B4I0L SA0000A051L SA000092D1L SA000092D1L SA000092D1L SA000092D1L SA00009TV1L SA00009TV1L SA00009TV1L SA00009TV1L SA00009U11L SA00009U11L SA00009U11L SA00009U11L
RV152 S4G@ RV153 S4G@ RV154 S4G@ RV146 M4G@ RV153 M4G@ RV154 M4G@ RV152 H4G@ RV147 H4G@ RV154 H4G@
UH1 QNVH@ UH2 QNYF@ UV1 N17P_G1@

R1 ES R1 QS R3
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
CFL-H_CL8068403359715 QNVH U0 2G CNL-H PCH FHHM370 QNYF B0 N17P-G1-A1
SA0000B041L SA0000BPF0L SA0000A061L SD028100380 SD028100380 SD028100380 SD028100380 SD028100380 SD028100380 SD028100380 SD028100380 SD028100380
PR818 S4G@ PR819 S4G@ PR818 M4G@ PR819 M4G@ PR818 H4G@ PR819 H4G@
UH1 QP87@ UH2 SR40B@

R1 QS i7-8750H R3 MP

CFL-H_CL8068403359524 QP87 U0 2.2G S IC FH82HM370 SR40B B0 BGA PCH-H PCB 30K_0402_1% 68.1K_0402_1% 30K_0402_1% 68.1K_0402_1% 30K_0402_1% 68.1K_0402_1%

SA0000BPZ0L SA0000BVP1L SD034300280 SD034681280 SD034300280 SD034681280 SD034300280 SD034681280

ZZZ PCB@
UH1 QP89@

X76 : S2G@X7673331L51 X76 : M2G@X7673331L53 X76 : H2G@X7673331L52

R1 QS i5-8300H

CFL-H_CL8068403373522 QP89 U0 2.3G PCB DDK51 LA-E993P LS-E991P/E992P 02

Samsung 2G Micron 2G Hynix 2G UV9 H2G@
UV6 S2G@ UV7 S2G@ UV8 S2G@ UV9 S2G@ UV6 M2G@ UV7 M2G@ UV8 M2G@ UV9 M2G@ UV6 H2G@ UV7 H2G@ UV8 H2G@
SA0000BPJ0L DAZ27Q00110
UH1 SR3YY@
R3
R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3
H5GC4H24AJR-R0C
R3 MP i7-8750H K4G41325FE-HC28 K4G41325FE-HC28 K4G41325FE-HC28 K4G41325FE-HC28 EDW4032BABG-70-F-R EDW4032BABG-70-F-R EDW4032BABG-70-F-R EDW4032BABG-70-F-R H5GC4H24AJR-R0C H5GC4H24AJR-R0C H5GC4H24AJR-R0C
SA00008HQ1L
CFL-H_CL8068403359524 SR3YY U0 2.2G SA00009TT1L SA00009TT1L SA00009TT1L SA00009TT1L SA00009E31L SA00009E31L SA00009E31L SA00009E31L SA00008HQ1L SA00008HQ1L SA00008HQ1L
RV146 S2G@ RV147 S2G@ RV148 S2G@ RV146 M2G@ RV152 M2G@ RV153 M2G@ RV154 M2G@ RV152 H2G@ RV147 H2G@ RV148 H2G@
C
SA0000BPZ2L C

UH1 SR3Z0@

R3 MP i5-8300H 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%

SD028100380 SD028100380 SD028100380 SD028100380 SD028100380 SD028100380 SD028100380 SD028100380 SD028100380 SD028100380
CFL-H_CL8068403373522 SR3Z0 U0 2.3G
PR818 S2G@ PR819 S2G@ PR818 M2G@ PR819 M2G@ PR818 H2G@ PR819 H2G@
SA0000BPJ2L

30K_0402_1% 68.1K_0402_1% 34.8K_0402_1% 52.3K_0402_1% 30K_0402_1% 68.1K_0402_1%

SD034300280 SD034681280 SD034348280 SD034523280 SD034300280 SD034681280

BOM config GPU type VRAM memory VRAM vender RVL PR818 PR819

X7673331L51 N17P-G0/G1 128Mx32 Samsung 1.35V & 1.5V 30K 68.1K

X7673331L52 N17P-G0/G1 128Mx32 Hynix 1.35V & 1.5V 30K 68.1K

X7673331L53 N17P-G0/G1 128Mx32 Micron 1.35V & 1.55V 34.8K 52.3K

X7673331L54 N17P-G0/G1 256Mx32 Samsung 1.35V & 1.5V 30K 68.1K

B B

X7673331L55 N17P-G0/G1 256Mx32 Hynix 1.35V & 1.5V 30K 68.1K

X7673331L56 N17P-G0/G1 256Mx32 Micron 1.35V & 1.5V 30K 68.1K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NOTE
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 56 of 78
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 2

Vinafix.com
D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/01/06 Deciphered Date 2018/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NOTE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 57 of 78
5 4 3 2 1
 5 4 3 2 1

+5VALW +1.0VS_VGA TDC: 0.9835A +1VS_GFX

VIN CHARGER B+ +3VALW TDC:5.823A RT8061
DC IN BQ24780 Page 66
Page 59 Page 60 +5VALW TDC:10.34A
TPS51285B (Module)
Page 61
+3VALW
+2.5V_MEM TDC:0.428A +2.5V_MEM
Vinafix.com RT9059GSP_SO8 (LDO)
Battery Page 63
D
56Whr 4S1P for 15' D

+1.2V_DDR
+1.2V TDC:7.95A
+0.6VS TDC:1.05A +0.6VS
RT8207P(Module) Page 62

+1P05VALW TDC:4.2805A +1P05VALW

SY8286 (Module)
Page 64

VCCIO_0.95V TDC: 3.85A +VCCIO

SY8286 (Module)
Page 76

C
+1.35VS_VGA TDC: 11A +1.35VS_VGA
C

RT8812A (Module)
Page 69

+1.8VSP TDC: 1.289A +1.8V_PRIM

SY8286 (Module)
Page 65

+VCC_CORE TDC: 49A +VCC_CORE

NCP81215 (Module)
Page 72/73

+VCCGT TDC: 38.5A +VCCGT

NCP81215 (Module)
Page 74

B B

+VCCSA TDC: 7.77A +VCCSA

NCP81215 (Module)
Page 74

N17P-GX GDDR5_50W +GPU_CORE

GPU_CORE TDC: 50A
RT8816A Page 67

N17P-GX GDDR5_50W +GPU_CORE_VDDS

GPU_CORE_VDDS TDC: 12.6A
RT8816A Page 68

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Block Diagram
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 58 of 78
5 4 3 2 1
 A B C D

@ PJPDC1 PL1 @EMI@

3A_Z120_40M_0603_2P
VIN
11 1 2 +3VALW
11
10
10
9
ADPIN PL2 EMI@ battery unplug prochot
3A_Z120_40M_0603_2P
9 8 1 2
8

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J
7 PL6 EMI@ H_PROCHOT#
7 <8,44,60,71> H_PROCHOT#

2.2K_0402_5%
100P_0402_50V8J
6 3A_Z120_40M_0603_2P
6

1
EMI@ PC1

EMI@ PC2

@EMI@ PC17

@EMI@ PC18

@EMI@ PC19

@EMI@ PC20
5 1 2
5

2
EMI@ PC3

EMI@ PC4
4 PL7 EMI@
4 3 3A_Z120_40M_0603_2P

2
Vinafix.com
3

PR2
2 1 2
2 1 PSID PL8 EMI@ PR1 PC12
1 3A_Z120_40M_0603_2P 33_0402_5% 0.1U_0402_25V6

1
D
1 2 PSID-0 1 3 PSID-3 1 2 PS_ID <44>

S
1 1
ACES_51202-00901-001 PL9 EMI@ PQ1 PBAT_PRES# 1 2PQ5_G 2 PQ5
3A_Z120_40M_0603_2P FDV301N_G 1N SOT23-3 G L2N7002WT1G 1N SC-70-3

100K_0402_1%

100K_0402_1%
1 2 S

G
2

3
2

2
PR3

PR21
PR4
EMI@ PL3
BLM15HG601SN1D_2P 2 1 +5VALW
2 1

1
1
C
PSID-1 2 PQ2 10K_0402_1%
B
Adapter connector: MMST3904-7-F_SOT323-3

15K_0402_1%
E
1.PSID

3
2
2.GND

PR5
PL11 EMI@ @ PD1
3A_Z120_40M_0603_2P L30ESD24VC3-2_SOT23-3 3.GND
1 2
PL12 EMI@ 4.GND

1
3A_Z120_40M_0603_2P 5.GND
1 2 BATT++ 6.ADPIN
PL13 EMI@
7.ADPIN
1
BATT+ 3A_Z120_40M_0603_2P
1 2 8.ADPIN
PL14 EMI@ 9.ADPIN
3A_Z120_40M_0603_2P
10.X
1000P_0402_50V7K

1 2 BATT++
11.X
PC7 EMI@

100P_0402_50V8J
1
0.022U_0402_25V7K

0.01UF_0402_25V7K
1

EMI@ PC8
PC6
EMI@ PC5

2
2

1
EMI@

2
PD3 PD4 2

TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
ESD@ ESD@
2

@ PBATT1 PBAT_PRES#
1
1 PBAT_PRES# <44,60>
2
2 3
3 4 CLK_SMB 1 2 PR13 <44,60> I_ADP_R
4 5 DAT_SMB 1 PR8 2 100_0402_1% 10K_0402_1%
5

1
6 BATT_PRS1 PR10 2 100_0402_1% 1 2
6 7 SYS_PRES PR12 100_0402_1% +3VALW PR27
7 8 10K_0402_1%
8
9
PBAT_CHG_SMBCLK <44,60>

2
GND 10
GND
PBAT_CHG_SMBDAT <44,60> <60> CMPIN
ACES_50458-01001-P01

adapter unplug prochot Erp lot 6 circuit adapter OC prochot

1
@
Battery connector: PR34
0_0402_5% PR26
1.BATT++ 1 2 36K_0402_1%
<23> GPU_LEVEL
2.BATT++

2H_PROCHOT#
+3VALW
3.BATT++ @
PR25

2
3 3

4.CLK_SMB H_PROCHOT# 1
5.DAT_SMB
2
VIN
6.BATT_PRS REGN_CHG
0_0402_5%
1

7.SYS_PRES PR32 @
8.GND

3.3K_1206_5%
10K_0402_5% PR24

1
9.GND 0_0402_5%
6

PR15
10.GND REGN=6V
2

1
DMN65D8LDW-7_SOT363-6

PC15

1
PQ7A

0.1U_0402_25V6 PR16 PR28

1 2 2 <15,44,60> ACAV_IN 1M_0402_1% 10K_0402_1%

2
PQ6A_D PR30
1

1
160K_0402_1% D
2

6
1 2 2

DMN65D8LDW-7_SOT363-6
PQ8
ACIN=ACOK <60> CMPOUT
3

PQ6A_G
DMN65D8LDW-7_SOT363-6

PR33 G L2N7002WT1G 1N SC-70-3

PQ6A
PR31 100K_0402_1% PR20 S

3
3
PQ7B

1M_0402_1% 200K_0402_1% 2

1
VIN 1 2 5
1

1
PQ6B PC14
2

1
1

PQ6B_G
5 DMN65D8LDW-7_SOT363-6 PR29 0.022U_0402_25V7K
L2N7002WT1G 1N SC-70-3
4

PR23 1M_0402_1% 12.4K_0402_1%

2
1

1M_0402_1% PC16 PR22

4

2
1

0.1U_0402_25V6 D 0.1U_0402_25V6
1

PC13
PQ9

1 2 2
2

G
S
3
2

PR35
100K_0402_1%
4 4
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DCIN / BATT CONN / OTP
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 59 of 78
A B C D
 A B C D

PQ700
CC =

1
D L2N7002WT1G 1N SC-70-3
VIN PQ701 P1 2PQ700_G
EMB04N03H_EDFN5X6-8-5 G
1 S PR700 PR701 CV =

3
2 3M_0402_5% 1M_0402_1%
5 3 2 1 2 1
P2

1000P_0402_50V7K

PQ701_G 4
1
PC700

2 1
PR702
4.7_0402_5%
2
Vinafix.com ADP_I = 40*Iadapter*Rsense
1
PQ703 1

PQ702 EMB04N03H_EDFN5X6-8-5 PR703

B+ PQ704 AON7506_DFN33-8-5

EMB04N03H_EDFN5X6-8-5 1 0.005_1206_1% 1
1 2 2
2 3 5 1 4 5 3 PQ703_S

0.1U_0402_25V6
5 3
2 3

1
1000P_0402_50V7K

PC702
<54> VCC_CHG

PQ704_G 4
4
1
PC701

2
PL700 CHG_B+

CSSP_1
PD700
PQ702_G

B2B_G
HCB3225KF-151T50_2P

2CSSN_1
2

3 1 2 PC703
PR704 BATT++ 1 2
1 2 1

1000P_0402_50V7K
1U_0402_25V6K

10U_0805_25V6K~D

10U_0805_25V6K~D
2200P_0402_50V7K
2

0_0402_5%

0_0402_5%
4.7_0402_5% 0.01U_0603_25V7K

0.1U_0402_25V6
1

1
BST_CHG

PR705

PR706

EMI@ PC708

EMI@ PC709

EMI@ PC704

PC706

PC707
2

EMI@ PC705
VIN PR707 PR708

0.047U_0402_25V7K
4.02K_0402_1% 10_0402_1%

2
4.12K_0603_1%

4.12K_0603_1%
1 BAT54CW_SOT323-3

1
PC710 PC711
PC712

1
0.1U_0603_25V7K 0.1U_0402_25V6

10_1206_1%
PR710
PR709

BATDRV_CHG 2

2
1

1
PC713
1 2 1 2 1 2

2.2_0603_5%
PR711

PR712

2
0.01UF_0402_25V7K +3VALW
2

BATSRC_CHG
PC714 @ PR713
2.2U_0603_16V6K 1 2

VCC_CHG_1 2

REGN_CHG 1
7.5K_0402_1%

5
20K_0402_1%
BTST_CHG
1 2

PQ707_D
UG_CHG

LG_CHG
PQ705

LX_CHG

2
PC715 AON6380_DFN5X6-8-5

PR714
1U_0603_25V6K
UG_CHG 4
PU700 @ PQ706

28

27

26

25

24

23

22

1
D L2N7002WT1G 1N SC-70-3
2TB_STAT#_CHG

PHASE

HIDRV

LODRV
BTST
VCC

REGN

GND

ILIM_CHG
G PR716

3
2
1
29 S PL701 0.01_1206_1%

CSSP_2

CSSN_2
2 2

3
PWPD 4.7UH_MMD-10DZ-4R7M-X2_9.5A_20%
PR715 LX_CHG 1 2 1 4 BATT+
1 21 1 2
ACN ILIM 2 3

1
5.76K_0402_1%

5
2 20 SRP_CHG PR717

CSON_1
CSOP_1
ACP SRP 4.7_1206_5%

AON7380_DFN3X3-8-5

22U_0805_25V6M

22U_0805_25V6M

22U_0805_25V6M
@EMI@
CMSRC_CHG 3 19 SRN_CHG

2
CMSRC SRN

1
SNUB_CHG

PC716

PC717

PC718
LG_CHG

PQ707
4

1
ACDRV_CHG 4 18 BATDRV_CHG PC719

2
ACDRV BQ24780SRUYR_QFN28_4X4 BATDRV 680P_0402_50V7K
@EMI@

2
5 17 BATSRC_CHG
<15,44,59> ACAV_IN

3
2
1
ACOK BATSRC
PR718
ACDET_CHG TB_STAT#_CHG
VIN
120K_0402_5%

1 2 6 16
REGN_CHG ACDET TB_STAT#
324K_0402_1%

100K_0402_1%
1

PR721 PC720 PC721 PC722

1

IADP_CHG 7 BATPRES#_CHG
PR719

1 2 15 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6

IADP BATPRES#

1
<44,59> I_ADP_R
PR720

1 2 1 2 1 2

PROCHOT#
0_0402_5% PR722

CMPOUT
100P_0402_50V8J
10K_0402_1%

IDCHG

CMPIN
2

PMON

2
SDA
2

SCL
2

PC723
AC Det PR723 PR724

2
0_0402_5% 10_0402_1%
Max:18.16V 1 2
1

10

11

12

13

14
Typ :17.98V

1
Min :17.8V +3VALW PR726
@

PMON_CHG

PROCHOT_CHG
10_0402_1%

SDA_CHG

SCL_CHG
1 2I_BATT_CHG 1 2
PQ708 BATT+
L2N7002WT1G 1N SC-70-3 PC725 3.7x4=14.8V
1

PR732

PR733
100P_0402_50V8J
Max Charge Current 4.096A
1

0_0402_5% PR730

0_0402_5% PR731
2
<44> AC_DIS
1

2
PR725
49.9K_0402_1%

G <44,59> PBAT_PRES# Switching Frequency 0.8 MHz

2
0_0402_5% PR729
3
S PC724 3
3
1

0_0402_5%

0_0402_5%

0_0402_5%
0.01UF_0402_25V7K
2

2
PR727

PR728

PR734
2

100K_0402_1%

1
1

1
@
2

1
0_0402_5%
1

@
PBAT_CHG_SMBDAT

PBAT_CHG_SMBCLK

CMPOUT
CMPIN
I_BATT_R

P_SYS

H_PROCHOT#

TYP MAX
Rdc : 15mohm 16.5mohm
TYP MAX
<59>
<71>

<59>

H/S Rds(on) : 8.2mohm 10.5mohm

<44>

L/S Rds(on) : 8.2mohm 10.5mohm

<8,44,59,71>

<44,59>

<44,59>

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 60 of 78
A B C D
 A B C D E

Input current
3.3V*7.21A=23.8W +3VLP
PC300
23.8/0.85/12=2.33A
Vinafix.com 4.7U_0603_6.3V6K
1 2

5V*8.61A=43.05W
1 1
51.7/0.85/12=4.22A Output capacitor ESR need follow
below equation to make sure feed back
loop stability
2.33A+4.22A=6.55A ESR=20mV*L*fsw/2V
PR300 PR301
6.49K_0402_1% 15.4K_0402_1%
1 2 1 2

PL311 EMI@
VFB=2V VFB=2V
3A_Z120_40M_0603_2P
1 2 PR302 PR303
+3VALWP 10K_0402_1% 10K_0402_1%
PL312 EMI@ 1 2 1 2
3A_Z120_40M_0603_2P POK need pull high, it
1 2
will pull high on VS

2
PL313 EMI@ transfer circuit PR314

1
3A_Z120_40M_0603_2P 100K_0402_1% 3/5V_B+
1 2 PR304 PR305
6.19K_0402_1% 16.5K_0402_1%

1
PL314 EMI@
3A_Z120_40M_0603_2P
B+ <55> POK

10U_0805_25V6K~D

10U_0805_25V6K~D
1 2 3/5V_B+

FB_3V

FB_5V

1
PC301

PC302
CS2

CS1
1000P_0402_50V7K

2200P_0402_50V7K
1U_0402_25V6K

10U_0805_25V6K~D

10U_0805_25V6K~D
0.1U_0402_25V6

PQ301

2
1

5
AON7380_DFN3X3-8-5
EMI@ PC305

EMI@ PC306

EMI@ PC303

EMI@ PC304

PC307

PC308

5
2

PU300 21 PQ303

CS2

VFB2

VREG3

VFB1

CS1
2 TP 2
AON7380_DFN3X3-8-5
4
3V_EN 6 20 5V_EN
EN2 EN1 PR306 4
200_0402_1%
7 19 VCLK 1 2
1
2
3
PGOOD VCLK

3
2
1
PL302 LX_3V 8 18 LX_5V
S COIL 1.5UH +-20% 9A 7X7X3 PC309 PR307 SW2 TPS51285BRUKR_QFN20_3X3 SW1 PR308 PC310 PL303
1 2 LX_3V 0.1U_0402_25V6 0_0603_5% 0_0603_5% 0.1U_0402_25V6 S COIL 1.5UH +-20% 9A 7X7X3
+3VALWP 1 2 BST_3V 1 2VBST2 9 17 VBST1 1 2 BST_5V 1 2 LX_5V 1 2
VBST2 VBST1 +5VALWP
1
4.7_1206_5%

4.7_1206_5%
UG_3V 10 16 UG_5V 1
DRVH2 DRVH1

1
@EMI@ PR309

@EMI@ PR310
VREG5
DRVL2

DRVL1
+ PC312
ESR = 18mohm

VO1

5
VIN
PQ304 220U_6.3V_M
5

1 AON6796_DFN5X6-8-5
2

11

12

13

14

15

2
+ PC311 PQ302 ESR = 18mohm
1 SNUB_3V

220U_6.3V_M AON6796_DFN5X6-8-5

SNUB_5V
LG_5V 4
2 4 LG_3V
680P_0402_50V7K

680P_0402_50V7K
+5VALWP
@EMI@ PC313

3/5V_B+
VL

3
2
1

@EMI@ PC314
1
2
3

3.3VALWP
2

2
1
TDC=7.21A
PC315
3 Peak Current 10.3A 4.7U_0603_6.3V6K 3

2
OCP current 12.36A
FSW=475kHz 5VALWP
TYP MAX TDC=8.61A
H/S Rds(on) : 8.1mohm 9.8mohm Peak Current 12.3A
OVP=Vout*(112.5%~117.5%) OCP current 14.76A
L/S Rds(on) : 4.6mohm 5.6mohm
FSW=400kHz
OCP=Vtrip/Rdson+Iripple/2 TYP MAX
Vtrip=Ics(min)*Rcs/8+1mV H/S Rds(on) : 8.1mohm 9.8mohm
PR311
@ 0_0402_5% Vcs=Ics*Rcs should be in the range of 0.2~2V L/S Rds(on) : 4.6mohm 5.6mohm
3V_EN 1 2
Vout=VFB*(1+Rtop/Rbot)
@ 0_0402_5%
PR312 VFB=2V
5V_EN
0.1U_0402_6.3V7K

1 2
1

PC317

PJP31 PJP33
+5VALWP 1 2 +5VALW +3VALWP 1 2 +3VALW
2

@ 1 2 1 2
JUMP_43X118 @ JUMP_43X118 @

PR313
3V_5V_EN

2.2K_0402_5% PJP32 PJP34

1 2 1 2 1 2
<44> ALWON 1 2 1 2
JUMP_43X118 @ JUMP_43X118 @
4 PQ305 4
PR315 L2N7002WT1G_SC70-3
0_0402_5%
S

1 2 3 1
<23,44> CMP_VOUT0
0.1U_0402_25V6
G
2

PC316

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/2/11 Deciphered Date 2014/2/11 Title
2

<15,44> ALL_SYS_PWRGD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 61 of 78
A B C D E
 5 4 3 2 1

Input Current: 1A
1.2V*8.54A/0.85/12V=1

Vinafix.com
D D

Pin19 need pull separate from +1.2VP.

If you have +1.2V and +0.6V sequence question, 0.6VSP
you can change from +1.2VP to +1.2VS. TDC 1.05A
PJP200@
B+ 1 2 1.2V_B+ PR200 Peak Current 1.5A
1000P_0402_50V7K 1 2

2200P_0402_50V7K
1U_0402_25V6K

0.1U_0402_25V6
2.2_0603_5%
BST_1.2V BOOT_1.2V

10U_0805_25V6K~D

10U_0805_25V6K~D
JUMP_43X39 1 2
+1.2VP
1

1
EMI@ PC204

EMI@ PC205

EMI@ PC200

EMI@ PC201

PC202

PC203

1
+0.6VSP
2

2
PC206 UG_1.2V
0.1U_0603_25V7K

2
LX_1.2V

10U_0805_6.3V6K

10U_0805_6.3V6K
PQ201

1
PC207

PC208
5
AON7408L_DFN8-5

16

17

18

19

20
C PU200 C

2
PR201=20.5K for OCP=15A,

PHASE

UGATE

BOOT

VTT
VLDOIN
21
Ron=15.8mohm, delta_I=3.94A PAD
TYP MAX 4 LG_1.2V 15 1
LGATE VTTGND
Rdc : 6.7mohm 7.4mohm
14 2
PL200 PR201 PGND VTTSNS

1
2
3
1UH_11A_20%_7X7X3_M 20.5K_0402_1%
1 2 1 2 CS_1.2V 13 3
+1.2VP PC209 CS RT8207PGQW_WQFN20_3X3 GND
1
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1U_0603_10V6K

5
1 2VDDP_1.2V 12 4 VTTREF_1.2V
VDDP VTTREF
1

1
PC217

PC218

PC219

PC220

@EMI@ PR202 PQ202

4.7_1206_5% AON7506_DFN33-8-5 30MA_30V_0.5UA_0.4V_SOD323-2 PD200
2 1 11 5
+1.2VP
2

VDD VDDQ

1
PGOOD
PR203
SNUB_1.2V 4 5.1_0603_5% PC212

TON
1 2 VDD_1.2V 0.033U_0402_16V7K

FB
S5

S3
+5VALW

2
1

2.2_0603_5%

2
@EMI@ PC213

10

6
1
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

PR204
680P_0402_50V7K
2

1
2
3

PC214
1

1
PC221

PC222

PC223

PC224

1U_0603_10V6K

EN_0.6VSP
PR205

EN_1.2V
1
12K_0402_1%

TON_1.2V
+1.2VP
2

FB_1.2V 1 2
1 2 1.2V_PGOOD
B +3VALW PR207 B

20K_0402_1%
@ PR206 100K_0402_1% 453K_0402_1%

PR208
1.2V_B+ 1 2

@
PR209
1.2VP
1 2
TDC=8.603A <55> 1.2V_VDDQ_EN

2
Ipeak=12.29A 0_0402_5%

1
OCP=14.748A @ PJP201 @ PC215
1 2 0.1U_0402_10V7K
Switching Frequency: 285kHz 1 2

2
JUMP_43X118
@ PJP202
+1.2VP 1 2 +1.2V_DDR @ PR210
1 2 0_0402_5%
JUMP_43X118 1 2
<15,31,33,35,36,54,55> SIO_SLP_S3#
OVP: 110%~120%
PJP203@ PR211
VFB=0.75V, Vout=1.2V 1 2 1 2
TYP MAX +0.6VSP 1 2 +0.6VS <8> SM_PG_CTRL
H/S Rds(on) : 23.3mohm 30mohm JUMP_43X39 0_0402_5%

1
0.1U_0402_10V7K
L/S Rds(on) : 11mohm 13.5mohm

PC216

2
Mode Level +0.6VSP VTTREF_1.2V
RLIMT=ILIMIT*Ron/10uA @
S5 L off off
A
S3 L off on where RILMT=PR201=20.5K,Ron=15.8m A

S0 H on on =>ILIMIT=15A

Note: S3 - sleep ; S5 - power off

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.2VP/0.6VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 62 of 78
5 4 3 2 1
 A B C D

Vinafix.com
1 1

Input Current:0.42A

2.5*0.428=1.07W
1.07/0.85/5=0.42A

+3VALW
@
PR25V00
1 2 EN_2.5V
<15,54,55> SIO_SLP_S4#

1
0.1U_0402_16V7K
1

1M_0402_1%
2 0_0402_5% @ PR25V02 2

1
PR25V01

PC25V00
100K_0402_1%

2
@

9
PU25V00
@ PJP25V1 2.5V_PGOOD 1 8

GND
2 PGOOD GND 7
+3VALW 1 2 VIN_2.5V 3 EN ADJ 6
1 2 4 VIN VOUT 5 +2.5V_MEMP
VDD NC
Rup

1
JUMP_43X79
1

1
22U_0603_6.3V6M

22U_0603_6.3V6M
RT9059GSP_SO8

22P_0402_50V8J
PC25V01

PC25V02
PR25V03

1
22U_0603_6.3V6M

22U_0603_6.3V6M
PC25V03
21.5K_0402_1%
2

PC25V04

PC25V05
2
2

2
FB_2.5V

+5VALW

1
PR25V04
1
Vout=0.8*(1+Rup/Rdown) 10K_0402_1%
Rdown
1U_0402_6.3V6K

2
PC25V06

@ PJP25V2

3 1 2 3

+2.5V_MEMP 1 2 +2.5V_MEM
JUMP_43X79

+2.5V_MEM
TDC 0.428A
Peak Current 0.612A
OCP Current 3.5A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+2.5V_MEM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 63 of 78
A B C D
 Vinafix.com

5 4 3 2 1

+1VALW
TDC 5.18A
D Peak Current 7.4A D

Input Current: 0.49A OCP current 9A

1V*5.18A/0.85/12V=0.49 FSW=500KHz

IL=1.9A@19.5V
ripple=7.3mV@19.5V
@ PJP12
JUMP_43X118
@EMI@ PR104 @EMI@ PC111 1 2
1V_PG 4.7_1206_5% 680P_0402_50V7K +1VALWP 1 2 +1P05VALW
1V_PG <44>
1 2 SNUB_1VALWP 1 2

PU100
+1V_B+
B+ 1
1 2
2 2
IN PG
9 PR101 PC106
1000P_0402_50V7K

1U_0402_25V6K

10U_0805_25V6K~D

10U_0805_25V6K~D
0.1U_0402_25V6

0_0603_5% 0.1U_0402_25V7K
2200P_0402_50V7K

@ PJP11 3 1 VBST_1V 1 2 BST_1V 1 2 PL100

IN BS
1

1
EMI@ PC100

EMI@ PC105

EMI@ PC102

EMI@ PC101

PC104

@ PC103

JUMP_43X79 1UH_PCMB063T-1R0MS_12A_20%
C
4
IN LX
6 LX_1V 1 2
+1VALWP C
2

15K_0402_1%

330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
5 19
IN LX

1
PR106

PC114

PC113

PC112

PC110

PC109
7 20
GND LX
8 14 FB_1V
R1

2
GND FB

2
PR103 18 17 LDO_1V 3V
100K_0402_1% GND VCC
1 2 EN_1V 11 10
<55,65> PCH_PRIM_EN EN NC

1
FB=0.6V

1
ILMT_1V 13 12 PC115
ILMT NC
1

PC107 2.2U_0402_6.3V6M

2
PR102 15 16 PR107
1M_0402_1%
0.1U_0402_25V6 +3VALW BYP NC Vout=0.6V* (1+R1/R2) R2 20K_0402_1%
2

+3VALW
21 =0.6*(1+(14/20))

2
PAD
2

SY8286RAC_QFN20_3X3
Vout=1.02V
1

PC108
1U_0402_6.3V6K
1

@ PR108
0_0402_5%
B B
2
1

@ PR109
0_0402_5%
2

The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
PWR.Plane.Regulator(35.25), Support component(35.26) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-E993P 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2018 Sheet 64 of 78
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D
Input Current:0.318A
1.8*1.806/0.85/12V=0.318A
+1.8VSP
TDC 1.75A
Peak Current 2.5A
OCP current 3A
FSW=500KHz

PRIM_PWRGD_R <44>

@ PJP18V1 PU18V00
B+ 1 2 1.8V_B+ 2 9 PR18V01 PC18V01
1 2 IN PG

10U_0805_25V6K~D

10U_0805_25V6K~D
0_0603_5% 0.1U_0603_25V7K
JUMP_43X39 3 1 BS_1.8V 1 2 BST_1.8V 1 2
IN BS PL18V00

2
PC18V00

PC18V02
4 6 LX_1.8V 1 2
IN LX
+1.8VSP

330P_0402_50V7K
1

20.5K_0402_1%
5 19 1UH_PCMB042T-1R0MS_4.5A_20%
IN LX

PC18V03

PR18V02
C C

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
7 20
GND LX

1
PC18V04

PC18V05

PC18V06

PC18V07
2
8 14 FB_1.8V

2
GND FB

2
PR18V00 18 17 VCC_1.8V
47K_0402_1% GND VCC

1
1 2 1.8V_EN 11 10

2.2U_0603_16V6K
<55,64> PCH_PRIM_EN EN NC @EMI@ PR18V03
Rup

PC18V08
13 12
0.1U_0402_16V7K

4.7_1206_5%
ILMT NC
PC18V09

Rdown
1

10K_0402_1%
15 16

2
BYP NC SUNB_1.8V

PR18V05
PR18V04
1M_0402_1% 21
2

PAD

1
SY8286RAC_QFN20_3X3 @EMI@ PC18V10
2

2
680P_0402_50V7K
+3VALW

2
2

@ PR18V06
0_0402_5%
Vout=0.6V* (1+Rup/Rdown)
1

ILMT_1.8V @ PJP18V2
2

+1.8VSP 1 2 +1.8V_PRIM
PR18V07 1 2
0_0402_5% +3VALW JUMP_43X79
B B
1U_0402_6.3V6K
1

PC18V11
1
2

The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 65 of 78
5 4 3 2 1
 5 4 3 2 1

Input Current:0.18A
1*0.77/0.85/5=0.18A
Vinafix.com +1.0VS_VGAP
D TDC 0.77A D

Peak Current 1.1A

OCP current 4A
FSW=1MHz

PU10V00
@ PJP10V1 11
+5VALW 1 2 1.0VS_VGAP_VIN 10 TP 1
1 2 PVIN NC PL10V00

10U_0603_6.3V6M
PC10V21 EMI@

PC10V22 EMI@
JUMP_43X39 9 2 LX_1.0VS_VGAP 1 2
PVIN LX
+1.0VS_VGAP

2
1000P_0402_50V7K

PC10V00
1U_0402_6.3V6K 8 3

1U_0402_6.3V6K
1 SVIN LX 1UH_1239AS-H-1R0M-P2_3A_20%

1
1

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PC10V01
7 4 @EMI@ PR10V00
NC PGOOD

1
PC10V02

PC10V03

PC10V04
4.7_1206_5%
2

2
6 5 1VS_GFX_PG <23>

1
FB EN

2
SNB_1.0VS_VGAP

2
Rup RT8061AZQW_WDFN10_3X3

1
C PR10V01 C
PR10V2 10K_0402_5% @EMI@ PC10V05
2 1 FB_1.0VS_VGAP 680P_0402_50V7K
+1.0VS_VGAP

2
1
6.81K_0402_1%

1
10K_0402_1%
1 2 +3VS

Rdown
PR10V03
PC10V06
22P_0402_50V8J
Vout=0.6V* (1+Rup/Rdown)

2
PR10V04 PJP10V3 @
<31,68> NVVDDS_EN EN_1.0VS_VGAP
1 2
+1.0VS_VGAP 1 2 +1VS_GFX
1 2
0.1U_0402_16V7K

0_0402_5%
1
1M_0402_1%

PC10V07

JUMP_43X79
1
PR10V06

@ PR10V05
1 2
+1.8V_GFX_AON
2

0_0402_5% @
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.0VS_VGA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 66 of 78
5 4 3 2 1
 GPU_B+

B+
EMI@ PL6000
1 2

FBMA-L11-453215800LMA90T_2P

1000P_0402_50V7K
1U_0402_25V6K
EMI@ PC6007

EMI@ PC6010

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
1

100U_25V_M

2
+

PC6002

PC6003

PC6004

PC6005
Vinafix.com

1
2
+5VS

4.7U_0603_6.3V
1
PC6006
2
NVVDD_LG1 NVVDD_LG2

2200P_0402_50V7K
0.1U_0402_25V6

10U_0805_25V6K~D

10U_0805_25V6K~D
NVVDD_HG1

EMI@ PC6011

EMI@ PC6012
1

1
NVVDD_SW1 NVVDD_SW2

PC6008

PC6013
PC6014 PC6009

1
0.22U_0603_25V7K 0.22U_0603_25V7K NVVDD_SW1

2
1

2
PQ6000 PQ6001

AON6962_DFN5X6D-8-7

AON6962_DFN5X6D-8-7
G1

D1

G1

D1
2 2

2 2
PU6000 +GPU_CORE

20

19

18

17

16
RT8816AGQW_WQFN20_3X3 +3VS
PR6001 PR6000 7 7

PHASE1

LGATE1

LGATE2

PHASE2
PVCC
D2/S1 D2/S1
2.2_0603_1% 2.2_0603_1%

2
NVVDD_BST1
1 15 NVVDD_BST2

G2

G2
S2

S2

S2

S2

S2

S2
1

1
BOOT1 BOOT2 PR6002
10K_0402_5%

3
NVVDD_HG1 2 14 NVVDD_HG2 PL6001
UGATE1 UGATE2 0.22UH_MMD-06DZER22MEM2L__32A_20%
PD=C*V*V*Freq

1
1 2
NVVDD_EN 3 13 GPU_CORE_PG <31>
<31> NVVDD_EN EN PGOOD NVVDD_LG1 PC6015 EMI@
PR6004 EMI@ 680P_0402_50V7K

330U_D3_2VM_R6M
1
1 2 4 12 NVVDD_COMP 2 1 1 2 1 2 GPU_B+
PSI OCSET/SS +

PC6016
PR6539
EN pin don't floating 1M_0402_1% PR6003 2.2_1206_5%
1 2 5 11 180K_0402_1%
<23> NVVDD_PWM_VID VID VSNS 2

REFADJ

REFIN

RGND
VREF
PR6006 10K_0402_1% PR6005 0_0402_5% 21

TON
1 2 GND
+1.8V_GFX_AON
PR6007
Rocset=Ivally*Ron*12/Iocset
where Rocset=180K,Ron=2.5mohm,Iocset=10uA,

2200P_0402_50V7K
0_0402_5%

0.1U_0402_25V6

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
6

10
NVVDD1_PSI =>Ivally=60A,delta_I=12.8A NVVDD_HG2

EMI@ PC6018

EMI@ PC6023
1 2
<23,68> GPU_PSI

2
PC6022

PC6019

PC6020

PC6024

PC6025
=>OCP=132.8A

2
@ PR6008 NVVDD_VIDBUF

1
1

2
0_0402_5% PR6009 PQ6002 PQ6003
1 2 0_0402_5%

G1

D1

G1

D1
1
+GPU_CORE

AON6962_DFN5X6D-8-7
@ PR6010

AON6962_DFN5X6D-8-7
1
71.5K_0402_1% NVVDD_SW2 7 7
D2/S1 D2/S1
R1 R4
1

499K_0402_1%
6.19K_0402_1%

1
PR6011

PR6012

16.5K_0402_1%

PC6027
R3

G2

G2
S2

S2

S2

S2

S2

S2
1

NVVDD_VREF

PR6014
2 1
4700P_0402_50V7K
@ PC6026
4.32K_0402_1%

3
PR6013

1000P_0402_25V PL6002
2

PD=C*V*V*Freq 0.22UH_MMD-06DZER22MEM2L__32A_20%
.1U_0402_16V7K

2
1 2
2

2
PC6028

NVVDD_LG2 PC6029 EMI@

PR6016

2
EMI@ 680P_0402_50V7K
R5

470U_D2_2VM_R4.5M~D
1
1
2

PR6015 PR6018 1 2 1 2
+

PC6031
0_0402_5% 0_0402_5%
PR6017
309_0402_1% 2.2_1206_5%
PR6019
1

1
2
1

2 1 +GPU_CORE
R2
2 1 100_0201_5% VCCSENSE_VGA <24>
+NVVDD1
C PR6020
20.5K_0402_1% Avoid high dV/dt VSSSENSE_VGA <24>
TDC 50A
Peak Current 106A
1

PC6030
PR6021
4700P_0402_50V7K
GPU_B+ 2 1
OCP=127.2A
Fsw=305KHz
2

100_0201_5% DCR:0.98mohm +-5%

TYP MAX
2Phase DEM 2Phase CCM H/S Rds(on):6.8mohm ,8.6mohm
Place close to GPU
PSI 1.22V 1.72V L/S Rds(on):2mohm ,2.5mohm
PR6006 10Kohm 10Kohm
PR6228+PR6230 21Kohm 215Kohm
N17P_G1 VDD VDDS
TDC 50 12.6
Operation Phase Number PSI Voltage Setting Peak 106 18
1phase with DEM 0V to 0.4V
1phase with CCM 0.7V to 0.88V
2phase with DEM 1.08V to 1.35V
2phase with CCM 1.6V to 5.5V

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+NVVDD1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 67 of 78
 1 2 3 4 5

GPU_B+

10U_0805_25V6K~D
2
PC6219
Vinafix.com

1
A A
+5VS

4.7U_0603_6.3V
1
PC6200

2200P_0402_50V7K
0.1U_0402_25V6

10U_0805_25V6K~D

10U_0805_25V6K~D
2
NVVDDS_HG1

EMI@ PC6203

EMI@ PC6204
1

1
PC6205

PC6206
PQ6200

2
1

2
NVVDDS_LG1

AON6962_DFN5X6D-8-7
G1

D1
NVVDDS_SW1 +GPU_CORE_VDDS
PC6207

1
0.22U_0603_25V7K NVVDDS_SW1 7
D2/S1

2 2
PU6101

20

19

18

17

16

G2

S2

S2

S2
RT8816AGQW_WQFN20_3X3
PR6203

PHASE1

LGATE1

LGATE2

PHASE2
PVCC

3
2.2_0603_1% PL6200
PD=C*V*V*Freq 0.22UH_MMD-06DZER22MEM2L__32A_20%
NVVDDS_BST1 1 15 1 2

1
BOOT1 BOOT2
EN pin don't floating
NVVDDS_LG1 EMI@ PC6224 EMI@
NVVDDS_HG1 PR6226
1 2 2 14 680P_0402_50V7K
UGATE1 UGATE2

470U_D2_2VM_R4.5M~D

330U_D3_2VM_R6M
1 2 1 2 1 1
PR6540
1M_0402_1% 3 13 + +
<31,66> NVVDDS_EN EN PGOOD 2.2_1206_5%

PC6225

PC6226
@ PR6229 NVVDD2_PSI 4 12 NVVDDS_COMP 2 1 2 2
0_0402_5% PSI OCSET/SS

+1.8V_GFX_AON 1 2 PR6208 PR6207

1 2 5 11 86.6K_0402_1%
<23> NVVDDS_PWM_VID VID VSNS

REFADJ

REFIN

RGND
VREF
Avoid high dV/dt 0_0402_5% 21
+NVVDD2

TON
1 2 GND
<23,67> GPU_PSI Rocset=Ivally*Ron*12/Iocset TDC 12.6A
B B
PR6228 where Rocset=86.6K,Ron=2.5mohm,Iocset=10uA,
Peak Current 18A

10
21K_0402_1% =>OCP=26A

2
OCP=26A
1

PR6214
PR6230 NVVDDS_VIDBUF 0_0402_5% Fsw=305KHz
0_0402_5% DCR:0.98mohm +-5%

1
TYP MAX

1
2

@ PR6213
240K_0402_1% H/S Rds(on):6.8mohm ,8.6mohm
R1 R4 L/S Rds(on):2mohm ,2.5mohm
1

1
6.19K_0402_1%

2
PR6216

PR6217

16.5K_0402_1%

PC6213
R3
1

NVVDDS_VREF

499K_0402_1%
2 1
4700P_0402_50V7K

1
@ PC6212
4.32K_0402_1%
PR6215

PR6240
1000P_0402_25V
.1U_0402_16V7K
2

2
PC6214
2

2
1

PR6219 PR6220
R5
2

0_0402_5% 0_0402_5%

PR6222
1

1
309_0402_1%
PR6223 100_0402_5%
1

2 1 +GPU_CORE_VDDS
R2
2 1 VDDS_SENSE_VGA <26>
4700P_0402_50V7K

PR6224 Avoid high dV/dt

C 20.5K_0402_1% GNDS_SENSE_VGA <26>
1
PC6215

PR6225 100_0402_5%
GPU_B+ 2 1
2

C C

Place close to GPU

1Phase DEM 1Phase CCM 1Phase DEM 1Phase CCM

PSI 0V 0.79V PSI 0V 0.8V
PR6229 NC NC PR6229 NC NC
PR6228 21Kohm 7.5Kohm PR6228 215Kohm 115Kohm
PR6230 0ohm 13.5Kohm PR6230 0ohm 100Kohm

Operation Phase Number PSI Voltage Setting

1phase with DEM 0V to 0.4V
1phase with CCM 0.7V to 0.88V
2phase with DEM 1.08V to 1.35V
2phase with CCM 1.6V to 5.5V

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/09/18 Deciphered Date 2016/09/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+NVVDD2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 68 of 78
1 2 3 4 5
 5 4 3 2 1

Vinafix.com B+
1.35VS_VGAP
TDC=14 A
D
Ipeak=20 A D

PJP800@
OCP=24 A
+1.35VS_B+ 1
1 2
2 Switching Frequency: 300kHz
+5VALW
JUMP_43X39
TYP MAX
H/S Rds(on):6.3mohm ,7.6mohm

1000P_0402_50V7K
1U_0402_25V6K
10U_0805_25V6K~D

10U_0805_25V6K~D
EMI@ PC802

EMI@ PC805

EMI@ PC806
2200P_0402_50V7K

0.1U_0402_25V6
L/S Rds(on):2.4mohm ,3mohm

1
EMI@ PC801

PC803

PC804
PR800
2.2_0603_5%

2
1
RT8812_PVCC

1
PC807 PQ800

1
2.2U_0603_16V6K AON6962_DFN5X6D-8-7
PC800

D1

G1
2 1PWR_VGA_CORE_TON_1 PL800

18
PU800 0.82UH_MMD-06CZ-R82M-V1L_13A_20%
0.1U_0402_25V6 7 1 2
+1.35VS_VGAP

PVCC
PR806 PR807 D2/S1

1
2.2_0402_1% 383K_0402_1%
2 1 2 1 PWR_VGA_CORE_TON 9 2 PWR_VGA_CORE_UGATE1

G2
S2

S2

S2
+1.35VS_B+ TON UGATE1 PC808 PR808 @EMI@

220U_D2 SX_2VY_R9M

220U_D2 SX_2VY_R9M
+3VS PR810
PR809 @ 2.2_0603_5% 0.22U_0603_25V7K 4.7_1206_5% 1 1

6
2 1 13 1 PWR_VGA_CORE_BOOT12 1PWR_VGA_CORE_BOOT1_1 2 1
+3VS

1 2
PGOOD BOOT1 + +

PC810

PC811
100K_0402_1%
12K_0402_1%

PC809 @EMI@
1

FBVDD/Q_ENP 3 20 PWR_VGA_CORE_PHASE1 680P_0402_50V7K

<15,23> DGPU_PWROK EN PHASE1 2 2
PR861

2
1

PC812 FBVDD_PSI 4 19 PWR_VGA_CORE_LGATE1

0.1U_0402_25V6 PSI LGATE1
PR812
2

FBVDD_PSI 2 1
2

PR813 8.87K_0402_1%
1

10K_0402_1%
PR862

1 2 5 14
<23,31> FBVDD_EN VID UGATE2
C C
10K_0402_1% 8 15
2

VREF BOOT2
1

7 16
PR815 REFIN PHASE2
10K_0402_1%
6 17
REFADJ LGATE2 PR816
2

100_0402_5%
PWR_VGA_CORE_SS 11 12 1 2 PJP801
SS VSNS
2200P_0402_50V7K

+1.35VS_VGAP 1 2 +1.35VS_VGA
1 2
0.1U_0402_25V6

21 10 JUMP_43X118 @

0.1U_0402_25V6
GND RGND
PR819 S1@

PJP802
1

PR818 S1@
PC816

1 2
PC817

1 2
1

1
@

PC819
30K_0402_1%

68.1K_0402_1%

PR818
PC818 RT8812AGQW-GP JUMP_43X118 @
2

47P_0402_50V8J
OPS
2

2
2

34.8K_0402_1%
S2@
3

DMN53D0LDW-7 2N SOT363-6
PQ802B

PR821 <25> FBVDDQ_SENSE

+3VALW 1 2 5 PR819

10K_0402_5%
DMN53D0LDW-7 2N SOT363-6

4
6

PQ802A

52.3K_0402_1%
PR822 S2@
1 2 2
<23> MEM_VDD_CTL
0_0402_5%
1

MEM_VDD_CTL VOUT
1
0.1U_0402_25V6
PC821

B B
BOM config GPU type VRAM memory VRAM vender RVL PR818 PR819
L 1.35V
2

@
S1@ 1.35V & 1.5V 30K 68.1K
H 1.5V/1.55V
S2@ 1.35V & 1.55V 34.8K 52.3K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.35VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 69 of 78
5 4 3 2 1
 D

1.0(A00)
Rev
For NV N17P latest spec

78
Compal Electronics, Inc.

of
70
Sheet
VGA DECOUPLING
LA-E993P
1

1
4.7uF_0603 X 2
22uF_0805 X 3
10uF_0603 X 7

1uF_0402 X 5

Tuesday, March 06, 2018

+NVVDDS

PC6525
Document Number

22U_0805_6.3VAM
1

PC6524
22U_0805_6.3VAM
1

PC6523
Date:
Title

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize

22U_0805_6.3VAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1

PC6522 PC6540
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

10U_0603_6.3V6M 4.7U_0603_6.3V6K
1 2 1 2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PC6521 PC6539
10U_0603_6.3V6M 4.7U_0603_6.3V6K
1 2 1 2
PC6520 PC6538
2016/09/18

1U_0402_6.3V6K 10U_0603_6.3V6M
2

2
1 2 1 2
PC6519 PC6537
1U_0402_6.3V6K 10U_0603_6.3V6M
1 2 1 2
PC6518 PC6536
1U_0402_6.3V6K 10U_0603_6.3V6M
1 2 1 2

Deciphered Date
Compal Secret Data
PC6517 PC6535
1U_0402_6.3V6K 10U_0603_6.3V6M
1 2 1 2
PC6516 PC6534
+GPU_CORE_VDDS

1U_0402_6.3V6K 10U_0603_6.3V6M
1 2 1 2

2015/09/18
For NV N17P latest spec
3

3
Security Classification
Issued Date
4.7uF_0603 X 16
22uF_0805 X 7
10uF_0603 X 9

1uF_0402 X 8
470uF X 1
+NVVDD

PC6559

@
470U_D2_2VM_R4.5M~D

+
1

2
Vinafix.com
4

4
PC6549 PC6558

@
10U_0603_6.3V6M 470U_D2_2VM_R4.5M~D

+
1

2
1 2
PC6507 PC6515 PC6533 PC6548 PC6557
1U_0402_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 470U_D2_2VM_R4.5M~D

+
1

2
1 2 1 2 1 2 1 2
PC6506 PC6514 PC6532 PC6547 PC6556
1U_0402_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 22U_0805_6.3VAM

2
1 2 1 2 1 2 1 2
PC6505 PC6513 PC6531 PC6546 PC6555
1U_0402_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 22U_0805_6.3VAM

2
1 2 1 2 1 2 1 2
PC6504 PC6512 PC6530 PC6545 PC6554
1U_0402_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 22U_0805_6.3VAM

2
1 2 1 2 1 2 1 2
PC6503 PC6511 PC6529 PC6544 PC6553
1U_0402_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 22U_0805_6.3VAM

2
1 2 1 2 1 2 1 2
PC6502 PC6510 PC6528 PC6543 PC6552
1U_0402_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 22U_0805_6.3VAM

2
1 2 1 2 1 2 1 2
PC6501 PC6509 PC6527 PC6542 PC6551
1U_0402_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 22U_0805_6.3VAM

2
1 2 1 2 1 2 1 2
5

5
PC6500 PC6508 PC6526 PC6541 PC6550
1U_0402_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 10U_0603_6.3V6M 22U_0805_6.3VAM

2
1 2 1 2 1 2 1 2
+GPU_CORE

A
 Vinafix.com
5 4 3 2 1

Place close to Choke in VCCSA first phase circuit

PH5000 PR5001 PR5002
100K_0402_1%_TSM0B104F4251RZ 12K_0402_1% 7.5K_0603_1%
PC5000 1 2 1 2 1 2 +VCCST
<74> CSN_1PH SW_1PH <74>
PR5000 @ 2200P_0402_50V7K

1
100_0402_1% 1 2 PC5001

100_0402_1%
1

2
1 2 PR5003 0.01UF_0402_25V7K

499_0402_1%

45.3_0402_1%

45.3_0402_1%
1 2

PR5004

PR5005

PR5006

PR5007
PR5008 PR5009 10_0402_1% PC5002
0_0402_5% 1.1K_0402_1% 10U_0402_6.3V6M

1
1 2 1 2 VSN_1PH
<10> VSSSA_SENSE

2
@

2
2
2 1 1 2 @
D PC5003 D

CSP_1PH
1000P_0402_50V7K PR5011 PC5004 PC5005 PR5012

470P_0402_50V8J
1
1.74K_0402_1% 3300P_0402_25V7K 2200P_0402_50V7K 100_0402_1%

1
1 2 1 2 VSP_1PH CSN_1PH_R 81215_VR_HOT
1 2

PC5006

28.7K_0402_1%
<10> VCCSA_SENSE H_PROCHOT# <8,44,59,60>

PR5013
PR5014 @ PR5010 +3VS
100_0402_1% 0_0402_5% PC5008

2
1 2 PR5091 1000P_0402_50V7K 81215_SCLK 1 2
+VCCSA 1 2 VSP_1PH_R
1 2 1 2 PR5015 49.9_0402_1%
VR_SVID_CLK <8>

IMON_1PH
PWM1_1PH/ICCMAX1 <74>

1
2.21K_0402_1% PC5007 PR5018 81215_ALERT 2 1
VR_SVID_ALERT# <8>
1000P_0402_50V7K 12.4K_0402_1% PR5016 PR5017 0_0402_5%
2 1 10K_0402_1% PR5022
PR5021 @ 38.3K_0402_1% 81215_SDIO 1 2
VR_SVID_DATA <8>

2
100_0402_1% PR5020 PC5009 PR5019 10_0402_1%
IMVP_VR_PG <15>
1 2 1.5K_0402_1% 0.015U_0402_25V7K 1 2
+VCC_CORE PR5023 2 1 2 1
0_0402_5% 81215_SCLK
1 2 VSP_4PH 81215_ALERT 1 2
<9> VCCSENSE VR_ON <15>
1 2 81215_SDIO

2
PR5024
PC5011 PC5010 0_0402_5% PR5027 @
1000P_0402_50V7K PR5026 100P_0402_50V8J 100_0402_1%

1
1K_0402_1% 1 2
<9> VSSSENSE 1 2 1 2 VSN_4PH VSN_1PH PR5029 +VCCGT
PR5028 @ 0_0402_5%

ILIM_1PH
COMP_1PH
100_0402_1% PR5025 1 2 VCCGT_SENSE <11>
1 2 0_0402_5% 1 2 VSP_1PH

1
PC5012 PC5013
2200P_0402_50V7K 1000P_0402_50V7K
PR5030

2
1.37K_0402_1%
1 2 1 2 VSSGT_SENSE <11>
PR5032 @
PU5000 PR5031 100_0402_1%
PC5015 PR5033 PC5016 1 2 0_0402_5% 1 2

53

52
51
50
49
48
47
46
45
44
43
42
41
40
NCP81215DPA0MNTXG_QFN52P_6X6
47P_0402_50V8J 49.9_0402_1% 470P_0402_50V8J
1 2 1 2 1 2 PR5034 PC5014

TAB

VR_RDY

SCLK
ALERT#
SDIO
VSP_1PH
VSN_1PH
COMP_1PH
ILIM_1PH
CSN_1PH
CSP_1PH
IMON_1PH

PWM_1PH/ICCMAX_1PH
EN
C C
26.1K_0402_1% 2200P_0402_50V7K
PR5035 PR5036 2 1 PR5037 PC5019 PC5020
3.65K_0402_1% 1K_0402_1% PR5038 49.9_0402_1% 470P_0402_50V8J 47P_0402_50V8J
1 2 1 2 1 2 26.1K_0402_1% 1 2 1 2 1 2
PC5017 VSP_4PH 1 39 81215_VR_HOT 1 2
PC5018 470P_0402_50V8J VSN_4PH 2 VSP_4PH VRHOT# 38 VSP_2PH PC5022 2 1 1 2 1 2
2200P_0402_50V7K 2 1 3 VSN_4PH VSP_2PH 37 VSN_2PH 470P_0402_50V8J
DIFFOUT_4PH 4 IMON_4PH VSN_2PH 36 1 2 PR5039 PR5040 PC5021
FB_4PH 5 DIFFOUT_4PH IMON_2PH 35 DIFFOUT_2PH 1K_0402_1% 3.65K_0402_1% 2200P_0402_50V7K
COMP_4PH 6 FB_4PH DIFFOUT_2PH 34 FB_2PH
1 2 ILIM_4PH 7 COMP_4PH FB_2PH 33 COMP_2PH
Place close to Choke in VCORE
220K_0402_5%_ERTJ0EV224J

CSCOMP_4PH PR5041 30.1K_0402_1% 8 ILIM_4PH COMP_2PH 32 ILIM_2PH 1 2

220K_0402_5%_ERTJ0EV224J
first phase circuit CSSUM_4PH 9 CSCOMP_4PH ILIM_2PH 31 PR5042 11.3K_0402_1% CSCOMP_2PH
CSSUM_4PH CSCOMP_2PH
1

10 30 CSSUM_2PH
75K_0402_1%

CSREF_4PH CSSUM_2PH

1
CSP1_4PH 11 29
PH5001

PR5043

75K_0402_1%
CSP2_4PH 12 CSP1_4PH CSREF_2PH 28 CSP1_2PH

PR5044

PH5002
PWM1_4PH/ICCMAX_4PH

PWM1_2PH/ICCMAX_2PH
CSP2_4PH CSP1_2PH
2

PWM4_4PH/ROSC_MPH
PC5024 CSP3_4PH 13 27 2 1
1000P_0402_50V7K

PWM2_2PH/ROSC_1PH
220P_0402_50V8J

100P_0402_50V8J
820PF_0402_50V7K
PR5046 CSP3_4PH CSP2_2PH +5VALW

TTSENSE_1PH/PSYS
2

1
PWM3_4PH/VBOOT
PC5023

PC5025

PC5026

PC5027
80.6K_0603_1% 0.1U_0402_25V7K PR5045

PWM2_4PH/ADDR
1

2
1 2 1K_0402_1% PC5028
<71,72> SW1_4PH

TTSENSE_2PH
PR5050
165K_0402_1%

0.1U_0402_25V7K Place close to Choke in VCCGT first phase circuit

TSENSE_4PH
2

2
1

1
80.6K_0603_1%

165K_0402_1%
CSP4_4PH
1 2
PR5047

PR5048
PR5075 @
<71,72> SW2_4PH
PR5051 2 1
+5VALW

DRON
VRMP
80.6K_0603_1% PR5049

VCC
1 2 1K_0402_1% 59K_0603_1%
<71,73> SW3_4PH
2

2
PR5052 1 2
SW1_2PH <71,74>
80.6K_0603_1% PR5053

14
15
16
17
18
19
20
21
22
23
24
25
26
1 2 1K_0402_1%
<71,73> SW4_4PH
CPU_B+ 1 2 PC5029 P_SYS <60>
0.1U_0402_25V6 CSP4_4PH
PC5030 2 1 TSENSE_4PH PC5031
0.01U_0402_50V7K 0.1U_0402_25V6 PR5055
1 2 TSENSE_2PH 1 2 24.9K_0402_1% CSREF_2PH
CSREF_4PH CSREF_2PH <74>
1 2 1 2
<72,73> CSREF_4PH +5VALW
<72,73,74> DRVON PWM2_2PH/ROSC1
PR5057 PR5054 1 2
1U_0402_6.3V6K
B B
6.98K_0402_1% 2.2_0603_5% PR5056
1
1 2 CSP1_4PH
PC5032
25.5K_0402_1%

100K_0402_1%
<71,72> SW1_4PH

1
2

PR5058

4.32K_0402_1%

24.9K_0402_1%

97.6K_0402_1%

97.6K_0402_1%
PWM1_2PH/ICCMAX2 <74>
2
2

1
@ PR5071

PR5059

PR5060

PR5061

PR5062
PC5033 100K_0402_1% PR5063
0.033U_0402_25V7K 6.98K_0402_1%
1

2
CSP1_2PH 1 2
<72> PWM1_4PH/ICCMAX4 SW1_2PH <71,74>
1

CSREF_4PH

2
<72> PWM2_4PH/ADDR
PR5064

2
6.98K_0402_1%
1 2 CSP2_4PH PC5034
<71,72> SW2_4PH
0.033U_0402_25V7K

1
2

<73> PWM3_4PH/VBOOT
2

PR5072
PC5035 14.3K_0402_1% CSREF_2PH
0.047U_0402_25V7K <73> PWM4_4PH/ROSCM
1

CSREF_4PH

PR5065
6.98K_0402_1%
1 2 CSP3_4PH
<71,73> SW3_4PH
2

TSENSE_4PH TSENSE_2PH
2

@ PR5073
1

1
0_0402_5%

0_0402_5%
PC5036 100K_0402_1%
PR5067

PR5068
0.033U_0402_25V7K
1

CSREF_4PH
Place close to H-side,L-side MOS
2

2
PR5066 Place close to H-side,L-side MOS in VCCGT first phase
6.98K_0402_1% in VCORE first phase
1 2 CSP4_4PH
<71,73> SW4_4PH
1

1
A A
2

1
PH5003
2

PR5074 PR5069 PH5004 PR5070

PC5037 5.49K_0402_1% 220K_0402_5%_ERTJ0EV224J 61.9K_0402_1% 61.9K_0402_1%
0.01U_0402_25V7K 220K_0402_5%_ERTJ0EV224J
1

2
1

CSREF_4PH

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_VCORE_NCP81215
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 71 of 78
5 4 3 2 1
 5 4 3 2 1

B+ CPU_B+
Main Func = CORE_Phase1&2 EMI@ PL5100
1 2

Vinafix.com

100U_25V_M
1000P_0402_50V7K
1U_0402_25V6K
FBMA-L11-453215800LMA90T_2P 1

EMI@ PC5110

EMI@ PC5111
1

1
+

PC5103
2

2
2
D D

10U_0603_25V6M
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

2200P_0402_50V7K
EMI@PC5109
0.1U_0402_25V6
1
1

1
PC5135
PC5105

PC5106

PC5107

EMI@PC5108
+5VALW

2
2

2
+VCC_CORE PR5100
TDC PL2 :80A 2_0603_5%
1 2 PU5101_VCC
Peak Current 128A

2
OCP Current PC5100
DCR 0.67mohm +/-5% 1U_0603_6.3V6M PR5105 PC5102

1
3.9_0603_1% 0.22U_0603_25V7K
Load Line 1.8mV/A PU5101
1 2CORE_BST1_R
1 2
PR5104 0_0402_5% 3 8
1 2 15 VCC VIN 9
<71,72,73,74> DRVON VCCD VIN
PR5102 0_0402_5%
1 2 17 5 CORE_BST1
<71> PWM1_4PH/ICCMAX4 THWN BOOT

1
PU5101_DRVON 16 7 CORE_BST1_PHASE 0.15UH_MHCB06040-R15M-C1R675__36A_20%
PU5101_PWM DISB# PHASE PL5101
PC5101 1
PWM
2.2U_0603_10V7K 2 11 CORE_SW1 1 4 +VCC_CORE

2
+5VALW SMOD# SW 12
SW 2 3

EMI@
4
10 CGND PR5109
PGND

1
4.7_1206_5%
C 14 PL5101_CSREF_4PH1 2 C
13 PGND 6 CSREF_4PH <71,72,73>
GL NC

PR5106
19 18 10_0402_1%
GL AGND

1CORE_SW1_SNB
2
NCP302045MNTXG_PQFN33_5X5
SW1_4PH <71>

EMI@
680P_0603_50V7K
PC5112
CPU_B+

2
10U_0603_25V6M

1000P_0402_50V7K
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

2200P_0402_50V7K

1U_0402_25V6K
EMI@ PC5120
0.1U_0402_25V6
+5VALW
1

1
1

1
PC5116

EMI@PC5122
PC5117

PC5118

PC5136

EMI@PC5119

EMI@PC5121
2

2
2

2
B B
PR5115
2_0603_5%
1 2 PU5102_VCC
2

PC5114
1U_0603_6.3V6M PR5118 PC5115
1

3.9_0603_1% 0.22U_0603_25V7K
1 2 CORE_BST2_R
1 2
PU5102
PR5117 0_0402_5% 3 8
1 2 15 VCC VIN 9
<71,72,73,74> DRVON VCCD VIN
PR5114 0_0402_5%
1 2 17 5 CORE_BST2
<71> PWM2_4PH/ADDR THWN BOOT
1

PC5113 PU5102_DRVON 16 7 CORE_BST2_PHASE 0.15UH_MHCB06040-R15M-C1R675__36A_20%

PU5102_PWM DISB# PHASE PL5102
1
PWM
2.2U_0603_10V7K 2 11 CORE_SW2 1 4 +VCC_CORE
2

SMOD# SW 12
+5VALW SW 2 3 PL5102_CSREF_4PH
PR5121 EMI@

4
CGND
1
4.7_1206_5%

10 PR5122
14 PGND 1 2
13 PGND 6 10_0402_1% CSREF_4PH <71,72,73>
19 GL NC 18
GL AGND
1CORE_SW2_SNB 2

NCP302045MNTXG_PQFN33_5X5
SW2_4PH <71>
A A
EMI@
680P_0603_50V7K

Security Classification Compal Secret Data Compal Electronics, Inc.

PC5123

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCC_CORE_Phase1&2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 72 of 78
5 4 3 2 1
 5 4 3 2 1

Main Func = CORE_Phase3&4 CPU_B+

Vinafix.com
D D

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

2200P_0402_50V7K

1000P_0402_50V7K
1U_0402_25V6K
+5VALW

EMI@PC5130
0.1U_0402_25V6
1

1
PC5127

PC5128

PC5129

PC5137

EMI@PC5131

EMI@PC5132

EMI@PC5133
PR5127
2_0603_5%

2
1 2 PU5103_VCC

2
PC5125
1U_0603_6.3V6M

1
PR5130 PC5126
3.9_0603_1% 0.22U_0603_25V7K
PU5103
PR5129 0_0402_5% 1 2 CORE_BST3_R 1 2
1 2 3 8
<71,72,73,74> DRVON VCC VIN
PR5126 0_0402_5% 15 9
1 2 VCCD VIN
<71> PWM3_4PH/VBOOT CORE_BST3
17 5
THWN BOOT

1
PU5103_DRVON 16 7 CORE_BST3_PHASE 0.15UH_MHCB06040-R15M-C1R675__36A_20%
PU5103_PWM DISB# PHASE PL5103
PC5124 1
PWM
2.2U_0603_10V7K 2 11 CORE_SW3 1 4 +VCC_CORE

2
SMOD# SW

EMI@
12
+5VALW SW 2 3

1
4.7_1206_5%
4
10 CGND PR5134
PGND

PR5131
14 PL5103_CSREF_4PH1 2
13 PGND 6 CSREF_4PH <71,72,73>

1CORE_SW3_SNB
C 19 GL NC 18 10_0402_1% C

2
GL AGND

NCP302045MNTXG_PQFN33_5X5 SW3_4PH <71>

EMI@
680P_0603_50V7K
PC5134

2
CPU_B+

+5VALW

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

2200P_0402_50V7K

1000P_0402_50V7K
1U_0402_25V6K
EMI@PC5219
0.1U_0402_25V6
PR5214

1
PC5216

PC5217

PC5218

PC5138

EMI@PC5220

EMI@PC5214

EMI@PC5215
2_0603_5%
1 2 PU5104_VCC

2
2

B PC5212 B

1U_0603_6.3V6M
1

PR5217 PC5213
3.9_0603_1% 0.22U_0603_25V7K
PU5104
PR5215 0_0402_5% 1 2 CORE_BST4_R 1 2
1 2 3 8
<71,72,73,74> DRVON VCC VIN
PR5213 0_0402_5% 15 9
1 2 VCCD VIN
<71> PWM4_4PH/ROSCM CORE_BST4
17 5
THWN BOOT
1

PU5104_DRVON 16 7 CORE_BST4_PHASE 0.15UH_MHCB06040-R15M-C1R675__36A_20%

PU5104_PWM DISB# PHASE PL5202
PC5211 1
PWM
2 11 CORE_SW4 1 4 +VCC_CORE
2

SMOD# SW 12
2.2U_0603_10V7K +5VALW SW 2 3
EMI@

4
10 CGND PR5221
PGND
1

PL5202_CSREF_4PH
4.7_1206_5%

14 1 2
13 PGND 6 CSREF_4PH <71,72,73>
1 CORE_SW4_SNB

GL NC
PR5218

19 18 10_0402_1%
GL AGND
2

NCP302045MNTXG_PQFN33_5X5
SW4_4PH <71>
EMI@
680P_0603_50V7K

A A
PC5221

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCC_CORE_Phase3&4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 73 of 78
5 4 3 2 1
 5 4 3 2 1

Main Func = VCC_GT/+VCC_SA CPU_B+

Vinafix.com
+5VALW

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

2200P_0402_50V7K

1000P_0402_50V7K
1U_0402_25V6K
EMI@PC5206
0.1U_0402_25V6
D PR5200 D

1
PC5203

PC5204

PC5205

PC5233

EMI@PC5210

EMI@PC5207

EMI@PC5208
2_0603_5%
1 2 PU5201_VCC

2
+VCCGT

2
TDC PL2 :22.4A PC5200
1U_0603_6.3V6M
Peak Current 32A

1
DCR 0.9mohm +/-5% PR5205
3.9_0603_1%
PC5202
0.22U_0603_25V7K
PU5201
Load Line 2.7mV/A 1 2 GT_BST_R 1 2
PR5204 0_0402_5% 3 8
1 2 15 VCC VIN 9
<71,72,73,74> DRVON VCCD VIN
PR5202 0_0402_5%
1 2 17 5 GT_BST
<71> PWM1_2PH/ICCMAX2 THWN BOOT

1
PU5201_DRVON 16 7 GT_BST_PHASE
PU5201_PWM DISB# PHASE PL5201
PC5201 1 0.15UH_MHCB06040-R15M-C1R675__36A_20%
2 PWM 11 GT_SW 1 4
2.2U_0603_10V7K

2
SMOD# SW
+5VALW SW
12 +VCCGT
2 3

EMI@PR5206
4

4.7_1206_5%
CGND

1
10 PR5209
14 PGND PL5201_CSREF_2PH 1 2
13 PGND 6 CSREF_2PH <71>
19 GL NC 18 10_0402_1%
GL AGND

2
NCP302045MNTXG_PQFN33_5X5
C SW1_2PH <71> C

GT_SNB

680P_0402_50V7K
1
EMI@ PC5209
2
CPU_B+

+5VALW

2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M

1000P_0402_50V7K
EMI@PC5224

1U_0402_25V6K
0.1U_0402_25V6
1

1
EMI@PC5223

PC5225

PC5226

EMI@PC5228

EMI@PC5229
PR5229
1 2 PU5203_VCC +VCCSA

2
TDC PL2 :7.77A
2_0603_5% Peak Current 11.1A
2

PC5230
1U_0603_6.3V6M
DCR 6.2mohm +/-5%
1

B
Load Line 10.3mV/A B
PR5225 PC5222
3.9_0603_1% 0.22U_0603_25V7K
PU5203 SA_BST_R
1 2 1 2
PR5223 0_0402_5% 3 8
1 2 15 VCC VIN 9
<71,72,73,74> DRVON VCCD VIN
PR5224 0_0402_5%
1 2 17 5 SA_BST PL5203
<71> PWM1_1PH/ICCMAX1 THWN BOOT
1

PU5203_DRVON 16 7 SA_BST_PHASE 0.47UH_NA__12.2A_20%

PC5231 PU5203_PWM 1 DISB# PHASE
2 PWM 11 SA_SW 1 4
2

SMOD# SW
2.2U_0603_10V7K
SW
12 +VCCSA
2 3
4
CGND
EMI@PR5226

10
4.7_1206_5%

PGND
1

14
13 PGND 6 CSN_1PH <71>
19 GL NC 18
GL AGND
SA_SNB 2

NCP302035MNTXG_PQFN33_5X5
SW_1PH <71>
EMI@

680P_0402_50V7K
1 2

A A
PC5232

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCCGT/+VCCSA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 74 of 78
5 4 3 2 1
 4
3
2
1

1uF*48
47uF*2
10uF*21
22uF*31
330uF*1
220uF*2

1uF*12
+VCCGT

10uF*10
22uF*26
220uF*2
+VCC_CORE

A
A

+VCC_CORE

2 1

+VCCGT
PC5701
22U_0603_6.3V6M

+VCCGT
2 1

PC5702 2 1 2 1 2 1 2 1 2 1 2 1

2
1
2
1

+
+

22U_0603_6.3V6M
2 1 PC5603 PC5593 PC5577 PC5568 PC5617 PC5544 PC5524 PC5500
1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 220U_D7_2VM_R6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 330U_D3_2VM_R6M
PC5703 2 1 2 1 2 1 2 1 2 1 2 1

2
1
2
1

+
+

22U_0603_6.3V6M
2 1 PC5604 PC5594 PC5578 PC5569 PC5618 PC5545 PC5525 PC5501
1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 220U_D7_2VM_R6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 220U_D7_2VM_R6M
PC5704 2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+

22U_0603_6.3V6M
2 1 PC5605 PC5595 PC5579 PC5570 PC5627 PC5546 PC5526 PC5502
1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0805_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 220U_D7_2VM_R6M
PC5705 2 1 2 1 2 1 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC5606 PC5596 PC5580 PC5571 PC5624 PC5547 PC5527
1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0805_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
PC5706 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC5607 PC5597 PC5581 PC5572 PC5638 PC5548 PC5528 PC5503
1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0805_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M
PC5707 2 1 2 1 2 1 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC5608 PC5598 PC5583 PC5636 PC5549 PC5529 PC5504
1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M
PC5708 2 1 2 1 2 1 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC5609 PC5599 PC5584 PC5622 PC5550 PC5530 PC5505
1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M

B
B

PC5709 2 1 2 1 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
Vinafix.com

2 1 PC5610 PC5600 PC5630 PC5551 PC5531 PC5506

1U_0201_6.3V6M 10U_0402_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M
PC5710 2 1 2 1 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC5611 PC5601 PC5615 PC5552 PC5532 PC5507
1U_0201_6.3V6M 10U_0402_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M
PC5711 2 1 2 1 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC5612 PC5602 PC5628 PC5553 PC5533 PC5508
1U_0201_6.3V6M 10U_0402_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M
PC5712 2 1 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC5613 PC5633 PC5554 PC5534 PC5509
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M
PC5713 2 1 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC5614 PC5619 PC5555 PC5535 PC5510
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M
PC5714 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC5623 PC5556 PC5536 PC5511
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M
PC5715 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC5626 PC5557 PC5537 PC5512
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M
PC5716 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
PC5632 PC5558 PC5538 PC5513
1uF*1

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 10U_0402_6.3V6M

10uF*7
22uF*2
47uF*4
+VCCSA

2 1 2 1 2 1

PC5620 PC5559 PC5514

1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1

PC5629 PC5560 PC5539 PC5515

C
C

1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0805_6.3V6M 10U_0402_6.3V6M

2 1 2 1 2 1 2 1

PC5634 PC5561 PC5540 PC5516

1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0805_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1
+VCCSA

PC5631 PC5562 PC5541 PC5517

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0805_6.3V6M 10U_0402_6.3V6M

Issued Date
2 1 2 1 2 1 2 1
2 1 2 1
2
1

2 1 PC5637 PC5563 PC5542 PC5518

Security Classification
PC5586 PC5582 PC5573 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0805_6.3V6M 10U_0402_6.3V6M
PC5639 10U_0402_6.3V6M 22U_0603_6.3V6M 47U_0603_6.3V6M 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 2 1 2 1
2
1

PC5616 PC5564 PC5543 PC5519

PC5587 PC5585 PC5574 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0805_6.3V6M 10U_0402_6.3V6M
10U_0402_6.3V6M 22U_0603_6.3V6M 47U_0603_6.3V6M 2 1 2 1 2 1
2 1
2
1

PC5635 PC5565 PC5520

PC5588 PC5575 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
10U_0402_6.3V6M 47U_0603_6.3V6M 2 1 2 1 2 1
2 1

2016/01/06
2
1

PC5621 PC5566 PC5521

PC5589 PC5576 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
10U_0402_6.3V6M 47U_0603_6.3V6M 2 1 2 1 2 1
2 1
PC5625 PC5567 PC5522
PC5590 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
2 1 10U_0402_6.3V6M 2 1
2 1
PC5801 PC5523
+VCC_CORE

22U_0603_6.3V6M PC5591 10U_0402_6.3V6M

2 1 10U_0402_6.3V6M
2 1
PC5802
22U_0603_6.3V6M PC5592
2 1 10U_0402_6.3V6M

D
D

PC5803
Compal Secret Data
Deciphered Date

22U_0603_6.3V6M
2 1

PC5804
22U_0603_6.3V6M
2 1

PC5805
22U_0603_6.3V6M
2 1
2017/01/06

PC5806
22U_0603_6.3V6M
2 1

PC5807
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

22U_0603_6.3V6M
2 1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PC5808
22U_0603_6.3V6M
2 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Title

Date:

PC5809
22U_0603_6.3V6M
2 1

PC5810
22U_0603_6.3V6M
2 1
Document Number

PC5811
22U_0603_6.3V6M
2 1

PC5812
Tuesday, March 06, 2018

22U_0603_6.3V6M
E
E

2 1

PC5813
22U_0603_6.3V6M
LA-E993P
Sheet
75
Compal Electronics, Inc.

of
PWR-CPU DECOUPLING

78
Rev
4
3
2
1

1.0(A00)
 5 4 3 2 1

Input Current:0.417A
0.95*3.85/0.85/12V=0.417A

10K_0402_5%

Vinafix.com <15> +VCCIO_PG 2

@ PR4001
1
+3VS
B+ 1
PJP4000@
2 B+_VCCIO 1
PJP4001
2
+VCCIO
D 1 2 +VCCIOP 1 2 D

1000P_0402_50V7K
1U_0402_25V6K

10U_0805_25V6K
EMI@PC4001
2200P_0402_50V7K
JUMP_43X39 JUMP_43X118 @

0.1U_0402_25V6
1

1
EMI@PC4003

EMI@PC4004

EMI@PC4000

PC4002
PU4000
2 9 PR4000 PC4005
IN PG 0_0603_5% 0.1U_0603_25V7K
2

2
3 1 BS_VCCIO 1 2 BST_VCCIO 1 2 PL4000
IN BS 1UH_PCMB042T-1R0MS_4.5A_20%
4
IN LX
6 LX_VCCIO 1 2
+VCCIOP
5 19

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
IN LX

1
PC4007

PC4009
7 20 PR4002
GND LX

PC4006

PC4008
4.7_1206_5%
8 14 FB_VCCIO

330P_0402_50V7K
@EMI@

2
GND FB

1
VCC_VCCIO

10_0402_1%
PC4010
18 17

SNB_VCCIO
GND VCC

PR4004
PR4003 0_0402_5%
<55> VCCIO_EN 1 2 EN_VCCIO 11 10

2.2U_0603_16V6K

2
EN NC

PC4012
13 12

0.22U_0402_10V6K

2
ILMT NC

1
1M_0402_1%
PC4011

PR4005
15 16 PC4013
+3VALW

2
BYP NC
680P_0402_50V7K
2

2
@ 21 @EMI@
PAD
Rup

1U_0402_6.3V6K
2

PC4014
SY8286RAC_QFN20_3X3 @ 0_0402_5%
PR4007

1
PR4006
2 1 FB_VCCIO_SENSE 1 2 VCCIO_SENSE <10>

2
21K_0402_1%
+3VALW
2

1
35.7K_0402_1%
PR4009
PR4008 @
0_0402_5% Rdown
1

2
C ILMT_VCCIO @ 0_0402_5% C
PR4010
2

1 2 VSSIO_SENSE <10>
PR4011 @
0_0402_5%
1

The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high.

+VCCIOP (0.95V)
TDC 4.48 A
Peak Current 6.4 A
OCP Current 9 A
FSW:500KHz

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+VCCIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 76 of 78
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1

Item Page# Title Date Request Issue Solution Rev.
Vinafix.com Owner Description Description
D 1 D

C
7 C

10

11

12
B B

13

14

15

16

17

A A

18

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NOTE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 77 of 78
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 2

Item Page# Title Date Request Issue Solution Rev.
Vinafix.com Owner Description Description
D 1 71 D

2 67

3 73

4 61

5 69

6 71

7 59
C C

8 59

9 59

10 59

11

12
B B

13

14

15

16

17

A A

18

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NOTE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E993P
Date: Tuesday, March 06, 2018 Sheet 78 of 78
5 4 3 2 1