Lab 1b: Schematic Editor (SE).

Basic schematic cell creation

Objective
The sequence of steps to be realized in this laboratory work is illustrated in the below mentioned
flow:

Start Custom Compiler

Create a NAND3 schematic cellview

Create and Place Instances

Edit Instance Parameters

Add Pins

Add Wires

Create Wire Names

Check and Save Design

Laboratory tasks
During SE Laboratory Work 1 the below mentioned steps will be observed:
2.1. Go to directory Ccompiler, created in advance.
2.2. Start CC from Ccompiler directory with custom_compiler & command.
2.3. Create a new schematic CellView named NAND3 in EXAMPLE library, if not created in advance.
The mentioned CellView opens in Schematic Editor window automatically if “open on create”
is marked. A new cell named NAND3 is added in the Cells column and a new schematic
cellview is added in the Views column in the Library Manager.
2.4. Add the pfet instance from SAED14nm library using Add > Instance command or
by clicking on the Add Instance button. The first transistor is named M0 by default.
Add > Instance command remains active until aborted.
When an instance is placed, a set of parameters and attributes are also displayed on the
canvas as illustrated in Fig.2.1.

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 Fig.2.1. PFET transistor

Copy already placed instance M0 using Edit > Copy command and place it next to M0 as
shown in the figure below.

Copying can be realized in two ways:

• Pre Selection: First objects are selected then Copy command is invoked. After copying,
the command is no longer active.
• Post Selection: First command is activated then copied objects are selected. After
copying the command remains active.
• Infix mode: In infix mode, when key is used to start a command, the tool generates an
implicit click at the current mouse location. Infix mode reduces mouse clicks for the object
creation commands as well as all interactive editing commands.
Infix Mode option can be enabled from the General Options dialog box.
When copied instance is placed, tool generates the name for the copied instance
automatically. In this case it will be M1 and M2 as shown in Fig.2.2.

Fig.2.2. Copying the instance

Use the same steps to place nfet transistors.

After completing all the previously mentioned steps the schematic should have the view
shown in Fig.2.3.

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 Fig.2.3. Placing the instances

2.5. After placing transistors supply voltages must be added. Place the global supply nets vdd
and vss from the library analogLib.
The Schematic Editor considers schematic nets with names ending with a “!” as global nets,
but the Schematic Editor does not require ending a global name with a “!”.
Global nets are used to electrically connect to other global nets with the same name anywhere
in the hierarchy without going through instance terminals.
The schematic looks like Fig.2.4.

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 Fig.2.4. Addition of global nets

Editing Instance Parameters

2.6. To change pfet transistor parameters simultaneously:
• Mark pfet transistors by Click,
• Call Property Editor Window by pressing ‘Q’ key,
• Give value 5 for pfet and 3 for nfet transistor in nfin field transistor,
• Give value 14m in Length field.
2.7. Apply changes by pressing button
2.8. Parameters can be edited by on-canvas editing mode. Move mouse over the parameter
and press Enter.

Add Pins
2.9. The next step is to create pins to define the inputs and outputs of the circuit. Pins are
the design objects which are used to define the interfaces of the design. Pins can be
created using Add > Pin command.
a. An input pin named “in1” must be connected to the gates of M2 and M3, input pin
“in2” must be connected to the gates of M1 and M4 and input pin “in3” must be
connected to the gates of M0 and M5 respectively.
• Choose the pin type input,
• Write in1, in2, in3 separated by spaces in Names line,
• Click on the canvas at the directions where pins in1, in2, in3 must be placed
respectively.
All pins can be placed simultaneously using the below written steps.

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 • Choose Array type in Pin toolbar,
• Choose pin type input,
• Write in1, in2, in3 separated by spaces in Names line,
• Click on the canvas to place the first pin, choose direction and angle by moving
mouse cursor and click to place them at the chosen directions.
b. An output pin named “out” must be connected to the drains of M0, M1, M2 and M3.
• Choose pin type output in Pin options toolbar,
• Write “out” in Names line,
• Click on the canvas to place the output pin named “out”.
c. Schematic should have the view shown in Fig.2.5.

Fig.2.5. Addition of pins

Add Wires
2.10. After placing transistors and pins the next step is to connect transistors by wires.
Wires can be added using Add > Wire command or by clicking on button in the toolbar.
Start creating wires from connecting the sources of pfet transistors M0, M1, M2 to vdd!.
During the wiring process, helpful hints are displayed in the status bar (bottom left side of
the Schematic Editor window).
After realizing the above mentioned steps, the part of a circuit looks like Fig.2.6.

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 Fig.2.6. Addition of wires

After creating all the wires, the circuit looks like Fig.2.7.

Fig.2.7. Wiring completion

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 Create Wire Name
2.11 When wires are created, CC generates a default net name for the wire.
Wire Name can be created manually using Add > Wire command.
a. Name the wire connecting the drains of M3 and M4 - A.
b. Name the wire connecting the drains of M4 and M5 - B.
The part of a circuit showing wires for which A and B wire names are created is illustrated in
Fig.2.8.

Fig.2.8. Addition of wire names

Checking and Saving the Circuit

2.12. In schematic design it is very important to verify the connectivity of the circuit before creating
the netlist to avoid simulation errors and warnings.

Use Design > Check and Save command or click on Check and Save button to check
and save the circuit.
Observe the Console window for error and warning messages. Observe the canvas and if
there are any conflicts in the circuit, markers are generated at the problematic regions.
The Console Window will have the view shown in Fig.2.9.

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 Fig.2.9. Console window

Open the ERC/SRC rule Check Options window using Check > Setup to see the various rule
setups performed during check and save.
Floating Input Pins in Check Options is set to a warning. Set the severity level for rule
Floating Input Pins to Error and click OK to commit the changes. The Check Options window
is shown in Fig.2.10.

Fig.2.10. Check Options window

Perform the check again using Check > Current View command or by pressing the X key.
The Console Window will have the view shown in Fig.2.11.

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 Fig.2.11. CC Console window

Marker Browser assistant appears on the right side of the schematic window and shows all
the violations.
A dialog box asking whether to save the design or not also appears. Click Save.
The gate of transistor is floating (i.e. is not connected to any input). Therefore, gate of that
transistor must be connected to “in1”.

The schematic looks like Fig.2.12.

Fig.2.12. Final view of schematic cell

After connecting gate check and save the design using Check Current Design command. The
following messages appear on the Console as shown in Fig.2.13.

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 Fig.2.13. CC Console window

The design is completed successfully if there are no warning and error massages anymore.
Save the design using command Design>Save.
Close the design using command Design>Close.

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