Instituto Tecnológico de Santo Domingo (INTEC)

Tema:

Práctica de Maquinas de Estado

Nombre

Horandy Isaac

ID:1104559

Asignatura: FUNDAMENTOS ELECTRÓNICA DIGITAL

Nombre del profesor/a: Jose Silva Archetti

IEC-208 FUND. ELECTRÓNICA DIGITAL
PRACTICA MAQUINA DE ESTADOS: DISEÑAR EL CIRCUITO DIGITAL E IMPLEMENTE EL CÓDIGO EN VHDL

1- Se necesita un circuito que indique si la cantidad de bits suministrados es par o impar. Los bits son
suministrados serialmente (1 a la vez) y la cantidad de bits es variable. Diseñe una máquina de estado
(Moore) que indica si la cadena de bits suministrados es par o impar. Dibuje el diagrama de estados e
implemente el código en VHDL(solo existe una entrada A y una salida llamada PAR, que indica que la
cantidad de bits recibidos son par).

-- testbench
library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;

ENTITY testbench IS
END ENTITY testbench;

ARCHITECTURE BENCH of testbench is

signal clock_in : std_logic;

signal Reset_in : std_logic;
signal A_in : std_logic;
signal PAR_out : std_logic;
signal cant_bits_out : integer;

signal Stop : BOOLEAN;

constant Period: TIME := 10 NS;

component stateM IS
PORT (clock: IN std_logic;
Reset: IN std_logic;
A: IN std_logic;
cant_bits: OUT integer;
PAR: OUT std_logic);
end component;

BEGIN
----------------------------------------
 -- CLOCK GENERATOR

Clock_gen: process
begin
while not Stop loop
clock_in <= '0';
wait for Period/2;
clock_in <= '1';
wait for Period/2;
end loop;
wait;
end process Clock_gen;

----------------------------------------
Stimulus: process
VARIABLE bits: integer:= -1;
begin
Reset_in <= '1';
A_in <= '1';
wait for Period;

Reset_in <= '0';

A_in <= '1';
wait for Period;

Reset_in <= '0';

A_in <= '1';
wait for Period;

Reset_in <= '0';

A_in <= '1';
wait for Period;

Reset_in <= '0';

A_in <= '1';
wait for Period;

Reset_in <= '0';

A_in <= '1';
wait for Period;

Reset_in <= '0';

A_in <= '1';
wait for Period;

Stop <= TRUE;

report "Stimulus finished";
wait;
end process;

DUT: stateM port map (

clock => clock_in,
Reset => Reset_in,
A => A_in,
 cant_bits => cant_bits_out,
PAR => PAR_out);

end architecture BENCH;

-- Design
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;

ENTITY stateM IS
PORT (clock: IN std_logic; --Señal de Reloj.
Reset: IN std_logic; -- Señal de Reset.
A: IN std_logic; --Señal de Carga
cant_bits: OUT integer;
PAR: OUT std_logic);--Señal Salida

END stateM;

ARCHITECTURE Behavioral OF stateM IS

TYPE state_type is (s_par, s_impar);
SIGNAL state: state_type;
BEGIN

logica_estado_siguiente: PROCESS(clock, A, Reset, state)

BEGIN
IF (Reset = '1') THEN
state <= s_par; -- Análisis de la posibilidad de RESET
cant_bits <= 0;
ELSIF (rising_edge(clock)) THEN -- Uso de la MACRO rising_edge
CASE state is
WHEN s_par =>
IF(A = '0') THEN
state <= s_par;
ELSIF(A = '1') THEN
state <= s_impar;
cant_bits <= cant_bits + 1;
ELSE
null;
END IF;
WHEN s_impar =>
IF(A = '0') THEN
state <= s_impar;
ELSIF(A = '1') THEN
state <= s_par;
cant_bits <= cant_bits + 1;
ELSE
null;
END IF;
END CASE;
ELSE NULL;

END IF;
 END PROCESS;

PAR <= '0' when (state = s_par) else

'1' when (state = s_impar);

END Behavioral;

2- Analice el siguiente diagrama de estados e indique que función secuencial está realizando (los valores de
salida están mostrados dentro de cada estado).

El diagrama de estado es una maquina de estado moore. Y su funcionamiento es desplazar los valores entre
3 bits, por la izquierda entra el valor de la entrada desplazando los demás valores hacia la derecha y el
valor que queda más a la derecha queda eliminado.

3- Diseñe una máquina de estado (Moore) para un contador de 0 a 9 (del 9 pasa al 0). Dibuje el diagrama de
estados e implemente el código en VHDL.

-- testbench
library IEEE;
use IEEE.STD_LOGIC_1164.all;

ENTITY testbench IS
END ENTITY testbench;

ARCHITECTURE BENCH of testbench is

signal clock_in : std_logic;

signal Reset_in : std_logic;
signal X_in : std_logic;
signal S_out : integer;

signal Stop : BOOLEAN;

constant Period: TIME := 10 NS;

component stateM IS
PORT (clock: IN std_logic;
Reset: IN std_logic;
X: IN std_logic;
S: OUT integer);
end component;

BEGIN
----------------------------------------

-- CLOCK GENERATOR

Clock_gen: process
begin
while not Stop loop
clock_in <= '0';
wait for Period/2;
clock_in <= '1';
wait for Period/2;
end loop;
wait;
end process Clock_gen;

----------------------------------------
Stimulus: process
begin
Reset_in <= '1';
X_in <= '1';
wait for Period;

Reset_in <= '0';

X_in <= '1';
wait for Period;

Reset_in <= '0';

X_in <= '1';
wait for Period;

Reset_in <= '0';

X_in <= '1';
 wait for Period;

Reset_in <= '0';

X_in <= '1';
wait for Period;

Reset_in <= '0';

X_in <= '1';
wait for Period;

Reset_in <= '0';

X_in <= '1';
wait for Period;

Reset_in <= '0';

X_in <= '1';
wait for Period;

Reset_in <= '0';

X_in <= '1';
wait for Period;

Reset_in <= '0';

X_in <= '1';
wait for Period;

Reset_in <= '0';

X_in <= '1';
wait for Period;

Stop <= TRUE;

report "Stimulus finished";
wait;
end process;

DUT: stateM port map (

clock => clock_in,
Reset => Reset_in,
X => X_in,
S => S_out);

end architecture BENCH;

-- Design
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY stateM IS
PORT (clock: IN std_logic; --Señal de Reloj.
Reset: IN std_logic; -- Señal de Reset.
X: IN std_logic; --Señales de Carga
S: OUT integer); --Señal Salida
END stateM;
ARCHITECTURE Behavioral OF stateM IS
TYPE state_type is (I0,I1,I2,I3,I4,I5,I6,I7,I8,I9);
SIGNAL state: state_type;
BEGIN

logica_estado_siguiente: PROCESS(clock, X, Reset, state)

BEGIN
IF (Reset = '1') THEN
state <= I0; -- Análisis de la posibilidad de RESET
ELSIF (rising_edge(clock)) THEN -- Uso de la MACRO rising_edge
CASE state is
WHEN I0 =>
IF(X = '0') THEN
state <= I9;
ELSIF(X = '1') THEN
state <= I1;
ELSE
null;
END IF;
WHEN I1 =>
IF(X = '0') THEN
state <= I0;
ELSIF(X = '1') THEN
state <= I2;
ELSE
null;
END IF;
WHEN I2 =>
IF(X = '0') THEN
state <= I1;
ELSIF(X = '1') THEN
state <= I3;
ELSE
null;
END IF;
WHEN I3 =>
IF(X = '0') THEN
state <= I2;
ELSIF(X = '1') THEN
state <= I4;
ELSE
null;
END IF;
WHEN I4 =>
IF(X = '0') THEN
state <= I3;
ELSIF(X = '1') THEN
state <= I5;
ELSE
null;
END IF;
WHEN I5 =>
IF(X = '0') THEN
state <= I4;
 ELSIF(X = '1') THEN
state <= I6;
ELSE
null;
END IF;
WHEN I6 =>
IF(X = '0') THEN
state <= I5;
ELSIF(X = '1') THEN
state <= I7;
ELSE
null;
END IF;
WHEN I7 =>
IF(X = '0') THEN
state <= I6;
ELSIF(X = '1') THEN
state <= I8;
ELSE
null;
END IF;
WHEN I8 =>
IF(X = '0') THEN
state <= I7;
ELSIF(X = '1') THEN
state <= I9;
ELSE
null;
END IF;
WHEN I9 =>
IF(X = '0') THEN
state <= I8;
ELSIF(X = '1') THEN
state <= I0;
ELSE
null;
END IF;
END CASE;
ELSE NULL;

END IF;

END PROCESS;

S <= 0 when (state = I0) else

1 when (state = I1) else
2 when (state = I2) else
3 when (state = I3) else
4 when (state = I4) else
5 when (state = I5) else
6 when (state = I6) else
7 when (state = I7) else
8 when (state = I8) else
9 when (state = I9);
 END Behavioral;

4- Implemente la máquina de estado del slide 30 de la presentación 6 que se encuentra en el aula virtual
e implemente su testbenchy analizar las señales de salida. Explicar cada parte del código.

4-

-- testbench
library IEEE;
use IEEE.STD_LOGIC_1164.all;

ENTITY testbench IS
END ENTITY testbench;

ARCHITECTURE BENCH of testbench is

signal clock_in : std_logic;

signal Reset_in : std_logic;
signal A_in : std_logic;
signal B_in : std_logic;
signal C_in : std_logic;
signal E_out : std_logic;
signal S_out : std_logic;

signal Stop : BOOLEAN;

constant Period: TIME := 10 NS;

component stateM IS
PORT (clock: IN std_logic;
Reset: IN std_logic;
A, B, C: IN std_logic;
E, S: OUT std_logic);
end component;

BEGIN
----------------------------------------

-- CLOCK GENERATOR

Clock_gen: process
begin
while not Stop loop
clock_in <= '0';
wait for Period/2;
clock_in <= '1';
wait for Period/2;
 end loop;
wait;
end process Clock_gen;

----------------------------------------
Stimulus: process
begin
Reset_in <= '1';
A_in <= '1';
B_in <= '1';
C_in <= '1';
wait for Period;

Reset_in <= '0';

A_in <= '0';
B_in <= '0';
C_in <= '1';
wait for Period;

Reset_in <= '0';

A_in <= '0';
B_in <= '1';
C_in <= '1';
wait for Period;

Reset_in <= '0';

A_in <= '1';
B_in <= '1';
C_in <= '1';
wait for Period;

Reset_in <= '0';

A_in <= '0';
B_in <= '0';
C_in <= '0';
wait for Period;

Reset_in <= '0';

A_in <= '0';
B_in <= '1';
C_in <= '1';
wait for Period;

Reset_in <= '0';

A_in <= '1';
B_in <= '1';
C_in <= '1';
wait for Period;

Stop <= TRUE;

report "Stimulus finished";
wait;
end process;

DUT: stateM port map (

 clock => clock_in,
Reset => Reset_in,
A => A_in,
B => B_in,
C => C_in,
E => E_out,
S => S_out);

end architecture BENCH;

-- Design
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY stateM IS
PORT (clock: IN std_logic; --Señal de Reloj.
Reset: IN std_logic; -- Señal de Reset.
A, B, C: IN std_logic; --Señales de Carga
E, S: OUT std_logic); --Señales de Salida
END stateM;

ARCHITECTURE Behavioral OF stateM IS

TYPE state_type is (VACIO,NORMAL,LLENO,ALARMA);
SIGNAL state, next_state: state_type;
BEGIN

-- Proceso dedicado a logica de estado

logic_next_state:PROCESS(state, A, B, C, clock, Reset, next_state)
BEGIN
--Inicialización con Reset
IF(Reset = '1') THEN
state <= VACIO;
ELSIF(rising_edge(clock)) THEN
state <= next_state;
END IF;
CASE state is
WHEN VACIO =>
IF(A = '0' AND B = '0' AND C = '0') THEN
next_state <= VACIO;
ELSIF(A = '0' AND B = '0' AND C = '1') THEN
next_state <= NORMAL;
ELSIF(A = '0' AND B = '1' AND C = '1') THEN
next_state <= LLENO;
ELSIF(A = '1' AND B = '1' AND C = '1') THEN
next_state <= ALARMA;
END IF;
WHEN NORMAL =>
IF(A = '0' AND B = '0' AND C = '0') THEN
next_state <= VACIO;
ELSIF(A = '0' AND B = '0' AND C = '1') THEN
next_state <= NORMAL;
ELSIF(A = '0' AND B = '1' AND C = '1') THEN
next_state <= LLENO;
 END IF;
WHEN LLENO =>
IF(A = '0' AND B = '0' AND C = '1') THEN
next_state <= NORMAL;
ELSIF(A = '0' AND B = '1' AND C = '1') THEN
next_state <= LLENO;
ELSIF(A = '1' AND B = '1' AND C = '1') THEN
next_state <= ALARMA;
END IF;
WHEN ALARMA =>
IF(A = '0' AND B = '0' AND C = '0') THEN
next_state <= VACIO;
ELSE
next_state <= ALARMA;
END IF;
END CASE;
END PROCESS logic_next_state;

-- Zona dedicada a modelar la logica de salida.

E <= '1' WHEN (state = NORMAL OR state = VACIO) ELSE '0';

S <= '0' WHEN (state = VACIO) ELSE '1';

END Behavioral;

Si analizamos el EPWave podemos darnos cuenta de que el circuito está simulando correctamente la máquina de estado, este
ejercicio se basó básicamente en crear el testbench para la máquina de estado del slide 30 de la ppt #6. Aunque no copie al detalle

el diseño de la ppt, al revisar mi diseño podrá darse cuenta de que es el mismo circuito, sólo que adapté una máquina de estado que
había hecho anteriormente al diagrama de estado de la ppt, para así poder manejar mejor el concepto.