Chapter 2 (C)

Instruction Set & Assembly Language

Guidelines from Microchip Technology

For writing assembly language program Microchip Technology has suggested the following guidelines.

1. Write instruction mnemonics in lower case. (e.g., movwf)

2. Write the special register names, RAM variable names and bit names in upper case. (e.g., PCL, RP0,
etc.)
3. Write instructions and subroutine labels in mixed case. (e.g., Mainline, LoopTime)

Important Words Being Used In Instruction Set

f any memory location in a microcontroller

W work register
b bit position in 'f' register
d destination bit
label group of eight characters which marks the beginning of a part of the program
TOS top of stack
[ ] option
<> bit position inside register

Instruction Set:
The instruction set for PIC16C74A consists of only 35 instructions. Some of these instructions are byte oriented
instructions and some are bit oriented instructions.

The byte oriented instructions that require two parameters (For example, movf f, F(W)) expect the f to be
replaced by the name of a special purpose register (e.g., PORTA) or the name of a RAM variable (e.g., NUM1),
which serves as the source of the operand. 'f' stands for file register. The F(W) parameter is the destination of the
result of the operation. It should be replaced by:

F, if the destination is to be the source register. W, if the destination is to be the working register (i.e.,
Accumulator or W register).

The bit oriented instructions also expect parameters (e.g., btfsc f, b). Here 'f' is to be replaced by the name of a
special purpose register or the name of a RAM variable. The 'b' parameter is to be replaced by a bit number
ranging from 0 to 7.

For example:
Z equ 2
btfsc STATUS, Z

Z has been equated to 2. Here, the instruction will test the Z bit of the STATUS register and will skip the next
instruction if Z bit is clear.

The literal instructions require an operand having a known value (e.g., 0AH) or a label that represents a known
value.

For example:
NUM equ 0AH ; Assigns 0AH to the label NUM ( a constant )
movlw NUM ; will move 0AH to the W register.

Instruction Set & Assembly Language 1

 Every instruction fits in a single 14-bit word. In addition, every instruction also executes in a single cycle, unless
it changes the content of the Program Counter. These features are due to the fact that PIC microcontroller has
been designed on the principles of RISC (Reduced Instruction Set Computer) architecture.

INSTRUCTION SET:

STATUAS
Mnemonics Description Cycles
bits affected
bcf f, b Clear bit b of register f 1
bsf f, b Set bit b of register f 1
clrw Clear W 1 Z

clrf f Clear f 1 Z

movlw k Move literal 'k' to W 1

movwf f Move W to f 1
movf f, F(W) Move f to F or W 1 Z

swapf f, F(W) Swap nibbles of f, putting result in F or W 1

Incf f, F(W) Increment f, putting result in F or W 1 Z

decf f, F(W) Decrement f, putting result in F or W 1 Z

comf f, F(W) Complement f, putting result in F or W 1 Z

andlw k AND literal value into W 1 Z

andwf f, F(W) AND W with F and put the result in W or F 1 Z

iorlw k INCLUSIVE-OR literal value into W 1 Z

iorwf f, F(W) INCLUSIVE-OR W with f and put the result in F or W 1 Z

xorlw k EXCLUSIVE-OR literal value into W 1 Z

xorwf f, F(W) EXCLUSIVE-OR W with f and put the result in F or W 1 Z

addlw k Add the literal value to W and store the result in W 1 C,DC,Z

addwf f, F(W) Add W to f and store the result in F or W 1 C,DC,Z

sublw k Subtract the literal value from W and store the result in W 1 C,DC,Z

subwf f, F(W) Subtract f from W and store the result in F or W 1 C,DC,Z

rlf f, F(W) Copy f into F or W; rotate F or W left through the carry bit 1 C

rrf f, F(W) Copy f into F or W; rotate F or W right through the carry bit 1 C

btfsc f, b Test 'b' bit of the register f and skip the next instruction if bit is clear 1 (2)
btfss f, b Test 'b' bit of the register f and skip the next instruction if bit is set 1 (2)
Decrement f and copy the result to F or W; skip the next instruction if
decfsz f, F(W) 1 (2)
the result is zero
Increment f and copy the result to F or W; skip the next instruction if
incfcz f, F(W) 1 (2)
the result is zero
goto label Go to the instruction with the label "label" 2
call label Go to the subroutine "label", push the Program Counter in the stack 2
retrun Return from the subroutine, POP the Program Counter from the stack 2
Return from the subroutine, POP the Program Counter from the stack;
retlw k 2
put k in W
retie Return from Interrupt Service Routine and re-enable interrupt 2
clrwdt Clear Watch Dog Timer 1 NOT_TO, NOT_PD

sleep Go into Sleep/ Standby mode 1 NOT_TO, NOT_PD

nop No operation 1

Instruction Set & Assembly Language 2

Encoding of instruction:
As it has been discussed, each instruction is of 14-bit long. These 14-bits contain both op-code and the operand.
Some examples of instruction encoding are shown here.

Example-1:
bcf f, b Clear 'b' bit of register 'f'
Operands: 0 ≤ f ≤ 127
0≤b≤7
Encoding:

0 1 0 0 b b b f f f f f f f
Op-Code Bit Address Register Address

The instruction is executed in one instruction cycle, i.e., 4 clock cycles. The activities in various clock cycles are
as follows.

Q1 Q2 Q3 Q4

Decode Read register ‘f’ Process data Write register ‘f’

Example-2:

goto K Go to label 'k' instruction

Operand: 0 ≤ K ≤ 2047 (11-bit address is specified)

Operation: K PC <10:0>
PCLATH <4:3> PC <12:11>

Encoding:

1 0 1 k k k k k k k k k k k
Op-Code 11-bit-address

Since this instruction requires modification of program Counter, it takes two instruction cycles for execution.

Q-Cycle activities are shown as follows.

Q1 Q2 Q3 Q4
1ST Instruction Read literal Process
Cycle Decode Write to PC
‘k’ Data

2ND Instruction No- No- No- No-

Cycle Operation Operation Operation Operation

Instruction Set & Assembly Language 3

Single-bit manipulation
bcf PORT, 0 ; Clear bit 0 of PORT B
bsf STATUS,C ; Set the carry bit

Clear/ Move
clrw ; Clear the Working register, W
clrf TEMP1 ; Clear Temporary variable TEMP 1
movlw 5 ; Load 5 into W
movlw 10 ; Load D’10’ or H’10’ or B’10’ into W
; depending upon the default representation
movwf TEMP1 ; move W into TEMP1
movwf TEMP1, F ; Incorrect syntax
movf TEMP1,W ; move TEMP1 into W
swapf TEMP1, F ; Swap 4-bit nibbles of TEMP1
swapf TEMP1, W ; Move TEMP1 to W, swapping nibbles
; and leave TEMP1 unchanged

Increment/ Decrement/ Compliment

incf TEMP1, F ; Increment TEMP1
incf TEMP1, W ; W < ̶ TEMP1+1; TEMP1 unchanged
decf TEMP1, F ; decrement TEMP1
comf TEMP1, F ; Change 0s to 1s and 1s to 0s

Multiple-bit Manipulation
andlw B’00000111’ ; Force uppar 5 bits of W to zero
andwf TEMP1, F ; TEMP1 < ̶ TEMP1 AND W
andwf TEMP1, W ; W< ̶ TEMP1 AND W
iorlw B’00000111’ ; Force lower 3 bits of W to one
iorwf TEMP1, F ; TEMP1 < ̶ TEMP1 OR W
xorlw B’00000111’ ; Complement lower 3 bits of W
xorwf TEMP1, W ; W< ̶ TEMP1 XOR W

Addition/ Subtraction
addlw 5 ; Add 5 to W
addwf TEMP1, F ; TEMP1< ̶ TEMP1+W
sublw 5 ; W< ̶ 5-W (not W < ̶ W-5)
subwf TEMP1, F ; TEMP1 < ̶ TEMP1 – W

Rotate
rlf TEMP1, F ;Nine-bit left rotate through C
; (C < ̶ TEMP1, 7; TEMP1, i+1 < ̶ TEMP1, i
; TEMP1, 0 < ̶ C)
rrf TEMP1, W ; Leave TEMP1 unchanged
; Copy to W and rotate W right through C
Conditional branch
btfsc TEMP1, 0 ; Skip the next instruction if bit 0 of
; TEMP1 equals zero
btfss STATUS, C ; Skip if C=1
decfsz TEMP1, F ; Decrement TEMP1; skip if zero
incfsz TEMP1, W ; Leave TEMP1 unchanged; skip if
; TEMP1 = H’FF’; W < ̶ TEMP1 + 1

Goto/call/return/return from interrupt

goto There ; Next instruction to be executed is

Instruction Set & Assembly Language 4

 ; labeled “There”
call Task1 ; Push return address; next instruction
; to be executed is labeled “Task1”
return ; Pop return address off of stack
retlw 5 ; Pop return address; W< ̶ 5
retfile ; Pop return address; re-enable interrupts

Miscellaneous
clrwdt ; If watchdog timer is enabled, this
; Instruction will reset it (before it resets the CPU)
Sleep ; Stop clock; reduce power; wait for watchdog timer or
; signal to begin program execution again
Nop ; Do nothing; wait one clock cycle

Simple Operation

Either-Or sequence

Assume that an instruction that affects the Z bit has just been executed. Then depending on the result, one
instruction sequence or another is to be executed, continuing on after either case.

btfsc STATUS, Z ; test Z bit, skip if clear

goto Zset
Zclear
. ; Instructions to execute
. ; if Z = 0
.
Goto Zdone
Zset
. ; Instructions to execute
. ; if Z = 1
.
Zdone ; Carry on

Decrement a 16-bit counter

Assume that the upper byte of the counter is called COUNTH and the lower byte is called COUNTL
movf COUNTL, F ; Set Z if lower byte = 0
btfsc STATUS, Z ; If so, decrement COUNTH
decf COUNTH, F
decf COUNTL, F ; In either case decrement COUNTL

Note how the movf instruction is first used to test COUNTL for zero without changing it, and even without
having to move it into W.

Test a 16-bit variable for zero

Using the same COUNTH, COUNTL variable as previously, the following sequence will either branch to an
instruction labeled BothZero if the variable equals zero or to an instruction labeled CarryOn otherwise.

movf COUNTL, F ; Set Z if lower byte = 0

btfsc STATUS, Z ; if not, then done testing
movf COUNTH, F ; Set Z if upper byte = 0

Instruction Set & Assembly Language 5

 btfsc STATUS, Z ; if not, then done
goto BothZero ; Branch if 16-bit variable = 0
Carryon

Note that the same scheme will work for a variable of any size.
These examples illustrate some of the tediousness of working with this “bare-bones” instruction set. However, it
is important to notice three things:

1. Because of pipelining and because the chip can execute five cycles every microsecond (when used with a 20-
MHz crystal), these sequences are executed quickly. For example, the 16-bit decrement sequence requires four
cycles and therefore takes only 0.8 micro-second to execute (whether or not the branch is taken).

2. Because the instruction set can operate directly on RAM variables, many operations avoid the “overhead”
associated with other microcontrollers wherein operands in memory must be first loaded into an accumulator,
then operated on, and then restored to memory.

3. Microchip Technology’s (free) assembler is a macro assembler. Consequently, sequences such as these can
be prepared once and for all as macros. Therefore any such code sequence looks like a newly defined
instruction. Furthermore, the assembler accepts include files. This means any number of macro definitions can
be put into one or more files and then have the assembler access these files as it assembles the file containing
our application code. Any macros that are used will generate object code, the code that is loaded into PIC for
execution. Unused macros generate no object code. Even macro files of complex operations can be included,
such as signed and unsigned multiply and divide routines for numbers of various lengths up to 32 bits long,
available over the internet from Microchip Technology. In fact, Microchip supports user of its various
microcontrollers with free books, application examples, assembler and simulator software, as well as macro files
over the internet.

Instruction Set & Assembly Language 6