Chapter 2 (A)

Microcontroller Architecture
The PIC microcontroller was developed by General Instruments in 1975. PIC was developed
when Microelectronics Division of General Instruments was testing its 16-bit CPU CP1600.
Although the CP1600 was a good CPU but it had low I/O performance. The PIC controller
was used to offload the I/O the tasks from CPU to improve the overall performance of the
system.

In 1985, General Instruments converted their Microelectronics Division to Microchip

Technology. PIC stands for Peripheral Interface Controller. The General Instruments used
the acronyms Programmable Interface Controller and Programmable Intelligent Computer
for the initial PICs (PIC1640 and PIC1650).

In 1993, Microchip Technology launched the 8-bit PIC16C84 with EEPROM which could be
programmed using serial programming method. The improved version of PIC16C84 with
flash memory (PIC18F84 and PIC18F84A) hit the market in 1998.

PIC16C57 GENERAL DESCRIPTION

The PIC16C57 is an EEPROM/ROM based 8-bit CMOS Microcontroller. It contains a
Reduced Instruction Set Computer (RISC) based Central Processing Unit (CPU) with only
33 single word instructions. All instructions are fetched and executed within a single cycle
except for program branches which take up 2 cycles. The maximum operating frequency is
40MHz.

ARCHITECTURAL OVERVIEW
The PIC16C5X microcontroller uses a 2 stage pipelined Harvard architecture in which
program and data are accessed using independent buses. This architecture enables
instructions to be fetched in one cycle. While program memory is being accessed, data
memory is on an independent bus and can be read and written. This improves bandwidth
over the traditional von Neumann architecture where program and data are fetched on the
same bus. The von Nuemann architecture requires more accesses across the bus to fetch
the instruction and the data will then need to be operated on and possibly written back. This
makes the bus extremely conjested. With the Harvard architecture, instruction opcodes are
12 bits wide while data word is 8-bits wide. With the addition of the pipeline stages, the fetch
and execution cycle are allowed to overlap.

The microcontroller contains an 8-bit Arithmetic Logic Unit (ALU) and working register. This
device is an accumulator-based architecture whereby one of the operands is implicitly in the
accumulator (also called the working register, W). The ALU performs arithmetic and boolean
functions between the data in the working (W) register and any register file. The W register is
an 8-bit working register used for ALU operations and is not an addressable register. Figure
1 shows the block diagram of the PIC16C57.

The clock for the system is obtained from an external memory component called an
“oscillator”. The clock enters the microcontroller and will be then divided into four non-
overlapping clocks which make up one instruction cycle, during which one instruction is
executed. With the pipeline stages, the execution of instructions start by calling an
instruction that is next in line. Fetching, decoding and execution of this instruction will then
be done during the next instruction cycle. Figure 2 shows the Clock/Instruction cycle for the
microcontroller.

Microcontroller Architecture 1
 FIGURE 1. PIC16C57 architecture block diagram.

FIGURE 2. Clock/Instruction cycle.

Microcontroller Architecture 2
From Figure 2, the instruction cycle consists of cycle Q1, Q2, Q3 and Q4. Through
pipelining, each instruction is effectively executed in one cycle. In the case when an
instruction modifies the Program Counter (PC) and makes it point to some other address,
two cycles are needed for execution of an instruction. This is because the instruction must
be processed again and from the right address. The Instruction Register (IR) is written
during the Q1 clock while the decoding and execution starts with Q2, Q3 and Q4 clocks.

Pipeline Flow
In a normal unpipelined architecture, each instruction takes a certain number of clock
periods to finish before the next instruction is fetched and executed. Any one component of
the processor is only used during one of the clock periods which means that it does nothing
else during the other clock periods. To make use of the other clock periods, pipelining is
introduced.

Pipelining is an implementation technique where multiple instructions are overlapped in

execution. It is like a an assembly line where different steps are completing different parts of
different instructions in parallel. The instructions enter at one end, progress through the
pipeline stages and exits out at the other end. Pipelining is implemented by adding a register
between each stage of the instruction cycle. For the PIC16C57, there are 2 pipeline stages.

The following figure (Figure 3) is an example illustrating the principle of pipelining. It shows
the instruction cycle (datapath) as it progresses through the pipeline.

FIGURE 3. Instruction pipeline flow

In Figure 3 above, TCY0 reads in instruction MOVLW 55h. TCY1 is when instruction
MOVLW 55h is being executed while the next instruction MOVWF PORT B is being read.
TCY2 executes MOVWF PORT B and reads in CALL SUB_1. TCY3 executes a call to
subprogram CALL SUB_1 and reads in the instruction BSF PORT A, BIT3. Since the PC has
been modified to point to the address determined by the call to subprogram, the BSF PORT
A, BIT 3 instruction which has already been fetched must be flushed from the pipeline while
the new instruction must be fetched and then executed.

The performance of a pipelined architecture can be summed up in the following equation:

Computer Operation Codes (Opcode)

The first step of a design of a microcontroller is to determine the type of operations it has to
perform. The operation code is part of the instruction set and essentially encodes all the
functions of the microcontroller, thus providing a unique code for each necessary operation.
Figure 5 shows the instruction set (opcodes + operands) and the operations that the
PIC16C57 can perform.

Microcontroller Architecture 3
Central Processing Unit (CPU)
The CPU is the brain of the microcontroller which is responsible for locating and fetching the
correct instruction, decoding it and executing it. This unit connects all parts of the
microcontroller through an 8-bit data bus and a 5-bit address bus and determines the
transfer of data from one location to another within the microcontroller via the controller. The
main components of the CPU are the Program Counter (PC), the Instruction Register (IR) ,
the Register File and the Arithmetic Logic Unit (ALU).

Program Counter (PC)

The program counter is a register that holds the address of the next instruction to fetch from
the program memory and is updated by one at every instruction cycle, unless an instruction
changes the PC. The processor then fetches the instruction from the memory location
pointed to by the PC, places it in the Instruction Register (IR) and then increments itself. The

Microcontroller Architecture 4
PIC16C57 has an 11-bit PC used to access the 2048 x 12 program memory. Figure 6 shows
a simple PC implementation.

FIGURE 6. Program counter example

Microcontroller Architecture 5
Instruction Register (IR)
The currently executing instruction is stored temporarily in the instruction register. The
processor interprets the contents of the IR via the instruction decoder and determines the
type of operation to be executed depending on the instruction set. Figure 7 shows the
contents of the IR if a byte-oriented instruction is loaded.

FIGURE 7. Instruction Register.

ALU
The Arithmetic Logic Unit (ALU) is the ‘core’ of any processor which performs the
calculations (arithmetic, boolean and shifts) on the operands. The ALU is basically a number
crunching mechanism which computes the results based on the control signals provided to it
by the opcode part of the instruction set. The opcode is used to select between the
arithmetic, boolean or shift operations. Figure 8 shows the block diagram of the ALU.
Depending on the type of operation performed by the ALU, the status register will be
affected.

FIGURE 8. Block diagram of ALU.

Register File
Highest level of the memory hierarchy which is determined by the data memory. The data
memory is actually divided into 2: Special Function Registers (SPRs) and General Purpose
Registers (GPRs). In the case of the PIC16C57, there are 8 SPRs and 24 GPRs which are
8-bits wide. SPRs are registers used by the CPU and peripheral functions to control the
operation of the device. The Register File for the PIC16C57 is a single port memory device

Microcontroller Architecture 6
which is implemented using Static Random Access Memory (SRAM) technology. Figure 9
shows the register file block diagram for the PIC16C57.

I/O Ports
Ports refer to a group of pins on a microcontroller
which can be accessed simultaneously, or on which
we set the desired combination of zeros and ones,
or read from them an existing status. They represent
the connection of the CPU and the outside world.
The ports are basically I/O registers which can be
read and written under program control. There are
16 fully programmable I/O’s on the PC16C57 which
can be used interchangeably for both input and
output. Figure 10 shows the equivalent circuit for a
single I/O pin. The Output Driver Control Registers
are loaded with the contents of the W register by
executing the TRIS f instruction. A ‘1’ from a TRIS
register bit puts the corresponding output driver in a
hi-impedance state (input mode). A ‘0’ puts the
contents of the output data latch on the selected
pins, enabling the output buffer.
FIGURE 9. Register file block diagram

Memory organization
The microcontroller is divided into program memory
and data memory. The PIC16C57 has 2K x 12
program memory space and is accessed using a
paging scheme. The program memory pages are
accessed using one or two STATUS register bits.
Figure 11 shows the program memory map or the
microcontroller. The data memory consists of 32
registers (8 SPRs and 24 GPRs).

FIGURE 10. I/O pin

FIGURE 11. Program memory

map

Microcontroller Architecture 7
Instruction set summary
Each instruction is 12-bits, which specifies the instruction type and one or more operands
which further specifies the operation of the instruction. The instructions are grouped into
byte-oriented, bit-oriented, and literal and control operations. For the PIC16C57, a 2 operand
format is adopted, where one operand is both the source and the destination of the result.

For byte-oriented instructions, ‘f’ represents a file register and ‘d’ represents a destination
register. The file register designator is used to specify which one of the 32 file registers is to
be used by the instruction. The destination designator specifies where the result of the
operation is to be placed. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is 1, the result
is placed in a file register specified in the instruction. Figure 5 shows the general format for a
byte oriented instruction.

FIGURE 12. Byte-oriented file register operations

For bit-oriented instructions, ‘b’ represents a bit field designator which selects the number of
the bit affected by the operation, while ‘f’ represents the number of the file in which the bit is
located. Figure 6 shows the general format for a bit-oriented instruction.

FIGURE 13. Bit-oriented file register operations

For literal and control operations, ‘k’ represents an 8 or 9-bit constant or literal value. Figure
7 shows the general format for literal and control instructions.

FIGURE 14. Literal and control operations

Instruction Examples
Consider the instruction to add the contents of the W register with the contents of the ‘f’
register. If ‘d’ = ‘0’, then the result will be stored in the W register. If ‘d’=’1’, then the results
will be stored back in the register designated by ‘f’.

Microcontroller Architecture 8
1) ADDWF f, d
Operation: (W) + (f) --> (dest)
Encoding: 0001 11df ffff
Example: ADDWF TEMP_REG, 0
Before instruction: W = 0x17 h
TEMP_REG = 0xC2 h
After instruction: W = 0xD9 h
TEMP_REG = 0xC2 h

In example 2 below, the contents of the W register are AND’ed with the eight-bit literal ‘k’.
The result is then placed in the W register.

2) ANDLW k
Operation: (W).AND.(k) --> (W)
Encoding: 1110 kkkk kkkk
Example: ANDLW H’ 5F’
Before instruction: W = 0xA3 h
After instruction: W = 0x03 h

In example 3 below, the contents of the W register are AND’ed with register ‘f’. If ‘d’ = ‘0’, the
result is stored in the W register. If ‘d’ = ‘1’, the result is stored back in register ‘f’.

3) ANDWF f,d
Operation: (W) .AND. (f) --> (dest)
Encoding: 0001 01df ffff
Example: ANDWF TEMP_REG, 1
Before instruction: W = 0x17 h
TEMP_REG = 0xC2 h
After instruction: W = 0x17 h
TEMP_REG = 0x02 h

In example 4 below, bit location designated by ‘b’ is set in register ‘f’.

4) BSF f,b
Operation: 1 --> (f<b>)
Encoding: 0101 bbbf ffff
Example: BSF FLAG_REG, 7
Before instruction: FLAG_REG = 0x0A h
After instruction: FLAG_REG = 0x8A h

In example 5 below, TRIS register ‘f’ (f=5,6 or 7) is loaded with the contents of the W
register.

5) TRIS f
Operation: (W) --> TRIS register f
Encoding: 0000 0000 0fff
Example: TRIS PORTB
Before instruction: W = 0xA5 h
After instruction: TRISB = 0xA5 h

Microcontroller Architecture 9