Chapter 2 (B)

Microcontroller Architecture
Low-end Architectures
Microchip PIC microcontrollers are available in various types. When PIC − Micro_MCU first
became available from General Instruments in early 1980’s, the microcontroller consisted of
a very simple processor executing 12-bit wide instructions with basic I/O functions. These
devices are known as low-end architectures. Previously discussed PIC16C5X is based on
low-end architecture.

Mid-range Architectures
Mid-range Architectures are built by upgrading low-end architecture with more number of
peripherals, more numbers of register and more data memory. Some of the mid-range
devices are
16C6X
16C7X, 16F87X
Program memory type
C = EPROM
F = Flash
RC = Mask ROM

Popularity of PIC microcontrollers is due to the following factors-

1. Speed: Harvard Architecture, RISC Architecture
1 instruction Cycle = 4 clock cycles.
For 20 MHz clock, most of the instructions are executed in 0.2μs or five instructions
per microsecond.
2. Instruction Set Simplicity:
Just 35 instructions (as opposed to 111 instructions for 8051)
3. Power on reset
Power-out reset
Watch-dog timer
Oscillator Options
• low-power Crystal
• Mid-range Crystal
• High-range Crystal
• RC Oscillator
4. Programmable timer options and on chip ADC
5. Up to 12 independent interrupt sources
6. Powerful output pin control
25mA (max.) current sourcing capability.
7. EPROM/OTP (One Time Programmable)/ROM/Flash memory options.
8. Free assembler and simulator support from microchip corp.

Microcontroller Architecture 1
 Fig: CPU Architecture and Instruction Set

Program
Memory

Fig: Basic Architecture of PIC Microcontroller

ALU Size is 8 bit and performs operations with temporary working register and (W register) and any
register file.

W register is 8 bit wide. It contains one of source operands during execution of instruction and may
serve as the destination for the result of operation. It is used only for ALU operations.

Microcontroller Architecture 2
Program Memory
CALL, RETURN
RETFIE, RETLW
 Up to 8K words (13 bit PC, 213=8K)
 Each word is 14 bits
 Each instruction is exactly 1 word long.
 General program structure – two special
addresses: Reset vector address (0000h) and
Interrupt vector address (0004h)
 8 level deep hardware stack for PC (program
counter)

The PIC 16C7X family has a 13-bit program counter

capable of addressing 8k×14 program memory.
PIC16C74A has 4k×14 program memory. For those
devices with less than 8k program memory, accessing
a location above the physically implemented address
will cause a wraparound.

Register File Structure and Addressing Modes

Register file → locations that an instruction can access via an address.
Register file consists of two components.
1. General purpose register file (same as RAM)
2. Special purpose register file

Register File also known as Data memory and consists of

Special Function Registers (SFR) area
General Purpose Registers (GPR) area

Microcontroller Architecture 3
  SFRs control the operation of the device 00 INDF INDF 80
 GPRs are area for data storage and 01 TMR0 OPTION 81
scratch pad operations 02 PCL PCL 82
 GPRs are at higher address than SFRs 03 STATUS STATUS 83
in a bank 04 FSR FSR 84
 Different PIC microcontrollers may have 05 PORTA TRIXA 85
different number of GPRs 06 PORTB TRIXB 86
07 PORTC TRIXC 87
08 PORTD TRIXD 88
Data memory is partitioned into banks 09 PORTE TRIXE 89
 Each bank extends up to 7Fh (128) bytes 0A PCLATCH PCLATCH 8A
 0B INTCON INTCON 8B
 4 banks : 4*128 bytes = 512 bytes 0C PIR1 PIE1 8C
 2 banks : 2*128 bytes = 256 bytes 0D PIR2 PIE2 8D
 Lower locations of each bank are 0E TMR1L PCON 8E
reserved for SFRs. Above the SFRs are 0F TMR1H . 8F
GPRs. 10 T1CON . 90
 Implemented as Static RAM 11 TMR2 . 91
 Some “high use” SFRs from bank0 are 12 T2CON PR2 92
mirrored in the other banks (e.g., INDF,
13 SSPBUF SSPADD 93
PCL, STATUS, FSR, PCLATH, INTCON)
14 SSPCON SSPSTAT 94
 RP0 and RP1 bits in the STATUS
register selects the bank when using 15 CCPR1L . 95
direct addressing mode. 16 CCPR1H . 96
17 CCP1CON . 97
18 RCSTA TXSTA 98
What are the Memory banks for? 19 TXREG SPBRG 99
 14-bit instructions use 7 bits to address a 1A RCCREG . 9A
location 1B CCPR2L . 9B
 Memory space is organized in 128 Byte/ 1C CCPR2H . 9C
bank. PIC 16F684 has two banks - Bank 1D CCP2CON . 9D
0 and Bank 1. 1E ADRES . 9E
 Bank 1 is used to control the actual 1F ADCON0 ADCON1 9F
operation of the PIC for example to tell 20 A0
the PIC which bits of Port A are input and GPR/RAM
which are output.
GPR/RAM BF
 Bank 0 is used to manipulate the data.
An example is as follows: Let us say we
want to make one bit on Port A high. 7F
First we need to go to Bank 1 to set the
BANK -0 BANK -1
particular bit, or pin, on Port A as an
output. We then come back to Bank 0
Fig: Register File Map (all addresses in HEX)
and send a logic 1 (bit 1) to that pin.

Microcontroller Architecture 4
Special Function Registers
STATUS (03h, 83h, 103h, 183h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-X R/W-X R/W-X

IRP RP1 RP0 TO PD Z DC C

bit 7 bit 0

IRP (Indirect Register Pointer): Register bank select bit (indirect addressing)
RP1, RP0 (Register Pointer): Register bank select bits (direct addressing)
NOT_TO= Reset status bit (Time Out bit)
NOT_PD= Reset status bit (Power Down)
These bits are used along with SLEEP mode. After coming out from SLEEP processor checks
these bits to determine which kind of event is responsible for bringing out of SLEEP mode.
Z: Zero bit: if arithmetic or logical operation results in ZERO
DC: Digital Carry bit similar to Auxiliary Carry AC in 8051/8085; if operation on lower 4 bits results in
carry.
C: Carry bit: if arithmetic operation results in some carry.

bit 7: IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes

bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred

bit 3: PD: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/ borrow bit (ADDWF, ADDLW,SUBLW,SUBWF) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complem ent of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

FSR /File Select Register: (04h, 84h, 104h, 184h)

 Indirect data memory addressing pointer

INDF/ Indirect thro FSR: (00h, 80h, 100h, 180h)

 INDF is used in instruction.
 INDF is not a physical register. Accessing INDF access is the location pointed to by FSR in
indirect addressing mode.

Microcontroller Architecture 5
  Accessing INDF accesses the location pointed by IRP+FSR in controllers where they use 9
bit address scheme, FSR otherwise.

PCL / Program Counter Low Byte: (02h, 82h, 102h, 182h)

 PCL is actually the lower 8-bits of the 13-bit program counter. This is a both readable and
writable register.

PCLATH/ Program Counter Latch: (0Ah, 8Ah, 10Ah, 18Ah)

4 0
Transferred to PC when
0 0 0 PCL is written to

12 8 7 0

PCL (02h, 82h, 102h, 182h)

 PCLATH is a 8-bit register which can be used to decide the upper 5bits of the program
counter. PCLATH is not the upper 5bits of the program counter. PCLATH can be read from or written
to without affecting the program counter. The upper 3bits of PCLATH remain zero and they serve no
purpose. When PCL is written to, the lower 5bits of PCLATH are automatically loaded to the upper
5bits of the program counter, as shown in the figure.

Input / Output Port

The PORTx (x=A,B,C,D,E): register is the latch for the data to be output. Reading PORTx register
read the status of the pins, whereas writing to it will write to the port latch.

For most ports, the I/O pin’s direction (input or output) is controlled by the data direction register
TRISx (x=A,B,C,D,E): a ‘1’ in the TRIS bit corresponds to that pin being an input, while a ‘0’
corresponds to that pin being an output

Direct and Indirect Addressing

Direct Addressing Accessed Direct Indirect

 Use only 7 bits of instruction to identify a Bank (RP1:RP0) (IRP)
register file address
0 0 0
 The other two bits of register address come 0
from RP0 and RP1 bits in the STATUS register 1 0 1
2 1 0
Indirect Addressing 1
3 1 1
 The INDF register is not a physical register.
Addressing the INDF register will cause indirect addressing.
 Any instructions using the INDF register actually access the register pointed to by the File
Select Register (FSR).
 The effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit
in STATUS register.
For indirect addressing example please go to:
http://www.pictutorials.com/Indirect_Addressing_Exam.htm

Microcontroller Architecture 6