JAYPEE UNIVERSITY OF INFORMATION TECHNOLOGY, WAKNAGHAT END-TERM EXAMINATION (DECEMBER 2013) B.Tech (5 Semester) Course Code: 10B11C1613, Max. Marks: 45 Course Name: Computer Organization & Architecture Max. Time: 3 Hrs Course Credits: 3 NOTE: Please write point to point. Deviation from most correct answer won't fetch any marks, Where required include correct diagrams in your answer. All questions are compulsory 1. (@) Give the formulas for calculating CPI, MIPS, MFLOPS rate, and time to execute a program. {2 Marks} (b) With the help ofa flowchart explain the cache read operation in brie. [2 Marks} 2. (a) What are the different methods to identify a device in an interrupt driven system? Explain the difference between dsisy chain and bus arbitration methods of device identification in an interrupt driven system. (1+1 Marks} (b) A system is based on an 8-bit microprocessor and has two 1/0 devices, The /]O controllers for this system use Separate control and status registers. Both devices handle data on a I-byte-at-atime basis. The fist device has (wo stats lines and three control ines. The second device has three statu lines and four contol lines, [-+1+1 Marks] a. How many 8-bit I/O control module registers do we need fr status reading and contol of each device? b. What is the total number of needed control module registers given that the first device is an output-only device? c. How many distinet addresses are needed to control the two devices? (©) What drawbacks of programmed and interrupt driven VO lead tothe development of DMA technique? [1 Marks] 3. (@) What is the purpose of swapping in a virtual memory system? Which techniques are most commonly used to implement swapping? [1+2 Marks} (6) What isa Translation Lookaside Buffer (TB)? Explain the sequence of operations for a memory reference (using & flowchart or algorithm) in atypical TLB system combined with paging. (142 Marks] \ (©) Suppose the page table forthe process currently executing on the processor looks like the following. All numbers are decimal, everything is numbered starting from zero, and all addresses are memory byte addresses. The page size is 1024 bytes. [142 Marks} ‘Viral Page Number [ Vaid Bit — [Reference Bi Mio — 0 i 0 — I 1 1 2 o 0 i H oO” a <__ 0 oT x i Lo a. Describe exactly how, in general, a virtual address generated By the CPU is Wanslated into physical main memory address b. What physical address, if any, would each of the following virtual addresses correspond to? (Do not try to handle any page faults, ifany.) i. 1082 i, 2224 iii, 5499 4. (@ Explain briefly the fundamental issues of consideration in an instruction set design? [3 Marks} (©) What do you understand by endianness of an architecture? Differentiate between litle and big endian machines with an example. Write a C language to find endianness of a computer, (1#1+1 Marks} S. (@) What do you understand by an instruction format? List the key characteristics ofan instruction format. [2 Marks} (b) What facts go into determining the use of the addressing bits ofan instruction? [2 Marks} 6. (2) What is instruction pipeline hazard? With an example, explain briefly the methods employed to deal with various pipeline hazards. [1+3 Marks) (©) How does branch prediction improve instruction pipelining efficiency? What are the different techniques employed for the same? With suitable illustrations explain Taken not taken strategy in detail. (+142 Marks} 7. (@) Briefly explain the key observations done while studying the dynamic behavior of high level language programs (operations, operands, and procedure calls) that led to the development of RISC. [2 Marks} (b) What is compiler-based register optimization in RISC? With the help of suitable example explain the graph coloring based approach to compiler-based register optimization, (142 Marks} (6) Discuss in brief the optimization techniques employed in a RISC instruction pipeline. [3 Marks] saeneenaneanepNDtteseeanenens