Semiconductor

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T E P
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ROD ACEMEN 47
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REP 00-442-7
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CA3060
OBS ENDED - 8
M ns 1 .com 110kHz, Operational
R E COM pplicatio @harris
January 1999 NO ntral A entapp Transconductance Amplifier Array
Ce : c
Call or email

Features Description
• Low Power Consumption as Low as 100mW Per The CA3060 monolithic integrated circuit consists of an array of
Amplifier three independent Operational Transconductance Amplifiers
[ /Title (see Note). This type of amplifier has the generic characteris-
• Independent Biasing for Each Amplifier
tics of an operational voltage amplifier with the exception that
(CA30 • High Forward Transconductance the forward gain characteristic is best described by transcon-
60) ductance rather than voltage gain (open-loop voltage gain is the
• Programmable Range of Input Characteristics
/Sub- product of the transconductance and the load resistance,
ject • Low Input Bias and Input Offset Current gMRL). When operated into a suitable load resistor and with
provisions for feedback, these amplifiers are well suited for a
(110k • High Input and Output Impedance wide variety of operational-amplifier and related applications. In
Hz, • No Effect on Device Under Output Short-Circuit addition, the extremely high output impedance makes these
Opera- Conditions types particularly well suited for service in active filters.
tional • Zener Diode Bias Regulator The three amplifiers in the CA3060 are identical push-pull
Transc Class A types which can be independently biased to achieve a
onduc- wide range of characteristics for specific application. The elec-
Applications trical characteristics of each amplifier are a function of the
tance • For Low Power Conventional Operational Amplifier amplifier bias current (IABC). This feature offers the system
Ampli- Applications designer maximum flexibility with regard to output current capa-
fier bility, power consumption, slew rate, input resistance, input bias
• Active Filters current, and input offset current. The linear variation of the
Array) parameters with respect to bias and the ability to maintain a
• Comparators
/Autho constant DC level between input and output of each amplifier
r () • Gyrators also makes the CA3060 suitable for a variety of nonlinear appli-
/Key- • Mixers cations such as mixers, multipliers, and modulators.
words • Modulators In addition, the CA3060 incorporates a unique Zener diode
(Har- regulator system that permits current regulation below sup-
• Multiplexers ply voltages normally associated with such systems.
ris
• Multipliers
Semi- NOTE: Generic applications of the OTA are described in AN-6668.
con- • Strobing and Gating Functions For improved input operating ranges, refer to CA3080 and CA3280
data sheets (File Nos. 475 and 1174) and application notes AN6668
ductor, • Sample and Hold Functions and AN6818.
triple,
transco
nduc-
Pinout Part Number Information
CA3060
tance (PDIP) TEMP. PKG.
ampli- TOP VIEW PART NUMBER RANGE (oC) PACKAGE NO.

fier, CA3060E -40 to 85 16 Ld PDIP E16.3

REGULATOR OUT 1 16 OUTPUT NO. 1
low BIAS
REG.
power REGULATOR IN 2 15 BIAS NO. 1

op 3 AMP 1 14 NON-INV. INPUT NO. 1

+

V+

amp, INV. INPUT NO. 3 4 13 INV. INPUT NO. 1

NON-INV. INPUT NO. 3 5 12 INV. INPUT NO. 2

+

AMP
+

BIAS NO. 3 6 3 11 NON-INV. INPUT NO. 2

AMP
OUTPUT NO. 3 7 2 10 BIAS NO. 2

V- 8 9 OUTPUT NO. 2

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number 537.4
Copyright © Harris Corporation 1999
3-1
 CA3060

Absolute Maximum Ratings Operating Conditions

Supply Voltage (Between V+ and V- Terminals) . . . . . . . 36V (±18V) Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to V-
Differential Input Voltage (Each Amplifier) . . . . . . . . . . . . . . . . . . 5V Thermal Information
Input Current (Each Amplifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1mA
Amplifier Bias Current (Each Amplifier) . . . . . . . . . . . . . . . . . . . 2mA Thermal Resistance (Typical, Note 2) θJA (oC/W)
Bias Regulator Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Output Short Circuit Duration (Note 1) . . . . . . . . . . . . . . . . Indefinite Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications TA = 25oC, VSUPPLY = ±15V

AMPLIFIER BIAS CURRENT

IABC = 1µA IABC = 10µA IABC = 100µA
PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Input Offset Voltage VIO - 1 - - 1 - - 1 5 mV
(See Figure 1)
Input Offset Current IIO - 3 - - 30 - - 250 1000 nA
(See Figure 2)
Input Bias Current IIB - 33 - - 300 - - 2500 5000 nA
(See Figures 3, 4)
Peak Output Current IOM - 2.3 - - 26 - 150 240 - µA
(See Figures 5, 6)
Peak Output Voltage
(See Figure 7)
Positive VOM+ - 13.6 - - 13.6 - 12 13.6 - V
Negative VOM- - 14.7 - - 14.7 - 12 14.7 - V
Amplifier Supply Current (Each IA - 8.5 - - 85 - - 850 1200 µA
Amplifier)
(See Figures 8, 9)
Power Consumption P - 0.26 - - 2.6 - - 26 36 mW
(Each Amplifier)
Input Offset Voltage Sensitivity
(Note 3)
Positive ∆VIO/∆V+ - 1.5 - - 2 - - 2 150 µV/V
Negative ∆VIO/∆V- - 20 - - 20 - - 30 150 µV/V
Amplifier Bias Voltage VABC - 0.54 - - 0.60 - - 0.66 - V
(Note 4, See Figure 10)
DYNAMIC CHARACTERISTICS At 1kHz, Unless Otherwise Specified
Forward Transconductance g21 - 1.55 - - 18 - 30 102 - mS
(Large Signal)
(See Figures 11, 12)
Common Mode Rejection CMRR - 110 - - 110 - 70 90 - dB
Ratio
Common Mode Input Voltage VICR +12 to +13 to - +12 to +13 to - +12 to +13 to - V
Range -12 -14 -12 -14 -12 -14
Slew Rate (Test Circuit) SR - 0.1 - - 1 - - 8 - V/µs
(See Figure 17)
Open Loop (g21) Bandwidth BWOL - 20 - - 45 - - 110 - kHz
(See Figure 13)

3-2
 CA3060

Electrical Specifications TA = 25oC, VSUPPLY = ±15V (Continued)

AMPLIFIER BIAS CURRENT

IABC = 1µA IABC = 10µA IABC = 100µA
PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Input Impedance Components
Resistance (See Figure 14) RI - 1600 - - 170 - 10 20 - kΩ
Capacitance at 1MHz CI - 2.7 - - 2.7 - - 2.7 - pF
Output Impedance Components
Resistance (See Figure 15) RO - 200 - - 20 - - 2 - MΩ
Capacitance at 1MHz CO - 4.5 - - 4.5 - - 4.5 - pF
ZENER BIAS REGULATOR CHARACTERISTICS I2 = 0.1mA
Voltage (See Figure 16) VZ Temperature 6.2 6.7 7.9 V
Coefficient = 3mV/oC
Impedance ZZ - 200 300 Ω
NOTES:
3. Conditions for Input Offset Voltage Sensitivity:
a. Bias current derived from the regulator with an appropriate resistor connected from Terminal 1 to the bias terminal on the amplifier
under test V+ is reduced to +13V for V+ sensitivity and V- is reduced to -13V for V- sensitivity.

VO ffset – VO ffset for +13V and -15V Supplies

b. V+ Sensitivity in µV ⁄ V = ------------------------------------------------------------------------------------------------------------------------------ ,
1V

VO ffset – VO ffset for -13V and +15V Supplies

V- Sensitivity in µV ⁄ V = ------------------------------------------------------------------------------------------------------------------------------.
1V

4. Temperature Coefficient; -2.2mV/oC (at VABC = 0.54, IABC = 1µA); -2.1mV/oC (at VABC = 0.060V, IABC = 10µA); -1.9mV/oC (at VABC = 0.66V,
IABC = 100µA)

Schematic Diagram
BIAS REGULATOR AND ONE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

ZENER BIAS REGULATOR

D4
2 3 V+
D2
Q10 Q4 Q5

1 Q6 Q7
D5

INVERTING INPUT -
Q1 Q2 OUTPUT (NOTE 8)
(NOTE 5)

NON-INVERTING INPUT + Q8
(NOTE 6) IABC
AMPLIFIER BIAS INPUT D3
Q3
(NOTE 7)
D1
8 V-

NOTES:
5. Inverting Input of Amplifiers 1, 2 and 3 is on Terminals 13, 12 and 4, respectively.
6. Non-inverting Input of Amplifiers 1, 2 and 3 is Terminals 14, 11 and 5, respectively.
7. Amplifier Bias Current of Amplifiers 1, 2 and 3 is on Terminals 15, 10 and 6, respectively.
8. Output of Amplifiers 1, 2 and 3 is on Terminals 16, 9 and 7, respectively.

3-3
 CA3060

Typical Performance Curves

2.0 1000
SUPPLY VOLTAGE: MAXIMUM
VS = ±6
VS = ±15
INPUT OFFSET VOLTAGE (mV)

INPUT OFFSET CURRENT (nA)

1.5
100
TYPICAL
125oC
1.0
25oC

-55oC TA = 25oC
10
SUPPLY VOLTAGE:
0.5 VS = ±6
VS = ±15

0.0 1
1 10 100 1000 1 10 100 1000
AMPLIFIER BIAS CURRENT (µA) AMPLIFIER BIAS CURRENT (µA)

FIGURE 1. INPUT OFFSET VOLTAGE vs AMPLIFIER BIAS FIGURE 2. INPUT OFFSET CURRENT vs AMPLIFIER BIAS
CURRENT CURRENT

10 10
SUPPLY VOLTAGE: VS = ±6
MAXIMUM VS = ±15
INPUT BIAS CURRENT (µA)

INPUT BIAS CURRENT (µA)

TYPICAL IABC = 100µA

1 1.0

IABC = 10µA

0.1 TA = 25oC 0.1

SUPPLY VOLTAGE:
VS = ±6
VS = ±15 IABC = 1µA

0.01 0.01
1 10 100 1000 -75 -50 -25 0 25 50 75 100 125
AMPLIFIER BIAS CURRENT (µA) TEMPERATURE (oC)
FIGURE 3. INPUT BIAS CURRENT vs AMPLIFIER BIAS CURRENT FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE

1000 1000
TYPICAL IABC = 100µA
PEAK OUTPUT CURRENT (µA)
PEAK OUTPUT CURRENT (µA)

IABC = 30µA
MINIMUM
100 100
IABC = 10µA

IABC = 3µA
10 TA = 25oC 10
SUPPLY VOLTAGE: IABC = 1µA
VS = ±6
VS = ±15
SUPPLY VOLTAGE: VS = ±6
VS = ±15
1 1
1 10 100 1000 -75 -50 -25 0 25 50 75 100 125
AMPLIFIER BIAS CURRENT (µA) TEMPERATURE (oC)

FIGURE 5. PEAK OUTPUT CURRENT vs AMPLIFIER BIAS FIGURE 6. PEAK OUTPUT CURRENT vs TEMPERATURE
CURRENT

3-4
 CA3060

Typical Performance Curves (Continued)

14 10,000
13 VOM+ (TYP) TA = 25oC
±15V SUPPLY

AMPLIFIER SUPPLY CURRENT (µA)

12 SUPPLY VOLTAGE:
VOM+ (MIN) VS = ±6
PEAK OUTPUT VOLTAGE (V)

6
±15V SUPPLY VS = ±15
5 TYPICAL
4 1000
MAXIMUM
3 VOM+ (TYP)
VOM+ (MIN)
-3 ±6V SUPPLY VOM- (MIN) ±6V SUPPLY
-4 ±6V SUPPLY
-5 100
-6
-12
VOM- (MIN) VOM- (TYP) VOM- (TYP)
-13
±15V SUPPLY ±15V SUPPLY ±6V SUPPLY
-14
-15 10
1 10 100 1000 1 10 100 1000

AMPLIFIER BIAS CURRENT (µA) AMPLIFIER BIAS CURRENT (µA)

FIGURE 7. PEAK OUTPUT VOLTAGE vs AMPLIFIER BIAS FIGURE 8. AMPLIFIER SUPPLY CURRENT (EACH AMPLIFIER)
CURRENT vs AMPLIFIER BIAS CURRENT

1000 800
SUPPLY VOLTAGE: VVS = ±6
IABC = 100µA VS = ±15
AMPLIFIER SUPPLY CURRENT (µA)

AMPLIFIER BIAS VOLTAGE (mV)

750

IABC = 30µA
100 700

IABC = 10µA
650

IABC = 3µA
10 600

IABC = 1µA
550
SUPPLY VOLTAGE: V+ = 6V, V- = -6V
V+ = 15V, V- = -15V
1 500
-75 -50 -25 0 25 50 75 100 125 1 10 100 1000
TEMPERATURE (oC) AMPLIFIER BIAS CURRENT (µA)

FIGURE 9. AMPLIFIER SUPPLY CURRENT (EACH AMPLIFIER) FIGURE 10. AMPLIFIER BIAS VOLTAGE vs AMPLIFIER BIAS
vs TEMPERATURE CURRENT

1000 1000
TA = 25oC, f = 1kHz TA = 25oC, f = 1kHz
FORWARD TRANSCONDUCTANCE (S)

SUPPLY VOLTAGE: VS = ±6 SUPPLY VOLTAGE: VS = ±6

FORWARD TRANSCONDUCTANCE (mS)

VS = ±15 VS = ±15
100
TYPICAL 100 IABC = 100µA

IABC = 30µA
10 MINIMUM
IABC = 10µA
10
1

IABC = 1µA

1
1 10 100 1000 -50 -25 0 25 50 75 100 125
AMPLIFIER BIAS CURRENT (µA) TEMPERATURE (oC)
FIGURE 11. FORWARD TRANSCONDUCTANCE vs AMPLIFIER FIGURE 12. FORWARD TRANSCONDUCTANCE vs
BIAS CURRENT TEMPERATURE

3-5
 CA3060

Typical Performance Curves (Continued)

100 0
IABC = 100µA 10,000
TA = 25oC, f = 1kHz
FORWARD TRANSCONDUCTANCE (mS)

-50

PHASE ANGLE (DEGREES)

SUPPLY VOLTAGE:
10 VS = ±6
-100
IABC = 10µA VS = ±15

INPUT RESISTANCE (kΩ)

IABC = 1µA -150 1000

1.0 -200

-250
100
0.1 TA = 25oC IABC = 10µA -300
SUPPLY VOLTAGE:
VS = ±6 IABC = 1µA -350
TYPICAL
VS = ±15
0.01 MINIMUM
0.001 0.01 0.1 1.0 10 100 10
1 10 100 1000
PHASE ANGLE FREQUENCY (MHz)
FORWARD TRANS. AMPLIFIER BIAS CURRENT (µA)

FIGURE 13. FORWARD TRANSCONDUCTANCE vs FREQUENCY FIGURE 14. INPUT RESISTANCE vs AMPLIFIER BIAS CURRENT

1000 7.0
TA = 25oC, f = 1kHz TA = 25oC
SUPPLY VOLTAGE:
SUPPLY VOLTAGE: BIAS REGULATOR VOLTAGE (V) VS = ±6
VS = ±6
OUTPUT RESISTANCE (MΩ)

VS = ±15 VS = ±15 TYPICAL

100 6.75

10 6.5

TYPICAL

1 6.25
1 10 100 1000 0 200 400 600 800 1000 1200 1400
AMPLIFIER BIAS CURRENT (µA) BIAS REGULATOR CURRENT (µA)

FIGURE 15. OUTPUT RESISTANCE vs AMPLIFIER BIAS CURRENT FIGURE 16. BIAS REGULATOR VOLTAGE vs BIAS
REGULATOR CURRENT

Test Circuit
RF VZ is measured between Terminal 1 and 8
VABC is measured between Terminals 15 and 8
V+
IN- [ ( V+ ) – ( V- ) – 0.7 ] V Z – VA BC
PUT RS - R Z = ------------------------------------------------, R ABC = -----------------------------
3 I2 I ABC
13
OUT- EXTERNAL
PUT LOAD Supply Voltage: For both ±6V and ±15V
RC
AMPLIFIER 16
1
CC 13 TYPICAL SLEW RATE TEST CIRCUIT PARAMETERS
+ 15 10
14 pF MΩ
1 SLEW
8 IABC RATE I2 RABC RS RF RB RC CC
2
RB IABC µA V/µs µA Ω Ω Ω Ω Ω µF

RZ 100 8 200 62K 100K 100K 51K 100 0.02

RABC
10 1 200 620K 1M 1M 510K 1K 0.005
I2
1 0.1 2 6.2M 10M 10M 5.1M ∞ 0
V-

FIGURE 17. SLEW RATE TEST CIRCUIT FOR AMPLIFIER 1 OF CA3060

3-6
 CA3060

Application Information In addition, the high output impedance makes these amplifi-
ers ideal for applications where current summing is involved.
The CA3060 consists of three operational amplifiers similar
The design of a typical operational amplifier circuit (Figure
in form and application to conventional operational amplifiers
19) would proceed as follows:
but sufficiently different from the standard operational
amplifier (op amp) to justify some explanation of their Circuit Requirements
characteristics. The amplifiers incorporated in the CA3060 Closed Loop Voltage Gain = 10 (20dB)
are best described by the term Operational Transconduc- Offset Voltage Adjustable to Zero
tance Amplifier (OTA). The characteristics of an ideal OTA Current Drain as Low as Possible
are similar to those of an ideal op amp except that the OTA Supply Voltage = ±6V
has an extremely high output impedance. Because of this Maximum Input Voltage = ±50mV
inherent characteristics the output signal is best defined in Input Resistance = 20kΩ
terms of current which is proportional to the difference Load Resistance = 20kΩ
between the voltages of the two input terminals. Thus, the Device: CA3060
transfer characteristics is best described in terms of +6V
transconductance rather than voltage gain. Other than the
difference given above, the characteristics tabulated are
0.1
similar to those of any typical op amp. 3 RF
200kΩ
The OTA circuitry incorporated in the CA3060 (Figure 18)
provides the equipment designer with a wider variety of RS
20kΩ
circuit arrangements than does the standard op amp; 13
INPUT -
because as the curves indicate, the user may select the
optimum circuit conditions for a specific application simply by AMPLIFIER 16
varying the bias conditions of each amplifier. If low power +6V 1
consumption, low bias, and low offset current, or high input RL
14 + 20kΩ
impedance are primary design requirements, then low 2.2MΩ 15
ROFFSET
current operating conditions may be selected. On the other <4MΩ
8
hand, if operation into a moderate load impedance is the 18kΩ
primary consideration, then higher levels of bias may be RABC
0.1 560kΩ
used. -6V
-6V TO +6V
V+
Q11 D5 D6 FIGURE 19. 20dB AMPLIFIER USING THE CA3060
Q7 Q15
Calculation
D7
Q10
Q14
1. Required Transconductance g21. Assume that the
Q3 open loop gain AOL must be at least ten times the closed
D8 loop gain. Therefore, the forward transconductance
INVERTING D2
INPUT required is given by:
Q2
- Q5 Q9 Q13 g21 = AOL/RL
D3 = 100/18kΩ
Q4
+ OUTPUT ≅ 5.5mS
AMPLIFIER Q12 (RL = 20kΩ in parallel with 200kΩ ≅ 18kΩ)
BIAS
CURRENT NON- 2. Selection of Suitable Amplifier Bias Current. The ampli-
INVERTING
Q1 INPUT fier bias current is selected from the minimum value curve
(ABC)
D4 of transconductance (Figure 11) to assure that the amplifi-
D1 Q6 Q8
er will provide sufficient gain. For the required g21 of
5.5mS an amplifier bias current IABC of 20µA is suitable.
V- V-
COMPLETE OTA CIRCUIT 3. Determination of Output Swing Capability. For a
closed loop gain of 10 the output swing is ±0.5V and the
FIGURE 18. COMPLETE SCHEMATIC DIAGRAM SHOWING BIAS
REGULATOR AND ONE OF THE THREE
peak load current is 25µA. However, the amplifier must
OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS also supply the necessary current through the feedback
resistor and if RS = 20kΩ, then RF = 200kΩ for ACL = 10.
Bias Consideration for Op Amp Applications Therefore, the feedback loading = 0.5V/200kΩ = 2.5µA.
The operational transconductance amplifiers allow the circuit The total amplifier current output requirements are, there-
designer to select and control the operating conditions of the fore, ±27.5µA. Referring to the data given in Figure 5, we
circuit merely by the adjustment of the amplifier bias current see that for an amplifier bias current of 20µA the amplifier
IABC. This enables the designer to have complete control output current is ±40µA. This is obviously adequate and it
over transconductance, peak output current and total power is not necessary to change the amplifier bias current
consumption independent of supply voltage. IABC.

3-7
 CA3060

4. Calculation of Bias Resistance. For minimum supply 0

current drain the amplifier bias current IABC should be fed
directly from the supplies and not from the bias regulator.
The value of the resistor RABC may be directly calculated RL = 10kΩ
-20 CL = 0

RELATIVE GAIN (dB)

using Ohm’s law.

V SUP – VA BC
R ABC = ------------------------------------- -40
I ABC

12 – 0.63
R ABC = -------------------------
–6 -60
20 × 10
RL = 10kΩ
CL = 15pF
R ABC = 568.5kΩ or ≅ 560kΩ
-80
0.01 0.1 1.0 10 100
5. Calculation of Offset Adjustment Circuit. In order to
FREQUENCY (MHz)
reduce the loading effect of the offset adjustment circuit
on the power supply, the offset control should be FIGURE 20. EFFECT OF CAPACITIVE LOADING ON
arranged to provide the necessary offset current. The FREQUENCY RESPONSE
source resistance of the non-inverting input is made
equal to the source resistance of the inverting input,
A B C D E F G
1000
20kΩ × 200kΩ
i.e., ---------------------------------------- ≅ 18kΩ
20kΩ + 200kΩ H
PEAK OUTPUT CURRENT (mA)
100 I
Because the maximum offset voltage is 5mV plus an
additional increment due to the offset current (Figure 2) J
flowing through the source resistance (i.e., 200 x 10-9 x
18 x 103V), the Offset Voltage Range = 5mV + 3.6mV = 10
K
±8.6mV. The current necessary to provide this offset is: L
8.6mV
------------------ ≅ 0.48µA
18kΩ 1

With a supply voltage of ±6V, this current can be

provided by a 10MΩ resistor. However, the stability of 0.01 0.1 1.0 10 100
such a resistor is often questionable and a more realistic
SLEW RATE (V/µs)
value of 2.2MΩ was used in the final circuit.
A. CL = 10,000pF G. CL = 10pF
Capacitance Effects B. CL = 3,000pF H. CL = 3pF
The CA3060 is designed to operate at such low power levels C. CL = 1000pF I. CL = 1pF
that high impedance circuits must be employed. In designing D. CL = 300pF J. CL = 0.3pF
E. CL = 100pF K. CL = 0.1pF
such circuits, particularly feedback amplifiers, stray circuit
F. CL = 30pF L. CL = 0.03pF
capacitance must always be considered because of its
adverse effect on frequency response and stability. For
FIGURE 21. EFFECT OF LOAD CAPACITANCE ON SLEW RATE
example a 10kΩ load with a stray capacitance of 15pF has a
time constant of 1MHz. Figure 20 illustrates how a 10kΩ Phase Compensation
15pF load modifies the frequency characteristic. In many applications phase compensation will not be
Capacitive loading also has an effect on slew rate; because required for the amplifiers of the CA3060. When needed,
the peak output current is established by the amplifier bias compensation may easily be accomplished by a simple RC
current, IABC (Figure 5), the maximum slew rate is limited to network at the input of the amplifier as shown in Figure 17.
the maximum rate at which the capacitance can be charged The values given in Figure 17 provide stable operation for
by the IOM. Therefore, SR = dv/dt = IOM/CL, where CL is the the critical unity gain condition, assuming that capacitive
total load capacitance including strays. This relationship is loading on the output is 13pF or less. Input phase compen-
shown graphically in Figure 21. When measuring slew rate sation is recommended in order to maintain the highest
for this data sheet, care was taken to keep the total possible slew rate.
capacitive loading to 13pF. In applications such as integrators, two OTAs may be
cascaded to improve current gain. Compensation is best
accomplished in this case with a shunt capacitor at the
output of the first amplifier. The high gain following compen-
sation assures a high slew rate.

3-8
 CA3060

Typical Applications Circuit Description

Figure 23 shows the block diagram of a tri-level comparator
Having determined the operating points of the CA3060
using the CA3060. Two of the three amplifiers are used to
amplifiers, they can now function in the same manner as
compare the input signal with the upper limit and lower limit
conventional op amps, and thus, are well suited for most op
reference voltages. The third amplifier is used to compare
amp applications, including inverting and non-inverting
the input signal with a selected value of intermediate limit
amplifiers, integrators, differentiators, summing amplifiers
reference voltage. By appropriate selection of resistance
etc.
ratios this intermediate limit may be set to any voltage
between the upper limit and lower limit values. The output of
Tri-Level Comparator the upper limit and lower limit comparator sets the corre-
sponding upper or lower limit flip-flop. The activated flip-flop
Tri-level comparator circuits are an ideal application for the
retains its state until the third comparator (intermediate limit)
CA3060 since it contains the requisite three amplifiers. A tri-
in the CA3060 initiates a reset function, thereby indicating
level comparator has three adjustable limits. If either the
that the signal voltage has returned to the intermediate limit
upper lower limit is exceeded, the appropriate output is
selected. The flip-flops employ two CA3086 transistor array
activated until the input signal returns to a selected
ICs, with circuitry to provide separate “SET” and “POSITIVE
intermediate limit. Tri-level comparators are particularly
OUTPUT” terminals.
suited to many industrial control applications.

V+ = 6V V+ = 6V SATURATES WHEN
UPPER LIMIT IS
INPUT SIGNAL 3 EXCEEDED
(ES)
100
1 REGULATOR CA3086
IN CA3060 LOAD

20K 8
V+ = 6V 10K 4.7K
2 8
5.1K 6 Q1
25K
IABC
15 7
5.1K V- = -6V
13K 5 1 150K
14 +
SET
1/3
CA3060 16 11 9 10 4 2
EU 5.1K WHEN
13 - UPPER
R4 LIMIT IS 3
IABC EXCEEDED
10K 10 UPPER LIMIT 13 12 14
R2 5.1K FLIP-FLOP
1K 12 - RESET
UPPER LIMIT 1/3
REFERENCE CA3060 9
WHEN INTERMEDIATE REFERENCE V+ = 6V SATURATES WHEN
VOLTAGE 11 + LOWER LIMIT IS
LIMIT IS EXCEEDED
EXCEEDED

CA3086 100
INTERMEDIATE LIMIT
LOAD
REFERENCE VOLTAGE
4.7K 10K 8
EU - EL
R3
10K 2 IABC
150K 6 Q2
LOWER LIMIT 6
REFERENCE 7
VOLTAGE 5.1K
5 1 5.1K
4 -
SET
EL 1/3
5.1K CA3060 7 10 11 9 4 2
5 + WHEN
LOWER
LIMIT IS 3
EXCEEDED LOWER LIMIT 12 14 13
R1 FLIP-FLOP
1K

NOTES:
9. Items in dashed boxes are external to the CA3086. 10. E > E = Q (ON), Q (OFF)
All resistance values are in ohms. S U 1 2 EU – EL
E L < E U = Q 2 (ON), Q 1 (OFF) E S < -------------------- = Q 1 (OFF), Q 2 (OFF)
2

FIGURE 22. TRI-LEVEL COMPARATOR CIRCUIT

3-9
 CA3060

V+ Active Filters - Using the CA3060 as a Gyrator

The high output impedance of the OTAs makes the CA3060
CA3060
TRI-LEVEL ideally suited for use as a gyrator in active filter applications.
DETECTOR V+
Figure 24 shows two OTAs of the CA3060 connected as a
UPPER LIMIT
REFERENCE SET gyrator in an active filter circuit. The OTAs in this circuit can
- CA3086 POSITIVE
VOLTAGE + FLIP-FLOP OUTPUT make a 3µF capacitor function as a floating 10kH inductor
INPUT (WHEN UPPER across Terminals A and B. The measured Q of 13 (at a
SIGNAL RESET LIMIT IS frequency of 1Hz) of this inductor compares favorably with a
+ REACHED)
INTERMEDIATE - calculated Q of 16. The 20kΩ to 2MΩ attenuators in this
LIMIT REFER- V+
ENCE VOLTAGE circuit extend the dynamic range of the OTA by a factor of
SET
LOWER LIMIT + CA3086 POSITIVE 100. The 100kΩ potentiometer, across V+ and V-, tunes the
REFERENCE - FLIP-FLOP OUTPUT
inductor by varying the g21 of the OTAs, thereby changing
VOLTAGE (WHEN LOWER
LIMIT IS the gyration resistance.
V- REACHED)

FIGURE 23. FUNCTIONAL BLOCK DIAGRAM OF A TRI-LEVEL Three Channel Multiplexer

COMPARATOR
Figure 25 shows a schematic of a three channel multiplexer
The circuit diagram of a tri-level comparator appears in Figure using a single CA3060 and a 3N153 MOSFET as a buffer
22. Power is provided for the CA3060 via terminal 3 and 8 by and power amplifier.
±6V supplies and the built-in regulator provides amplifier bias
current (IABC) to the three amplifiers via terminal 1. Lower V+ = 15V V+ = 15V
limit and upper limit reference voltages are selected by appro-
priate adjustment of potentiometers R1 and R2, respectively.
When resistors R3 and R4 are equal in value (as shown), the 0.01µF
3
intermediate limit reference voltage is automatically estab- 2kΩ
lished at a value midway between the lower limit and upper 4 -
limit values. Appropriate variation of resistors R3 and R4 per- 2kΩ 7
5 +
mits selection of other values of intermediate limit voltage. 8
Input signal (ES) is applied to the three comparators via termi-
6
nals 5, 12 and 14. The “SET” output lines trigger the appropri- 0.02
300kΩ
ate flip-flop whenever the input signal reaches a limit value. µF
When the input signal returns to an intermediate value, the STROBE V- = -15V
common flip-flop “RESET” line is energized. The loads in the 3N153
circuits, shown in Figure 22 are 5V, 25mA lamps. 2kΩ
12 -
2kΩ 9 3 4
V+ = 6V 11 +
390Ω
2
TERMINAL 3 10
A 20kΩ 300kΩ 0.001µF
14
20kΩ AMP 1 16 STROBE OUTPUT
13
2kΩ
15 13 - 3kΩ
V+ 2kΩ 16
14 +
560kΩ V- = -15V
20 20 15
2MΩ 100kΩ kΩ kΩ
L = 10kH 300kΩ +15V STROBE “ON”
560kΩ
-15V STROBE “OFF”
STROBE
V-
10
3µF FIGURE 25. THREE CHANNEL MULTIPLEXER
12
9 AMP 2
When the CA3060 is connected as a high input impedance
voltage follower, and strobe “ON”, each amplifier is activated
11
and the output swings to the level of the input of the
8 amplifier. The cascade arrangement of each CA3060
TERMINAL 2MΩ amplifier with the MOSFET provides an open loop voltage
B V- = -6V
gain in excess of 100dB, thus assuring excellent accuracy in
the voltage follower mode with 100% feedback. Operation at
±6V is also possible with several minor changes. First, the
resistance in series with the amplifier bias current (IABC) ter-
FIGURE 24. TWO OPERATIONAL TRANSCONDUCTANCE minal of each amplifier should be decreased to maintain
AMPLIFIERS OF THE CA3060 CONNECTED AS A 100µA of strobe “ON” current at this lower supply voltage.
GYRATOR IN AN ACTIVE FILTER CIRCUIT Second, the drain resistance for the MOSFET should be

3-10
 CA3060

decreased to maintain the same value of source current. and 3 is shown in Figure 27 and a typical circuit is shown in
The low cost dual gate protected MOSFET, 40841 type, may Figure 28. The multiplier consists of a single CA3060 and,
be used when operating at the low supply voltage. as in the two quadrant multiplier, exhibits no level shift
The phase compensation network consists of a single 390Ω between input and output. In Figure 27, Amplifier 1 is
resistor and a 1000pF capacitor, located at the interface of the connected as an inverting amplifier for the X-input signal.
CA3060 output and the MOSFET gate. The bandwidth of the The output current of Amplifier 1 is calculated as follows:
system is 1.5MHz and the slew rate is 0.3V/µs. The system IO(1) = [-VX] [g21(1)] EQ. 1
slew rate is directly proportional to the value of the phase
compensation capacitor. Thus, with higher gain settings Amplifier 2 is a non-inverting amplifier so that
where lower values of phase compensation capacitors are IO(2) = [+VX] [g21(2)] EQ. 2
possible, the slew rate is proportionally increased.
Because the amplifier output impedances are high, the load
Non-Linear Applications current is the sum of the two output currents, for an output
AM Modulator (Two Quadrant Multiplier) voltage
Figure 26 shows Amplifier 3 of the CA3060 used in an AM VO = VXRL [g21(2) - g21(1)] EQ. 3
modulator or two quadrant multiplier circuit. When modula-
tion is applied to the amplifier bias input, Terminal B, and the The transconductance is approximately proportional to the
carrier frequency to the differential input, Terminal A, the amplifier bias current; therefore, by varying the bias current
waveform, shown in Figure 26 is obtained. Figure 26 is a the g21 is also controlled. Amplifier 2 bias current is propor-
result of adjusting the input offset control to balance the tional to the Y-input signal and is expressed as
circuit so that no modulation can occur at the output without ( V- ) + V Y
a carrier input. The linearity of the modulator is indicated by I ABC(2) ≈ ------------------------ EQ. 4
R1
the solid trace of the superimposed modulating frequency.
The maximum depth of modulation is determined by the ratio
Hence,
of the peak input modulating voltage to V-.
g21(2) ≈ k [(V-) + VY] EQ. 5
The two quadrant multiplier characteristic of this modulator is
easily seen if modulation and carrier are reversed as shown in Bias for Amplifier 1 is derived from the output of Amplifier 3
Figure 26. The polarity of the output must follow that of the dif- which is connected as a unity gain inverting amplifier.
ferential input; therefore, the output is positive only during, the IABC(1), therefore, varies inversely with VY. And by the same
positive half cycle of the modulation and negative only in the reasoning as above
second half cycle. Note, that both the input and output signals
g21(1) ≈ k [(V-) - VY] EQ. 6
are referenced to ground. The output signal is zero when
either the differential input or IABC are zero.
Combining Equations 3, 5 and 6 yields:
Four Quadrant Multiplier
VO ≈ VX x k x RL {[(V-) + VY] - [(V-) - VY]} or
The CA3060 is also useful as a four quadrant multiplier. A
VO ≈ 2kRLVXVY
block diagram of such a multiplier, utilizing Amplifiers 1, 2

+6V

3
CARRIER
4 - MODULATED
TERM. OUTPUT
A 10kΩ
1kΩ AMP 3 7

5 + 100kΩ
1kΩ 8

1MΩ 6
-6V
1MΩ
V+ V-
100kΩ
MODULATION
TERM.
B
10kΩ

FIGURE 26. TWO QUADRANT MULTIPLIER CIRCUIT USING THE CA3060 WITH ASSOCIATED WAVEFORMS

3-11
 CA3060

Figures 29B and 29C, respectively, show the squaring of a

- IO(1)
triangular wave and a sine wave. Notice that in both cases
AMP the output is always positive and returns to zero after each
+ 1
cycle.
X
INPUT VO
R1
IABC (1)
RL CA3060
X
+ INPUT 1MΩ
AMP 13 OUTPUT
- 2 IO(2) AMP 16
1MΩ 270Ω 1
1MΩ
15 1MΩ
R2 100Ω
IABC (2) 270Ω 14
RF 200kΩ 270Ω
Y
INPUT 51kΩ 4
RIN
Y - 51
4 kΩ
INPUT
+ AMP 100Ω AMP 7 560kΩ
3 3
5 240kΩ
0.02µF 6 V+ V-
24kΩ 100kΩ
FIGURE 27. FOUR QUADRANT MULTIPLIER 100kΩ
3

Figure 28 shows the actual circuit including all the adjust- 1.1MΩ

ments associated with differential input and an adjustment 10

for equalizing the gains of Amplifiers 1 and 2. Adjustment of
the circuit is quite simple. With both the X and Y voltages at 11
AMP 9
zero, connect Terminal 10 to Terminal 8. This procedure 2 560kΩ
12
disables Amplifier 2 and permits adjusting the offset voltage
8
of Amplifier 1 to zero by means of the 100kΩ potentiometer.
Next, remove the short between Terminal 10 and 8 and 270Ω
connect Terminal 15 to Terminal 8. This step disables
Amplifier 1 and permits Amplifier 2 to be zeroed with the
other potentiometer. With AC signals on both the X and Y
inputs, R3 and R11 are adjusted for symmetrical output FIGURE 28. TYPICAL FOUR QUADRANT MULTIPLIER CIRCUIT
signals. Figure 29 shows the output waveform with the
multiplier adjusted. The voltage waveform in Figure 29A
shows suppressed carrier modulation of 1kHz carrier with a
triangular wave.

FIGURE 29A. FIGURE 29B. FIGURE 29C.

FIGURE 29. VOLTAGE WAVEFORMS OF FOUR QUADRANT MULTIPLIER CIRCUIT

3-12