EE105 – Fall 2015

Microelectronic Devices and Circuits

Prof. Ming C. Wu
wu@eecs.berkeley.edu
511 Sutardja Dai Hall (SDH)

8-1

Circuit Symbol for NMOS

4 terminal including Modified circuit symbol Simplified circuit symbol

Body with arrow on source with body connected to
(Arrow pointing to (Arrow indicating source (or when the effect
channel indicating direction of current flow) of the body on device
substrate is p-type) operation is unimportant)

Note in NMOS
1. Drain voltage is always more positive than Source voltage
2. Current always flows from Drain to Source
8-2

1
 I-V Curves of NMOS

Vtn : threshold voltage of NMOS

8-3

Relative Voltage Levels of NMOS

Analog circuit (e.g., linear

amplifiers) usually biased in
Saturation region

Digital circuit (e.g., inverter)

use Triode region as one of
the states

Vtn : threshold voltage of NMOS

Vtn is usually fixed once a process

(technology) is selected

8-4

2
 Drain Current vs Gate Voltage

In Saturation Region
1 W 2
iD = µ nCox vOV
2 L
1 W 2
= µ nCox ( vGS −Vtn )
2 L

To experimentally determine Vtn :

Measure and plot iD versus vGS
iD 1 W
iD = µ nCox ( vGS −Vtn )
2 L
Vtn = intercept with horizontal axis

Vtn vGS
8-5

Finite Output Resistance due to

Channel Length Modulation
When vDS = vOV , the channel pinch of near the Drain. With further increase
in vDS , the pinch off point moves slowly towards the source, effectively reducing the
channel length from L to L − ΔL (this is called "channel length modulation") :
1 W 2
iD = µ nCox (vGS −Vtn )
2 L − ΔL
The continual increase of iD with vDS is modeled by
1 W 2
iD = µ nCox ( vGS −Vtn ) (1+ λ vDS )
2 L

8-6

3
 Output Resistance of MOSFET
1 W 2
iD = µ nCox ( vGS −Vtn ) (1+ λ vDS )
2 L
−1
# ∂v & # ∂i & 1 1
ro = % DS ( =% D ( = ≈
# 1 W &
∂i ∂v
$ D 'vGS =VGS $ DS 'vGS =VGS λ % µ C (V −V ) ( I Dλ
2

$ 2 n ox L GS tn '
1 1 W 2
ro = where I D = µ nCox (VGS −Vtn ) is the DC bias current at Drain.
λID 2 L

8-7

Circuit Symbol of PMOS

4 terminal including Modified circuit symbol Simplified circuit symbol

Body with arrow on source with body connected to
(Arrow pointing away (Arrow indicating source (or when the effect
from channel indicating direction of current flow) of the body on device
substrate is n-type) operation is unimportant)

Note in PMOS
1. Source voltage is always more positive than Drain voltage
2. Current always flows from Source to Drain
3. Source is usually drawn on top so current flows downward
(convention)
8-8

4
 PMOS I-V Equations

Triode Region:
W" 1 2 %
iD = µ pCox $ vOV vDS − vDS '
L# 2 &
vOV = vSG − Vtp Saturation Region:
Use same equation as NMOS but 1 !W $ 2

add absolute sign on all voltages 2 "L%

(
iD = µ pCox # & vGS − Vtp )
since most voltages are negative: 1 !W $ 2
= µ pCox # & vOV
Vtp < 0, vDS < 0, v GS < 0 2 "L%
So either use vSD or vDS

8-9

Relative Voltage Levels of PMOS

Digital circuit (e.g., inverter)

use Triode region as one of
the states

Analog circuit (e.g., linear

amplifiers) usually biased in
Saturation region

Vtp : threshold voltage of PMOS

Vtp is usually fixed once a process

(technology) is selected

8-10

5
Diode-Connected Transistor

With Gate connected to Drain, it becomes a 2-terminal device.

This is called "diode-connected transistor"
In this configuration, the transistor is always in "Saturaiton".
Its I-V relationship is:

1 W 2
i = I D = µ nCox vOV
2 L
vGS = vDS = v
vOV = vGS −Vtn = v −Vtn
1 W 2
i = µ nCox ( v −Vtn )
2 L

8-11

Example Circuit (1)

Design Problem:
Determine RS and RD such that the NMOS is biased at I D = 0.4mA
and VD = 0.5V. The NMOS has Vt = 0.7V, µ nCox = 100µ A / V 2 ,
L = 1µ m and W = 32µ m.

Solution:
VDD −VD 2.5 − 0.5
RD = = = 5kΩ
ID 0.4
1 W 2
I D = µ nCox vOV = 0.4mA --> vOV = 0.5V
2 L
(channel length modulation can usually be ignored
when solving DC bias)
vGS = Vt + vOV = 0.7 + 0.5 = 1.2V
VG = 0 (grounded) --> VS = −1.2V
VS −VSS −1.2 − (−2.5)
RD = = = 3.25kΩ
ID 0.4
8-12

6
Example Circuit (2)
The resistor divider is a common bias circuit.
To solve the DC bias condition, it means to solve
I D ,VDS ,VGS
W
The NMOS has Vtn = 1V, kn = µ nCox = 1mA / V 2
L
RG 2 5
First, solve VG = VDD = 10 = 5V
RG1 + RG 2 5+ 5
VGS = 5 − I D RS = 5 − 6I D (with I D in mA)
Next, assume the transistor is in saturation:
1 2 2 2
I D = kn vOV = 0.5 (VGS −Vtn ) = 0.5 ( 5 − 6I D −1)
2
18I D2 − 25I D + 8 = 0 --> I D = 0.89mA or 0.5mA
If I D = 0.89mA, VGS = −0.34V, NMOS will be cut-off
--> not a physical solution.
If I D = 0.5mA, VGS = 2V, VOV = 2 −1 = 1V
VDS = VDD − I D (RD + RS ) = 10 − 6 = 4V > VOV
Saturation assumption verified !
8-13

Example Circuit (3)

Design Problem:
Design the circuit such that I D = 0.5mA and VD = 3V.
PMOS has Vtp = −1V, µ pCox (W / L) = 1mA / V 2 .
Also find the maximum RD for PMOS to remain in
Saturation

Solution:
1 2
I D = k pVOV = 0.5mA --> VOV = 1V
2
VGS = Vtp + VOV = 1+1 = 2V
VS = 5V --> VG = 3V
We can choose R G1 = 2MΩ and R G 2 = 3MΩ
Saturation: VD ≤ 5 − VOV = 4V
VD,max 4
RD,max = = = 8kΩ
ID 0.5

8-14