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Shortening Burn-In Test: Application of Weibull Statistical Analysis & HVST

Conference Paper in Conference Record - IEEE Instrumentation and Measurement Technology Conference · June 2005
DOI: 10.1109/IMTC.2005.1604066 · Source: IEEE Xplore

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 IM-5533

Shortening Burn-In Test: Application of HVST & Weibull Statistical Analysis

Melanie Po-Leen Ooi, Member, IEEE
Monash University Malaysia
No. 2 Jalan Kolej
Bandar Sunway, Petaling Jaya
46150 Selangor,
MALAYSIA
melanie.ooi@eng.monash.edu.my
Zainal Abu Kassim, Member, IEEE Serge Demidenko, Fellow, IEEE
Freescale Semiconductor Massey University
No. 2, Jalan SS 8/2 Wellington Campus
Free Industrial Zone Sungei Way, Private Bag 756
47300 Selangor Darul Ehsan 6140 Wellington
MALAYSIA NEW ZEALAND
zainal.abu.kassim@freescale.com s.demidenko@massey.ac.nz

Abstract – Testing plays an important role in controlling and ensuring required quality and reliability of manifactured

integrated circuits (ICs) before supplying them to final users. Several types of testing are performed at different stages of the

IC manufacturing process. One of them is so-called burn-in testing (i.e. accelerated testing performed under elevated

temperature and other stress conditions). Burn-in aims at accelerating detection and screening out of so-called ‘infant

mortalities’ (early-life latent failures). Burn-in is normally associated with lengthy test time and high cost, making it a

bottleneck of the entire IC manufacturing process. It is no surprise therefore, that much attention and efforts have been

dedicated towards possible ways of reducing or even eliminating the burn-in testing in IC manufacturing (for at least some

types of products). This paper presents a methodology for burn-in test time reduction based on the use of the High-Voltage

Stress Test (HVST) technique. The Weibull statistical analysis is employed to model the infant mortality failure distribution.

Weibull distribution parameters were estimated using the Linear Rectification Method. The implemented industrial

experimental study showed that the burn-in duration can be significantly reduced with the application of the proposed

approach.

Keywords – integrated circuits, burn-in testing, test time reduction, high voltage stress, Weibull statistical analysis

I. INTRODUCTION

The current stage of development of the electronics industry is characterized by the push for higher quality and reliability

standards – a burden now shouldered by semiconductor manufacturers. A quality product is one that fully functions when it is

shipped from its manufacturing site to a customer, installed into a target application system and commissioned into operation.

On the other hand, a reliable product is one that can be trusted to work well within its published lifespan in spite of extensive

usage. Extensive testing is performed by the Integrated Circuit (IC) manufacturing companies to confirm the required quality
and reliability of their semiconductor products. Under normal operating conditions, most electronic devices exhibit required

high reliability, often with a lifespan of several years. If tested under such conditions, a very long period of time would be

required to gather the data required to model the failure characteristics of a device and then to introduce necessary

improvements into design or fabrication process. The irony of this scenario is that a device may become obsolete by the time it

can be guaranteed to be reliable. A plausible solution would be to exaggerate or intensify selected conditions in the testing

environment in order to speed up the time-to-failure of the device. This is known as Accelerated Testing [1].

Accelerated testing is an approach for obtaining more reliability-related results from a given test time than would normally

be possible. It has been introduced into the IC manufacturing process to address the need of providing the guarantee of

reliability that conforms to an industry standard. Under accelerated testing conditions an integrated circuit is exercised under

environments that are much more severe than those experienced during its normal operating conditions. This allows to shorten

the time-to-failure process of the IC without changing its failure characteristics. By gathering data from acceleration tests, the

reliability of the IC can be evaluated. Burn-in is currently one of the most widely-used accelerated testing methods in the

semiconductor industry [2, 3]. It was first introduced in the sixties to screen out low-volume immature parts and was soon

incorporated in military standards [2-5].

Fig. 1 shows a simplified flow of testing of assembled integrated circuits. It can be seen that ICs have to undergo several

types of extensive testing procedures such as pre-burn-in test, monitored burn-in test and final test before their shipping to the

customers.

Pre Burn-In Monitored Final Test

Test Burn-In Test
DC Parametric Tests
DC Parametric Test Dynamic Stressing AC Parametric Tests
Gross Functional Test Long Functional Tests Functional Tests, etc.

Assembled ICs Good Devices

Rejects

Fig. 1. Flow of Integrated Circuit Testing

Pre-burn-in test provides limited check to ensure that the IC chips are not damaged during assembly before sending them to

a long and expensive monitored burn-in test. During the pre-burn-in test, some limited electrical parameters (DC Parametric

Test) and functionality (Gross Functional Test) of IC are checked using standard Automatic Test Equipment (ATE). At the pre

burn-in stage the DC Parametric Test checks for open short connections of the circuit, leakage and output drive currents,
voltage threshold levels, etc. The Gross Functional Test is a rough check to determine if the chip is ‘alive’ and working as

intended based on its design. The term ‘Gross’ refers to performing an often simplified or shortened functional test with

relaxed conditions (i.e., where frequency, timings, voltages and current loading are generally less stringent). Sets of test vectors

are supplied to the inputs of the Device Under Test (DUT) and its operation is verified by acquiring signals at the circuit

outputs and comparing them with the reference values (corresponding to fault-free operation).

The burn-in test is executed inside special burn-in chambers. It subjects chips (that are placed onto load boards) to elevated

temperature often combined with functional test application. There are four main types of burn-in tests employed in the

industry. They are Static, Dynamic, Monitored and so-called Test-In Burn-In (TIBI). TIBI is also known as in-situ burn-in [3].

An overview of them is as summarized in Table 1.

Table 1. Types of Burn-In

Type Input/ Output Description

Static No I/O, read point DUT is stressed at elevated constant

at test temperature for an extended period
of time

Dynamic Stimulus input, Similar to static, but with test vectors

read point test applied to toggle internal nodes of
the device
Monitored Stimulus input and Identifies failed units and separate
live output, read them from good devices
point at burn-in
and test

Test-In Stimulus input A combination of functional and

Burn-In and responsive burn-in testing. Functional input
(TIBI) output, read point patterns are applied and output
at burn-in responses are observed.

The burn-in test conditions should trigger IC failures due to defective components without damaging good components of

the circuit [6]. A proper burn-in process should stabilize device characteristics, provoke early failures of weak devices and

screen out those with excessive parametric drift. Figure 2 shows the typical failure rate of a part (electronic product) before and

after application of burn-in [1-4].

The rapidly decreasing dotted-line curve in the figure represents the so-called infant mortality region – ICs that fail (due to

manufacturing defects or foreign particles) during initial period of circuit application, but were not screened out during the

Wafer (Probe) Testing or Final Testing. After the infant mortality period, the ICs (parts) reach steady state stage, whereby they

have a constant failure rate. ICs will remain in this period for the rest of their useful life. Eventually, parts will fail due to
overuse or fatigue. This is termed as the wear-out stage, represented by the rapidly increasing dotted-line curve in Fig. 2.

Manufacturers usually specify the product lifetime to be well below the wear-out stage.

Fig. 2 Failure rate and the effect of burn-in

With burn-in, ICs are stressed under conditions which induce accelerated infant mortality, thus detecting these unreliable

parts. This is shown by the solid-line curve in Fig. 2 which illustrates the accelerated rate in which the steady state is reached. It

is important to choose burn-in conditions such that they do not lower the life expectancy of the parts. At the same time burn-in

conditions must be able to sufficiently stress the DUT to effectively screen out weak infant parts.

After ICs passed burn-in, each of them goes through the Final Test to ensure that the electrical specifications are met. Final

testing normally includes DC Parametric Test (to verify steady-state electrical parameters of IC), AC Parametric Test (to

verify time-related parameters of IC as well as to check that it operates over its full frequency range) and Functional Test (to

verify that IC performs all its functions as the design intended) performed at room, hot and cold temperatures. Upon passing

final testing, ICs are sorted (binned) into various grades according to their test results.

II. BURN-IN TEST REDUCTION

While burn-in can provide some guarantee of the reliability and quality of a product, it is a time-consuming and highly

expensive process. Devices may require very long burn-in test duration (up to 24 - 48 hours, or even more) [2-5]. In addition to

that, there are procedures that have to be carried out between actual burn-in sessions. For example, test floor operators must

ensure that all the test boards (load boards) are properly connected to the sockets in the test chamber before starting the

process. Upon completion of the burn-in testing, the test chambers must cool down before any of the load boards can be
removed. As a result, burn-in testing may take up to 80% of the total time of product testing thus reducing the production

throughput.

The burn-in process also incurs high manufacturing costs. Each burn-in load board can house a limited number of devices,

and each burn-in chamber can house up to a specific number of boards. If there is a high demand for a particular device, it

would mean that more burn-in load boards and chambers have to be made available. As the boards and chambers are

expensive, this incurs a very significant capital expenditure.

Although burn-in can somewhat validate the reliability of the shipped population as a whole, it actually does not increase

the reliability of individual parts [3]. In fact, if the chosen burn-in conditions are inappropriate for a specific device, the test

itself can actually wear out or damage the DUT, leading to a reduction in manufacturing yield and lowering profits [7]. An

example of such a scenario is when the burn-in test conditions over-stresses the DUT, raising its junction temperature high

enough to cause a rapid increase in the leakage current of the semiconductor device, resulting in a thermal runaway and

damaging the part.

In order to efficiently screen out weak devices while not overstressing the good ones, burn-in test parameters must be

carefully chosen. Additionally, the test time and cost should be reduced whenever possible. Shortening (reduction) of the burn-

in process by means of optimal selections of the stress parameters is the main goal of the research presented in this paper.

Several methods have been proposed for burn-in reduction or elimination in the literature and engineering practice. The

most efficient of them include IDDQ testing (for circuits implemented in CMOS technology), statistical methods and high

voltage stress testing [8-14].

In-depth researches showed that burn-in was successfully eliminated from the production testing of certain devices through

proper selection of IDDQ test vectors [8, 9, 13]. Burn-in elimination was also possible for CMOS ICs from poor quality lots by

utilizing sensitive limits and techniques [13, 14]. However, it was also shown that the method was mainly effective at wafer-

level test and was not beneficial for employment at a package-level testing [13]. Since the presented study concentrates solely

on packaged devices, the IDDQ burn-in reduction/elimination methods will not be discussed here, and the use of the following

methods was researched in the presented study to achieve the required burn-in reduction:

 Weibull Statistical Method

 High Voltage Stress Test Method

The Weibull statistical method is widely regarded as a model for product failure since it is extremely flexible and can

accommodate many types of distribution [12]. The Cumulative Density Function (CDF) of the two-parameter Weibull
distribution written as: for variable, t (usually lifespan), characteristic life scale parameter c, and Weibull slope or shape

parameter m, can be

 t m

F (t )  1  exp     , t  0 (1)
  c  

A change of the scale parameter c (while keeping all the other Weibull parameters constant) will stretch the CDF. If the

scale parameter is increased, the peak of the distribution will decrease since the area under the CDF is constant [12]. The scale

parameter c has the same unit as the variable t (lifespan). In simple terms the scale parameter determines when, in time, a given

portion of the population will fail.

The slope (shape) parameter in the key feature of the Weibull distribution that enables it to be applied to any phase of the

bathtub curve (i.e., failure rate vs time plot - Fig. 2). The value of the slope parameter is related to the device life-span failure

rate type as follows [8]:

 m<1  Infant mortality failure

 m=0  Random failure during normal life period

 1 < m < 4  Wear-out failure

 m>4  Old age failure/rapid wear-out

To best understand or analyze failure trends related to some IC population, its failure rate distribution is modeled using

statistical methods. Various statistical models could be employed to achieve the goal while providing different level of success.

For instance, the Poisson distribution can be used to model the constant failure rate region during the useful life period of the

device population under analysis. The Weibull distribution is a very flexible life model that can be used to characterize failure

rate trends in all three phases on the bathtub curve. However in the state-of-the art semiconductor device manufacturing, very

often the Weibull distribution is used to model just the infant mortality stage (decelerating failure region) as it provides a very

close matching to the real life failure rate data (with the typical slope parameter in the range of 0.2 to 0.6 for complex, high

density integrated circuits like CPUs, microcontrollers, video processing ICs, etc.).

By applying the Weibull analysis, the test data on failures during the Early Life Failure Rate (ELFR) study (i.e., without

burn-in) and after the burn-in can be employed to model the infant mortality rate of the device population. Failure trends from

various wafer lots can also be combined and used for analysis. This provides significant additional advantage over previous

burn-in reduction methods whereby rejects from every wafer lot have to be analyzed separately.
 By obtaining and comparing the Weibull distributions for the IC population without and with burn-in, the efficiency of

burn-in process of circuit “ageing” and its equivalence to a period of time of IC working under normal operation conditions can

be established. There are numerous examples of application of the technique presented in the literature, e.g., [15].

Weibull models in general are very flexible and can be used to represent a wide range of the distributions. By calculating its

variables (m and c) and computing the CDF, the distribution that best describes a set of failure data can be obtained and

predictions can be made on future failures, including the number of parts that can be expected to fail after a certain timeframe.

This facilitates the correction of the test parameters (voltage and temperature) used to carry out burn-in. Thus, burn-in test

hours can be reduced in order to optimize the manufacturing cost while maintaining the required level of reliability of the ICs

under test.

The High Voltage Stress Test (HVST) technique follows the argument that elevated temperatures may not necessarily stress

certain devices, making it sometimes a needless process. In some cases, high voltage stress testing is required in addition to

burn-in to screen defects and thus to improve reliability of IC population to be shipped to customers. However, the sole

application of HVST does not reliably screen all the defects occurring on the wafers (for example, those related to heavy metal

contamination). Also, not every device is suitable for HVST application. Previous studies have shown that HVST is unsuitable

for testing CMOS integrated circuits with large embedded non-volatile memory (such as FLASH memory) and devices with

internal voltage regulators without an on-board circuitry to disable them [11]. Thermal-only activated failures may not be

detectable under HVST and the elevated voltage applied during HVST may even temporarily heal these failures.

Thus burn-in is still a necessary procedure for the absolute majority of the produced ICs (particularly those implemented

using “state-of-the-art” technology and ICs aimed for use in mission-critical application systems) to meet their specific Parts

per Million (PPM) requirements [15]. PPM is an industry standard of measure for reliability that refers to the number of parts

that are allowed to fail per 1 million parts shipped to the customer. All devices have to meet a specific PPM requirement

depending on their intended usage and grade. Parts intended for automotive applications or other high dependability areas have

more stringent PPM compared to parts meant for less critical devices. For parts with lower PPM standards, HVST has proven

to be a successful burn-in reduction technique [11].

 Traditional Flow Proposed Flow

Pre burn-in tests Pre burn-in tests + HVST

Burn-in Burn-in (reduced hours)

Post burn-in tests Post burn-in tests

Fig. 3 Burn-in test time reduction plan

The aim of the presented study is to shorten the burn-in test time by employing the Weibull statistical analysis and extended

HVST (Fig. 3). Upon successful implementation, the new test flow should have a much shorter overall test time without

sacrificing the reliability of ICs.

III. BURN-IN REDUCTION EXPERIMENTAL FLOW

In the industry, monitored burn-in is normally done in a number of time intervals, whereby each interval represents a

fraction of the total burn-in process. Such interval-based arrangement allows sufficient amounts of data to be collected. The

data is then used to determine the suitable number of burn-in hours for the newly specified burn-in conditions. After each burn-

in interval, the electrical tests at a high temperature (so-called hot tests) must be performed, and all failures must be verified

using the specifications datasheet. Devices that have met the data specifications but still fail (so-called non-device related

failures) should not increment the number of failures recorded during the experiment, and their number must be subtracted

from the sample size for that interval. Examples of such failures include damaged/missing balls (contacts terminals), count

variance (missing devices) and situations whereby the integrity of the manufacturing process has been compromised (e.g.,

missing wire-bonding due to assembly process faults).

Fig. 4 shows the burn-in intervals and the tests involved.

Fig. 4 Burn-in test done in intervals

 The tests are indicated by the arrows in the diagram. The grey boxes represent intervals of burn-in time. The total burn-in

hours executed on the device is indicated in the bottom row. For a reliable Weibull analysis, the post burn-in hot tests should be

carried out at two intervals before the target burn-in hours tBI and one interval after it [16]. In the reported research, based on

the design specification and given reliability requirements, the tBI has been identified as 3 hours. Hence the burn-in cycle times

are chosen as 0.75 hours and 1.5 hours (two intervals before the desired tBI), 3 hours (target tBI) and 6 hours (one interval after

the target) as shown in Fig. 4.

After the third hour of burn-in, devices have to undergo DC parametric tests, AC parametric tests and functional tests that

are similar to the final production tests that devices normally undergo after burn-in and prior to shipping out. These tests are

done at room, hot and cold temperatures. A data log is taken for each test. These data logs are important, especially in the event

of any anomaly, since they allow the cross checking of the various testing parameters.

The experimental flow for application of HVST combined with the use of Weibull analysis is shown in Fig. 5.
 Start

1 Hot Test

2 Room Test

Burn-in Control Flow 3 Cold Test HVST & Weibull Experiment Flow

B1 12hr Burn-in H1 Room HVST Test

B2 Room Test H2 0.75 Hrs BI (New Condition)

HVST Effectiveness study
B3 Hot Test H3 Hot Test 1

B4 Cold Test H4 0.75 Hrs BI (New Condition)

H5 Hot Test 2
Stop
H6 1.5 Hrs BI (New Condition)

H7 Hot Test 3

Weibull Analysis H8 3 Hrs BI (New Condition)

H9 Hot Test 4

H10 Room Test

H11 Cold Test

H12 48 Hrs BI (Old Condition)

H13 Hot Test

H14 Room Test

Fig. 5 Burn-in reduction experiment

A sample size of 3 wafer lots (about 3000 units per wafer lot) was used in this experiment. Firstly, pre-burn-in electronic

tests at hot, room and cold temperature were executed to screen all defective units. That was done to ensure that any failures

that occurred during tests H1 to H14 (Fig. 5) were “true” failures induced by the HVST and burn-in. The aim of this

experiment was to determine the suitable burn-in duration and conditions that would be used in the production testing of this

device.

A control flow was required as a standard for results comparison. Half the units from each wafer lot entered the processing

in accordance with the control flow, while the remaining units undergone the procedures that correspond to the HVST &

Weibull experimental flow. The 12-hour burn-in corresponding to the control flow followed the old (existing) test procedure.
The burn-in intervals in the HVST & Weibull flow followed the ones shown in Fig. 4. The new burn-in conditions used in the

experimental flow were based on calculations discussed later in this paper.

A special 48-hour proof-of-concept burn-in was added into the industrial experiment as a check to ensure that the new burn-

in conditions were reliable. This 48-hour burn-in will not be a part of the final test routine to be implemented on the production

floor should the new test flow prove to be successful – its aim is to validate the developed test flow before its final

implementation into the IC manufacturing process. The essence of the proof is as follows: if any additional fallout (in

comparison with the control test flow results) is observed after the 48 hour burn-in, it is an indication that the new burn-in

conditions are not reliable enough and they must be revised. If there are no additional fallouts after the 48 hour proof burn-in,

the results for tests H1 to H11 can be used for further data analysis.

IV. HVST PROGRAM

The specific IC type used in the study contained a 400MHz MPC603e series G2 Core connected directly a memory

controller providing intensive I/O data transfer with a high speed Double Data Rate. It had also a Floating Point Unit, and

some other circuitry. The device applications include networking media, industrial control, video detection, electronic/medical

instrumentation and automotive electronics.

Figure 6 shows the process adopted in implementing the HVST for the experimental device [11].

Fig. 6. HVST Implementation Plan

 A good HVST test pattern should provide maximum nodal (fault) coverage within the shortest possible time length.

However, some test patterns may not be as effective as others in terms of nodal coverage. Industry-recommended patterns

include Built-in Self Test (BIST), Core and System DC Scan test patterns [6]. The HVST patterns chosen in for the reported

research were: Core DC Scan (tests the circuitry in the core of IC), System DC Scan (tests transistors in the rest of the chip),

Analog BIST (tests analog circuitry in IC by using its built-in internal test tools) and Motorola BIST (or MBIST, also known as

array BIST, which tests IC peripheral memory) [11].

HVST can be integrated into the existing test flow at two stages of manufacturing: at wafer-level or package-level (level of

the packaged IC). In this research, HVST is implemented at package-level and is integrated into the monitored burn-in test

flow. It is planned to incorporate HVST to wafer-level test through final-test-to-probe correlation in the future.

Device characterization is an important step before HVST can be implemented. Although functional tests are performed

during HVST, fail flags must not be set if a device fails during periods of elevated voltage. This is because at elevated voltages,

the timing specifications of IC may not be met although the device is actually functioning. Hence, if a device fails during

HVST, it should be retested later at nominal voltages to confirm the functional failure.

For optimum reliability, voltage levels should be selected to be as aggressive as possible. This would minimize the test

duration without inducing permanent damage to IC. As a general rule-of-thumb, the HVST voltage should always be kept

below the intrinsic breakdown voltage of the device and less than the aggressive time-dependent dielectric breakdown (TDDB)

cell. At the same time, extrinsic defects should occur below the HVST voltage. Based on the previous experiments done at

Freescale Semiconductor, the HVST voltage level should ideally be equal to 80% of the chip breakdown voltage (this data was

confirmed by Failure Analysis lab data within the company). The breakdown voltage of IC is normally unknown and not

specified by the datasheet. Thus the device has to be first characterized.

To determine the Vdd(i/o) and Vdd(core) breakdown voltages for the device, six Known Good Units (KGU) – i.e., guaranteed

fault-free devices, were employed. The process started by first setting the voltages to their maximum specifications. As long as

the chip did not fail, both supply voltages were increased by 100mV and the KGU was retested. When the chip failed, the

supply voltages at the time of failure were noted as the initial breakdown voltages (A1 and A2 for I/O and core respectively)

and the KGU was labeled and stored. The flow was repeated for another KGU to verify the result. It is important to label and

store every KGU that failed to confirm all failures in the Failure Analysis lab.

After the initial breakdown voltages were found, the next step was to characterize the breakdown voltage for Vdd(i/o) for the

I/O circuitry of the device. Both the voltages, Vdd(i/o) and Vdd(core) were set to 300mV below the initial breakdown values A1 and
A2 respectively (found earlier). The KGU was tested using the pattern list while the Vdd(i/o) was incremented by 100mV each

time until the chip failed. The voltage for Vdd(core) was held constant at A2. Once the chip did fail, the Vdd(i/o) was noted as the

I/O breakdown voltage value B1, and the failed unit was labeled and stored. Again, the test procedure was verified for another

KGU.

The third step was to identify the core breakdown voltage. The core voltage supply was set to 300mV below the initial

breakdown level A2 while Vdd(i/o) was set to 300mV below the I/O breakdown voltage B1. The Vdd(core) level was then

incremented by 100mV until the KGU fail. The core voltage of the device under test at the time of failure was marked as the

core breakdown voltage B2. The entire flow was then implemented again (to verify the result) on another unit.

With both the I/O and core breakdown voltages found as B1 and B2 respectively, the next step was to verify the reliability of

these voltage levels by testing their repeatability. Both supply voltages were set to 300mV below their found breakdown

voltages B1 and B2, and the list of the HVST test pattern list was applied.

When testing for the core voltage repeatability, the Vdd(core) level was incremented by 50mV until failure occurred while the

Vdd(i/o) level was held constant. A sample size of 20 units was used for this test. Similarly, when testing for I/O voltage

repeatability, the Vdd(i/o) level was incremented by 50mV until failure occurred while the Vdd(core) level was left unchanged. The

sample set of 20 units was also used for this purpose. The failed units were segregated and the voltage levels at the times of

failure were noted. If the data showed that repeatability was unsatisfactory, the breakdown voltage characterization must be

repeated for a new set of KGUs.

Once the breakdown voltages were found to be repeatable, the test program was modified to run the test patterns with the

HVST voltages at 80% of the breakdown levels for Vdd(core) and Vdd(i/o). To verify the HVST pattern in Step 4 (Fig. 6) a set of 3

wafer lots (200 units each) was used. The HVST pattern was executed repeatedly on all 600 units. The rejects were segregated

and verified. The procedure was repeated until the entire set passed 3 consecutives times without a single reject. In other

words, if after X times of HVST execution the sample set passed, and the same was true for (X+1)th and (X+2)th executions as

well, the repetition for the HVST pattern was established as X times (the first of the 3 consecutive reject-free passes on the

entire set).

Burn-in study is required to validate the infant mortality, whereby failure rate must be within the pre-specified

requirements. Reliability can be assured if there is no degradation or early wear-out. This study was carried out in the burn-in

reduction experiment flow shown in Fig. 5.

 V. BURN-IN TEST CONDITIONS

As mentioned above, burn-in is a form of accelerated testing. It shortens the time required for weak devices to fail during

nominal (operating) conditions tN by stressing them at an acceleration factor A. The equation below describes the relationship

between, the time to failure under stress (burn-in conditions) tS , the acceleration factor A(tS) for the given time under stress,

and the nominal time to failure tN.:

t N  A(t S )  t S (2)

In order to reduce the burn-in test time while providing the required level of defect screening, the test stress parameters have

to be made harsher (i.e., increased supply voltages and/or burn-in temperature are to be applied). Hence the acceleration factor

for the burn-in conditions must first be calculated. For oxide-related failures, appropriate acceleration models from JEDEC

standards JESD74 [17] and JEP122 [18] were chosen based on the technology parameters of the device used in the presented

research. The acceleration factor A for time t0 can be presented as the voltage acceleration AV(t0) multiplied by the temperature

acceleration AT(t0) factors as shown below [18]:

A(t0 )  AT (t0 )  AV (t0 ) (3)

Temperature acceleration AT follows the Arrhenius equation [1, 9]:

E  1 1  
AT (t0 )  exp  a    , (4)
 k  TN (t0 ) TS (t 0 )  

where: Ea is the activation energy dependant on the type of device (eV); k is the Boltzmann’s constant (8.62 x 105 eV/K); TN is

the nominal (operating) junction temperature; TS is the stress junction temperature (under burn-in conditions); and t0 is initial

time to failure under stress conditions.

The voltage acceleration AV is modeled by:

AV (t0 )  exp PVA VS (t0 )  VN (t0 ) (5)

where: VS is the gate voltage under stress (burn-in) conditions; VN is the gate voltage under nominal (operating) conditions; PVA

is the parameter for voltage acceleration (1/V) that can be found from the values in Table 2 [19].
 Table 2 Voltage acceleration parameters

Nominal Core Voltage (V) PVA

(1/V)
5.0 2.8
3.3 3.0
2.5 4.5
1.8 5.9
1.5 7.4
1.2 8.0
The values in the table were derived from acceleration experiments done on the package-level at the semiconductor

manufacturing company. The rest of the used above parameters can be found from the device specifications sheet.

Apart from the voltage acceleration model described in the presented research, employment of appropriate alternative

voltage acceleration models is also possible depending on the technology parameters of the device. These models can be found

from JEDEC standards [17, 18] as well as from the literature, for example [20-22].

Table 3 shows the calculated acceleration factors.

Table 3. Calculated acceleration factors

Acceleration Factors Burn-in Conditions

Voltage Acceleration on Power Supply 1 (V) 171.91
Voltage Acceleration on Power Supply 1 and 2 (V) 49.06
Temperature Acceleration Factor, AT 37.6
Voltage Acceleration Factor, AV 171.9
Total Acceleration Factor, A 6461.05

The acceleration factor that was discussed so far refers to the acceleration achieved by a burn-in testing with the stress

duration of t0 hours (in the case under discussion t0 is 12 hours). To reduce the burn-in time to some target duration of t1 hours

(e.g., 3 hours), the voltage supply can be increased while keeping unchanged the burn-in temperature (hence, AV is increased

while AT remains unchanged). Equations (2), (3) and (4) are used to calculate the new voltage acceleration factor AV(t1) as:

t 0 A(t 0 )
AV (t1 )  (6)
t1 AT (t 0 )

For example, in order to achieve the equivalent burn-in results of just 3 hours (rather than 12 hours) with unchanged burn-in

test temperature, the desired voltage acceleration is to be 4 times of the original voltage acceleration.

AV (3)  4 AV (12) (7)

 The above considerations were used to carry out an industrial experimental study aiming to validate the proposed approach

for burn-in test time reduction.

VI. EXPERIMENTAL STUDY RESULTS

As mentioned earlier, the total number of 9000 ICs from 3 different wafer lots was used in the experimental study. The

results of the study are summarized in Table 4 (only the percentage yield is discussed here due to confidentiality).

No fallouts were observed after the 48-hour proof burn-in (H13 and H14), indicating that the there was no degradation in

device reliability while the failure rate was within specified requirements.

Table 4 Experimental Results

Read point Average Yield

Control Flow
B2 99.60
B3 99.96
B4 99.46
Experiment Flow
H1 98.47
H3 99.71
H5 99.71
H7 100.0
H9 99.77
H10 99.94
H11 99.77
H13 100.00
H14 100.00

In order to justify the application of HVST, its effectiveness and reliability have to be confirmed. The results taken at point

H1 of the experimental burn-in flow were compared with those obtained at the point B2 of the control flow (Fig. 5). Table 5

shows the comparison between the yields of the study flow and control flow (room temperature tests). It can be seen that the

room temperature test combined with HVST screens out 1.13% more rejects compared to a room test after 12-hour burn-in.

This shows that HVST can effectively screen out weak infant devices compared to a 12-hour burn-in.
 Table 5 Control Test Flow vs. Experimental Test Flow

Test code Test Description Average Yield (%)

Control flow room
B2 test 99.60
Experiment flow
H1 HVST room test 98.47
Yield Difference = 1.13
Control flow room
B3 test 99.96
Experiment flow
H3 HVST room test 99.71
Yield Difference = 0.25

The yield difference between the hot temperature test in the control flow (B3) and the hot test in the experiment flow (H3)

for the 9000 units used for this experiment is only 0.25% (Table 5). Since the yields for these two tests are almost similar, it is

a good indication that the HVST did not damage good units while stressed the device population well enough to screen out

weak infants. In short, the test results show that the HVST program was both effective and reliable.

Next the Weibull distribution was used to calculate the Early Life Failure Rate (ELFR) against the burn-in duration based

on the obtained results. The Weibull CDF expression (1) was rewritten using the linear rectification method as shown in

equation below:

ln ln1  F t   m lnt   m lnc (8)

The concept of linear rectification implies doing what is necessary to convert an equation into its linear form. By using

y = ln{-ln[1-F(t)]} and x = ln(t) a least-squares fit can be employed to estimate the Weibull parameters. The least-squares

method is generally preferred because it is an effective and computationally simple means to model the complex nature of

failures of a product [23].

The expression for the slope parameter c was found by:

1
1 n ˆ m
ˆ
cˆ    (ri  1)t im  (9)
 n i 1 

And the scale parameter m was found as [24]:

n ˆ
 (ri  1)ti log ti
m
1 1 n
  log xi  i 1 n 0 (10)
mˆ n i 1 mˆ
 (ri  1)ti
i 1
 Once the Weibull distribution parameters that best describes the failure distribution of the device was found, the estimated

Parts per Million (PPM) values against burn-in time can be calculated.

Fig. 7. ELFR burn-in duration

An Early Life Failure Rate (ELFR) burn-in duration study graph (Fig. 7) was obtained by extrapolating the calculated

Weibull distribution. This plot provides information on ELFR achieved at various burn-in durations. The new burn-in hours

can then be calculated based on pre-determined criteria specific to the device such as PPM, confidence level and duty cycle.

The results show that the burn-in time can be reduced by up to 90% and while still achieving the required PPM. This is an

extremely valuable outcome of the research. The HVST program was highly effective in screening out weak devices, resulting

in a very significant reduction of burn-in time.

VII. CONCLUSIONS AND FUTURE WORK

Accelerated testing is vital to ensure the reliability of products. Burn-in test is one of the mort popular techniques of

accelerated testing in the modern semiconductor industry. In a very significant extend it can provide a form of guarantee on

reliability and quality of the final electronic products. However, the burn-in incurs a high turnaround time and inevitably high

cost in testing. The research and experimental results presented in this paper show that the application of HVST combined with

the use of Weibull statistical analysis can reduce the burn-in time very significantly while still providing required level of

reliability and quality.

Plans for our future work include study of influence of the elevated clock frequency on the accelerated infant mortality and

the combined use of several stress factors (temperature, voltage, clock frequency) with the aim of further reduction of burn-in
test duration. Since a large portion of modern CPU chips contain non-volatile memory and often use voltage regulators for

compatibility with bus or I/O voltages, we plan to expand our study towards researching of how the proposed HVST technique

can be employed to test such devices. Finally, we plan also to look at the possibility of extending our research on HVST and

Weibull analysis application to wafer-level burn-in testing in the manufacturing environment.

ACKNOWLEDMENTS

The authors would like present their thanks to Freescale Semiconductor Malaysia (formerly Motorola SPS Malaysia) for the

research opportunity, resources, equipment and data without which the study would not be possible, and to Monash University

Malaysia for the postgraduate scholarship that was granted to one of the authors (M.O).

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