CSE 260 – Introduction to Digital Logic and Computer Design Jonathan Turner

Exam 1 Solutions
2/13/2014

1. (10 points) Draw a logic diagram that implements the expression A(B+C)(C’+D)(B+D’)
directly (do not simplify first), using only simple gates.

B
C

D A

Simplify the expression as much as you can.

A(B+C)(C’+D)(B+D’) = A(BC’+BD+CD)(B+D’) = A(BC’+BD) = AB(C’+D)

How many simple gates of each type are required to implement the simplified expression?
The circuit corresponding to this expression requires 2 and gates, 1 or gate and 1 inverter.

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2. (15 points) Draw a circuit that implements the VHDL code fragment shown below. Assume
that x and z are two bit signals. All others are of type std_logic. You may use simple
gates, multiplexors and flip flops in your circuit diagram.
with z select
x <= a & b when “00” | “01”,
“01” when “10”,
“11” when others;
process (clk) begin
if rising_edge(clk) then
if a > b then
y <= a and c;
elsif a /= c then
y <= x(0);
end if;
end if;
end process;

1
D y
x(0) 1 0
0 >C
2
0
clk
1 2
x
01 2
11 3
2
z
a
b
c

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3. (10 points) Consider the circuit shown below, which includes four copies of the same basic
building block.

a(3) b(3) a(2) b(2) a(1) b(1) a(0) b(0)

z(4)
z(3) z(2) z(0)
z(1)

0
1

0
1
x(3) x(2) x(1) x(0)

Write a VHDL process containing a loop that specifies this circuit.

process(a,b,z) begin
for i in 0 to 3 loop
if b(i) /= z(i) then
x(i) <= a(i) or z(i);
else
x(i) <= b(i);
end if;
z(i+1) <= a(i) and z(i);
end loop;
end process;

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4. (10 points) Draw a diagram of an 8-to-1 multiplexor with data inputs D0 to D7 and a 3 bit
control input C, using smaller multiplexors as building blocks. Make sure that the all signals
and mux inputs are labeled appropriately. Pay special attention to the control inputs of the
mux components in your circuit.

D0 0
D1 1
D2 2
D3 3
0
1
D4 0
D5 1 C(2)
D6 2
D7 3

C(1..0)

How many LUT4s does it take to implement this circuit?

It takes 3 LUTs to implement each 4:1 mux, plus one more to implement the 2:1 mux, so 7 in all.

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5. (15 points) The VHDL module shown below counts the number of odd length pulses that
have been observed on the dIn input since the last reset. What is the smallest number of flip
flops needed to implement this VHDL spec?
We need at least three for the state register and eight for the oddCount register. So 11.
entity oddPulseCounter is port(
clk, reset, dIn: in std_logic;
oddCount: out std_logic_vector(7 downto 0));
end oddPulseCounter;
architecture a1 of oddPulseCounter is
type stateType is (resetState, start1, prev0, prev1odd, prev1even);
signal state: stateType;
begin
process(clk) begin
if rising_edge(clk) then
if reset = ‘1’ then state <= resetState;
else case state is
when resetState =>
oddCount <= (others => ‘0’);
if dIn = ‘0’ then state <= prev0;
else state <= start1; end if;
when start1 =>
if dIn = ‘0’ then state <= prev0; end if;
when prev0 =>
if dIn = ‘1’ then state <= prev1odd; end if;
when prev1odd =>
if dIn = ‘0’ then
state <= prev0; oddCount <= oddCount + 1;
else state <= prev1even; end if;
when others =>
if dIn = ‘0’ then state <= prev0;
else state <= prev1odd; end if;
end case; ... end a1;
Complete the state diagram for this VHDL module. Show updates to stored values.

1//oddCount<=0
resetState start1 1//..

0//oddCount<=0 0//..

0//.. prev0

dIn 0//oddCount<=oddCount+1
0//..
1//..

1//..
prev1even prev1odd
1//..

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6. (10 points) Consider the state diagram shown at left below. Fill in the entries in the state
table at right. You may abbreviate the state names as R, G and B.
AB/XY current next
AB XY
01/11 state state
1x/10 red green 11/00 red 00 11 blue
01/00
01 11 green
1x/01 10 10 red
00/11 01/00
x0/00 11 10 red

green 00 00 blue

01 00 red
00/00 blue
10 00 blue

11 00 green

blue 00 00 blue

01 00 red

10 01 green

11 01 green

Consider the state table shown below. Draw a state diagram corresponding to this state
table. Is this state machine a Mealy-mode machine or a Moore-mode machine?
It’s a Mealy-mode state machine.

1/10
up
current next A/XY
A XY
state state 0/10
up 0 10 down 1/01 0/00
1 10 up
0/11
down 0 01 left
left right
1 11 right
1/10
left 0 11 right
1 01 up
right 0 00 up
0/01 1/11
1 10 left
down

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7. (15 points) The VHDL module shown below defines a sequential circuit that looks for the
minimum value present on the input A and counts the number of clock periods when this
minimum value is present. It has two outputs, minVal and minCount. So for example, if the
input sequence on A is 57, 85, 23, 34, 36, 23, 46, 23 then the sequences of values on the two
two outputs will be 57, 57, 23, 23, 23, 23, 23, 23 and 1,1,1,1,1,2,2,3.
entity minValCount is port (
clk, reset: in std_logic;
A : in std_logic_vector(7 downto 0);
minVal, minCount : out std_logic_vector(7 downto 0));
end minValCount;
architecture a1 of minValCount is
signal val, count: std_logic_vector(7 downto 0);
begin
process (clk) begin
if rising_edge(clk) then
if reset = '1' then
val <= x”FF”; count <= x”00”;
else
if A < val then val <= A; count <= x”01”;
elsif A = val then count <= count + 1;
end if;
end if;
end if;
end process;
minVal <= val; minCount <= count;
end a1;
Complete the circuit shown below, so that it implements the VHDL module above. Use only
simple gates and 2:1 multiplexors.

x01
8 bit reg increment
A 1 (count)
1 0 A A+1
0 D
0 x00 1
compare >C
X
X=Y
Y
compare minVal
X
X<Y
Y

8 bit reg
0 (val)
0
D
1
xff 1 minCount
>C
reset
clk

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