National Semiconductor DM74S381 Arithmetic Logic Unit/Function Generator General Description ‘The ‘S961 is Schotky TTL simatic ogi unit (ALUI/ function gnoratr tat performs eight binary arthnot/log- ic operations on two 4-b8 words as shown in tho function tabla. Those operations are selected by tho too functon- select nes (So, $1, 82) Atul cary tokeahoad ore provided for fas, simuitaneous cary generation by moans ‘of two cascade outputs (P and G) for the four bits in the Backago. To mato of cascading 54S182/74S 82 look head cany generators wih theso ALU’ to provide mal level ul cary lookahead stato under ypeal pte tons data for the 'S182. The typical adtion times shown Husate th short dla dna requret for adton of longer ‘word when ul lookahead i employed. The excuse: OR, Features =A fuly paral 4-Bit ALU in 20-pin package for 0:200- inch row spacing 1 Ideally suited for high-density economical processors 1 Parallol inputs and outputs and full look-ahead provide systom flexibility 1 Aiithmetic and logic operations selected specifically 1o ‘simplify system implementation: ‘A minus B B minus A Aplus 8 and five other functions 1= Schotthy-clampod for high performance 16-bit add timo ... 26 ns typ Using look-ahead AND, or OR function of two Boolean variables is provided Seb ad tme .., 4 se Uo wag look anew without the use of extemal circuit. Als, the outputs can be ether cleared (ow) or preset high) as desire. Connection Diagram Pin Designations Dual-in-Line Package eRe ee Fe Designation | PinNos. Function Boe eG ee 43,A2,41,A0_|_17,19,1,3_| Word Alnputs 83,62,61,60 | 16,1624 | Word B Inputs $2,$1,80 7.85 params Carry Input for ‘Addiion, Invert SH o | = | sie woe me oo ‘Subtraction ve ors F3,°2,F1,F0 | 1211.98 | Function Outputs sures iamriceey Order Number DM74S301N F “ ‘See NS Package Number N20A Propagate Output 5 3 seaaioe : eneratod Output Function Table To 2 Supply Votage Selection ‘Arithmetie/Logie ‘GNO 10 Ground se] s1 | 60 Operation L L L CLEAR C L 4 BMINUS A L H L AMINUS 8 L H # ‘APLUSB # L L AeB # L 4 A+B H L 48 4 H # PRESET = Neh va = low toe 9135 tees,$381 Absolute Maximum Ratings qo) Supply Voltage w Input Votage 5sv Operating Free ArTomperatue Range —O'Cto +700 Storage Temperature Range ~85°Cto +1800 Recommended Operating Conditions Note: The “Absolute Maximum Ratings" are those values ‘beyond which the saloty of the device cannot be guaran- teed. The device should not be operated at these limits. The parametric values defined inthe “Electrical Characteristics” {table aro not guarantood at the atssoluto maximum ratings. The “Recommended Operating Condltons” table wil define {the conditions for actual device operation. ‘Symbol Parameter min Nom Max Units Veo Supply Votage 475 5 5.25 v Vin High Love Input Vottage 2 v Vu. Low Level input Voltage 08 v lon High Level Output Gurent [ = mA fou Low Lovel Output Gurent 2 mA Ts Free Ar Operating Temperature 0 70 *c Electrical Characteristics ove: recommended operating free air temperature (unless otherwise noted) yp Symbot Parameter Conditions, win | gee | Mee | Unite vi Input Ciamp Voltage _| Voc = Min = —18 mA n12 v Vou igh Level Output Yoo = Min. ion = Max Vottage Vig = Max, Vin = Min a7 34 v Vou Low Lovet Output Voltage u Di Input Curent @ Max | Voo = Max Vi = 6.5 1 mA Input Votage a High Lovet input ‘anys: 20 Curent on 250 HA ‘Any Other 200) mh Low Level nput Voo=Max | _AnyS ~2 Curent vi=0sv | ~o, a ea ‘Any Othor -6 los ‘Shor Gircut Voc = Max (Note 2) - - m Output Current “ 100 " oe ‘Suppy Current Yoo = Max 105, 160, mA Wote 1 AT Wpals we a Vor = WV. Ta = BFC. Note 2: Not more thn one cout shoud be seria a We, an a rato shou ot exceed one Seco 3196Switching Characteristics at voc = 5v and T, = 25°C (See Section 1 for Test Waveforms and Output Load) R= 200, From (put) = bo Parameter 10 ane ate Le To (Output) S- t6e ae win [wax] win | Max wn Propagation Oey Timo one = | w Low to High Love Oto eye ore Propagetion Delay Time onto 7 ~ | w Hight Low vel Oui, ney oH Propegtion Delay Time nore Low 9 High Level Outpt ‘08 2 emia oe Propageton Delay Time nore wo = lw tight Low Love Opt 8 oH ropageion Delay Time Aare . now Lon Fgh Level Out oF om Propagation Oeay Tine nore 7 a Highto Low Level Outpt oP mH Propagation Delay Time ‘ore 5 a Low Fgh evel Opt woh PH Propagation Delay Tine rery Hig Low evel Outpt to a eae eH Propagaon Delay Tine sto Low High Level Output Any % 2 | va Propagation Delay Time Sto wo = bo. High Low Love Ope ay 3437 teesLogic Diagram oo, 3198