Ordering number : ENN6169

CMOS IC

LC75384NE-R, 75384NW
Electronic Volume and Tone Control
for Car Stereo Systems

Overview • Input switching: The left and right channels can each be
selected from one of 5 inputs. (Four are
The LC75384NE-R and LC75384NW are electronic
single-ended inputs and one is a
volume and tone control ICs that can implement volume,
differential input.)
balance, fader, bass/treble/mid, loudness, input switching,
• Loudness: Taps are output from a 2-dB step volume
and input gain control functions with a minimum number
control ladder resistor starting at the –32-dB
of external components.
position. A loudness function can be
Features implemented by attaching external capacitors
and resistors.
• Volume: 81 positions: from 0 dB to –79 dB in 1-dB steps
• On-chip buffer amplifiers minimize the number of
and –∞.
required external components.
A balance function can be implemented by
• Minimal switching noise when no input signals are
controlling the left and right volume settings
present due to fabrication in a silicon gate CMOS
independently.
process that minimizes the noise generated by internal
• Fader: Either the rear or front outputs can be attenuated
switches.
over 16 positions. (16 positions: From 0 dB to
• Use of zero-cross switching circuits for internal switches
–2 dB in 1-dB steps, from –2 dB to –20 dB in
minimizes switching noise when signals are present.
2-dB steps, from –20 to –30 dB in one 10-dB step,
• Built-in VDD/2 reference voltage generator circuit
–45 dB, –60 dB, and –∞.)
• All controls can be set from serial input data.
• Bass/treble/mid: Control over ±12 dB in 2-dB steps in
each band.
• Input gain: The input signal can be amplified by from
0 dB to +18.75 dB in 1.25-dB steps.

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.

Any and all SANYO products described or contained herein do not have specifications that can handle

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applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51000TH (OT) No.6169-1/25

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 LC75384NE-R, 75384NW

Package Dimensions
unit: mm
3159-QIP64E 3190-SQFP64
[LC75384NE-R] [LC75384NW]
17.2
14.0 1.6 12.0
1.0 1.0 10.0
0.15
1.6

48 33 1.25 0.5 0.18 1.25 0.15

32 48 33
49 49
1.0

32

1.25
14.0
17.2

0.8

10.0
12.0
1.0

0.5
64 17
1 16 17
64
0.8 0.35 0.1

1.7max
1.25
2.7 1 16
3.0max

0.1
0.5 0.5
15.6 0.8
SANYO: QIP64E SANYO: SQFP64E

Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage VDD max VDD 11 V
Maximum input voltage VIN max All input pins VSS – 0.3 to VDD + 0.3 V

Ta ≤ 85°C, when mounted on a printed LC75384NE-R 500

Allowable power dissipation Pd max mW
circuit board LC75384NW 420
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –50 to +125 °C

Allowable Operating Ranges at Ta = 25°C, VSS = 0 V

Ratings
Parameter Symbol Conditions Unit
min typ max
Supply voltage VDD VDD 6.0 10.5 V
Input high-level voltage VIH CL, DI, CE, MUTE 4.0 VDD V
Input low-level voltage VIL CL, DI, CE, MUTE VSS 1.0 V
Input voltage amplitude VIN VSS VDD Vp-p
Input pulse width tøW CL 1 µs
Setup time tsetup CL, DI, CE 1 µs
Hold time thold CL, DI, CE 1 µs
Operating frequency fopg CL 500 kHz

No.6169-2/25
 LC75384NE-R, 75384NW

Electrical Characteristics at Ta = 25°C, VDD = 9 V, VSS = 0 V

Ratings
Parameter Symbol Pins Conditions Unit
min typ max
[Input Block]
Input resistance Rin L1 to L4, R1 to R4 30 50 70 kΩ
Minimum input gain Ginmin L1 to L4, R1 to R4 –1 0 +1 dB
Maximum input gain Ginmax +16.5 +18.75 +21 dB
Inter-step setting error ATerr ±0.6 dB
Left/right balance BAL ±0.5 dB
[Volume Block]
Input resistance Rvr LVRIN, RVRIN, loudness off 113 226 339 kΩ
Inter-step setting error ATerr ±0.5 dB
Left/right balance BAL ±0.5 dB
[Tone Control Block]
Inter-step setting error ATerr ±1.0 dB
Bass control range Gbass max. boost/cut ±9 ±12 ±15 dB
Mid control range Gmid max. boost/cut ±9 ±12 ±15 dB
Treble control range Gtre max. boost/cut ±9 ±12 ±15 dB
Left/right balance BAL ±0.5 dB
[Fader Block]
Input resistance Rfed LFIN, RFIN 25 50 100 kΩ
0 dB to –2 dB ±0.5 dB
–2 dB to –20 dB ±1 dB
Inter-step setting error ATerr
–20 dB to –30 dB ±2 dB
–30 dB to –60 dB ±3 dB
Left/right balance BAL ±0.5 dB

Overall Characteristics
Ratings
Parameter Symbol Conditions Unit
min typ max
THD 1 VIN = –10 dBV, f = 1 kHz 0.004 %
Total harmonic distortion
THD 2 VIN = –10 dBV, f = 10 kHz 0.006 %
Inter-input crosstalk CT VIN = 1 Vrms, f = 1 kHz 80 88 dB
Left/right channel crosstalk CT VIN = 1 Vrms, f = 1 kHz 80 88 dB
VO min 1 VIN = 1 Vrms, f = 1 kHz 80 88 dB
Maximum attenuation
VO min 2 VIN = 1 Vrms, f = 1 kHz, INMUTE, with the fader set to –∞ 90 95 dB
VN 1 All controls flat, with the IHF-A filter 5 10 µV
Output noise voltage
VN 2 All controls flat, with a 20 Hz to 20 kHz bandpass filter 7 15 µV
Current drain IDD 33 40 mA
Input high-level current IIH CL, DI, CE, VIN = 9 V 10 µA
Input low-level current IIL CL, DI, CE, VIN = 0 V –10 µA
Maximum input voltage VCL THD = 1 %, RL = 10 kΩ, all controls flat, fIN = 1 kHz 2.5 2.9 Vrms
Common-mode rejection ratio CMRR VIN = 0 dBV, f = 1 kHz 45 dB

No.6169-3/25
 LC75384NE-R, 75384NW

[LC75384NE-R] [LC75384NW]
Pd max — Ta Pd max — Ta
1400 1.4
Printed circuit board size: 114.3 × 76.1 × 1.6 mm3
Allowable power dissipation, Pdmax — mW

Printed circuit board: 114.3 × 76.2 × 1.5 mm3

Allowable power dissipation, Pdmax — W

Mounted on the printed circuit board Printed circuit board material: Fiberglass/epoxy
1200 1.2
Mounted on the stipulated printed circuit board
1.04
1000 1.0

800 0.8
Independent IC

600 0.6
Independent IC
0.50

400 0.4 0.42

200 0.2 0.20

0 0
–40 –20 0 20 40 60 80 100 –20 0 20 40 60 80 100
Ambient temperature, Ta — °C Ambient temperature, Ta — °C

Pin Assignment
LVROUT

LTOUT
LSELO

LF1C1
LF1C2
LF1C3
LF2C1
LF2C2
LF2C3
LF3C1
LF3C2
LF3C3
LVRIN

LCOM

LTIN
LCT

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

L5P 49 32 LFIN

L5M 50 31 LFOUT

L4 51 30 LROUT

L3 52 29 LAVSS

L2 53 28 LZCLP

L1 54 27 DVSS

LVref 55 26 CL

VDD 56 LC75384NE-R 25 DI

Vref 57 24 CE

RVref 58
LC75384NW 23 MUTE

R1 59 22 RAVSS

R2 60 21 RZCLP

R3 61 20 TIM

R4 62 19 RROUT

R5M 63 18 RFOUT

R5P 64 17 RFIN

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(Top view)
RF1C1
RTIN
RVRIN
R CT

RVROUT
RSE LO

RCOM

RF1C3
RF2 C1

RF3C1

RTOUT
RF2 C3

RF3C3
RF1C2

RF3C2
RF2 C2

No.6169-4/25
 68 kΩ 4.7 kΩ 0.1 µF
1 MΩ [BASS fo = 100 Hz] [MID fo = 1000 Hz] [TREBLE fo = 10000 Hz]

220 pF

1 µF
µF
0.033
µF
0.1
µF
0.0033
µF
0.01

10 µF
330 pF
1µF

LVref
10 µF

LTIN

LVRIN

LVref
LF1C1
LF1C2
LF1C3
LF2C1
LF2C2
LF2C3
LF3C1
LF3C2
LF3C3

LCT

LSELO
LTOUT

LVROUT

10 µF LCOM
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 µF × 6
L5P LFIN
49 32
L5M LFOUT 10 µF
50 31 PA

LVref
L4 LVref LVref LVref LROUT
51 30 PA

L3 LVref LAVSS 10 µF
52 29

LVref
L2
53 28 LZCLP

L1 DVSS

LVref
54 27

10 µF LVref CL
55 Multiplexer ZERO CROSS DET 26 CL
CCB DI
VDD 56 25 DI µCOM
CONTROL INTERFACE
Vref LOGIC CIRCUIT CE
22 µF CIRCUIT VDD
57 24 CE
10 µF RVref MUTE
58 Multiplexer ZERO CROSS DET 23 47 kΩ
Equivalent Circuit and Sample Application Circuit Diagram

R1 RAVSS
59 22 VDD
LC75384NE-R, 75384NW

R2

RVref
60
NO SIGNAL 21 RZCLP 1 MΩ
TIMER
R3 TIM

RVref
61 20
RVref 0.033 µF
R4 RROUT
62 19 PA
RVref RVref RVref
R5M RFOUT 10 µF
63 18 PA
RVref

R5P RFIN 10 µF

• In the LC75384NW version, LZCLP (pin 28) and RZCLP (pin 21) are unused, and must be left open.
64 17

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

RCT
RTIN

RVRIN
RF1C1
RF1C2
RF1C3
RF2C1
RF2C2
RF2C3
RF3C1
RF3C2
RF3C3

RSELO
RTOUT

RVref
10 µF

RVROUT
1 µF

RVref
µF
µF

µF
µF
0.1

RCOM 10 µF
220 pF
0.01

1 µF

10 µF
0.033

0.1 µF
0.0033
330 pF

1 MΩ [BASS fo = 100 Hz] [MID fo = 1000 Hz][TREBLE fo = 10000 Hz]

68 kΩ 4.7 kΩ

No.6169-5/25
 LC75384NE-R, 75384NW

Pin Functions
Pin No. Pin Function Notes

54 L1 VDD
53 L2
52 L3
51 L4
• Single end inputs
59 R1
60 R2
61 R3 LVref
62 R4 RVref
VDD
M
50 L5M
49 L5P
• Differential inputs
63 R5M VDD
64 R5P
P
LVref
RVref
VDD

48 LSEL0
• Input selector outputs
1 RSEL0

VDD

47 LVRIN • Inputs for the 2-dB step volume control

2 RVRIN • These inputs must be driven from low-impedance circuits.

LVref
RVref
VDD
• Loudness function pins. Connect the high-band
46 LCT compensation RC circuits between the LCT (RCT) and the
LVRIN (RVRIN) pins and connect the low-band
3 RCT compensation RC circuits between the LCT (RCT) and
LVREF (RVREF).

• 2-dB step volume control outputs VDD

45 LCOM
• To reduce switching noise, each of these pins should be
4 RCOM
connected to LVREF (RVREF) through a capacitor.

VDD
44 LVROUT
• Output from the 1-dB step volume control
5 RVROUT

Continued on next page.

No.6169-6/25
 LC75384NE-R, 75384NW

Continued from preceding page.

Pin No. Pin Function Equivalent circuit

VDD

43 LTIN
• Equalizer input
6 RTIN

LVref
RVref
42 LF1C1 • Connections for the capacitors for the equalizer’s F1 band
41 LF1C2 filter.
40 LF1C3 The low band compensation capacitors must be connected
7 RF1C1 between the following pins:

8 RF1C2 LF1C1 (RF1C1) and LF1C2 (RF1C2)

LF1C2 (RF1C2) and LF1C3 (RF1C3)
C2
9 RF1C3
C3
39 LF2C1 • Connections for the capacitors for the equalizer’s F2 band
38 LF2C2 filter.
37 LF2C3 The low band compensation capacitors must be connected LVref
10 RF2C1 between the following pins: RVref
11 RF2C2 LF2C1 (RF2C1) and LF2C2 (RF2C2)

12 RF2C3 LF2C2 (RF2C2) and LF2C3 (RF2C3) VDD

36 LF3C1 • Connections for the capacitors for the equalizer’s F3 band C1
35 LF3C2 filter.
34 LF3C3 The low band compensation capacitors must be connected
13 RF3C1 between the following pins:

14 RF3C2 LF3C1 (RF3C1) and LF3C2 (RF3C2)

15 RF3C3 LF3C2 (RF3C2) and LF3C3 (RF3C3)

VDD
33 LTOUT
• Equalizer output
16 RTOUT

VDD
32 LFIN • Fader block inputs
17 RFIN • These inputs must be driven from low-impedance circuits.

VDD
31 LFOUT
• Fader block outputs. The front and rear outputs can be
30 LROUT
attenuated independently. The attenuation is the same in
18 RFOUT the left and right channels.
19 RROUT

• VDD/2 voltage generator block. A capacitor with a value of VDD

57 Vref about 10 µF must be inserted between Vref and AVSS (VSS)
to reduce power supply ripple.

• Internal analog system ground

55 LVref
• These pins must be handled as shown in the sample
58 RVref
application circuit.
LVref
RVref

Continued on next page.

No.6169-7/25
 LC75384NE-R, 75384NW

Continued from preceding page.

Pin No. Pin Function Equivalent circuit

56 VDD • Power supply

27 DVSS • Logic system ground

29 LAVSS
• Analog system ground
22 RAVSS

LC75384NE-R
VDD
• Band limiting for the zero cross detection circuit
28 LZCLP • These pins are normally left open.
21 RZCLP • These pins are unused in the LC75384NW version and
must be left open.
LVref
RVref

VDD
• External muting control
23 MUTE • When this pin is set to the VSS level, the fader volume block
is forcibly set to –∞.

• Used for the zero cross circuit no-signal timer function. VDD
20 TIM If a zero cross signal does not occur between the point
when data is loaded and the point when the timer times out,
the data will be stored forcibly when the timer times out.

26 CL
• Serial data and clock inputs used for device control
25 DI VDD

• Chip enable input. Data is written to the internal latch when

this pin goes from high to low. The analog switches then
24 CE operate.
Data transfers are enabled when this pin is high.

No.6169-8/25
 LC75384NE-R, 75384NW

Internal Equivalent Circuits

Selector Block Equivalent Circuit

R3 = 22.65 k
L5P
LSELO
R4 = 25 k
LVref 0dB
L5M R2 = 25 k 6.702 k
R1 = 22.65 k 1.25dB
5.804 k
L4 2.50dB
50 k 5.026 k
3.75dB
LVref 4.532 k
L3 5.00dB
50 k 3.769 k
6.25dB
LVref 3.264 k
L2 7.50dB
50 k 2.826 k
8.75dB
LVref 2.447 k
L1 10.0dB
50 k 2.119 k
11.25dB
LVref INMUTE SW 1.835 k
12.5dB
1.589 k
13.75dB
LVref 1.376 k
15.0dB
Total resistance: 50 kΩ 1.192 k
16.25dB
1.032 k
The right channel is identical.
Unit (Resistance: Ω) 17.5dB
0.894 k
18.75dB
5.774 k

LVref

No.6169-9/25
 LC75384NE-R, 75384NW

2-dB Step Volume Control Block Equivalent Circuit

LVRIN
0dB To the left
41.139 k channel 1-dB
-2dB step block
32.678 k
-4dB
25.957 k
-6dB
20.618 k
-8dB
16.378 k
-10dB
• The total resistance above the 13.009 k
tap is 195 kΩ -12dB
10.334 k
-14dB
8.208 k
-16dB
6.520 k
-18dB
5.179 k
-20dB
4.114 k
-22dB
3.268 k
-24dB
2.596 k
-26dB
2.062 k
-28dB
1.638 k
-30dB
1.301 k The right channel is identical.
LCT -32dB Unit (Resistance: Ω)
6.344 k
-34dB
5.040 k
5.750 k -36dB
4.003 k
-38dB
3.180 k
-40dB
2.526 k
-42dB
2.006 k
-44dB
1.594 k
-46dB
1.266 k
• The total resistance below -48dB
the tap is 30.847 kΩ 1.006 k
-50dB
0.799 k
-52dB
0.634 k
-54dB
0.504 k
-56dB
0.400 k
-58dB
0.318 k
-60dB
0.253 k
-62dB
0.201 k
-64dB
0.159 k
-66dB
0.127 k
-68dB
0.101 k
-70dB
0.080 k
-72dB
0.063 k
-74dB
0.050 k
-76dB
0.040 k
-78dB
0.154 k
-∞ dB

LVref

No.6169-10/25
 LC75384NE-R, 75384NW

1-dB Step Volume Control Block Equivalent Circuit

From the left channel

2-dB volume control
block LVROUT
0 dB
5.438 k
-1 dB
Switch used for initial setup 44.564 k
-∞ dB
Vref Unit: (Resistance : Ω)
Switch used for initial setup Total resistance: 50 kΩ
The right channel is identical.
LCOM

Three-Band Graphic Equalizer Block Equivalent Circuit Diagram

LTIN
50 k 5.1 k LTOUT

LVref 5.1 k

0.711 k 0.711 k 0.711 k

12 dB 12 dB 12 dB
0.648 k 0.648 k 0.648 k
10 dB 10 dB 10 dB
1.015 k 1.015 k 1.015 k
8 dB 8 dB 8 dB
1.751 k 1.751 k 1.751 k
6 dB 6 dB 6 dB
3.595 k 3.595 k 3.595 k
4 dB 4 dB 4 dB
10.977 k 10.977 k 10.977 k
68 k

68 k

68 k
LVref

LVref

LVref
1k
1k

1k
LVref

LVref

LVref

LF1C1 LF1C2 LF1C3 LF2C1 LF2C2 LF2C3 LF3C1 LF3C2 LF3C3

Unit: (Resistance : Ω)

No.6169-11/25
 LC75384NE-R, 75384NW

The external capacitors C1 and C2 used with the LC75384W form the structural element of the simulated inductor
implemented by the IC. This section present the equivalent circuit and the method for calculating the constants required
to obtain the desired center frequency.

(A) Simulated inductor equivalent circuit

R3
+
–

R3 C1 R1
CUT BOOST R1 = 1 kΩ
C2 – R2 = 68 kΩ
R4 + R3 = 5.1 kΩ
R2
Zo: Impedance at resonance Zo

(B) Calculation

Specifications: 1. Center frequency: F0 = 100 Hz

2. Q at maximum boost: Q+12dB = 0.9

1. Determine the sharpness, Q0, of the simulated inductor itself.

(R1 + R4)
Q0 = × Q+12dB ≈ 1.5399
R1

2. Determine C1.

C1 = 1/2πF0R1Q0 ≠ 1 (µF)

3. Determine C2.

C2 = Q0/2πF0R2 ≠ 0.036 (µF)

Note: * See the equivalent circuit diagram for the tone control block on page 11 for details on the internal resistor.

No.6169-12/25
 LC75384NE-R, 75384NW

Fader Volume Control Block Equivalent Circuit

S1
LFIN
LFOUT
0dB
5.437 k S2
-1dB S3
4.846 k
-2dB S4 LROUT
8.169 k
-4dB
6.489 k
-6dB
5.154 k
-8dB When FADER is set to 1, S2 and S3 will be turned on.
4.094 k When FADER is set to 0, S1 and S4 will be turned on.
-10dB
3.252 k
-12dB
2.583 k
-14dB
2.052 k
-16dB
1.630 k
-18dB
1.295 k
-20dB
3.419 k
-30dB
1.300 k
-45dB
0.231 k
-60dB
0.050 k Unit: (Resistance : Ω)
Total resistance: 50 kΩ
-∞ dB

LVref

If data that sets the main volume control 1-dB step circuit to –∞ is sent to the device, switches S1
and S2 will be opened (off) and switches S3 and S4 will be closed (on).

No.6169-13/25
 LC75384NE-R, 75384NW

Control System Timing and Data Format

The LC75384NE-R/NW are controlled by applying the stipulated data to the CL, DI, and CE pins. The data consists of a
total of 52 bits, of which 8 bits are the device address and 44 bits are the actual control data.

CE

DI B0 B1 B2 B3 A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D38 D39 D40 D41 D42 D43

CL

CE 1 µs 1 µs 1 µs 1 µs
min min min min

1 µs
min
CL

DI

1 µs ≤ TDEST

• Address code (B0 to A3)

The LC75384NE-R/NW have an 8-bit address codes, and can be used along with other ICs that support the Sanyo CCB
serial bus.
Address code

(LSB) B0 B1 B2 B3 A0 A1 A2 A3 (81HEX)
1 0 0 0 0 0 0 1

• Control code allocation

Input switching control

D0 D1 D2 Setting
0 0 0 L1 (R1)
1 0 0 L2 (R2)
0 1 0 L3 (R3)
1 1 0 L4 (R4)
0 0 1 L5 (R5)
0 1 1 IC test values. These values must not
1 1 1 be used during normal operation.

D3 IC test bit. This bit must be set to 0 during normal operation.

No.6169-14/25
 LC75384NE-R, 75384NW

Input gain control

D4 D5 D6 D7 Operation
0 0 0 0 0 dB
1 0 0 0 +1.25 dB
0 1 0 0 +2.50 dB
1 1 0 0 +3.75 dB
0 0 1 0 +5.00 dB
1 0 1 0 +6.25 dB
0 1 1 0 +7.50 dB
1 1 1 0 +8.75 dB
0 0 0 1 +10.0 dB
1 0 0 1 +11.25 dB
0 1 0 1 +12.5 dB
1 1 0 1 +13.75 dB
0 0 1 1 +15.0 dB
1 0 1 1 +16.25 dB
0 1 1 1 +17.5 dB
1 1 1 1 +18.75 dB

No.6169-15/25
 LC75384NE-R, 75384NW

Volume Control

D8 D9 D10 D11 D12 D13 D14 D15 Operation

1-dB step
0 0 dB
1 –1 dB
2-dB step
0 0 0 0 0 0 0 0 dB
1 0 0 0 0 0 0 –2 dB
0 1 0 0 0 0 0 –4 dB
1 1 0 0 0 0 0 –6 dB
0 0 1 0 0 0 0 –8 dB
1 0 1 0 0 0 0 –10 dB
0 1 1 0 0 0 0 –12 dB
1 1 1 0 0 0 0 –14 dB
0 0 0 1 0 0 0 –16 dB
1 0 0 1 0 0 0 –18 dB
0 1 0 1 0 0 0 –20 dB
1 1 0 1 0 0 0 –22 dB
0 0 1 1 0 0 0 –24 dB
1 0 1 1 0 0 0 –26 dB
0 1 1 1 0 0 0 –28 dB
1 1 1 1 0 0 0 –30 dB
0 0 0 0 1 0 0 –32 dB
1 0 0 0 1 0 0 –34 dB
0 1 0 0 1 0 0 –36 dB
1 1 0 0 1 0 0 –38 dB
0 0 1 0 1 0 0 –40 dB
1 0 1 0 1 0 0 –42 dB
0 1 1 0 1 0 0 –44 dB
1 1 1 0 1 0 0 –46 dB
0 0 0 1 1 0 0 –48 dB
1 0 0 1 1 0 0 –50 dB
0 1 0 1 1 0 0 –52 dB
1 1 0 1 1 0 0 –54 dB
0 0 1 1 1 0 0 –56 dB
1 0 1 1 1 0 0 –58 dB
0 1 1 1 1 0 0 –60 dB
1 1 1 1 1 0 0 –62 dB
0 0 0 0 0 1 0 –64 dB
1 0 0 0 0 1 0 –66 dB
0 1 0 0 0 1 0 –68 dB
1 1 0 0 0 1 0 –70 dB
0 0 1 0 0 1 0 –72 dB
1 0 1 0 0 1 0 –74 dB
0 1 1 0 0 1 0 –76 dB
1 1 1 0 0 1 0 –78 dB
Mute
1 1 1 1 1 1 0 –∞

No.6169-16/25
 LC75384NE-R, 75384NW

Three-band equalizer control

D16 D17 D18 D19 f1 band

D20 D21 D22 D23 f2 band
D24 D25 D26 D27 f3 band
0 1 1 0 +12 dB
1 0 1 0 +10 dB
0 0 1 0 +8 dB
1 1 0 0 +6 dB
0 1 0 0 +4 dB
1 0 0 0 +2 dB
0 0 0 0 0 dB
1 0 0 1 –2 dB
0 1 0 1 –4 dB
1 1 0 1 –6 dB
0 0 1 1 –8 dB
1 0 1 1 –10 dB
0 1 1 1 –12 dB

Fader Volume Control

D28 D29 D30 D31 Operation

0 0 0 0 0 dB
1 0 0 0 –1 dB
0 1 0 0 –2 dB
1 1 0 0 –4 dB
0 0 1 0 –6 dB
1 0 1 0 –8 dB
0 1 1 0 –10 dB
1 1 1 0 –12 dB
0 0 0 1 –14 dB
1 0 0 1 –16 dB
0 1 0 1 –18 dB
1 1 0 1 –20 dB
0 0 1 1 –30 dB
1 0 1 1 –45 dB
0 1 1 1 –60 dB
1 1 1 1 –∞

Channel Selection Control

D32 D33 Setting

0 0 Left and right together. This is the mode set up initially
1 0 RCH
0 1 LCH
1 1 Left and right together

Fader Rear/Front Control

D34 Setting
0 Rear
1 Front

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Loudness Control

D35 Setting
0 Off
1 On

Zero Cross Control

D36 D37 Setting

0 0 Data is written when a zero cross is detected
1 1 The zero cross detection operation is disabled and data is written on the falling edge of the CE signal

Zero Cross Signal Detection Block Control

D38 D39 D40 D41 Setting

0 0 0 0 Selector
1 0 0 0 Volume
0 1 0 0 Tone
1 1 0 0 Fader

Test Mode Control

D42 D43 Setting

0 0 These IC test mode control bits must be set to 0

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Usage Notes

Data Transmission after Power Is First Applied

• When power is first applied, the state of the internal analog switches will be undefined. Applications that use this IC
must include external circuits to provide muting until control data has been transferred to the IC.
• After power is first applied, applications should send initial setup data to stabilize the bias levels in each of the IC
circuit blocks in a short time.

1. The time between initial setup mode and the first actual data settings
• Applications should send the initial setup data as soon as VDD rises above 6 V.
• After the LCOM and RCOM pins have stabilized at the Vref level, applications should set the initial data.

The time required for the capacitors connected to the LCOM

and RCOM pins to be charged to the Vref level

The 1/2 VDD level

VREF
VDD = 9 V (TYP)

VDD = 6 V
VDD

Data

First data for

Initial setup First data for
the right
mode the left channel
channel

These operations
clear initial setup
mode

2. Procedure for setting up initial setup mode

• When D32 and D33 are set to 00, the IC’s internal initial setup switch is turned on and the IC goes to quick charge
mode. At this time the other data (D0 to D31 and D34 to D43) will also be set up for the left and right channels at the
same time. This means that applications can set up the states of the various blocks at the same time as specifying initial
setup mode.

3. Procedure for clearing initial setup mode

• Initial setup mode is cleared by setting D32 and D33 to any value other than 00. In other words, any normal left or
right channel specification will turn the internal initial setup switch off and clear quick charge mode.

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Zero Cross Switching Circuit Operating Principles

• The LC75384NE-R/NW include functions for switching the place where the zero cross comparator operates and thus
allows applications to select the optimal detection location for the block for which the control data is updated.
Basically, switching noise will be minimized if the signal immediately following the block for which the control data is
updated is input to the zero cross comparator. Thus the detection location must be changed for each data update
operation. Another issue is the point that if the signal amplitude is lower than the detection sensitivity (a few mV rms)
of the zero cross comparator (for example if the volume is set to a low level), the switching noise can be minimized
further by selecting a point before the volume control block, namely the selector block output, as the zero cross
detection point than by simply waiting for the data write to occur due to the overflow of the zero cross timer. For
example, if the volume block input is 1 V rms, and the volume is set to –40 dB or lower, the output will be under
10 mV rms. In this case, detecting at the selector output block will result in lower switching noise.

Selector Volume Tone Fader

Switch

Zero cross
comparator

Zero Cross Detection Circuit

Zero Cross Switching Control Procedure
• The zero cross switching control procedure consists of first setting the zero cross detection mode with the zero cross
control bits (D36 and D37 = 0) and then, after specifying the detection block (with bits D38, D39, D40, and D41),
sending the control data. Since these control bits are latched first immediately after the data is sent, i.e. on the falling
edge of the CE signal, it is possible to both set the IC mode as well as specify zero cross switching operation in a single
data transfer, even when updating the volume and other data. The following presents an example of the control
operation when updating the volume block data.

D36 D37 D38 D39 D40 D41

0 0 1 0 0 0

Zero cross detection Volume block setting

mode specification

Zero Cross Timer Setting

• When the input signal has a level lower than the detecting sensitivity of the zero cross comparator, or consists only of
extremely low frequencies, the zero cross detection circuit will remain in the state in which it cannot detect a zero cross
and the data will not be latched during that period. The zero cross timer specifies a time after which the data will be
latched forcibly in states where a zero crossing cannot be detected. The time is determined by the lowest frequency for
which a zero cross can be detected reliably.

For example, if the timer is set to 25 ms:

T = 0.69 CR
If C is taken to be 0.033 µF, then R will be:
25 × 10-3
R= ≈ 1.1 MΩ
0.69 × 0.033 × 10-6

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Notes on Serial Data Transfer

1. The CL, DI, and CE pin signal lines must be covered (and thus shielded) by the ground pattern or formed from
shielded cable to prevent the high-frequency digital signals on those lines from entering the analog system.
2. The LC75384NE-R/NW data formats consist of 8 bits of address and 44 bits of data. When the data is sent in units of
8 bits each (i.e. 48 bits are actually sent), use the data transfer technique shown in figure 1.

LC75384NE-R/NW data receptions in 8-bit units

X X X X D0 D1 D2 D3 ....... D36 D37 D38 D39 D40 D41 D42 D43

Dummy data Input switching control Test mode control

X: don't care

3. During CCB transfers, this IC detects address matches on the rising edge of the CE signal. Therefore, applications
must set the CL signal low and then set it high at this time.

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Output Level Characteristics

20
VDD = 9 V, VSS = 0 V, VIN = 0 dBV
Flat overall
Input = L1, Output = LFOUT
Settings: the 0 dB to –54 dB positions (in –2 dB steps)
10

0
0
-2
-4
-6
-8
-10
-10
-12
-14
-16
Level — dB

-18
-20
-20 -22
-24
-26
-28
-30
-30 -32
-34
-36
-38
-40
-40
-42
-44
-46
-48
-50
-50
-52
-54

-60
10 2 3 5 7 100 2 3 5 7 1k 2 3 5 7 10 k 2 3 5 7 100 k

Frequency, f — Hz

Loudness Characteristics
20
VDD = 9 V, VSS = 0 V, VIN = 0 dBV
Flat overall
Input = L1, Output = LFOUT
Settings: the 0 dB to –54 dB positions (in –2 dB steps)
10

0
0
-2
-4
-6
-8
-10
-10
-12
Output level — dBV

-14
-16
-18
-20
-20
-22
-24
-26
-28
-30 -30
-32
-34
-36
-38
-40 -40
-42
-44
-46
-48
-50 -50
-52
-54

-60
10 2 3 5 7 100 2 3 5 7 1k 2 3 5 7 10 k 2 3 5 7 100 k

Frequency, f — Hz

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Main Volume Step Characteristics Gain Step Characteristics

0 20
VDD = 9 V VDD = 9 V
-10 18
VSS = 0 V VSS = 0 V
VIN = 0 dBV 16 VIN = –20 dBV
-20
f = 1 kHz f = 1 kHz
14
-30

Output level — dB
Attenuation — dB

12
-40
10
-50
8
-60
6

-70 4

-80 2

-90 0
-∞ -70 -60 -50 -40 -30 -20 -10 0 0 2 4 6 8 10 12 14 16 18 20

Step — dB Step — dB
Graphic equalizer block

Graphic equalizer block

Main volume block
Main volume block
Input gain block

Input gain block

Fader block
Fader block

V V

Fader Volume Step Characteristics THD – Frequency Characteristics

0 1.0
7
VDD = 9 V VDD = 9 V, VSS = 0 V, VIN = –10 dBV
5
-10 VSS = 0 V
Total harmonic distortion, THD — %

Input = L1, Output = LFOUT

3
Fader volume attenuation — dB

VIN = 0 dBV 80-kHz low pass weighting

2
-20 f = 1 kHz
0.1
-30 7
5
-40 3
2
-50
0.01
7
-60 5
3
-70
2

-80 0.001
-∞ -70 -60 -50 -40 -30 -20 -10 0 10 2 3 5 7100 2 3 5 71 k 2 3 5 7 10 k 2 3 5 7 100 k
Step — dB Frequency, f — Hz
Graphic equalizer block

Graphic equalizer block

THD
Main volume block

Main volume block

Input gain block

Input gain block

METER
Fader block

Fader block

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THD – Input Level Characteristics THD – Supply Voltage Characteristics

1.0 1.0
7 VDD = 9 V, VSS = 0 V 7 VSS = 0 V
5 80-kHz low pass weighting 5

Total harmonic distortion, THD — %

80-kHz low pass weighting
Total harmonic distortion, THD — %

3 With VR set to the 0 dB position 3

2 2

0.1 0.1 VI
7 7 N=0
5 f= V dBV
20 5
IN = VI ,f=
kH N = -1 20 k
3 f= z 3 0d 0 Hz
2 1k BV dBV
Hz
2
V ,f , f = 20
IN = =1 kHz
0.01 0.01 -10 kH
7 7 dB z
5 5 V,
f=
3 3 1k
2 2 Hz
0.001 0.001
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 4 5 6 7 8 9 10 11 12 13
Input level, VIN — dBV Supply voltage — V

Graphic equalizer block

Graphic equalizer block

THD THD
Main volume block

Main volume block

Input gain block
Input gain block

METER METER

Fader block
Fader block

F1 Band Characteristics F2 Band Characteristics

0 0
VDD = 9V,VSS = 0V,VIN = –20dBV VDD = 9V,VSS = 0V,VIN = –20dBV
-5 Input = L1, Output = LF OUT -5 Input = L1, Output = LF OUT

-10 -10

-15 -15
Level — dB

Level — dB

-20 -20

-25 -25

-30 -30

-35 -35

-40 -40
10 2 3 5 7100 2 3 5 7 1k 2 3 5 7 10k 2 3 5 7100k 10 2 3 5 7100 2 3 5 7 1k 2 3 5 7 10k 2 3 5 7100k
Frequency — Hz Frequency — Hz
F3 Band characteristics
0
VDD = 9V,VSS = 0V,VIN = –20dBV
-5 Input = L1, Output = LF OUT

-10
Level — dB

-15

-20

-25

-30

-35

-40
10 2 3 5 7100 2 3 5 7 1k 2 3 5 710k 2 3 5 7100k
Frequency — Hz

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 LC75384NE-R, 75384NW

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

This catalog provides information as of May, 2000. Specifications and information herein are subject to
change without notice.

PS No.6169-25/25