FPGA Training Course

Eng. Moustafa Ali

Mentronix
Application Engineer
 Agenda
Technology
• 1‐FPGA
1 FPGA Overview
• 2‐VHDL Overview
• 3
3‐Timing
Timing Optimization
• 4‐Area Optimization
• 5
5‐Architecting
Architecting Power
• 6‐High Level Design
• 7
7‐Clock
Clock Domains
omains
• 8‐Sythesis Optimization
• 9‐Static Timingg Analysis
y
 Agenda
Technology
• 1‐FPGA
1 FPGA Overview
• 2‐VHDL Overview
• 3
3‐Timing
Timing Optimization
• 4‐Area Optimization
• 5
5‐Architecting
Architecting Power
• 6‐High Level Design
• 7
7‐Clock
Clock Domains
omains
• 8‐Sythesis Optimization
• 9‐Static Timingg Analysis
y
FPGA overview
Memory Cell
Slice
 COUT
YB
Y

G4 I4 Look‐Up Carry D S Q YQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
G1 I1 R Each slice has two
identical
F5IN logic cells (LC)
BY
SR
CLK
CE

XB
X

G4 I4 Look‐Up Carry D S Q XQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
C A Configurable
g Logic
g Block
G1 I1 R
(CLB) has two
identical slices

BX
CIN
Spartan‐II CLB Slice
 COUT
YB
Y

G4 I4 Look‐Up Carry D S Q YQ
G3 I3 Table and A logic cell has a
O CK
G2 I2 Control 4i
4‐inputt function
f ti generator,t
Logic EC
G1 I1 R carry logic and an
storage element.
F5IN
BY The output from the
SR function generator
CLK
CE drives the CLB output
and the D input of
XB
X
the flip‐flop.

G4 I4 Look‐Up Carry D S Q XQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
C A CLB also contains logic to
G1 I1 R
combine function generators
to provide functions of five
or six inputs.
BX
CIN
Spartan‐II CLB Slice
 COUT
YB
Y

G4 I4 Look‐Up Carry D S Q YQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
G1 I1 R The storage element
can be configured as:
F5IN • edge‐triggered
edge triggered D flip‐flop
flip flop
BY • level‐sensitive latch.
SR
CLK
CE

XB
X

G4 I4 Look‐Up Carry D S Q XQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
C
G1 I1 R

BX
CIN
Spartan‐II CLB Slice
 COUT
YB
Y

G4 I4 Look‐Up Carry D S Q YQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
G1 I1 R The D input can be driven
by the function generator
F5IN or directly from the slice
BY inputs.
SR
CLK
CE

XB
X

G4 I4 Look‐Up Carry D S Q XQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
C
G1 I1 R

BX
CIN
Spartan‐II CLB Slice
 COUT
YB
Y

G4 I4 Look‐Up Carry D S Q YQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
G1 I1 R The D input can be driven
by the function generator
F5IN or directly from the slice
BY inputs.
SR
CLK
CE

XB
X

G4 I4 Look‐Up Carry D S Q XQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
C
G1 I1 R

BX
CIN
Spartan‐II CLB Slice
 COUT
YB
Y

G4 I4 Look‐Up Carry D S Q YQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
G1 I1 R
The FF receive the same
F5IN clock signal.
signal
BY
SR
CLK
CE

XB
X

G4 I4 Look‐Up Carry D S Q XQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
C
G1 I1 R

BX
CIN
Spartan‐II CLB Slice
 COUT
YB
Y

G4 I4 Look‐Up Carry D S Q YQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
G1 I1 R
Each slice has synchronous
set and reset signals
F5IN
BY
SR
CLK
SR forces a storage
CE element into
the initialization state
XB
X specified for it
in the configuration
G4 I4 Look‐Up Carry D S Q XQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
C
G1 I1 R

BX
CIN
Spartan‐II CLB Slice
 COUT
YB
Y

G4 I4 Look‐Up Carry D S Q YQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
G1 I1 R
Each slice has synchronous
set and reset signals
F5IN
BY
SR
CLK
SR forces a storage
CE element into
the initialization state
XB
X specified for it
in the configuration
G4 I4 Look‐Up Carry D S Q XQ
G3 I3 Table and
O CK
G2 I2 Control
Logic EC
C BY forces it
G1 I1 R
into the opposite
state.
BX
CIN
Spartan‐II CLB Slice
SR and BY can be configured to work asynchronously.
 IO Block
T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR
• • Bi &
Bias
ESD Network
P k
Package Pi
Pin

•
SR
O D Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q
Programmable • Package Pin
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
 IOB Registers may be:
• edge‐triggered D‐type flip‐flops
• level‐sensitive
level sensitive latches
T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR
• • Bi &
Bias
ESD Network
P k
Package Pi
Pin

•
SR
O D Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q
Programmable • Package Pin
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
The three registers share a The SR input can be • synchronous Set
Set/Reset (SR) line. independently configured • synchronous Reset
in each register as: • asynchronous Preset
• asynchronous Clear
T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR • • Bi &
Bias P k
Package Pi
Pin
ESD Network

O • D
SR
Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q • Package Pin
Programmable
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
 Input Path: The IOB routes an input signal either directly
or through an optional input flip‐flop.

T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR
• • Bi &
Bias
ESD Network
P k
Package Pi
Pin

•
SR
O D Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q
Programmable • Package Pin
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
 Input Path: The IOB routes an input signal either directly
or through an optional input flip‐flop.

T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR
• • Bi &
Bias
ESD Network
P k
Package Pi
Pin

•
SR
O D Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q
Programmable • Package Pin
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
 Input Path: The optional delay eliminates pad‐to‐pad hold time.
The delay matches the internal clock distribution delay of the FPGA,
assuringg that the pad‐to‐pad
p p hold time is zero.
T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR • • Bi &
Bias P k
Package Pi
Pin
ESD Network

•
SR
O D Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q
Programmable • Package Pin
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
 Output path: a three‐state output buffer drives the signal onto the pad.

T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR • • Bi &
Bias P k
Package Pi
Pin
ESD Network

•
SR
O D Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q • Package Pin
Programmable
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
 Output path: the output signal can be routed directly to the buffer
or through an optional IOB output flip‐flop.

T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR
• • Bi &
Bias
ESD Network
P k
Package Pi
Pin

•
SR
O D Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q
Programmable • Package Pin
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
 Output path: the output signal can be routed directly to the buffer
or through an optional IOB output flip‐flop.

T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR
• • Bi &
Bias
ESD Network
P k
Package Pi
Pin

•
SR
O D Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q
Programmable • Package Pin
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
 Output path: the three‐state control of the output
can also be routed directly to the buffer
or through an optional IOB output flip‐flop.
flip flop
T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR
• • Bi &
Bias
ESD Network
P k
Package Pi
Pin

•
SR
O D Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q
Programmable • Package Pin
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
 Output path: the three‐state control of the output
can also be routed directly to the buffer
or through an optional IOB output flip‐flop.
flip flop
T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR
• • Bi &
Bias
ESD Network
P k
Package Pi
Pin

•
SR
O D Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q
Programmable • Package Pin
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
 All pads are protected against damage from electrostatic discharge (ESD)
and from over‐voltage transients.

T •
•
SR Package
D Q
Pin
CLK • CK
TCE EC VCC
TFF
Programmable
SR
• • Bi &
Bias
ESD Network
P k
Package Pi
Pin

•
SR
O D Q Programmable
• CK ff
Output Buffer Internal
Reference
OCE EC
OFF

Programmable
IQ Delay

I • D
SR
Q
Programmable • Package Pin
CK I
Input
t Buffer
B ff
ICE EC
IFF
To Next I/O

To Other
External VREF Inputs
Spartan‐II Input/Output Block (IOB) of Bank
IO Block
 Agenda
Technology
• 1‐FPGA
1 FPGA Overview
• 2‐VHDL Overview
• 3
3‐Timing
Timing Optimization
• 4‐Area Optimization
• 5
5‐Architecting
Architecting Power
• 6‐High Level Design
• 7
7‐Clock
Clock Domains
omains
• 8‐Sythesis Optimization
• 9‐Static Timingg Analysis
y
VHDL Overview
Design Flow
Design Units
 Design
g units
• Libraries
– The libraries with the tool need to convert words to codes
known as the word std_logic the library will but the truth table
suitable for this word
LIBRARIRY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
• Ports
– Contains the inputs and the output of the system
ENTITY PROJ_NAME IS
PORT (A,B :IN std_logic; D:OUT std_logic);
END PROJ_NAME;
• Architecture
– The core of the program
ARTHITECTURE TYP_NAME OF PROJ_NAME IS
BEGIN
END;
 Entityy
• Note VHDL not case sensitive
Entity‐(cont’d)
y( )
Architecture
Package declaration
Package body
Using Package
Configuration Declaration
 Configuration Declaration (cont
(cont’d)
d)
Entity Name
keyword Configuration Name

Configuration CFG_AND2 of AND2 is

for RTL Architecture Name
endd for;
f
end CFG_AND2;

• A configuration statements selects a unique architecture of an

entityy
• When no explicit configuration exists, the latest compiled
architecture is used (called the null configuration)
Configuration Declaration (cont
(cont’d)
d)
Entity XR2 is
port (…)
end XR2 ;
Architecture fast of XR2 is Configuration ONE of XR2 is
for fast
… end for ;
end fast; end ONE;

Architecture small of XR2 is Configuration TWO of XR2 is

for small
… end for ;
end small; end TWO;
Configuration Declaration(cont’d)
 libraries
• std_logic_1164
– 'U': uninitialized. This signal
g hasn't been set yyet.
– 'X': unknown. Impossible to determine this value/result.
– '0': logic 0
– '1': logic 1
– 'Z': High Impedance
– 'W': Weak signal, can't tell if it should be 0 or 1.
– 'L': Weak signal that should probably go to 0
– H : Weak signal that should probably go to 1
'H':
– '‐': Don't care
• std_logic_arith
– The basic
Th b i arithmetic
ith ti operations(+),(‐),(*)
ti (+) ( ) (*)
– The basic comparison operations(<),(<=),(>),(>=),(=),(/=)
– function shl and shr
– conv_integer
g ,conv
, _unsigned
g ,conv
, _signed
g ,conv
, _std_logic
g _vector
• std_logic_signed
• std_logic_unsigned
Libraries
Behavioral and structural
 Behavioral
• The two types of architecture
• 1 Behavioral
1‐Behavioral
 Behavioral‐(cont’d)
( )
• the right one have process which have the instructions in it is
Sequential but the left one is concurrent because there are not process
note also if we have more than I processes will excute concurrentially
 Process statement
• Algorithmic modeling
Process‐(cont’d)
( )
Process (cont’d)
Process‐(cont d)
 Process‐(cont’d)
( )
• Note if you have not sensitive list the process will not be
synthesizable this mean it cannot converted to gate level
• The signed library
– SIGNED will always give a result in 2's compliment
• The unsigned library
– UNSIGNED will never give a result in 2's compliment
• Complete sensitivity list
The sensitivity list should contain all of the signals that are read in
tthee process.
p ocess.
 Signed
g and unsigned
g
• library ieee;
use ieee.std_logic_1164.all;use ieee.numeric_std.all;
entity qual is
end qual;
architecture sim of qual is
begin
what : process is
constant a : signed := "111";
111 ; ‐‐ ‐1
1
constant b : unsigned := "111"; ‐‐ 7
constant d : std_logic_vector := "111";
begin
report "a = " & integer'image( to_integer(a));
report "a > 2 is " & boolean'image( a>2 );
report "b = " & integer'image( to_integer(b));
report
p "b > 2 is " & boolean'image( g ( b>2 ));
report "d = ""111"" ";
report "d > ""010"" is " & boolean'image( d>"010");
wait;
end p process what;;
end sim;
‐‐# ** Note: a = ‐1
‐‐# ** Note: a > 2 is false
‐‐## ** Note: b = 7
‐‐# ** Note: b > 2 is true
‐‐# ** Note: d = "111"
‐‐# ** Note: d > "010" is true
Sequential assignment
If condition
If condition‐(cont’d)
( )
CASE Statement
CASE Statement‐(cont’d)
( )
Inferring Latches
LOOP statement
LOOP statement‐(cont’d)
( )
LOOP statement‐(cont’d)
( )
LOOP statement‐(cont’d)
( )
LOOP statement‐(cont’d)
( )
 Synthesizable loop
• Loops and Generate‐this syntax construction
can be used onlyy for constant integer
g
generation or loops
Dataflow
When statement
When statement‐(cont’d)
( )
Select statement
Select statement‐(cont’d)
( )
Structural modelingg
Structural modeling‐(cont’d)
g( )
Structural modeling‐(cont’d)
g( )
• Component Example:
Structural modeling‐(cont’d)
g( )
Structural modeling‐(cont’d)
g( )
 Data objects
j
• Constants
 Data objects‐(cont’d)
j ( )
• Signals
 Data objects‐(cont’d)
j ( )
• Variables
 Variables versus Signals
g
• The difference bet. Variable and signal
 vectors and concatenation
SIGNAL x: STD
STD_LOGIC_VECTOR(3
LOGIC VECTOR(3 DOWNTO 0);
SIGNAL y: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL z, m, n: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= ”0000”;
b <= ”1111”;
c <= a & b; -- c = ”00001111”

m <= ‘1’ & ”0001111”; -- d <= ”10001111”

n <=
< ‘1’ & ‘1’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &
‘1’ & ‘1’;
-- e <= ”11001111”
 Data types
yp
• Std_logic_1164
 Data types‐(cont’d)
yp ( )
• Attributes
Data Type
Type‐(cont
(cont’d)
d)
 Enumerated Type Definition
• You can define
d fi your own enumerated
d data
d
types
– Handy when defining states and transitions
– Form is:

TYPE type
yp _name IS ((value list);
);

• Once declared
declared, the data type is used to define
new signals of that type
 Enumerated Type Example
type state_type
state type is (reset,
(reset sync
sync, load
load, out);
signal pstate: state_type;

ss: process (clk)

begin
if (clk’event and clk = ‘1’) then
case pstate is
when reset => ….

when sync
y => ….

etc.
end if;
end process;
 Operators
p
• Std_logic_arith
Operators‐(cont’d)
p ( )
Operators‐(cont’d)
p ( )
Operators‐(cont’d)
p ( )
Operators‐(cont’d)
p ( )
Operators‐(cont’d)
p ( )
Wait statement
Delta Delay
Transport versus inertial delay
 Design Levels

Register level (RTL):

• The
h design
d is divided
d d d into combinational
b l logic
l and
d storage
elements.
• Storage
St elements
l t (Fli
(Flip‐Flops,
Fl l t h ) are controlled
latches) t ll d by
b a
system clock.
• Synthesizable
Logic level:
• The
h design
d i is i represented d as a netlist
li with
i h logic
l i gates
(AND, OR, NOT,...) and storage elements.
 First time errors
• Typing "elseif" instead of "elsif"
• Forgetting "end
end ifif" especially in nested if
statements.
• Un
Un-respecting
respecting the rules of writing combinatorial
logic (either in editor or "HDL Designer").
• Two drivers for one signal
• Using VHDL reserved words.
Test Bench
Test Bench
Parity Example
Behavioral
Structural
Structural
Test bench
 Example
p 1
• ADDER
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
_ g _

entity adder is
Port (a, b : in unsigned(7 downto 0);
d : out unsigned(7 downto 0));
end adder;

architecture rtl1 of adder is

Begin
d <=
< a + b;
b
end rtl1;
 Example
p 1‐(cont’d)
( )
‐‐ VHDL code for n‐bit adder
‐‐ function of adder:
‐‐ A plus B to get n‐bit sum
‐‐ we may use generic statement to set the parameter n of the
adder.
entity adder_unsigned is
generic(n : integer);
Port (a
(a,b
b : in std
std_logic_vector(n‐1
logic vector(n 1 downto 0);
c: out std_logic_vector(n‐1 downto 0));
end adder_unsigned;

architecture rtl of adder_unsigned is

begin
c<= unsigned(a) + unsigned(b);
end rtl;
 Example
p 2
• Following is VHDL code for a 4‐bit unsigned up counter
• with asynchronous clear.
lib
library iieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3
std logic vector(3 downt 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
 Example
p 3
• Following is the VHDL code for a 4‐bit unsigned down counter with
synchronous set.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is port(C, S :in std_logic;
Q : out std_logic_vector(3 downto 0)); end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
if (S='1') then
tmp <= "1111";
else tmp <= tmp ‐ 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
 Example
p 4
• Following is the VHDL code for a 4‐bit unsigned up/down counter with
asynchronous clear.
libraryy ieee;;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is port(C, CLR, UP_DOWN : in std_logic;
Q : out std_logic_vector(3
std logic vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin process (C, (C CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C
(C'event
event and C='1')
C= 1 ) then
if (UP_DOWN='1') then
tmp <= tmp + 1;
else tmp <= tmp ‐ 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
archi
 Example
p 5
• Following is the VHDL code for a 4‐bit unsigned up accumulator with
asynchronous clear.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity accum is port(C, CLR : in std_logic;
D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3
d l i (3 downto
d 0))
0));
end accum;
architecture archi of accum is
signal tmp: std_logic_vector(3 downto 0);
b i
begin process (C,(C CLR)
begin if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + D;
end if;
end process;
Q <= tmp;
end archi;
 Example
p 6
‐‐ALU with 3 bit selection
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit
l b IS port(a,
( b : in std_logic_vector(7
d l ( downto
d 0);
)
‐‐ a and b are busses
op : in std_logic_vector(2 downto 0);
zero : outt std_logic;
td l i
f : out std_logic_vector(7 downto 0));
END alu8bit;
architecture behavioral of alu8bit is
begin
process(op)
variable temp: std_logic_vector(7
std logic vector(7 downto 0);
Examples 6‐(cont’d)
6 (cont’d)
begin
case op is when "000" => temp := a and b;
when "100" => temp := a and b;
when "001" => temp p := a or b;;
when "101" => temp := a or b;
when "010" => temp := a + b;
when "110" => temp := a ‐ b;
when "111" => if a < b then temp := "11111111";
else temp := "00000000";
end if;
when others => temp := a ‐ b;
end case;
if temp="00000000" then zero <= '1';
else zero <= '0';
end if;
f <= temp;
endd process;
end behavioral;
 Examples
p 7
‐‐ALU with 4 bit selection
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY alu IS
‐‐ Declarations
port(a,b: in std_logic_vector(7 downto 0);
sel: in std_logic_vector(3 downto 0);
cin: in std_logic;
y:out std_logic_vector(7 downto 0));
END alu ;

‐‐ hds interface_end
ARCHITECTURE alu OF alu IS
signal arith,logic: std_logic_vector(7 downto 0);
BEGIN
with sel(2 downto 0) select
arith<= a when "000",
a+1 when "001",
a‐1 when"010",
b when "011",
b+1 when "100",
Examples
p 7‐(cont’d)
( )
b‐1 when "101",
a+b
b when
h "110",
"110"
a+b+cin when others;

with
ith sel(2 downto
do nto 0) select
logic<= not a when "000",
not b when "001",
a and b when "010"
010 ,
a or b when "011",
a nand b when "100",
a nor b when "101"
101 ,
a xor b when "110",
not (a xor b) when others;

with sel(3) select

y<= arith when '0',
logic
g when others;;
END alu;
 Examples
p 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY unsigned_mult
d l IS
PORT (
a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
b
b: IN STD LOGIC VECTOR (7 DOWNTO 0);
STD_LOGIC_VECTOR 0)
clk: IN STD_LOGIC;
aclr: IN STD_LOGIC;
result:OUT STD LOGIC VECTOR (15 DOWNTO 0)
STD_LOGIC_VECTOR
);
END unsigned_mult;
ARCHITECTURE rtl OF unsigned_mult
unsigned mult IS
SIGNAL a_reg, b_reg: std_logic_vector (7 DOWNTO 0);
Examples
p 8‐(cont’d)
( )
BEGIN
PROCESS (clk, aclr)
BEGIN
IF (aclr ='1') THEN
a_reg <= (OTHERS => '0');
b
b_reg <= (OTHERS
( => '0');
' ')
result <= (OTHERS => '0');

ELSIF ((clk'event
lk' t AND clk
lk = '1') THEN
a_reg <= a;
b_reg <= b;

result <= unsigned(a_reg) * unsigned(b_reg);

END IF;
END PROCESS;

END rtl;