Problem 1: 4-to-1 Muxtiplexer using Data Flow

module mux41_rtl(
input [3:0] a,
input [1:0] s,
output o);
assign o = s[1]?(s[0]?a[3]:a[2]):(s[0]?a[1]:a[0]);
endmodule
//Testbench
module mux41_rtl_tb;
reg [3:0] a;
reg [1:0] s;
wire o;
integer i;
mux41_rtl Mux(a,s,o);
initial begin
a<=4'b1010;
for(i=0;i<4;i=i+1) begin
#5;
s<=i;
end
end
initial
$monitor("s=%b output=%b",s,o);
Endmodule

Problem 2:4-bit Carry Lookahead Adder using Data Flow

assign p[3:0] = a[3:0] ^ b[3:0];

assign c[0] = cin;

assign c[1] = g[0] | (p[0] & c[0]);

assign c[2] = g[1] | (p[1] & g[0]) | (p[1] & p[0] & c[0]);

assign c[3] = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0])
| (p[2] & p[1] & p[0] & cin);

assign c[4] = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1])
| (p[3] & p[2] & p[1] & g[0])
| (p[3] & p[2] & p[1] & p[0] & cin);
assign sum[4:0] = {1'b0, p[3:0]} ^ c[4:0];
endmodule
//Testench
module carrylook_adder_tb;
reg [3:0] a,b;
reg cin;
wire [4:0] sum;
carrylook_adder CLA(a,b,cin,sum);
initial begin
a<=4'b1010;
b<=4'b1101;
cin<=0;
#10;
a<=4'b1111;
b<=4'b1000;
cin<=1;
end
initial
$monitor("Output=%b",sum);
endmodule

Problem 3:
1.Describe the statement assign: The assignment syntax starts with the keyword assign followed by the
signal name which can be either a single signal or a concatenation of different signal nets. The drive
strength and delay are optional and are mostly used for dataflow modeling than synthesizing into real
hardware.
The expression of signal on the right hand side is evaluated and assigned to the net or expression of nets
on the left hand side.
Expression: assign <net_expression> = [drive_strength] [delay] <expression of different signals or
constant value>
*Verilog Arithmetic Opertators

Operator Description

a+b a plus b

a -b a minus b

a*b a multiplied by b

a/b a divided by b

a%b a modulo b
a ** b a to the power of b

*Verilog Relational Operators

Operator Description

a<b a less than b

a>b a greater than b

a <= b a less than or equal to b

a >= b a greater than or equal to b

*Verilog Equality Operators

Operator Description

a === b a equal to b, including x and z

a !== b a not equal to b, including x and z

a == b a equal to b, result can be unknown

a != b a not equal to b, result can be unknown

*Verilog Logical Operators

Operator Description
a && b evaluates to true if a and b are true

a || b evaluates to true if a or b are true

!a Converts non-zero value to zero, and vice versa

*Verilog Bitwise Operators

& 0 1 x z

0 0 0 0 0

1 0 1 x x

x 0 x x x

z 0 x x x

| 0 1 x z

0 0 1 x x

1 1 1 1 1

x x 1 x x

z x 1 x x

*Verilog Shift Operator