NATIONAL UNIVERSITY OF HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING

CHAPTER 5: DATAFLOW MODELING

Lecturer: Ho Ngoc Diem

Agenda
 Chapter 1: Introduction
 Chapter 2: Modules and hierarchical structure
 Chapter 3: Fundamental concepts
 Chapter 4: Structural modeling (Gate & Switch-level modeling)
 Chapter 5: Dataflow modeling (Expression)
 Chapter 6: Behavioral modeling
 Chapter 7: Tasks and Functions
 Chapter 8: State machines
 Chapter 9: Testbench and verification
 Chapter 10: VHDL introduction

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 Verilog model for hardware
Verilog design
design
RTL Design

Gate/Switch level modeling Dataflow modeling Behavioral modeling

- Primitive switch, gate -Continuous assignment - Procedural assignment

- User defined primitive (assign) - initial, always block
- Expression (operators) - Conditional statement…

 There are different ways of modeling a hardware design. Choose an

appropriate model to design Combinational or Sequential Circuit.
 Some books do not classify Dataflow modeling as a separate modeling
type.

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Content
 Dataflow modeling
 Continuous assignment
 Expression, operator, operands
 Design examples

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Dataflow model
 For complex design: number of gates is very large
-> need a more effective way to describe circuit
 Dataflow model: Level of abstraction is higher than gate-
level, describe the design using expressions instead of
primitive gates
 Circuit is designed in terms of dataflow between register,
how a design processes data rather than instantiation of
individual gates
 RTL (register transfer level): is a combination of dataflow
and behavioral modeling

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Continuous assignment
 Drive a value onto a net
assign out = i1 & i2; //out is net; i1 and i2 are nets
Left-hand side Right-hand side
Net (vector or scalar) Net, register, function
Bit-select or part-select of a vetor net call (any expression that
Concatenation of any of the above gives a value)
 Always active
 Delay value: control time when the net is assigned value
assign #10 out = in1 & in2; //delay of performing computation,
//only used by simulator, not synthesis

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Continuous assignment
Examples:
wire out = in1 & in2; //scalar net
//implicit continuous assignment, declared only once
assign addr[15:0] = addr1_bits[15:0] ^ addr2_bits[15:0]; //vector net
assign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in; //concatenation
module adder (sum, carry_out, carry_in, ina, inb);
output [3:0] sum;
output carry_out;
input [3:0] ina, inb;
input carry_in;
wire carry_out, carry_in;
wire [3:0] sum, ina, inb;
assign {carry_out, sum} = ina + inb + carry_in;
endmodule
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 Continuous Assignment
Examples
Question: What shall be the result of the following assignment?
(1) wire [3:0] y;
assign y[3:0] = -3;

(2) wire [3:0] y;

assign y[3:0] = 2’b10;
(3) wire [3:0] y;
In your program, always make bit
assign y[3:0] = 6’b111000; width of left-hand side and right-
hand side equal
(4) wire [3:0] y;
assign y[3:0] = 1’b0;
(5) wire [3:0] y;
assign y[3:0] = 1’bx;
(6) wire [3:0] y;
assign y[3:0] = 4’bx;
(7) wire [3:0] y;
assign y[3:0] = 4’b1;
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Continuous Assignment
Examples
A sample answer
(1) wire [3:0] y; y = 4’b1101
assign y[3:0] = -3;
There may be
(2) wire [3:0] y;
y = 4’b0010 tool dependency
assign y[3:0] = 2’b10;
on these result.
(3) wire [3:0] y;
y = 4’b1000
assign y[3:0] = 6’b111000;
(4) wire [3:0] y;
y = 4’b0000
assign y[3:0] = 1’b0;
(5) wire [3:0] y;
y = 4’b000x
assign y[3:0] = 1’bx;
(6) wire [3:0] y;
y = 4’bxxxx
assign y[3:0] = 4’bx;
(7) wire [3:0] y;
y = 4’b0001
assign y[3:0] = 4’b1; 9
 Continuous Assignment
Examples
Question: Check if the following statements are correct or not?
(1) wire [7:0] a, b;
assign b[7:0] = a[3:0] – 4’b0010;

b[7:0] = 8’b1111_1110 if a is 8’h00

In your program, always make bit
(2) wire [7:0] a, b;
assign a[3:0] = b[7:0] – 4’b0100;
width of left-hand side and right-
hand side equal
a[3:0] = 4’hC if b[7:0] is 8’h00
(3) wire [7:0] a, b;
assign b[7:0] = a[3:0] – 6’b110001;

b[7:0] = 8’b0000_1111 if a is 8’h00

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 Continuous Assignment
Examples
A sample answer

(1) wire [7:0] a, b; Correct,

assign b[7:0] = a[3:0] – 4’b0010;
sign extended
b[7:0] = 8’b1111_1110 if a is 8’h00
(2) wire [7:0] a, b;
assign a[3:0] = b[7:0] – 4’b0100; Correct

a[3:0] = 4’hC if b[7:0] is 8’h00

(3) wire [7:0] a, b; Wrong,
assign b[7:0] = a[3:0] – 6’b110001;
b[7:0] is 8’b1100_1111
b[7:0] = 8’b0000_1111 if a is 8’h00

There may be tool dependency. Do not assume the above is true in

the future
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Continuous Assignment
 Because the assignment is done always, exchanging the
written order of the lines of continuous assignments has no
influence on the logic
 Common error
- Not assigning a wire a value
- Assigning a wire a value more than one
 Target (LHS) is NEVER a reg variable

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Delay
Regular assignment delay

Implicit continuous assignment delay

Net declaration delay

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Expression: Operands
 Constant number or string Constant
 Parameter
 Net
 Variable (reg, integer, time, real, realtime)
 Array element Data types

 Bit-select or part-select (not for real, realtime)

 Function call that returns any of the above

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Expression: Operators
Arithmetic + - * / % **
Logical ! && ||
Logical equality == !=
Case equality === !===
Bitwise ~ & | ^ ^~ (or ~^)
Relational < > >= <= Operators not
allowed for real
Unary reduction & ~& | ~| ^ ^~ (or ~^) expression
Shift << >> <<< >>>
Concatenation {}
Replication {{}}
Condition ?: Ref. book for detail
of each operator!
Unary + - 15
Arithmetic Operators

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Arithmetic Operators (cont.)
Example

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 Logical Operators

- Return a single bit 1 (true), 0 (false), x (unknown, if any operand has bits x).
- Treat all values that are nonzero as “1”
Example:

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 Logical and Case equality Operators

 For the == and != operators:

- The result is 0, if two bits in two operands that have the same position is
different in 0 and 1
Ex. 4'b1z00 == 4'b1x10  0
4'bxxx1 == 4'bzzz0  0

- The result is x, if either operand contains an x or a z (except the above case)

Ex. 4'b1z00 == 4'b1000  x
4'b1x00 == 4'b1x00  x
 For the === and !== operators
bits with x and z are included in the comparison and must match for the
result to be true. 19
Logical and Case equality Operators (cont.)

Example 1:

Example 2:
4'b1x00 == 4'b1x00 (x) 4'b1z00 == 4'b1x00 (x)
4'b1x00 === 4'b1x00 (1) 4'b1z00 == 4'b1z00 (x) 4'bxxx0 == 4'bzzz1 ( 0)
4'b1z00 == 4'b1x10 ( 0)
4'b1100 == 4'b1100 (1) 4'b1100 == 4'b1z10 ( 0)
4'b0000 == 4'b0000 (1) 4'b1100 == 4'b1x10 ( 0) 20
Relational Operators

- Compare two operands and return a single bit 1 or 0.

- Be synthesized into comparators.
- The result is x if any of the operands has an unknown (x) or high
impedance (z)
Example:

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Bit-wise Operators

Bit-to-bit combination between two operand

• ~z = x
• (0,1, x, z) & z = x
• (0,1, x, z) | z = x

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 Bit-wise Operators (cont.)

Example:

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Unary Reduction Operators

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 Unary Reduction Operators (cont.)
Example:

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Shift Operators
Unsigned data type

Signed data type

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 Shift Operators (cont.)
Example:

unsigned shift = 00001010

signed shift = 11111010

unsigned shift = 01010100

signed shift = 01010100

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Concatenation Operators

Example:

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Replication Operators

Example:

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 Conditional Operator

Example:

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 Operators
 Examples of basic operators

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 Operators
 Examples of Equality operator

 Examples of Shift operator

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 Operators
 Logical, Bit-wise, Reduction operator

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Operator precedence

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Expression example
 Bitwise operator
module xor3 (input a, b, c, output y);
assign y = a ^ b ^ c;
endmodule

 Concatenation
module add_1bit (input a, b, ci, output s, co);
assign #(3, 4) {co, s} = {(a & b)|(b & ci)|(a & ci), a^b^ci};
endmodule

 Conditional operator
module quad_mux2_1 (input [3:0] i0, i1, input s, output [3:0] y);
assign y = s ? i1 : i0;
endmodule
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 Expression example
 Relational & Equality operator
module comp_4bit ( input [3:0] a, b, output a_gt_b, a_eq_b, a_lt_b);
assign a_gt_b = (a>b),
a_eq_b = (a==b),
a_lt_b = (a<b);
endmodule

 Arithmetic operator
module add_4bit (input [3:0] a, b, input ci, output [3:0] s, output co);
assign { co, s } = a + b + ci;
endmodule

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 Combinational circuit
 4 to 1 mux
module mux4_1(out, in1, in2, in3 ,in4, module mux4_1 (out, in1, in2, in3, in4,
cntrl1, cntrl2); cntrl) ;
output out; output out ;
input in1, in2, in3, in4, cntrl1, cntrl2; input in0,in1,in2,in3 ;
input [1:0] cntrl;
assign out = (in1 & ~cntrl1 & ~cntrl2) | assign out = (cntrl == 2'b00) ? in0 :
(in2 & ~cntrl1 & cntrl2) | (cntrl == 2'b01) ? in1 :
(in3 & cntrl1 & ~cntrl2) | (cntrl == 2'b10) ? in2 :
(in4 & cntrl1 & cntrl2); (cntrl == 2'b11) ? in3 :
endmodule 1'bx ;
endmodule

OR
// Use nested conditional operator
assign out = cntrl1 ? (cntrl2 ? in4 : in3) : (cntrl2 ? in2 : in1);
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 Combinational circuit
 1 bit full adder
module fa (input a, b, cin,
output s, cout);
assign s = a^b^cin;
assign cout = (a & b) | (cin & (a^b));
endmodule
t1
t2
• Let’s design 8-bit adder
module adder(cout,s,a,b) ;
output cout;
output [7:0] s ;
input [7:0] a,b ;
assign {cout,s} = a + b ; t3
endmodule
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 Combinational circuit
 Comparator
Parameters that may be set
when the module is instantiated.
Comparator makes the comparison A ? B
“?” is determined by the input greaterNotLess
and returns true(1) or false(0).

module comparator (result, A, B, greaterNotLess);

parameter width = 8;
parameter delay = 1;
input [width-1:0] A, B; // comparands
input greaterNotLess; // 1 - greater, 0 - less than
output result; // 1 if true, 0 if false
assign #delay result = greaterNotLess ? (A > B) : (A < B);
endmodule

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 Sequential circuit
 4-bit ripple carry counter

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 Sequential circuit
 4-bit ripple carry counter

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 Summary
 Continuous assignment: main construct in dataflow modeling,
always active
 Left hand side of assignment must be a net
 Using expression with operators & operands
 Delays on a net can be defined in the assign statement,
implicit continuous assignment, or net declaration.
 To describe much sophisticated logic easily, procedural
assignment is available in Verilog RTL programming (see later)

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