EE-307

FPGA BASED SYSTEM DESIGN

Spring 2015

Verilog
Combinational Logic in Verilog

Lecture # 04
Today’s Lecture

 Gate Level Example

 Data Flow modeling
 Verilog Operators
Gate level Example
 Verilog -- Design Levels
4

 Gate-Level modelling
 Verilog gate Primitives
 Dataflow Modelling
 Continuous Assignment using assign statement
 Expressions, Operators, Operands
 Behavioural Modelling
 Structured Procedures: Initial & always blocks
 Blocking & Non-blocking statements
 HLL Higher language constructs (if, switch, case, loops)
Moving to Data Flow Model
Dataflow Level
 Characterized by assign statement
 Allows Expressions, Operators, Operands
 Example:
 wire c
 assign c = a + b;
 Example
 wire d;
 assign d = a || b; // explicit continuous assignment
 Example
 wire d = a || b; //implicit continuous assignment
 Data Flow for full adder

[SHO]
 Port Connection Styles
Instantiating a Module in another block

 Verilog 95 vs Verilog 2001 style

 Lets use the previous FA to make a 3 bit Ripple Carry Adder

[SHO]
 This
method is
better for
block with
greater no.
of ports
 Combinational Logic
 Output is Boolean
function of its input
variables on
instantaneous basis

CIL
 Verilog Operators
Logical Right Logical Left

 Arithmetic operators: +, -, *, /, %
 Bitwise operators: &, |, ~, ^, ^~
 Reduction operators: &, ~&, |, ~|, ^

 Logical operators: ==, !=, &&, ||, !

 Relational operators: >, <, >=, <=

 Shift operators: >>, << Arithmetic right

 Concatenation{} (Left is same as Logical)

 Conditional: cond_expr ? true_expr : false_expr

 Arithmetic Shift (Signed Shift) >>>, <<<

Arithmetic and logic shift left by n performs the same operation, as both drop n MSBs of the
operand without any consideration of the sign bit.
 Examples
13

 ~4'b0001 = 1110
 4'b0001 & 4'b1001 = 0001
 4'b0001 | 4'b1001 = 1001
 & 4'b1001 = 0 // And across all the bits, Can be used
to raise flags such as waiting for a 1 from multiple
inputs
 | 4'b1001 = 1
 4'b1001 << 1 = 0010
 4'b1001 >> 1 = 0100
 {4'b1001,4'b1111} = 10011111 // Can be used to
concatenate wires/buses
 Date Flow: conditional operator

The Conditional Operator

assign y = cond_expr ? true_value : false_value

assign y = (a==b) ? 1’b1 : 1’b0

assign y =((a==b)&&(c==d)) ? 1’b1 : 1’b0

Example
2-1 MUX at Dataflow Level

 module mux21(
 input in1,in2,sel,
 output out);

 assign out = sel ? in2 : in1;

 end module
 What does the following statement shows ?

 Assign out = sel[1] ? ( sel[0] ? in3 : in2 ) : ( sel[0] ? in1 : in0 );