Received 9 September 2022; revised 14 November 2022; accepted 10 December 2022.

Date of publication 26 December 2022;

date of current version 21 February 2023. The review of this article was arranged by Editor S. Menzel.
Digital Object Identifier 10.1109/JEDS.2022.3230542

3-D Monolithic Stacking of Complementary-FET

on CMOS for Next Generation
Compute-In-Memory SRAM
MD. AFTAB BAIG 1 , CHENG-JUI YEH1 , SHU-WEI CHANG2,3 (Member, IEEE), BO-HAN QIU1 ,
XIAO-SHAN HUANG1 , CHENG-HSIEN TSAI1 , YU-MING CHANG1 , PO-JUNG SUNG3 , CHUN-JUNG SU4 ,
TA-CHUN CHO 3 , SOURAV DE 1,5 (Member, IEEE), DARSEN LU 1 (Senior Member, IEEE),
YAO-JEN LEE 6 (Senior Member, IEEE), WEN-HSI LEE 2 ,
WEN-FA WU 3 , AND WEN-KUAN YEH3
1 Institute of Microelectronics, National Cheng Kung University, Tainan 701, Taiwan
2 Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
3 Taiwan Semiconductor Research Institute, Hsinchu 300091, Taiwan
4 Department of Electrophysics, National Yang Ming Chiao Tung University, Hsinchu 300093, Taiwan
5 Center Nanoelectronic Technologies, Fraunhofer-Institut für Photonische Mikrosysteme, 01109 Dresden, Germany
6 Institute of Pioneer Semiconductor Innovation, Industry Academia Innovation School, National Yang Ming Chiao Tung University, Hsinchu 300093, Taiwan

CORRESPONDING AUTHOR: D. LU (e-mail: darsenlu@mail.ncku.edu.tw)

This work was jointly supported by the Ministry of Science and Technology under Grant MOST-108-2634-F-006-008 and Grant MOST-109-2628-E-006-010-MY3,
and the Center for Future Computing, Miin Wu School of Computing, NCKU.

ABSTRACT Monolithic 3D stacking of complementary FET (CFET) SRAM arrays increases integration
density multi-fold while supporting the inherent SRAM advantages of low write power and near-infinite
endurance. We propose stacking multiple 8-transistor CFET-SRAM layers on regular CMOS periphery to
achieve an ultra-high-density array for computing-in-memory (CIM). CFET and regular CMOS (FinFET)
devices are measured and calibrated with BSIM-CMG compact model. SPICE simulations are performed
to evaluate the delay of CIM operation, power consumption, and analog computational error due to device
non-linearity. The impact of device non-linearity on neural network inference accuracy is evaluated using
the CIMulator simulation platform. Lower CFET current drive due to amorphous (deposited) silicon
channel is shown to have negligible impact on CIM operational delay in many cases, as the maximum
allowable current is limited by wiring resistance, not transistor drive strength while maintaining accurate
weighted sum. Compared to regular 2D CMOS FinFET array. CFET SRAM cells show an improvement
up to 57.19% in TOPS/W. Furthermore, the performance in TOPS/W mm2 is improved up to 19×. A
factor proportional to the number of stacked layers for monolithically stacked CFET SRAM cells, makes
it highly promising for future edge intelligence.

INDEX TERMS Complementary FET (CFET), compute-in-memory (CIM), monolithic 3D integration,

SRAM.

I. INTRODUCTION random-access memory (SRAM) is a promising candidate

The exponential growth of neural network (NN) size for
artificial intelligence (AI) has placed an enormous demand
on data-centric computational power. Computing-in-memory
(CIM) has come to the rescue by integrating processors
and data to overcome the von Neumann bottleneck. Static
to achieve on-chip CIM [1], [2] compared to other elec-
tronic memory types for its superior endurance, low write
power, noise immunity, etc., yet it occupies the largest layout
area among all Fig. 1(a). This may be addressed by verti-
cally stacking nFET and pFET nanosheet devices into the

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 BAIG et al.: 3-D MONOLITHIC STACKING OF CFET ON CMOS FOR NEXT GENERATION CIM SRAM
FIGURE 1. (a) Advantages of SRAM cell in many aspects compared to
other memory devices, while lacking in integration density and
non-volatility [8]. (b) Combining n-channel and p-channel devices into one
CFET [4], and monolithic stacking of multiple CFET layers to improve the
device footprint. (c) Cross-sectional TEM images showing CFET structure
with p-channel on top and n-channel at bottom. Inset showing EDS
mapping of the TEM image for Ti and Hf.
complementary FET (CFET) structure Fig. 1(b) [3], [4], and
further stacking of CFET-SRAM layers via monolithic 3D
integration, reduces the footprint by more than a factor of
n, where n is the number of CFET-SRAM stacks Fig. 1(c).
Silicon channel deposited at low temperature (< 600◦ C)
degrades carrier mobility, so transistor drive current is much
lower than regular CMOS [5], yet for CIM where multiple
SRAM rows are activated simultaneously for weighted sum
operation, in many cases maximum current is limited by
I-R drop rather than transistor drive strength. To mini-
mize latency, we may employ regular CMOS FinFET in
the bottom single-crystalline silicon layer for peripheral
drive/read-out circuitry to drive and sense CFET SRAM
arrays on top. The 8-transistor (8T) SRAM is suitable for
CIM due to its high linearity and low read disturb. In this
work, we designed and laid out CFET-based 8T-SRAM cell
and compare it with regular CMOS FinFET 8T-SRAM pro-
cessed with the same fabrication facilities in a similar test
vehicle. BSIM-CMG [6] is calibrated to both technologies
and SPICE simulations are performed to compare the two
cases to quantify improvements in terms of power con-
sumption, linearity, and latency. We used the CIMulator [7]
platform to compare CIM-SRAM build in the two tech-
nologies in terms of NN inference accuracy with a given
set of software-trained 5-bit-weight network, taking into
account hardware extracted device variation and nonlinearity
as found during SPICE simulation [1]. The advantages of 3D
monolithic-integrated CFET SRAM is highlighted in terms
of CIM operations per power, and operations per power per
area.
108
FIGURE 2. Schematic showing two adjacent CFET 8T-SRAM cells, each has
two CFETs and an average of 2.5 double-layer n-channel nanosheet FET
(NSFETs) (RA2/RA’2 share one NSFET).
FIGURE 3. Layout of proposed CFET 8T-SRAM with schematic shown in
Fig. 2.
II. CFET SRAM CELL DESIGN AND MONOLITHIC 3D
INTEGRATION
Compute-in-memory operations is efficiently realized using
8T-SRAM cell. These cells have less read bitline discharge
current compared to 7T-SRAM and a reduced footprint
compared to 10T-SRAM. However, 10T-SRAM are used to
perform other Boolean operations. Hence, this paper con-
siders standard 6T-SRAM for memory and 8T-SRAM for
computing-in-memory applications. The CFET device com-
prising of bottom n-channel and top p-channel is fabricated
with a low temperature process (< 600◦ C) [4]. CFET device
is then used to realize an 8T-SRAM comprising of 2 p-
channel and 6 n-channel transistors (2P6N configuration)
with the aid of an additional dummy transistor T1 sharing
the gate with transistor RA1 Fig. 2. The second read access
transistor RA2 is combined with the read access transistor
of adjacent SRAM cell RA’2 to complete the structure. The
layout of the structure is shown in Fig. 3, it has an area of
240 λ2 compared to the standard FinFET area of 270 λ2 (not
shown here for simplicity). Stacking the p-channel on top of
the n-channel reduces the footprint for both 6T-SRAM and
8T-SRAM as shown in Table 1. The advantage is reduced in
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BAIG et al.: 3-D MONOLITHIC STACKING OF CFET ON CMOS FOR NEXT GENERATION CIM SRAM
TABLE 1. Footprint reduction of 6T and 8T SRAM cells using CFET.
FIGURE 4. Benchmarking flow adopted in this study to evaluate and
compare CFET and FinFET technologies.
the realization of the 8T-SRAM design due to the addition
of the dummy transistor for realizing the CFET structure.
Further layout area reduction for CFET is possible via the
buried power rail approach [3], yet such method is not com-
patible with 3D monolithic stacking. The main advantage
of our polysilicon-channel CFET device is that its chan-
nel is deposited using Plasma Enhanced Chemical Vapour
Deposition (PECVD) and solid-phase crystallization. This
enables us to monolithically stack one SRAM layer on top
of another by simply repeating the fabrication process steps.
The stacking of multiple SRAM layers also provides shorter
global interconnects which minimizes R-C delay. Besides,
the effective cost per layer would be less as we will use the
same photomasks for each layer. However, the complexity
of multiple layers will increase total processing costs and
might cause yield reduction.
FinFET devices, on the other hand, are made of single-
crystalline silicon and hence has superior drive strength
compared to polysilicon. The FinFETs [9], [10], [11], [12]
are fabricated with a gate-first high-K and metal gate process,
with Hf0.5 Zr0.5 O2 gate dielectric of 10 nm thickness. The
device is primarily made as part of ferroelectric-FinFET (Fe-
FinFET). Nevertheless, the device can be used as a regular
FinFET.
III. DEVICE CHARACTERIZATION AND PARAMETER
EXTRACTION
For fair comparison, CFET and FinFET devices are made
in the same nanofabrication facility with similar baseline
processes. Fabricated devices are then characterized and cal-
ibrated to BSIM-CMG multiple-gate CMOS compact model
(CFET and FinFET devices) following the benchmarking
flow shown in Fig. 4. To ensure that the parameters are
consistent with the physical properties we follow the extrac-
tion method mentioned in the BSIM-CMG manual [6]. The
measured data show asymmetric threshold voltages (Vth )
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FIGURE 5. Transfer characteristics (Id − Vgs ) of n-channel (Blue) and
p-channel (Red) (a) CFET and (b) FinFET devices. Relatively low drain
current of CFET is due to the polycrystalline silicon channel. (c) Output
characteristics (Id − Vds ) and (d) output conductance (Gds − Vds ) of the
n-channel CFET device used for realizing the read access transistors of the
CFET SRAM cell.
for n-channel and p-channel CFETs. The threshold volt-
age is tuned using post-calibration adjustment of effective
gate work function assuming Vth engineering is available
by channel or gate stack engineering [13], [14]. 8T-SRAM
is cell is designed and the widths of the transistors are
tuned for better hold, read, and write stability which is
described in Section IV. Peripheral components including
sense amplifiers, counter, and drivers are realized using
FinFET devices and perfected for speed and linearity and
are described in Section V. Fig. 5(a) and 5(b) show the
measured transfer characteristics of both the CFET and the
FinFET, respectively. One key difference between CFET and
FinFET devices is that the smaller current in CFET due to
the lower mobility of carriers in the polycrystalline channel.
Fig. 5(c) and 5(d) show the output characteristics and out-
put conductance of n-channel CFET devices which will be
discussed in detail in Section VI.
IV. READ, WRITE AND HOLD STABILITY OF CFET 8T-SRAM
8T-SRAM cells are designed for optimum stability, speed,
and linearity. For accurate CIM results, and enhanced image
recognition accuracy, superior read stability is needed. To
enhance the read stability, an 8T SRAM cell is considered
in which the additional two transistors provide the neces-
sary decoupling of output loading from the storage node
during the read operation [15], thus significantly improving
the read stability. In fact, for 8T-SRAM the read static noise
margin (RSNM) is nearly the same as hold static noise mar-
gin (HSNM) Fig. 6(a). Variation of HSNM as a function of
Vdd is shown in Fig. 6(b). Read stability is also quantified
by read N-curve that is produced by biasing both the bitlines
with Vdd . Sweeping the voltage at one of the storage nodes
and measuring the current that flows into it. Write stability,
on the other hand, is quantified with write N-curves by bias-
ing one bitline with Vdd , and the other bitline to ground [16].
Subsequently, we sweep the voltage at the storage node to
extract nodal current. Fig. 6(c) and 6(d) show the critical
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 BAIG et al.: 3-D MONOLITHIC STACKING OF CFET ON CMOS FOR NEXT GENERATION CIM SRAM

FIGURE 6. (a) Simulated hold static noise margin (HSNM) of 6T-SRAM and
read static noise margin (RSNM) of 8T-SRAM using CFET, (b) HSNM as a
function of Vdd , (C) Critical write current as a function of Vdd with inset FIGURE 8. Components of read and write peripheral circuits placed at the
showing the write N-curve, (d) Critical read current as a function of Vdd bottom of the CFET SRAM stack. Inset shows the discharge current flowing
with inset showing the read N-curve. The above curves are obtained after through read access transistors responsible for MAC nonlinearity.
fine tuning the SRAM cell stability and balancing of read and write speeds.

write operation for initialization of the neural network (NN)

weights and to update them. Selection of a single row is
made by selecting the layer first, followed by the row in that
layer, employing layer decoder and row decoder simultane-
ously. MAC operation or read operation is done by applying
pulses corresponding to the input image data on wordlines
that get multiplied with the contents of the SRAM cell. MAC
operation results in the current being discharged from the
SRAM cell in accordance to data stored in the SRAM cell
or weight WN and excitation on the read word line (RWL)
TWL . Discharged current IN gets added along the column
of the SRAM array and an equivalent amount of charge
T
WN × C1BL × 0 WL IN (t)dt is discharged from the charge-
sharing capacitors located on the bottom layer. The leftover
FIGURE 7. Block diagram of 3D monolithically stacked GAA CFET SRAM resultant voltage of capacitors (Eq. (1)) [1] is then used to
array. The peripheral read and write blocks are made of standard FinFET to estimate the MAC output using a flash Analog to Digital
retain speed; the SRAM arrays are made of CFET with deposited channel
for high density.
Converter (ADC). The overall block diagram is shown in
Fig. 8. The 8-bit input image is split into eight batches, each
comprising of 5-bit input pulses (8 × 25 = 256 pulses). The
write current and critical read current of the CFET SRAM adders and registers of the read periphery circuit carry out
cell as a function of Vdd with the inset showing the write the accumulation of partial sums of each cycle resulting from
N-curve and read N-curve respectively [17]. the splitting of an 8-bit input image (256 pulses).
  TWL 
1
V. 3D CFET SRAM COMPUTE-IN-MEMORY ARCHITECTURE VBL = W1 × × I1 (t)dt
CIM is a highly energy-efficient way of performing CBL 0
  TWL 
multiply-and-accumulate (MAC) operations. Fig. 7 shows 1
+ W2 × × I2 (t)dt
the proposed novel CIM architecture for 3D monolithically CBL 0
stacked CFET SRAM arrays. Peripheral circuitry aiding in   TWL 
1
data reading, data writing, and digital transformation of MAC + · · · + WN × × IN (t)dt . (1)
CBL 0
results are placed in the first layer (bottom) with single crys-
talline silicon for optimal read/write latency. Multiple CFET
SRAM layers with deposited silicon channels are placed VI. SPICE AND NEURAL NETWORK
above. The weights obtained from off-chip training of the COMPUTE-IN-MEMORY SIMULATION
neural network are stored as SRAM cell contents through To compare CFET and regular CMOS FinFET in terms of
write operation. CIM generally employs a word-by-word MAC latency, power consumption per operation, and impact

110 VOLUME 11, 2023

BAIG et al.: 3-D MONOLITHIC STACKING OF CFET ON CMOS FOR NEXT GENERATION CIM SRAM
FIGURE 9. (a) Transient analysis of CFET SRAM array of size 64 × 5
(rows × columns) with 5-bit inputs, outputs, and weights. (b) Energy
consumed at various stages of the CIM Operation. SRAM arrays of CFET are
more energy efficient compared to that of FinFET due to lower wiring
capacitance.
FIGURE 10. The CIMulator platform is run in python using a tensor flow
library. The Neural network comprises 784, 200, and 10 nodes in input,
hidden, and output layers, respectively. Trained weights are then
quantized. RBL nonlinearity is then added to the CIMulator platform to
conduct the realistic simulation. Retraining of the network is done to
address the RBL nonlinearity of the neural network.
of read bitline nonlinearity [1], SPICE simulation is per-
formed with 4 and 5-bit unary input pulses (24 and 25 pulses
respectively) of 0.8 V each on arrays with 64, 256 rows and
having 4 and 5-bit precision (weights). The resultant tran-
sient analysis and energy consumed in each of the step are
shown in Fig. 9(a) and 9(b) respectively. The input pulse
width to be applied on the worldline is tuned to ensure that
VBL does not drop below 3% of Vdd after the application
of 24 and 25 pulses with all the SRAM weight being 1.
Performance evaluation of CFET 8T-SRAM array is
obtained using CIMulator [7] a circuit-level benchmarking
tool for neuromorphic circuits such as Neurosim [18]. We
employ a 3-layer multi-layer perceptron (MLP) NN com-
prising 784, 200, and 10 neurons respectively to recognize
handwritten digits from the MNIST [19] database. Table 2
describes the realization of the NN weights and biases of
layers 1 and 2 using the SRAM CIM Marco of the size
of 64 × 60 (Rows and Column) with 5-bit precision. The
dimension of the macro 64 × 60 is chosen because in the
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TABLE 2. Mapping of neural network layers 1 and 2 to CIM SRAM macro of
size 64 × 60 (rows × columns).
case of 64 × 64 for 5-bit precision the last 4 columns would
be unusable. To keep the number of computational units or
neurons of the NN low. We have considered one device
as synapse (1D1S) architecture [20] that makes use of a
reference column of weights instead of negative synaptic
devices. For instance, layer 1 comprises of 784 × 200 × 5
SRAM cells. The 784 rows in layer 1 are realized by
using the 64 × 60 macro using 12 instances/copies of the
64 × 60 macro and using 16 rows from the 13th instance.
200 × 5 (columns × precision) is realized 16 instances of
64 × 60 macro and using 40 columns from the 17th instance.
Training the network-on-chip is fine given the SRAMs have
infinite endurance but the process is energy-draining and
training the NN every time is discouraged. Moreover, for
training a NN, one needs higher bit precision (8-bit) but
for image recognition (feed-forward inference) a lower bit
precision (4 or 5-bit) may be sufficient. Hence, we train
the network off the chip with 8-bit weights and optimize it
to 4 and 5-bit for feed forward inference. The above tech-
nique effectively reduces the footprint of the CIM macro and
reduces the energy consumed by the chip with very minimal
degradation in accuracy.
Access transistors of the SRAM cell connected to the
RBL needs to be operated in the saturation regime. In a
saturation regime, a device will pass a constant current irre-
spective of the voltage applied. The CFET technology is
newly developed and is particularly very vulnerable to pro-
cess variation. Fig. 5(c) and 5(d) shows a device having
finite output conductance due to process variation [4]. Finite
output conductance causes degradation in the forward infer-
ence accuracy of analog summing, or MAC operation [1].
NN are in general robust to synaptic array non-idealities and
one can often retrain a NN with a small number of epochs
to recover back the lost accuracy as described in the next
paragraph.
Fig. 11 shows the RBL curves of the CFET device for
4-bit and 5-bit ADC corresponding to 4-bit and 5-bit input
pulses and weights, respectively. nonlinearity θ is extracted
by fitting the ADC output to the nonlinearity model as shown
in the inset of Fig. 11. The value of θ is easily adopted in
the CIMulator platform to study the impact of the MAC non-
linearity on forward inference accuracy for the entire NN.
Inference accuracy is severely degraded after considering
MAC nonlinearity. Inference accuracy can be improved by
retraining the NN Fig. 12(a). Following a brief re-training
111
 BAIG et al.: 3-D MONOLITHIC STACKING OF CFET ON CMOS FOR NEXT GENERATION CIM SRAM
FIGURE 11. RBL characteristics (θ ) modeling and fitting for FinFET and
CFET device for 4-bit inputs, and weights with the inset showing the MNIST
inference accuracy as a function of epochs during retraining.
FIGURE 12. (a) Image recognition accuracy is degraded due to MAC
non-linearity. A brief re-training significantly improves the accuracy.
(b) Accuracy of 4 and 5-bit weight CFET SRAM cells at various stages of AI
process flow.
(less than 5 epochs) inset of Fig. 11, accuracy is recovered to
85.19% and 89.63% for 4-bit and 5- bit weights, respectively.
Fig. 12(b) shows the accuracy of NN at various stages of
feed forward inference. It should be noted that the accuracy
after retraining is limited to 90% is because of lower bit
precision (4 and 5 bits).
VII. PARASITIC EXTRACTION
Parasitic resistance is obtained using the equation R =
ρ(L/A). Resistivity ρ of the copper interconnect, A being
the cross-sectional area of the interconnect trench. Length
of the read bitline LRBL , and the corresponding resistances
RRBL per unit SRAM cell using CFET and FinFET devices
is summarized in Table 3. Unit capacitance C/L of value
0.378 fF/μm [17] is used to obtain the read bitline capaci-
tance CRBL . Signals on wordline on the other hand do not
impact the performance of the CIM if driven with sufficient
power. Hence, we consider the parasitics of bitline in our
simulations.
112
TABLE 3. Parasitic resistance and capacitance of the read bitline of SRAM
cells using CFET and FinFET. [17].
TABLE 4. Key performance parameters of CFET and regular CMOS (FinFET)
for array sizes with 64 rows and 256 rows.
VIII. PERFORMANCE BENCHMARKING
Table 4 shows the device, circuit, and system-level compar-
ison of CFET and regular CMOS FinFET technology for
SRAM-CIM. Both 64-rows and 256-rows arrays are consid-
ered for the evaluation. The area of the CFET SRAM cell
(Areacell ) is smaller than the FinFET SRAM cell due to the
stacking of the n-channel and p-channel in CFET. Smaller
CFET SRAM cell area leads to small read bitline resistance
and capacitance (RBL and CRBL ) of CFET SRAM arrays in
comparison to FinFET SRAM arrays. Read bit line discharge
current ICell is a function of RBL , CRBL . FinFET having a
large current and 3× lower latency due to higher mobility,
has slightly larger wiring capacitance for the 64 rows case.
CFET on the other hand, shows 3× lower power due to low
Icell and hence the power efficiency (TOPS/W) is better for
the CFET case. For 256 rows, to ensure that VBL does not
drop below 3% of Vdd , Icell is reduced by tuning the input
pulse voltage and therefore has low bit-line current for the
extracted RBL , CRBL values of 256 × 256 macro. The latency
of CFET and CMOS FinFET become similar due to similar
Icell currents.
CFET shows an improvement of 4.24% and 57.19% for
power efficiency in terms of TOPS/W due to lower CFET
SRAM cell area leading to lower parasitics and the bene-
fit becomes significant for large arrays. CFET SRAM cell
requires about 7 masks for 1 stack of SRAM cells built
using 2 metal layers. FinFET also needs 7 masks for the
realization of SRAM cells using 1 poly and 2 metal layers.
Multiple stacks of SRAM cells (3D Stacking) are workable
in the case of a CFET device. The realization of the 3-layer
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MLP neural network described in Fig. 10 requires 17 stacks
of CFET SRAM cells of dimension 64 × 60 and 4 stacks
of SRAM cells of dimension 256 × 256. Stacking the lay-
ers on top of each other greatly improves the performance
in terms of TOPS/(W-mm2 ) proportional to the number of
stacked layers. However, stacking would incur larger process-
ing costs due to repeated processing steps for every SRAM
stack at the expense of improved performance proportional
to the stacked layers in terms of performance per power per
layout area.
IX. CONCLUSION
Measured CFET and regular CMOS FinFET devices are
accurately calibrated in transfer and output characteristics
using the BSIM-CMG compact model. 8T-SRAM cell is
realized using CFET technology and SPICE simulations
of 8T-SRAM CIM macros are conducted for CFET and
FinFET technologies. Evaluation of MAC latency, power,
and non-linearity is carried out, a non-linearity model is
developed and transferred to a higher-level NN simulator
to evaluate system-level inference accuracy. Though FinFET
has an advantage in-terms of latency, CFET shows better
performance per power due to shorter SRAM cell height and
reduced wiring resistance and the efficiency becomes more
evident for large array sizes. Performance in (TOPS/W mm2 )
gets improved by 19× and 7× for 17 and 4 stacked layers of
CFET SRAM cells of dimension 64 × 60 and 256 × 256
respectively. Device nonlinearity caused due finite output
conductance is recovered by retraining the NN with epochs
as few as 5. CFET being a gate-all-around device has supe-
rior gate controllability and reduced short channel effects,
making it scalable beyond N3 [3]. In addition, CFET with
deposited channel has reduced footprint and is stackable in
comparison to regular CMOS.
ACKNOWLEDGMENT
The authors are grateful to the Taiwan Semiconductor
Research Institute for Nanofabrication facilities, and services.
National Center for High-Performance Computing for GPU
computing facilities. They appreciate PROPLUS Solutions
for support on software licenses for model parameter
extraction.
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 Received 17 December 2022; revised 18 February 2023; accepted 4 April 2023. Date of publication 10 April 2023; date of current version 18 April 2023.
The review of this article was arranged by Editor S. Reggiani.
Digital Object Identifier 10.1109/JEDS.2023.3265372

Monolithic Dual-Gate E-Mode

Device-Based NAND Logic Block
for GaN MIS-HEMTs IC Platform
YUHAO ZHU 1,2 , FAN LI1,2 , MIAO CUI1,2 , ZHICHENG FANG1,2 ,
ANG LI 1,2 (Graduate Student Member, IEEE), DONGYI YANG1,2 , YINCHAO ZHAO3 ,
HUIQING WEN 1,2 (Senior Member, IEEE), AND WEN LIU 1,2 (Member, IEEE)
1 School of Advanced Technology, Xi’an Jiaotong–Liverpool University, Suzhou 215123, China
2 Department of Electrical Engineering and Electronics, University of Liverpool, L69 3GJ Liverpool, U.K.
3 School of Intelligent Manufacturing Ecosystem, Xi’an Jiaotong–Liverpool University, Suzhou 215123, China

CORRESPONDING AUTHOR: W. LIU (e-mail: wen.liu@xjtlu.edu.cn)

This work was supported in part by the National Key Research and Development Program of China under Grant 2022YFB3604400; in part by the Suzhou
Science and Technology Program under Grant SYG202131; in part by the Key Program Special Fund in XJTLU under Grant KSF-T-07;
and in part by the XJTLU Research Development Funding under Grant RDF-20-02-43.

ABSTRACT In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND)
and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the
GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility-transistors) platform. The DG-
NAND circuit has an area of 0.118 mm2 with the probe pad, which is 24% lower than the area of the
DD-NAND circuit. Both static and dynamic experimental results validate the advantages of performance
improvement of NAND circuits designed by dual-gate technology at an input voltage of 9 V. This paper
demonstrates the design potential of dual-gate NAND in an all-GaN MIS-HEMTs platform through
compact design.

INDEX TERMS Logic circuits, GaN, MIS-HEMTs, dual-gate E-mode device, monolithic integration.

I. INTRODUCTION HEMTs (high-electron-mobility-transistors) with Al2 O3 gate

AlGaN/GaN HEMTs become a promising candidate for
power converter switches in recent years due to high
switching frequency, power density, and conversion effi-
ciency [1], [2], [3], [4]. Stray inductances and commutation
loops are the main factors that limit the switching speed of
GaN-based power electronics with discrete driver chips [5].
The lateral structure of the GaN-on-Si technology allows
the monolithic integration of several devices for a compact
design to restrain parasitic effects [6].
For GaN devices, the dual-gate technology could be
applied to realize the unique function and reduce require-
ments on the extra component [7], [8], [9], [10]. With the
back gate technology, Hazra et al. [8] proposed a dual-
gate structure to control the threshold voltage. A cascade
dual-gate structure is proposed by Lin et al. to suppress cur-
rent collapse [11]. Gong et al. [12] reported a normally-on
dual-gate AlGaN/GaN MIS (metal-insulator-semiconductor)
This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
oxide layer, which showed a lower reverse gate leak-
age current than its normally-on dual-gate Schottky HFET,
while the gate insulators are also used to enhance the
gate swing [13], [14], [15]. However, all the above applica-
tions are examined with depletion-mode (D-mode) devices.
Since D-mode HEMT technology requires a negative volt-
age control, its counterpart, the enhancement-mode (E-mode)
HEMT, is more suitable for the power conversion applica-
tion [16], [17]. Wolf et al. [18] fabricated a monolithically
integrated bidirectional switch based on E-mode p-GaN
HFETs using dual-gate technology.
For a high-level integrated power system, dual-gate tech-
nology is a feasible solution for monolithic design [19].
Chvála et al. demonstrated a monolithic NAND cell that
is based on InAlN/GaN MIS-HEMTs with a maximum
gate voltage of 3 V, and confirming the validity of the
proposed models [20]. As an essential building block for

230 VOLUME 11, 2023

ZHU et al.: MONOLITHIC DUAL-GATE E-MODE DEVICE-BASED NAND LOGIC BLOCK
FIGURE 1. Schematic cross-section of the AlGaN/GaN MIS-HEMT
DG-NAND logic circuit.
digital circuits, implementing dual-gate E-mode NAND (DG-
NAND) by p-GaN HEMTs with a smaller area provides
an optimization method [21]. However, as a result of the
limitations of p-GaN technology with low gate breakdown
voltage, the gate driver voltage is limited to 5 V, which
requires extra protection circuits for an all-GaN integrated
circuit (IC) development. Moreover, the dynamic test is nec-
essary to analyze the superior characteristics of the dual-gate
design.
In this work, we demonstrate double E-mode devices
NAND (DD-NAND) and dual-gate E-mode device NAND
logic gate circuits by monolithic integrated E/D mode
MIS-HEMTs. The static and dynamic measurements are
conducted to evaluate the performance of the logic gate.
The experimental investigation is reported about the compact
solution to logic blocks for power IC applications.
II. EXPERIMENTS AND DISCUSSION
Fig. 1 depicts a schematic cross-section of the proposed DG-
NAND circuit by utilizing the AlGaN/GaN MIS-HEMTs
technology. All devices are fabricated on a Si substrate con-
sisting of a 4.2 μm GaN buffer layer, a 420 nm layer GaN
channel layer, a 1 nm AlN spacer and a 25 nm AlGaN
layer. GaN devices with D-mode and E-mode are capable of
forming logic circuits by Direct Coupled FET Logic (DCFL)
structure [22], [23]. For E-mode devices, recessed-gate tech-
nology has been utilized [24], and MIS gates have been
implemented to extend the swing voltage of the gate and
thus improve performance [25]. An interconnect layer of Al
is deposited to allow the integration of monolithic integrated
circuits. An in-depth description of the fabrication process is
provided in [26]. The D-mode device features a 5 μm source
to gate distance (LGS ), a 3 μm gate length (LG ), a 5 μm
gate width (WG ), and a 10 μm drain to gate distance (LGD ).
For dual-gate E-mode device dimension, LGS /LG /LGD /WG
= 5/3/5/200 μm, and the separation between the two gates
is set to 10 μm.
The schematic diagram of the GaN-based double device
E-mode (DD-E) structure is illustrated in the red border,
as shown in Fig. 2 (a) and reported in [19]. Unlike tradi-
tional NAND design uses two E-mode devices connected
in series [27], the two E-mode devices share the common
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FIGURE 2. DD-NAND logic circuit: (a) schematic of the logic circuit,
(b) microscope photo (E-mode device dimension: LGS /LG /LGD /WG =
5/3/10/200 µm). DG-NAND logic circuit: (c) circuit diagram, (d) microscope
view.
pad for the connection part to optimize the chip layout.
The D-mode device functions as an active load resistor and
two E-mode gates serve as logic input. In this work, the
presented GaN-based dual-gate E-mode (DG-E) structure is
used to replace the counterpart DD-E structure. Thus the
DG-NAND logic circuit is formed, as shown in Fig. 2 (c).
The employment of dual-gate devices aims to replace two
E-mode HEMTs in the logic circuit design and eliminates
redundant ohmic contacts [28], which could reduce on-
state resistance and parasitic capacitance. The corresponding
microscope views of the DD-NAND and DG-NAND circuits
are shown in Fig. 2 (b) and Fig. 2 (d), respectively. The size
of the layout with the probe pad reduces from 0.155 mm2
to 0.118 mm2 owing to the advantages of a dual-gate
structure.
A. EXPERIMENTAL SETUP
The static test platform is illustrated in Fig. 3 (a), and the
experimental setup is represented by the blue and black
connection. A fixed DC bias voltage is provided to V2 .
It is worth pointing out that DD-E structure measurements
use V1 and V2 to regulate the switching states of the two
E-mode devices. For DG-E device, V1 and V2 are utilized
to control the G1 and G2 gates of the dual-gate E-mode
device, as shown in Fig. 3 (a) left part. Meanwhile, the static
performance of the NAND circuits is monitored by the same
analyzer, the supply voltage VDD is provided. The dynamic
experimental setup is represented by the red and black arrows
in Fig. 3 (a). Two input signals V1 and V2 are supplied by
231
 ZHU et al.: MONOLITHIC DUAL-GATE E-MODE DEVICE-BASED NAND LOGIC BLOCK
FIGURE 3. (a) The experimental setup diagram of the DG-NAND logic
circuit for static (blue and black line) and dynamic measurement (red and
black line), (b) test setup, (c) monolithic integrated GaN driver with
DG-NAND circuit.
a signal generator, and they are set to output different logic
levels. The dynamic performance of the NAND logic circuit
is monitored and recorded by an oscilloscope. The test setup
is demonstrated in Fig. 3 (b). Fig. 3 (c) shows an integration
of the logic unit into the pre-drive module [13], in which
the dual-gate NAND circuit could be utilized to replace the
first-level DCFL inverter in the driver stage. This method
would contribute to the high integration level all-GaN power
conversion system.
B. STATIC CHARACTERISTICS MEASUREMENT FOR DD-E
STRUCTURE AND DG-E DEVICE
The characteristics of the devices and the NAND circuits
were measured by an Agilent B1505A power device ana-
lyzer. As illustrated in Fig. 4 (a), the threshold voltage (Vth )
of the DD-E structure is 1.9 V, and the Vth of the DG-E
device is 1.7 V. Fig. 4 (b) shows the ID -VD curve, the cur-
rent density (ID, max ) is approaching 124.8 mA/mm when
two gates are biased at 9 V for DD-E structure. As could
be observed in Fig. 4 (b), the current density of the DG-E
structure reaches a peak value of 133.9 mA/mm.
C. STATIC AND DYNAMIC CHARACTERISTICS
MEASUREMENT FOR GAN-BASED TWO-INPUT NAND
LOGIC CIRCUIT
In all-GaN monolithic IC design, the logic circuit serves as
the drive control module applied to modify the drive voltage
232
FIGURE 4. Comparison of DD-E structure and DG- E device at V2 is biased
at constant 9 V: (a) Transfer characteristics, (b) output characteristics.
FIGURE 5. Comparison between measured voltage transfer characteristics
of the DG-NAND and DD-NAND logic circuits.
based on the feedback signal [29]. The voltage transfer char-
acteristics (VTC) of the investigated DG-NAND circuit are
demonstrated in Fig. 5, and it is compared with the VTC
of the DD-NAND circuit. A supply voltage VDD of 9 V
is applied. The minimum output voltage (VOL ) of the DD-
NAND circuit is about 1.69 V, and VOL of the DG-NAND
circuit is nearly 1.56 V. Meanwhile, the output voltage of
9 V are obtained in Fig. 5 at V1 = 0 V.
The NAND dynamic test is used to emulate different oper-
ating conditions on an all-GaN integrated power chip. Logic
circuits are designed to generate a drive signal based on the
input operating signal (V1 ) and enable signal (V2 ) as shown
in Fig. 3 (c). Different output states could be observed in
the output waveforms by adjusting the phase between the
input operating signal and enable signal. In Fig. 6, the volt-
age output waveforms of the DG-NAND and DD-NAND
logic circuits working at 100 kHz are monitored by the
oscilloscope. The black and red curves represent the gate
voltages applied on the first gate and the second gate, respec-
tively, from signal generators. When the DD-NAND circuit
and DG-NAND circuit work at a switching frequency of
100 kHz, the falling time of the DG-NAND circuit is 15
percent shorter than the DD-NAND circuit.
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ZHU et al.: MONOLITHIC DUAL-GATE E-MODE DEVICE-BASED NAND LOGIC BLOCK
FIGURE 6. Measured output voltage waveforms of the DD-NAND (green
line) and DG-NAND (blue line) logic circuits.
TABLE 1. Comparison for GaN-based dual-gate device.
Table 1 compares the dual gate technology for differ-
ent applications. References [8], [10], and [12] apply a
second gate in the D-mode to improve device performance.
Papers [18] and [30] uses a second gate to complete
the design of a bidirectional device. Both papers [20]
and [21] utilize a dual-gate structure for the functional block
of the monolithic integrated GaN platform. Verifying the
dynamic performance and comparing it with the conventional
design is necessary. In this paper, a logic circuit module
for the GaN MIS-HEMTs platform is designed based on
DG-E device and compared with the conventional design
of the DD-E structure through dynamic and static tests.
Furthermore, this design also exploits the advantages of
the MIS-HEMTs platform. The large gate swing lowers the
demand for gate voltage protection, resulting in a compact
design.
III. CONCLUSION
In this work, two types of AlGaN/GaN -based NAND logic
circuits are demonstrated. Static and dynamic measurements
experimentally validate the NAND logic circuit of both struc-
tures. The dual-gate E-mode device NAND logic cell utilizes
VOLUME 11, 2023
fewer devices and the die area drops by 24%. Indicated par-
asitic parameters are also reduced due to the elimination of
redundant ohmic contacts. The static characterization of the
dual-gate E-mode device NAND circuit indicates a lower
VOL about 1.46 V. From the dynamic measurement results,
the DG-NAND logic circuit observed less falling time, which
decreased by 15%. Furthermore, the dual-gate NAND will
be applied as a subunit of the drive unit development for
compact design and functional integration of the all-GaN
MIS-HEMTs IC platform.
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