Synopsys EDA Tool Flow for

Front-End Digital IC Design

Professor: Sci.D., Professor

Vazgen Melikyan

Synopsys University Courseware

Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Developed By: Vazgen Melikyan
1
Administration

 Total 42H, 32H Lectures + 10H Labs

 Course mailing list: send e-mail to
vazgenm@synopsys.com

Synopsys University Courseware

Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Developed By: Vazgen Melikyan
2
Grading

 Grades will be assigned on:

 Lectures (70 scores)
 Laboratory Works (30 scores)
 Final exam

Synopsys University Courseware

Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Developed By: Vazgen Melikyan
3
Course Overview

 Digital Design Flow

 2 lectures
 Logic Simulation
 2 lectures
 Logic Synthesis
 4 lectures
 Formal Verification
 4 lectures
 Static Timing Analysis
 4 lectures

Synopsys University Courseware

Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Developed By: Vazgen Melikyan
4
References

 A. Reis, R. Drechsler. Advanced Logic Synthesis.

Springer; 2017
 R. Drechsler. Formal System Verification: State-of the-
Art and Future Trends. Springer, 2017.
 C. Unsalan, B. Tar. Digital System Design with FPGA:
Implementation Using Verilog and VHDL. McGraw-Hill
Education; 1 edition, 2017
 J. Bhasker, R. Chadha. Static Timing Analysis for
Nanometer Designs: A Practical Approach. Springer;
2013

Synopsys University Courseware

Copyright © 2018 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Front-End Digital IC Design
Developed By: Vazgen Melikyan
5