Lecture 3 - MUX - 1bit Adder and ALU Design

DLD Review
1
Logic Blocks
❑ A logic block has a number of binary inputs and produces a number of binary outputs
❑ Combinational Logic Block
▪ The output is only a function of the inputs
▪ There is no memory involved
❑ Sequential Logic Block

▪ Block has some internal memory (state)
▪ The memory also influences the output
❑ Basic Logic Block

▪ Recall from DLD: AND, OR, NOT etc.
▪ You can combine these basic logic blocks to create complex and interesting circuits
2
Standard Notations
❑ Recall from DLD
Short-hand
3
Boolean Algebra
4
Boolean Algebra
Equations involving two values and three primary operators
❑ OR
▪ Symbol: +
▪ 𝑋 = 𝐴 + 𝐵 → 𝑋 is true if at least one of A or B is true
Can you recall truth tables
❑ AND for these operators?
▪ Symbol: .
▪ 𝑋 = 𝐴. 𝐵 → X is true if both A and B are true
❑ NOT
▪ Symbol: ̅
▪ 𝑋 = 𝐴̅ → X is the inverted value of A
5
Implementing MUX
❑ If S = 0, output A
❑ If S = 1, Output B
0 A.0 = 0
B+0 = B =B
B.1 = B
=1
6
Implementing MUX
❑ If S = 0, output A
❑ If S = 1, Output B
1 A.1 = A
A+0 = A =A
B.0 = 0
=0
7
Boolean Algebra Rules
❑ Identity Law
▪ 𝐴 + 0 = 𝐴 (Read as 𝑨 𝑶𝑹𝒆𝒅 𝒘𝒊𝒕𝒉 𝟎)
▪ 𝐴. 1 = 𝐴 (Read as 𝑨 𝑨𝑵𝑫𝒆𝒅 𝒘𝒊𝒕𝒉 𝒐𝒏𝒆)
❑ Zero and One Laws

▪ 𝐴+1=1
▪ 𝐴. 0 = 0
❑ Inverse Laws
▪ 𝐴. 𝐴̅ = 0
▪ 𝐴 + 𝐴̅ = 1
8
Boolean Algebra Rules
❑ Commutative Laws
▪ 𝐴 + 𝐵 = 𝐵 + 𝐴 (can be read as A or B is same as B or A)
▪ 𝐴. 𝐵 = 𝐵. 𝐴 (can be read as A and B is nothing but B and A)
❑ Associative Laws
▪ It does not really matter in which order you perform the operations
▪ 𝐴+ 𝐵+𝐶 = 𝐴+𝐵 +𝐶
▪ 𝐴. 𝐵. 𝐶 = 𝐴. 𝐵 . 𝐶
Same as Linear Algebra
❑ Distributive Laws:
▪ 𝐴. 𝐵 + 𝐶 = 𝐴. 𝐵 + (𝐴. 𝐶) (Read as A ANDed with B ORed C is A AND B ORed with A AND C)
▪ 𝐴 + 𝐵. 𝐶 = 𝐴 + 𝐵 . (𝐴 + 𝐶)
9
DeMorgan’s Law
❑ 𝐴 + 𝐵 = 𝐴.̅ 𝐵ത
❑ 𝐴. 𝐵 = 𝐴̅ + 𝐵ത
To Do: Confirm if these hold true
10
Quick Test
❑ Write Boolean algebra equation
❑ Apply DeMorgan’s Law (𝐴 + 𝐵 = 𝐴.̅ 𝐵)

ത
▪ 𝐴. 𝐵ത ഥ+𝑩
𝑨
Two inverse cancel out
OR
A
B
=
11
Logic Simplification: Cheat Sheet
12
Recall the following Truth Table
❑ Consider a block with 3 inputs, A, B, C and an output E that is true only if exactly 2 inputs are
true
❑ 𝐸= 𝐴. 𝐵 + 𝐵. 𝐶 + 𝐴. 𝐶
What’s the problem here?
❑ 𝐸= 𝐴. 𝐵 + 𝐵. 𝐶 + 𝐴. 𝐶 . (𝐴. 𝐵. 𝐶)
Two must be true but all three cannot be true
Credits: Rajeev Balasubramonian 13

Recall the following Truth Table
❑ Consider a block with 3 inputs, A, B, C and an output E that is true only if exactly 2 inputs are
true
❑ 𝐸 = 𝐴. 𝐵. 𝐶̅ + 𝐴. 𝐶. 𝐵ത + (𝐶. 𝐵. 𝐴)̅
Product of Sums?
Sum of product representation
Credits: Rajeev Balasubramonian 14

Home Work (Non-graded)
❑ From:
▪𝐸= 𝐴. 𝐵 + 𝐵. 𝐶 + 𝐴. 𝐶 . (𝐴. 𝐵. 𝐶)
❑ Derive:
▪ 𝐸 = 𝐴. 𝐵. 𝐶̅ + 𝐴. 𝐶. 𝐵ത + (𝐶. 𝐵. 𝐴)̅
Hint: Distributive Law -> DeMorgan’s Law -> Distributive Law
15
Arithmetic and Logical Unit
16
1-Bit Adder
CarryIn 1 0
A 1 0 0 1
B 0 1 0 1
Sum 0
CarryOut 1
17
1-Bit Adder
CarryIn 1 0
A 1 0 0 1
B 0 1 0 1
Sum 1 0
CarryOut 1
18
1-Bit Adder
CarryIn 1 0
A 1 0 0 1
B 0 1 0 1
Sum 1 0
CarryOut 0 1
19
1-Bit Adder
CarryIn 0 1 0
A 1 0 0 1
B 0 1 0 1
Sum 1 0
CarryOut 0 1
20
1-Bit Adder
CarryIn 0 1 0
A 1 0 0 1
B 0 1 0 1
Sum 1 1 0
CarryOut 0 1
21
1-Bit Adder
CarryIn 0 1 0
A 1 0 0 1
B 0 1 0 1
Sum 1 1 0
CarryOut 0 0 1
22
1-Bit Adder
CarryIn 0 0 1 0
A 1 0 0 1
B 0 1 0 1
Sum 1 1 0
CarryOut 0 0 1
23
1-Bit Adder
CarryIn 0 0 1 0
A 1 0 0 1
B 0 1 0 1
Sum 1 1 1 0
CarryOut 0 0 0 1
24
1-bit Adder: Truth Table
A B CarryIn CarryOut Sum
0 0 0
25
0 0 0 0 0
26
0 0 0 0 0
0 0 1
27
0 0 0 0 0
0 0 1 0 1
28
0 0 0 0 0
0 0 1 0 1
0 1 0
29
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
30
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1
31
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
32
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0
33
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
34
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1
35
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
36
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0
37
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
38
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1
39
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
40
How to convert this table Write Boolean expression
to the equations? with term covering each
A B CarryIn CarryOut Sum “1” in the output.
0 0 0 0 0
0 0 1 0 1 𝑆𝑢𝑚 = 𝐶𝑎𝑟𝑟𝑦𝐼𝑛. 𝐴.̅ 𝐵ത + 𝐵. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛. 𝐴̅ + 𝐴. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛. 𝐵ത + 𝐴. 𝐵. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
41
Identify “Don’t Cares”
How to convert this table
A B CarryIn CarryOut Sum to the equations?
0 0 0 0 0
0 1 0 0 1 ത 𝐶𝑎𝑟𝑟𝑦𝐼𝑛 + 𝐴.̅ 𝐵. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛

𝐶𝑎𝑟𝑟𝑦𝑂𝑢𝑡 = 𝐴. 𝐵. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛 + 𝐴. 𝐵.
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0 𝐶𝑎𝑟𝑟𝑦𝑂𝑢𝑡 = 𝐴. 𝐵 + 𝐴. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛 + 𝐵. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛
1 1 0 1 0
1 1 1 1 1
42
How to convert this table
A B CarryIn CarryOut Sum to the equations?

0 0 1 0 1 𝐶𝑎𝑟𝑟𝑦𝑂𝑢𝑡 = 𝐴. 𝐵 + 𝐴. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛 + 𝐵. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
43
Adder Block for Carry Out Signal
44
1-bit Adder
❑ Full adder (3,2 adder)
❑ Half adder (2,2 adder)
Useful Link:
https://www.geeksforgeeks.org/differ
ence-between-half-adder-and-full-
adder/
45
How to do 1+1 = 2?
Binary Decimal
0 0
1 1
46
How to do 1+1 = 2?
Binary Decimal
0 0
1 1
10 2
11 3
100 4
101 5
110 6
512 256 128 64 32 16 8 4 2 1
0 0 0 0 0 0 0 0 0 1
47
How to do 1+1 = 2?
Binary Decimal
0 0
1 1
10 2
11 3
100 4
101 5
110 6
512 256 128 64 32 16 8 4 2 1
0 0 0 0 0 0 0 0 1 0
48
How to do 1+1 = 2?
Binary Decimal
0 0
1 1
10 2
11 3
100 4
101 5
110 6
512 256 128 64 32 16 8 4 2 1
0 0 0 0 0 0 0 0 1 1
49
How to do 1+1 = 2?
Binary Decimal
0 0
1 1
1
10 2
11 3 0
100 4 1
101 5
110 6
1
512 256 128 64 32 16 8 4 2 1
0 0 0 0 0 0 0 0 0 1 10
50
How to do 1+1 = 2?
Binary Decimal
0 0
1 1
1
10 2
11 3 0
100 4 1
101 5
110 6
1
512 256 128 64 32 16 8 4 2 1
0 0 0 0 0 0 0 0 1 0 10
51
How to do 2+2 = 4?
Binary Decimal 10+10=100
0 0
1 1
10 2
11 3
100 4
101 5
110 6
512 256 128 64 32 16 8 4 2 1
0 0 0 0 0 0 0 0 1 0
52
How to do 2+2 = 4?
0 0
0 0 0
1 1
10 2 1
11 3 100 1
0
100 4 1
101
110
5
6
4 0
0
1
512 256 128 64 32 16 8 4 2 1
0 0 0 0 0 0 0 0 1 0
53
How to do 2+2 = 4?
0 0
0 0 0
1 1
10 2 1
11 3 100 1
0
100 4 1
101
110
5
6
4 0
0
1
512 256 128 64 32 16 8 4 2 1
0 0 0 0 0 0 0 1 0 0
54
How is it 1-bit adder when there are two
bits input?
The operations are always 1-bit adder means that each input
between two inputs. would be of 1 bit (0 or 1).
55
Similarly for 32-bit adder…
32-bit adder means that each of

the two inputs would be of 32 bit.
Would a 32-bit adder/ALU would

take same amount of time as 1-bit
adder/ALU?
56
Time taken by a 32-bit ALU
There would be a delay as each
subsequent ALU is waiting for
carryIn from previous ALU.
So if each ALU takes 1ns to

execute, total time for a 32bit
input would be 32ns.
We can reduce this time by using

“carry look-ahead adder” instead
of “ripple carry adder”.
57
1-Bit ALU
58
Performing More Operations…
❑ AND
❑ OR
Multiplexer (MUX)
a.b
00
a+b
01
Sum
10
1-bit Adder
59
Recall Binary Addition Table
CarryIn 0 0 1 0 …
A 1 0 0 1 …
B 0 1 0 1 …
Sum 1 1 1 0 …
CarryOut 0 0 0 1 …
60
0 10
32-bit ALU Sum

❑ Connect 1-bit ALUs in a series
CarryOut
CarryIn 0 0 1 0 …
A 1 0 0 1 …
B 0 1 0 1 …
Sum 1 1 1 0 …
CarryOut 0 0 0 1 …
What if we want to perform AND , OR operations?

Bit-wise operations would be performed on A and B,
without any CarryOut.
Also known as 32-bit Ripple Carry Adder
61
Incorporating Subtraction
❑ Subtraction is the same as adding the negative version of an operand
▪ Negating a two’s complement number is to invert each bit (aka One’s complement) and then add 1.
𝑎 − 𝑏 = 𝑎 + (−𝑏)
𝑎 − 𝑏 = 𝑎 + −𝑏 = 𝑎 + 𝑏ത + 1 = 𝑎 + 𝑏ത + 1
62
1-bit ALU with Subtraction
❑ Invert bits of b and add 1 00 – AND
1
▪ Include an inverter 1 01 – OR
▪ CarryIn for the first bit is 1 10 – ADD
𝒂 10 – ADD
▪ 𝑎 + 𝑏ത + 1
(But set
▪ So basically if Binvert is 1, CarryIn for the first
Binvert = 1)
bit has to be 1
ഥ
𝒂+𝒃
ഥ
𝒃
Inverter
63
Incorporating NOR
❑ NOR is nothing but an inverted OR
❑ 𝐴+𝐵
❑ Recall DeMorgan’s Law
▪ 𝐴 + 𝐵 = 𝐴̅ . 𝐵ത
64
Incorporating NOR
❑ NOR is nothing but an inverted OR
❑ 𝐴+𝐵
▪ 𝐴 + 𝐵 = 𝐴̅ . 𝐵ത
65
Incorporating NOR
❑ NOR is nothing but an inverted OR 1
1
❑ 𝐴+𝐵 00 – AND
▪ 𝐴 + 𝐵 = 𝐴̅ . 𝐵ത
ഥ
𝒂
ഥ
𝒃
66
Incorporating NAND
❑ NAND is nothing but an inverted AND
❑ 𝐴. 𝐵
▪ 𝐴. 𝐵 = 𝐴̅ + 𝐵ത
67
Incorporating NAND
❑ NOR is nothing but an inverted AND 1
1
❑ 𝐴. 𝐵 01 – OR
▪ 𝐴. 𝐵 = 𝐴̅ + 𝐵ത
ഥ
𝒂
ഥ
𝒃
68
Additional Functions
❑ Self Study (Tailoring 32Bit ALU to MIPS: Page B-31)
▪ Set on Less Than (slt) instruction
▪ Conditional Branch instruction (a==b)
69
Final 32Bit ALU Implementing ==:
Do A-B and give to
NOR gate at the end.
70
ALU Control Lines
ALU Operation
Ai Bn OpCode
AND
OR
Add
Sub
Slt
NOR
NAND
Beq
71
ALU Control Lines
ALU Operation
Ai Bn OpCode
AND 0 0 00
OR
Add
Sub
Slt
NOR
NAND
Beq
72
ALU Control Lines
ALU Operation
Ai Bn OpCode
AND 0 0 00
OR 0 0 01
Add
Sub
Slt
NOR
NAND
Beq
73
ALU Control Lines
ALU Operation
Ai Bn OpCode
AND 0 0 00
OR 0 0 01
Add 0 0 10
Sub
Slt
NOR
NAND
Beq
74
ALU Control Lines
ALU Operation
Ai Bn OpCode
AND 0 0 00
OR 0 0 01
Add 0 0 10
Sub 0 1 10
Slt
NOR
NAND
Beq
75
ALU Control Lines
ALU Operation
Ai Bn OpCode
AND 0 0 00
OR 0 0 01
Add 0 0 10
Sub 0 1 10
Slt 0 1 11
NOR
NAND
Beq
76
ALU Control Lines
ALU Operation
Ai Bn OpCode
AND 0 0 00
OR 0 0 01
Add 0 0 10
Sub 0 1 10
Slt 0 1 11
NOR 1 1 00
NAND
Beq
77
ALU Control Lines
ALU Operation
Ai Bn OpCode
AND 0 0 00
OR 0 0 01
Add 0 0 10
Sub 0 1 10
Slt 0 1 11
NOR 1 1 00
NAND 1 1 01
Beq
78
ALU Control Lines
ALU Operation
Ai Bn OpCode
AND 0 0 00
OR 0 0 01
Add 0 0 10
Sub 0 1 10
Slt 0 1 11
NOR 1 1 00
NAND 1 1 01
Beq 0 1 -
79
Quiz 1
❑ Tuesday 28th February
▪ Lecture 1-3
80
Book Reading
❑ T1: B.1 – B.3, B.5
81

Lecture 3 - MUX - 1bit Adder and ALU Design

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Lecture 3 - MUX - 1bit Adder and ALU Design

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DLD Review

❑ Sequential Logic Block

❑ Basic Logic Block

❑ Zero and One Laws

To Do: Confirm if these hold true

❑ Apply DeMorgan’s Law (𝐴 + 𝐵 = 𝐴.̅ 𝐵)

Credits: Rajeev Balasubramonian 13

Credits: Rajeev Balasubramonian 14

Hint: Distributive Law -> DeMorgan’s Law -> Distributive Law

0 1 0 0 1 ത 𝐶𝑎𝑟𝑟𝑦𝐼𝑛 + 𝐴.̅ 𝐵. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛

0 0 0 0 0 𝑆𝑢𝑚 = 𝐶𝑎𝑟𝑟𝑦𝐼𝑛. 𝐴.̅ 𝐵ത + 𝐵. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛. 𝐴̅ + 𝐴. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛. 𝐵ത + 𝐴. 𝐵. 𝐶𝑎𝑟𝑟𝑦𝐼𝑛

512 256 128 64 32 16 8 4 2 1

512 256 128 64 32 16 8 4 2 1

512 256 128 64 32 16 8 4 2 1

512 256 128 64 32 16 8 4 2 1

512 256 128 64 32 16 8 4 2 1

512 256 128 64 32 16 8 4 2 1

32-bit adder means that each of

Would a 32-bit adder/ALU would

So if each ALU takes 1ns to

We can reduce this time by using

32-bit ALU Sum

What if we want to perform AND , OR operations?

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