NOISE VOLTAGE OBJECTIVES. Since noise problems in digital logic produce marginal performance, proper operation of z lab model or protorype system is not enough to guarantee @ reliable Gesign. [n addition to proper operation the following measurements should be made: (1) ground noise voltage and (2) power-supply noise voltage. The best method for determining the quality of the power and ground system on 9 printed wiring board is to measure the peak-differential ground. noise voltage between various points on the bourd, and also the V,, ground voltage on each IC. Although many digital devices will work with ground noise differentials as large as 1 V (Motorola Application Note AN-707), operational margins and reliability may well be compromised. Therefore every effort should be made to limit the peak-differential ground voltage to SU0mV or less. Experience has shown that this can be achieved with s ground grid or plane A well-designed grid system can hold the peak- — (CURRENT, GARAYING CONDUCTOR 8 Figure 10.10, Tost ot up to mzarare the volhage drop betwen points A end B an a curren! erring condurior (A) Tes: lee pale! eurtenvcnnrsing comelactor pick up au erat vali tue to the carrenecrrsing conductor's magnetic jeld. (1B) Tes leads perpenaialar to ear earning conducior do net pick up at errr voltae MEASURING NOISE VOLTAGES When measuring digital logie noise voltages consideration must be given to (1) the bandwidth of the measuring instrumentation, (2) the high-frequency common-mode rejection ratio (CMRR) of the instrumentation, and (3) the dress of the leads trom the measuring instrument to the circuit under test Nowe measurements must be made with a wide-bandwidth oscilloscope (100 MHz. minimum, with 20) MHz preferred) and with a wide-bandwidth differential probe with a good high-frequency CMRR (100 to 1 at 100 MHz Logic FAMILIES 235 or better; ¢.g., Tektronix P6046 Active Differential Probe). ‘This type of differential probe has high common-mode rejection at high frequencies because it performs the common-mode rejection within the probe body and then transmits the sional back to the single-ended oscilloscope. Instrumenta- tion with large bandwidth and large CMRR is required to measure the high-frequency components of the noise pulses. Equal length leads should be connected to the two terminals of the Aifferential probe. These leads should be dressed perpendicular to the circuit board to minimize the inductive coupling between the conductors on the board and the test leads (Paul, 1986; also Skilling, 1951, pp. 103-105). Figure 10-10 shows two methods of measuring the voltage between points A and B of @ current-carrying conductor. Figure 10-104 shows an incorrect setup, and Fig, 10-108, a correct one. When the test leads are ran close 10. and parallel with, the curtent-carrying conductor (Fig. 10-10A), the mag- netic field from the conductor encircles the test leads, thereby coupling a fe into the leads. When the leads are perpendicular fo the conductor 4s 10-10 coupling does not occur, Ideally the leads should be perpen- dicular to the conductor for a great distence, to minimize the coupling, Normally the test leads are routed perpendicular to the conductor for at least Sem If differential probe is not available. measurements can be made with i wide-bandwidth, single-ended probe and scope, provided the circuit ean be floated (with no gronnd connection) and powered from 2 battery. This way the only ground on the circuit will be the ground connection of the seope, and common-mode problems will be minimized, The routing of the test Teads should be done in the way previously discussed. UNUSED INPUTS To prevent unintentional switching and aoise generation, all unused inputs must be connected somewhere, and not lef open. Otherwise, a floating input, picking up noise, may cause a gate to switch randomly. ‘This connec tion is especially important for CMOS because of its high input impedance, but applies to other logic families as well. In addition, for CMOS circuits, an unused gate whese inputs are not connected may, hecause of noise, bias itself into the linear region and significantly increase the ée current drawn by the circuit, The unused inputs are normally connected to V., voltage through 2 series resistor, or to ground, LOGIC FAMILIES ‘The principles discussed in this chapter are independent of logic families ‘They can be applied to TIL, STTL, LSTTL, CMOS, HCMOS. FAST. ALS. ACL. and ECL. ‘The most important parameters are the rise/fall time296 10 + OIGITAL GICUIT NOISE AND LAYOUT and the magnitude of the trensient switching current. The faster the rise/all time and the greater the transient current, the more important the principles discussed here ate. For exemple, poor grounds and improper decoupling can often be tolerated, although they should not be encouraged, in the case 0: slow-speed CMOS when the rise! fell times are 30 to S0 ns, When rise times are under Ins, however, these principles are very important With the many different logic technologies available today, designers should resist the temptation to use the fastest logic available. Instead, ihe slowest- and lowest-power logic family that ean do the job should be used, ¢ noise and interference.