2018 2nd IEEE Advanced Information Management,Communicates,Electronic and Automation Control Conference(IMCEC 2018)
Design and Implementation of DDR4 SDRAM
Controller Based on FPGA
Jia Zheng, Kai Yan, Yue Zhang, Zengping Chen
School of Electronic Science and Engineering, National University of Defense Technology
Changsha, China
jia_zheng77@163.com
Abstract—The DDR4 SDRAM is the latest Double-Data-Rate
Fourth Generation Synchronous Dynamic Random Access
Memory with the advantages of large capacity, high speed, low
power consumption and good stability. In order to solve the data
cache problem of the ultra-high-speed sampling and processing
system, this paper designs DDR4 SDRAM read-write controller
module based on UltraScale DDR4_v2.2 IP core. This paper
mainly introduces the characteristics and working principle of
DDR4, introduces the DDR4 read-write controller module in
detail, and packages it as the FIFO interface and finally tests and
gives the test results. System tests results verify that the module
meets the requirements of large-capacity data cache, and has the
advantages of good stability and high portability.
Keywords—DDR4 SDRAM, UltraScale, DDR4_v2.2 IP core,
read-write controller
I. INTRODUCTION
DDR4 SDRAM is the latest generation of Double-Data-
Rate Synchronous Dynamic Random Access Memory.
Compared to the previous generation, DDR3 SDRAM, its
performance has greatly improved. When applied to FPGA
system based on UltraScale architecture, DDR4 SDRAM data
transfer rate up to 2400Mb/s, increased by 30% compared to
DDR3.At the same time, its power consumption is very low,
the data voltage is only 1.2V, which is 20% less than that of
DDR3, but the memory capacity is greatly increased. DDR4
has newly added the Bank Group data group design. Each
Bank Group has the characteristics of independent startup,
operation reading and writing, which makes it more efficient
than DDR3. In addition, the functions of DBI (Bata Bus
Inversion), CRC (Cyclic Redundancy Check) and CA parity
are also added. These functions enhance the signal integrity of
DDR4 and improve the reliability of data transmission and
storage. In addition, DDR4 also inherits the function of DDR3.
It has three channel modes of x4, X8 and x16. It is compatible
with AXI interface protocol, supports ECC, data mask, and has
reset and ZQ calibration functions.
This paper introduces the design and implementation of
DDR4 SDRAM read and write controller based on UltraScale
DDR4_v2.2 IP core, and finally completes the DDR4 SDRAM
read and write controller tests based on Airtex UltraScale series
FPGA [1]. The test results show that the DDR4 SDRAM read-
write controller can meet the data rate requirements, and has
the advantages of good stability, simple interface and strong
portability.
978-1-5386-1803-5/18/$31.00 ©2018 IEEE
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II. DDR4 WORKING PRINCIPLE
After the system is powered on or reseted, DDR4 SDRAM
needs to be initialized according to the given initialization flow.
DDR4 SDRAM provides 8 mode registers for users to use
more easily [2]. The user configures a specific value of the
MRS command during the initialization process. These mode
registers are mainly used for initialization such as burst type,
burst length, ODT resistance, ZQ calibration, CAS latency,
TDQS enable, DBI enable, CA parity and Write Leveling
enable [4]. When the initialization operation is completed, the
system enters the IDLE state, waiting for the read-write
controller access. The main operating commands is as follows:
A. Precharge Command (PRE)
The PRECHARGE command is used to close the row that
has been opened with the Bank. After the PRECHARGE
command, it is necessary to wait a certain amount of time
before the next row is activated. Once a bank has executed a
pre-charge command, the Bank is in IDLE state and the next
command can be executed. This row must be activated before
sending read and write commands to any ROW in the Bank.
B. Activation Command (ACT)
The ACT command is used to open (or activate) a row of a
specified Bank. The BG0-BG1 in the X8 device is used to
select the Bank group, and the BA0- BA1 is used to select a
specific Bank of the Bank group, and A0-A17 is the choice of
the specific row. The row remains active until the self- refresh
command arrives. In the same Bank, if you need to open
another row, you need to close the already open row, that is,
you need to send a self-refresh command.
C. Refresh Command
Refresh command is used in different operations, and the
command does not continue. Before entering the refresh
command, all the banks need to complete the PRECHARGE
command [3]. After the refresh command is completed, all the
banks enter the IDLE state. The refresh addressing is generated
by the internal refresh controller and does not require external
address information.
D. Self-refresh Command
DDR4 SDRAM, like DDR3 SDRAM, requires constant
self-refresh operations to maintain the effective storage of data
onto the storage unit. The self-refresh command has an
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inherent operation cycle that operates on all rows in turn. The the input/output buffer, and ensure the instruction and address,
self-refresh command also does not require the external supply data synchronization and signal maintenance. The memory
of row address information on operation. When the other parts control module is located between the user interface module
of the system power down, the self-refresh command still and the physical layer module. The front end of the memory
maintains its function. control module provides a local interface for the user interface
module. The rear interface connects to the physical layer
E. Read/Write Command interface and handles all the interface requests for the module.
When DDR4's Bank executes the row activation command, Users can directly control the user interface module read and
the read / write command can be sent to the row to read / write. write operations to meet the user interface module timing and
When the read / write command is executed, it is possible to logic requirements can be.
choose whether an automatic PRECHARGE operation is sys_clk_p DDR4 IP CORE
allowed. When the command is read, the data transfer will be sys_clk_n
triggered after the column address is submitted to the DDR4 sys_rst Physical
interface again [5]. However, after the data is triggered, it takes Layer
a certain amount of drive time to reach the data I/O bus and ddr_cs_n
output it. app_en
app_rdy ddr_ui_clk_sync_rst
app_autoprecharge ddr_cke
ddr_ck_n
III. DESIGN OF DDR4 SDRAM READ WRITE CONTROLLER app_wdf_rdy ddr_act_n
User
Memory
The DDR4 SDRAM read-write controller of this paper is app_wdf_wren Interface Native Control MC/PHY IOB ddr_ui_clk
Interface
Module Interface ddr_ck_c
designed based on the UltraScale DDR4_v2.2 IP core. This ddr_reset_n
section first introduces the internal structure of the IP core, app_wdf_end ddr_ck_t
secondly introduces the overall structure of the design, and
finally introduces the principle of read-write controls state app_rd_data
machine. The structure of the DDR4 SDRAM IP core based on app_rd_data_valid
the UltraScale architecture is shown in Fig.1 [6]. app_rd_data_end
Init_calib_complete
app_hi_pri ddr_odt
The IP core consists of three parts: user interface module, ddr_parity
memory control module and physical layer interface module.
The back end of the physical interface module is directly Fig. 1. UltraScale Architecture-Based FPGAs DDR4 Memory Interface
Solution
connected to the peripheral circuit of the DDR4 hardware, and
the front end is connected to the memory control module. Its In the design, first consider the system structure as a whole.
main function is to capture the data sent by DDR4, generate the In order to facilitate the user, this article will be read-write
control instruction signals required by DDR4, and send all controller package in the form of FIFO. The overall structure
DDR4 control signals, address signals and data signals through shown in Fig.2.

read_fifo_rd_en

data fifo_out_data fifo_in_data data

valid valid
DDR4_read_write_c
write_fifo wr_prog_full read_fifo
ontrol valid
valid wr_prog_empty rd_prog_empty
fifo_rd_en rd_prog_full

DDR4 IP Core

Fig. 2. The overall structure of the read-write controller

As a whole, the user's method of using the read-write

controller is similar to the FIFO. This saves more control signal
lines of the IP core, which is more convenient.
To read and write controller module, read and write control
process is divided into three state processes, respectively, the
wait state, write state and read state. The conversion to these
three states is controlled by the signal line init_calib_complete
of the IP core along with the read/write FIFO empty flag
signals line and the internal flag signals line. The specific
schematic diagram of state switching is shown in Fig.3.
A. Wait State
At the beginning, DDR4 SDRAM needs to initialize the
configuration, so first need to wait for the initialization
completion. If the initialization is not completed, or the
app_rdy signal is not raised, or the read and write condition is
not satisfied when writing FIFO and read FIFO, the read and
write control logic will always be in wait state. Only when
conditions are satisfied, they begin to enter the next state.

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B. Write Status
When the IP core is initialized and the FIFO fifo_prog_full
signal is pulled high, the read and write control logic enters the
write state until the write FIFO fifo_prog_empty is pulled high
to stop writing. During the writing process, DDR4 SDRAM
cannot be full. For the IP core, when the IP core is given a
write command and the app_rdy and app_wdf_rdy signals are
both high, it indicates that the IP core is ready to write. The
app_rdy signal is an indication that user interface of the IP core
is ready, and app_wdf_rdy is a ready signal for the user data
interface. Only when the write address and write data are valid,
the data is written into the correct address. As shown in the
following write timing diagram, the write address is valid only
when the app_rdy signal and app_en signal are both high.
When app_wdf_rdy and app_wdf_wren both go high, the write
data is valid. However, writing addresses and writing data does
not require that it was valid at the same time, and can differ by
a few clock cycles.

!wr_fifo_prog_full && !rd_fifo_prog_full

&& cnt >= low_cnt

wr_fifo_prog_full &&!ddr_full

IDLE WRITE READ

wr_fifo_prog_empty ||
ddr_full

wr_fifo_prog_full || rd_fifo_prog_full
|| cnt <= low_cnt

Fig. 3. Read write state machine

When designing the write state in this paper, write address control logic enter the read state. When writing a state, the
and write data is controlled to be valid at the same time in amount of data required to be read out should be less than the
order to prevent the clock cycle of writing address and write amount of data written. The read state stops until the
data onto exceeding the valid value. That is, both app_rdy and fifo_prog_full signal of the FIFO is pulled up, or the FIFO is
app_wdf_rdy are simultaneously written with valid addresses read, or the remaining unread data onto memory is less than
and valid data. Other clock cycles pull down the address valid low_cnt.
signal app_en and the data valid signal app_wdf_wren.
For the IP core, when the IP core is given a read command
and the app_rdy signal is pulled high, it indicates that the IP
clk core is ready to read. When the read address is valid, the data
corresponding to the address in DDR4 will be read out after
app_cmd WRITE WRITE WRITE several cycles. When the read and write control logic are in the
app_addr Addr a Addr b Addr c
read state, and when the app_rdy signal is high, the effective
read address is written, and the address effective signal app_en
app_en is pulled down in other clock cycles.
app_rdy

app_wdf_rdy
clk

app_maks app_cmd WRITE WRITE

app_wdf_data W a0 W b0 W c0 app_addr Addr a Addr b

app_wdf_wren app_en

app_wdf_end
app_rdy

Fig. 4. Write operation timing diagram

app_rd_data R0 R1

C. Read State app_rd_data_valid

When the IP core is initialized and the capacity of writing app_rd_data_end

FIFO is in the process from fifo_prog_empty to fifo_prog_full,
and when the read FIFO is not yet full, the read and write Fig. 5. Read operation timing diagram

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 IV. READING AND WRITING EFFICIENCY TEST AND
ANALYSIS
Because the activation command and PRECHARGE
command will be activated when the row address is refreshed
in BANK. When DDR4 SDRAM read and write data, there
will be some time gaps. Therefore, reading and writing control
modules need to be read and write efficiency test.
First, in the actual test, an error checking module was added
to the DDR4 read-write controller. This article gives the actual
signal waveform captured by the ILA, as shown in Fig. 6:
Fig. 6. DDR4 read and write operation test diagram
As you can see in Fig. 6, when reading and writing, the
error signal has been low, and the error is not caught.
Second, the data rate calculation formula for DDR4 read-
write controller is given.
1 [6]
Data rate width u clk u efficiency u (1)
2 Sci. & Tech., vol. 29, issue 11, pp. 47-50, 2016.
Where, width is the data bit width of the IP core user
interface, clk is the clock rate of the user interface, and
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efficiency is the read-write efficiency of the read-write control
module.
In order to test the read-write controller module, the
memory capacity of DDR4 SDRAM used in this paper is 8GB
and the maximum communication speed is 2400MT/s. IP core
user interface data width is 512 bits, and the interface clock
rate is 300MHz. The steady reading and writing efficiency of
the final test results is 90%. According to the formula, the final
data rate can be calculated to be 8.64GB/s, which fully meets
the data rate requirements of the DDR4 SDRAM cache part in
the ultra-high speed acquisition and processing system.
V. CONCLUSIONS
This paper analyzes the DDR4 SDRAM operation principle,
and analyzes, designs and realizes the DDR4 read-write
controller logic based on the Virtex UltraScale DDR4_v2.2 IP
core. In order to make the module easier to use, the read-write
controller is packaged as a FIFO. Finally, this paper tested read
and write efficiency in a Virtex UltraScale series of FPGAs.
After testing, the controller has the advantages of stable work,
high efficiency, simple interface and good portability.
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