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UVM RAL – Part 10- Different register Methods

Understanding Desired and Mirror Value:

Desired Value:
Value of register for next transaction

Allow to specify value before transaction/write.

Mirrored value:
Store current known state of hardware registers.
Updated at the end of each read/write .

Both are updated at each transaction.

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METHODS BEFORE TRANSACTION

This method do not perform any actual transaction.
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Methods after transaction

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Working with Mirrored value

class top_reg_seq extends uvm_sequence;

`uvm_object_utils(top_reg_seq)

top_reg_block regmodel;

function new(string name = "top_reg_seq");

super.new(name);
endfunction

task body();
uvm_status_e status;
bit[7:0] rdata,rdata_m;//temporary reg for desired and mirror

//initial value
//we are checking default value
rdata = regmodel.temp_reg_inst.get();
rdata_n = regmodel.temp_reg_inst.get_mirrored_value();
`uvm_info("SEQ",$sformatf("Initial value -> Desired value : %0d and Mirrored value :
%0d:,rdata,rdata_m),UVM_NONE);

//Update desire value

// in set method mirror value wont be affected
regmodel.temp_reg_inst.set(8'h11);

//get desire value

rdata = regmodel.temp_reg_inst.get();
rdata_n = regmodel.temp_reg_inst.get_mirrored_value();
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`uvm_info("SEQ",$sformatf("Initial value -> Desired value : %0d and Mirrored value :

%0d:,rdata,rdata_m),UVM_NONE);

// call write method

//we havent added any predictor block,but still want to see current state of hardware
register. in that case we work with implicit predictor
// we have to call auto predict method in uvm_reg_block.
// Syntax for auto predict: default_map.set_auto_predict(1);
// Without auto_predict we get only desired value not mirrored value
regmodel.temp_reg_inst.update(status);
rdata = regmodel.temp_reg_inst.get();
rdata_n = regmodel.temp_reg_inst.get_mirrored_value();
`uvm_info("SEQ",$sformatf("Initial value -> Desired value : %0d and Mirrored value :
%0d:,rdata,rdata_m),UVM_NONE);
endtask
endclass

https://www.edaplayground.com/x/w35V
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Understanding Predict and Mirror value

Predict method update mirrored value for this register

It return bit type
If the prediction successful Returns true.
Set method specifically deals with desired value.
When we consider predict method, update desired as well as mirrored value.
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Mirror method Read the register and update/check its mirror value
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Code : Understanding predict and mirror

class top_reg_seq extends uvm_sequence;

`uvm_object_utils(top_reg_seq)

top_reg_block regmodel;

function new(string name = "top_reg_seq");

super.new(name);
endfunction

task body();
uvm_status_e status;
bit[7:0] rdata,rdata_m;//temporary reg for desired and mirror

// WRITE METHOD
regmodel.temp_reg_inst.write(status,5'h10);
rdata = regmodel.temp_reg_inst.get();
rdata_n = regmodel.temp_reg_inst.get_mirrored_value();
`uvm_info("SEQ",$sformatf("Initial value -> Desired value : %0d and Mirrored value :
%0d:,rdata,rdata_m),UVM_NONE);

//PREDICT METHOD : override the current as well as desired value

// predominately used for reg model
regmodel.temp_reg_inst.predict(5'h05);
rdata = regmodel.temp_reg_inst.get();
rdata_n = regmodel.temp_reg_inst.get_mirrored_value();
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`uvm_info("SEQ",$sformatf("Initial value -> Desired value : %0d and Mirrored value :

%0d:,rdata,rdata_m),UVM_NONE);
//MIRROR METHOD
regmodel.temp_reg_inst.mirror(status,UVM_CHECK);//two argument
// mirror used for read transaction
// If value 5'h10 not equal to 5'h05 (it will throw an error)
rdata = regmodel.temp_reg_inst.get();
rdata_n = regmodel.temp_reg_inst.get_mirrored_value();

`uvm_info("SEQ",$sformatf("Initial value -> Desired value : %0d and Mirrored value :

%0d:,rdata,rdata_m),UVM_NONE);

endtask

endclass

Single Read and Write Transaction

 Write method is used to write the specified value in a DUT register.
 Once we performed write transaction,Mirror value will be updated.
 Read method is used to read the value from a register

Code :
class top_reg_seq extends uvm_sequence;
`uvm_object_utils(top_reg_seq)

top_reg_block regmodel;

function new(string name = "top_reg_seq");

super.new(name);
endfunction

task body();
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uvm_status_e status;
bit[7:0] rdata,rdata_m;//temporary reg for desired and mirror
bit [7:0] dout_t;

regmodel.temp_reg_inst.write(status,5'h05);
rdata = regmodel.temp_reg_inst.get();
rdata_m = regmodel.temp_reg_inst.get_mirrored_value();

`uvm_info("SEQ",$sformatf("Write Tx to DUT -> Des:%0d and Mir :

%0d",rdata,rdata_m),UVM_NONE);

regmodel.temp_reg_inst.read(status,dout_t);
rdata_m = regmodel.temp_reg_inst.get_mirrored_value();
`uvm_info("SEQ",$sformatf("Read Tx to DUT -> Des:%0d and Mir : %0d Data
read=%0d",rdata,rdata_m,dout_t),UVM_NONE);

endtask
endclass

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Multiple Read and Write Transaction

class top_reg_seq extends uvm_sequence;

`uvm_object_utils(top_reg_seq)

top_reg_block regmodel;

function new(string name = "top_reg_seq");

super.new(name);
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endfunction

task body();
uvm_status_e status;
bit[7:0] rdata,rdata_m;//temporary reg for desired and mirror
bit [7:0] dout_t;
bit [7:0] din_temp;

for(int i=0;i<5;i++) begin //5 random transaction

din_temp = $urandom_range(5,20)
regmodel.temp_reg_inst.write(status,din_temp);
rdata = regmodel.temp_reg_inst.get();
rdata_m = regmodel.temp_reg_inst.get_mirrored_value();

`uvm_info("SEQ",$sformatf("Write Tx to DUT -> Des:%0d and Mir :

%0d",rdata,rdata_m),UVM_NONE);

regmodel.temp_reg_inst.read(status,dout_t);
rdata_m = regmodel.temp_reg_inst.get_mirrored_value();
`uvm_info("SEQ",$sformatf("Read Tx to DUT -> Des:%0d and Mir : %0d Data
read=%0d",rdata,rdata_m,dout_t),UVM_NONE);

endtask

endclass

Using randomize

class top_reg_seq extends uvm_sequence;

`uvm_object_utils(top_reg_seq)
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top_reg_block regmodel;

function new(string name = "top_reg_seq");

super.new(name);
endfunction

task body();
uvm_status_e status;
bit[7:0] rdata;

for(int i=0;i<10;i++)
begin
regmodel.temp_reg_inst.randomize();
regmodel.temp_reg_inst.write(status,regmodel.temp_reg_inst.temp.value);//write
method:regblock.reg_instance.(single or multiple field).Randomized_value
`uvm_info("SEQ",$sformatf("Randm
value=%0d",regmodel.temp_reg_inst.temp.value),UVM_NONE)
end
endtask
endclass