Modelling mismatch effects in CMOS translinear loops and

current mode multipliers

Mirko Gravati∗, Maurizio Valle ∗
Abstract − MOS translinear circuits can be effectively phase, the linearity and accuracy of circuit topologies
employed in systems and applications demanding very on the basis of device matching.
low power consumption and low operating frequency In Section 2, the weak inversion region mismatch
ranges (i.e. few kHzs) e.g. in bioelectronics and model for translinear loops is introduced. In Section
neuroengineering. Nevertheless weak inversion 3, the model is extended to the four quadrant current
mismatch modelling for design applications is still
mode Gilbert multiplier and the results of the
lacking. In this paper we present a mismatch model for
MOS translinear loops and current mode multipliers experimental validation are reported. Moreover, an
which accounts for non linearity and accuracy. The example of a statistical analysis for the evaluation of
model has been experimentally validated and the results the output current accuracy due to device matching is
are reported. We report also an example of the shown. The conclusions are drawn in Section 4.
application of the model to the statistical accuracy
analysis of the MOS current mode Gilbert multiplier in
the circuit design phase.
2 MODELLING MISMATCH EFFECTS IN
MOS TRANSLINEAR LOOPS
1 INTRODUCTION To model mismatch effects in CMOS translinear
loops, we refer to the following expression of the
In modern integrated circuits the need of very low channel current in a MOS transistor biased in weak
power consumption (and usually also of low supply inversion [5]:
voltage) has moved the region of operation of devices
VGS −VTH
to the weak inversion region. Besides low power
nφ t
 V
− DS 
consumption, in weak inversion the gm/IDS value (i.e. I DS = I DC ⋅ e 1 − e φ t  (1)
the efficiency of the transistor) at a given bias current  
is the maximum available. On the other hand, the
frequency performances are limited. Nevertheless where IDC is a current term, VTH is the threshold
bioelectronics and neuroengineering systems exhibit voltage, n is the weak inversion slope factor. The
specifications which match the performances mismatch causes random variations of the values of
achievable with circuits operating in the weak IDC and VTH [6]. With reference to Eq. (1) and to a
inversion region of MOS transistors. In this generic transistor i of a translinear loop, we can
perspective, a promising circuit implementation −
VDSi
approach is based on the translinear principle [1]. φt
define: δ i = δ (VDS ) = 1 − e as a generic error
Analog current mode four – quadrant multipliers i

which exploit the translinear principle have been
presented in the literature and they exhibit very
interesting performances (see, among others, [2]).
One of the major limiting factors of weak inversion
biased translinear circuits is the device matching [3].
Many papers dealing with the modeling of mismatch
in MOS devices, even in the weak inversion region,
term whose value depends on the drain to source
voltage value.
If, due to mismatch between devices, the terms IDC
and VTH experience variations (i.e. errors) of ∆IDC
and ∆VTH respectively from their nominal/typical
values, then we can write for a generic device i:
VGSi −VTH ∆VTH i

( )
have been presented (see, among others, [4]). −
nφ t nφ t
Unfortunately, silicon foundries characterize their I DSi = 1 + ∆I DCi I DC ⋅ e ⋅e δi (2)
technology usually only in strong inversion and then
mismatch models are often of limited applicability in Please note that in Eq. (2), the term ∆IDC represents
the weak inversion region. a percentage variation with respect of the nominal
The goal of our work is to develop a mismatch model value; on the other hand ∆VTH represents an absolute
for MOS translinear circuits e.g. translinear loops and variation.
current mode multipliers (i.e. the Gilbert multiplier). In other words:
The model is meant to evaluate, during the design

∗
Department of Electronic and Biophysical Engineering, University of Genova, Italy, e-mail: mirko.gravati@accent.it,
valle@dibe.unige.it, tel.: +39 010 3532775, fax: +39 010 3532096.
I DC _ real = (1 + ∆I DC ) I DC , VTH _ real = VTH + ∆VTH non linearity term γ from the statistical features of the
terms ∆IDC and ∆ VTH. We have derived the statistical
Let us take into account the (basic) translinear loop features of γ through a Monte Carlo simulation. The
shown in Fig. 1. By applying the Kirchhoff voltage terms ∆IDC and ∆VTH can be modelled as stochastic
law, we obtain: variables with Gaussian distribution and average
VGS1 − VGS 2 + VGS 3 − VGS 4 = 0 (3) value equal to zero. The values of their variance can
be computed on the basis of the sizes of the
IDS1 IDS2 I DS3 IDS4 transistors of the translinear loop [7]:
Aβ2 AV2TH
M1 M2 M3 M4 σ 2
∆I DC = , σ 2
∆VTH = where Aβ2 and A2VTH
2WL 2WL
are technological parameters. In the technology that
we used (AMI Semiconductor CMOS 0.35µm), their
Figure 1: Generic (alternate) translinear loop. values are: Aβ2=6 [%2 µm2 ] and A2 VTH = 130 [mV2
µm2].
From Eq. (2) and (3) one can obtain: Usually the term ∆IDC is neglected in the weak
∆VTH 1 ∆VTH 3 ∆VTH 2 ∆VTH 4
nφt nφt nφt nφt inversion region of operation (please remember that
I DS1 e I DS3 e I DS2 e I DS4 e
⋅ = ⋅ in a MOS translinear loop, all transistors work in the
(1 + ∆I )δ (1 + ∆I )δ (1 + ∆I )δ (1 + ∆I )δ
DC1 1 DC3 3 DC 2 2 DC4 4 weak inversion region of operation): in fact the value
of ∆IDC is usually much smaller than the one of ∆ VTH.
where we have approximated n to the value of one.
This is the reason why only the ∆VTH is used to model
In the previous equation, we introduce a “non the effect of the spread of MOS transistor parameters
linearity” factor γ which takes into account the in the weak inversion region [8], [9].
effects of mismatch between the devices of the Through a Monte Carlo analysis we found that γ
translinear loop. Then we can write: has mean value equal to one and variance given by:
I DS 1 ⋅ I DS 3 = γ I DS 2 ⋅ I DS 4 σ γ2 = 0.68 . The histogram of γ, as result of the
Monte Carlo analysis, is shown in Figure 2 (the
where the term γ is defined as follows: number of simulations is 106). The histogram is an

γ=
(1 + ∆I )(1 + ∆I ) δ δ
DC1 DC3 1 3
e
−
∆VTH1 + ∆VTH 3 − ∆VTH 2 − ∆VTH 4
nφt (4)
estimation of the probability density function of γ.
(1 + ∆I )(1 + ∆I ) δ δ
DC 2 DC 4 2 4
5
Frequency percentage occurcence

The non linearity factor γ is given, besides by the

spread of the technological parameters ∆IDC and 3

∆VTH, by the bias point value through the terms 2

VDS 1
−
φt
δ i = 1− e . In the following we will consider all
1

terms δi equal to 1. The error given by this 0

-1 0 1 2 3 4 5

approximation is fairly low: in fact if, let say, VDS is γ

equal to only 100 mV, the error is in the order of

magnitude of about 0.05%. Following the previous Figure 2: Histogram of γ. On the x-axis the value of γ is
considerations, the non linearity term γ depends on reported, on the y-axis the percentage frequency of
occurrence is reported.
the spread of technological (and geometric) variables
which induce variation on the terms IDC e VTH. Please
note that the non linearity term γ depends on the
3 MODELLING MISMATCH EFFECTS IN
topology of the circuit too.
THE MOS CURRENT MODE GILBERT
MULTIPLIER
2.1 Statistical analysis of the non linearity term
γ To demonstrate our model in a real circuit
implementation we refer to the four quadrant MOS
Statistical features of the non linearity term γ are not Gilbert multiplier reported in [2]. The input and
a priori known. Due to the complexity of the output signals are differential and balanced current
expression (4), it is not straightforward to mode signals:
mathematically derive the statistical properties of the
 IB , − I γ2 become very relevant thus increasing the overall
I X+ = (1 + x) I X = (1 − x ) B
2 2 non linear behaviour of the multiplier.
I I We can further express the output current as
IW+ = (1 + w) B , IW = (1 − w) B
−
follows:
2
2
where x and w are the information carrying
+
I OUT = I OUT −
− I OUT [
= 1 − nγ 1 ,γ 2 ( x ) − n'γ 1 ,γ 2 ( x) w I B ]
variables (please note that -1 ≤ x ≤+1, -1 ≤w ≤+1)
where nγ 1,γ 2 ( x) and n'γ 1,γ 2 ( x) are non linear
and IB is a bias (reference) current. The output
variable can be expressed as: functions of the x input variable and depend on the
+ −
IOUT = IOUT − I OUT = xwI B spread of the technological parameters through the
The circuit is based on two translinear loops as non linearity terms γ1 and γ2:
shown in Figure 3. To each translinear loop, we apply (1 − x ) (1 + x )
the model introduced in Section 2: nγ 1,γ 2 ( x) = +
2 + (1/ γ 1 − 1)(1 + x ) 2 + (γ 1γ 2 − 1)(1 − x )
I X+ I M 9 = γ 1I M 6 I X− nγ′ 1 ,γ 2 ( x ) =
(1 − x ) −
(1 + x )
translinear loop 1 2 + (1 / γ 1 − 1)(1 + x ) 2 + (γ 1γ 2 − 1)(1 − x )
It is then worth noting that the output current is a
I M 6 I M 8 = γ 2 I M 7 I M 9 translinear loop 2 non linear function of the x input and a linear
function of the w one; in other words, the non linear
IOUT - IOUT +
behaviour of the circuit only depends on the x input
IX+ I X- (see Section 3.1). Please note that in case of ideal
M6 M9 matching γ1 = γ2 =1. Then: nγ 1,γ 2 ( x) = 1 ,
M5 M7 M8 M10
n'γ 1,γ 2 ( x) = − x and the output current is exactly
2
1 equal to the product of the two inputs i.e.:
I OUT = xwI B .
IW + IW -
3.1 Experimental validation of the model
Figure 3: Basic circuit topology of the Gilbert multiplier We performed an experimental validation of the
reported in [2]. The two translinear loops are highlighted.
model on the basis of the measurements on a test
chip. In Figure 4, the model (line) and the
Following Section 2, the non linearity terms γ1 and
measurements (symbols) are shown (w is the input
γ2 can be expressed as: and x the parameter).

γ1 =
(1 + ∆I DC5 )(1 + ∆I DC9 ) ⋅e −
∆VTH 5 +∆VTH 9 −∆VTH 6 −∆VTH 10
nφt 300

(1 + ∆I DC6 )(1 + ∆I DC10 ) 200

γ2 =
(1 + ∆I DC5 )(1 + ∆I DC8 ) ⋅e −
∆VTH 5 +∆VTH 8 −∆VTH 7 −∆VTH 10
nφt
100
x = -1
x = -0.6

(1 + ∆I )(1 + ∆I )
I_out [nA]

0
x = -0.3
x = +0.3
DC7 DC10 x = +0.6
-100
x = +1
After some mathematical derivations, the differential
-200
multiplier output current, when taking into account
the translinear loop transistor mismatch effect, can be -300

expressed as: -300 -200 -100 0 100 200 300

I_w [nA]

2 I X− IW+ 2 I X+ IW− (5)

I OUT = IW+ + IW− − − Figure 4: Comparison between the measured and computed
I B + (1 / γ 1 − 1)I X I B + (γ 1γ 2 − 1)I X−
+
output current values.
Please note that the two translinear loops are not
independent on each other; in fact transistors M6 and In Figure 5, the model (line) and the measurements
M9 belong both translinear loops. This fact causes (symbols) are shown for a test chip (x is the input and
the presence of the term γ1γ2 whose value can be w the parameter).
greater than the values of γ1 and γ2 (if γ1 > 1, γ2 > 1).
From Eq. (5), one can note that, when I+X or I-X
increases, the effect of the non linearity terms γ1 and
 300
200
100
I_out [nA]
0 w = -0.3
-100
-200
-300
-300 -200 -100 0
I_x [nA]
100
Figure 5: Comparison between the measured and computed
output current values.
The percentage error is below 4%. The measured
values of γ1 and γ2 vary between 0.55 and 1.62. The
maximum percentage error in all measurements is
below 6%. Please note that the translinear loop has
been implemented using simply only interdigitized
structures: this account for the fairly high values of γ1
and γ2.
3.2 Statistical accuracy analysis of the Gilbert
multiplier
The model of the mismatch effects in translinear
loops applied to an analog current mode multiplier,
can be used during the design phase to statistically
evaluate mismatch effects. In fact, on the basis of the
statistical analysis of the non linearity terms (see
Section 2) related to translinear loops, and following
the mathematical expression developed in Section 3,
it is possible to perform a Monte Carlo simulation
which gives as output the statistical distribution (i.e.
estimated probability density function) of the output
current due to mismatch effects. The result of such
analysis is shown in Figure 6 for the Gilbert
multiplier of Section 3. Please note that the average
of the output current is the ideal expected value (i.e.
the current value with zero mismatch): in Figure 6
the variance of the output current is reported as
function of the two inputs x and w. The behaviour is
due obviously by the technology spread but, what is
more, once fixed the technology, it depends on the
topology of the circuit and on the size of the devices
as shown in the analysis reported in Section 3.
Figure 6: Variance of the output current of the multiplier of
Section 3.
4 CONCLUSIONS
In this paper a mismatch model for MOS translinear
w = -1 loops and current mode multipliers is reported. The
w =-0.6
model has been experimentally validated and an
w = +0.3
w = +0.6 example of the application of the model to the
w = +1
statistical accuracy analysis of the MOS current mode
Gilbert multiplier is reported. Future work will
concern also a more accurate modelling of the γ
200 300
statistics.
Acknowledgments
The authors wish to thank Prof. Andrea Trucco for
the fruitful discussions.
References
[1] C. Toumazou, et al. “Analogue IC Design: the
current mode approach” IEE Circuits and
Systems.
[2] F. Diotalevi, M. Valle, An analog CMOS four
quadrant current-mode multiplier for low power
artificial neural networks implementation, 15th
European Conference on Circuit Theory and
Design, ECCTD’01, 2001, pp. III – 325 – III 328
156 (ISBN: 951 – 22 – 5572 – 3).
[3] A.G. Andreou and K.A. Boahen,
“Translinear Circuits in Subthreshold MOS,”
Journal of Analog Integrated Circuits and Signal
Processing, Vol. 9, pp. 141-166, March 1996.
[4] Drennan and McAndrew, Understanding
MOSFET Mismatch for Analog Design, IEEE
JSSC 38(3):450-456, March 2003.
[5] Y. Tsividis, Mixed Analog-Digital VLSI Devices
and Technology, Mc Graw Hill, 1996.
[6] B. Razavi, Design of Analog Integrated Circuits,
Mc Graw Hill, 2001.
[7] M. J. M. Pelgrom, et al., “Matching properties of
MOS transistor,” IEEE J. Solid-State Circuits,
vol. 24, pp. 1433–1439, Oct. 1989.
[8] A. Pavasonic, et al., “Chacterization of
subthreshold MOS mismatch in transistor for
VLSI systems,” Analog Integr. Circuits Signal
Process., vol. 6, no. 6, pp. 75–85, 1994.
[9] A.Graupner, et. al., Statistical Analysis of Parallel
Analog Structures, in Proc. of Workshop on
System Design Automation - SDA 2000, March
13th-14th, 2000, Rathen, Germany.