MeN DATA SHEET For a complete data sheet, please also download: + The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The ICO6 74HC/HCT/HCU/HCMOS Logic Package Information + The ICO6 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT138 3-to-8 line decoder/demultiplexer; inverting Product specification September 1993 File under Integrated Circuits, ICO6 Philips Semiconductors PHILIPSPhilips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting T4HC/HCT138 FEATURES + Demuitiplexing capability + Multiple input enable for easy expansion + Ideal for memory chip select decoding + Active LOW mutually exclusive outputs + Output capability: standard + loc eategory: MSI GENERAL DESCRIPTION ‘The 74HCIHCT 138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (USTTL). They are specified in compliance with JEDEC standard no, 7A, QUICK REFERENCE DATA GND = OV, Tare = 25°C: t= th= 6 ns The T4HCIHCT138 decoders accept three binary \weighted address inputs (Ao, A, Aa) and when enabled provide 8 mutually exclusive active LOW outputs (Yo to Yo) ‘The "138" features three enable inputs: two active LOW , and, and one active HIGH (E,). Every output willbe HIGH unless E; and Ep are LOW and HIGH. This multiple enable function allows easy parallel expansion of the "138" to a 1-of-32 (5 lines to 32 lines) decoder with just four "138" ICs and one inverter. ‘The "138" can be used as an eight outout demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. ‘The "138" is identical to the "238" but has inverting outputs. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT He HCT propagation delay CL = 15 pF: Voc = 5V tera! teu, Y, 12 7 ns teva! tou 14 19 ns C, input capacitance 35 35 pF Coo) power dissipation capacitance per package | notes 1 and 2 67 a7 pF Notes 1. Crp is used to determine the dynamic power dissipation (Pp in «W): Po = Cro » Veo? +E (Ci Voc? - fo) where: {= input frequency in MHZ {= output frequency in MHz TC. - Voc? - f.) = sum of outputs C. = output load capacitance in pF Voc = supply voltage in V 2. For HC the conaition is Vi = GND to Voc For HCT the condition is V, = GND to Voc - 1.5 ORDERING INFORMATION See “74HC/HCTIHCUHCMOS Logie Package Information September 1993Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting T4HC/HCT138 PIN DESCRIPTION PINNO. SYMBOL NAME AND FUNCTION 123 AytoAy ‘adaress inputs 45 E;, Ee ‘enable inputs (active LOW) 6 E: enable input (active HIGH) 8 GND ground (0 V) 18,14, 13,12,11,10,.8.7 | ¥ot0Ye outputs (active LOW) 16 Veo positive supply voltage af TO fax 1 “a fave 2 =D fa 5g [ai¥, eg] fae so [a yo fal? ‘ oo fav : Fig.1. Pin configuration. Fig.2 Logic symbol Fig.3. IEC logic symbol Fig.4. Functional diagram September 1993Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting T4HC/HCT138 FUNCTION TABLE INPUTS OUTPUTS: EB] Ee | | Ao | Ar | Ae | Yo | M% | Ye | Ys | Y% | Ys | Ye | Hix i[xi{xi{xifxiParfaflafre{]aAfala]a x |u| x] x] x} x} a] aw] a] wa] a] aA] wR] xtxite} x} xt x} a} w |e] aw] aw | aw] a U uy H v L cy eofyH{rfafa]afayea L ee L Lo} oH tL} aH] H | aH] a] RY A L Lo} oH Lo] oH cL} uw tL} Hw] H | H] RH L cL} ala] # cL} al] wH | # ce} al] Hw] wR] a L Lo} oH L Ly} aH] aH} a} a] aw] ep a] | a L Lc} uw tc} aH] Hw | H}] Rl] aH] aA Lo} oR] L Lo} oH tL} wu] H | aH] w]e] aA] a] a Lo} oH L c}alHei{ se} a} ae]| we} wei? H i] aH] afk L Notes IGH voltage level L = LOW voltage level X =don't care Fig.5 Logie diagram. September 1993 4Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 DC CHARACTERISTICS FOR 74HC. For the DC characteristics see “74HC/HCT/HCU/HCMOS Logie Family Specifications” Output capability: standard lec category: MSI AC CHARACTERISTICS FOR 74HC GND = OV, =t;= 6s; C= 60 pF Tams (°C) TEST CONDITIONS TaHC SYMBOL | PARAMETER UNIT | yg | WAVEFORMS +25 40 to +85 | -40 to +125 wy min. [ typ. | max. | min. | max. | min. | max. vopagation de a | 150 180 225 20 teal to | gration delay 1s |30 2 4 |ns (45 |Fins tee 12_|26 33 38 60 vopagation de a7_| 150 180 225 20 teva! ton | PeePasation delay 17/30 8 45 |ns [45 |Fig6 20% 14 [26 33 38 60 a7_| 150 180 225 20 feral tous | PeePagation delay 17 |30 38 45 |ns [45 |Fig7 10 Yo 14 [26 33 38 60 18/75 5 110 20 tral tray | puUBMtanstion 7 \15 19 22 |ns [45 | Figs 6and7 6 | 18 ‘9 60 September 1993 5Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logie Family Specifications” Output capability: standard lec category: MSI Note to HCT types ‘The value of additional quiescent supply current (Acc) for 2 unit load of 1 is given in the family specications. To determine Alec per input, multiply this value by the unit load coefficient shown in the table below. INPUT _[UNITLOAD COEFFICIENT Ay 150 E, 1.25 Es 1.00 AC CHARACTERISTICS FOR 74HCT GND = OV, t= t= 81s; CL = 50 pF Tam (°C) TEST CONDITIONS TaHCT ‘SYMBOL | PARAMETER: UNIT | Vg | WAVEFORMS: 5 4010-26 | -s010 105 Vee rain: yp-[ max | min.[ max. [min | max. tea tus | Pgmagaion dey | Tay a5 “ so [ns (45 [Fes propagation delay coal ous [PER 12 [a0 0 co [as 45 [Fes teat [PgPRBBHON AY | Tag Lag 0 co [a5 [For os | eubutrnstion . ; traf tH | ime 7 18 19 2 1S 45 | Figs 6 and7 September 1993 6Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 ‘AC WAVEFORMS DV = GND to Vo 30. M=GNDWS¥, Fig.6 Waveforms showing the address input (A) and enable input (E;) to output (¥,) propagation delays and the output transition times. DV = GND to Vo 3¥.M= GNDS¥, Fig.7 Waveforms showing the enable input (E,) to output (¥,) propagation delays and the output transition times PACKAGE OUTLINES. See ‘74HC/HCTHCU/HCMOS Logic Package Outlines” September 1993 7