a ‘TN TRODUCTIONS is Drei kien 2 |] 0 ¢ 2 6 ic KGa eat An A On LUNA Int Tha Tp ul a DLA OW. om poniunin (ie LOnitled a 1 Has _O. tines syn g 7 s B Tt frobudin Phase ommponunta (CRE alin a | Balers « Signalsi = Comnittigl : er bot f ie Conpsendd Wut tas what ordi Shoulel be — tha_pasts should —bt— —| computer Architecture Computer Organization | | | | |. Computer arch is concerned with the structure and behaviour of a computer system as seen by the user, Tt acts as the interface between hardware and software. Computer Architecture helps us to understand the functionalities of a system A\ programmer can view architecture in terms of instructions, addressing modes _ ond registers { While designing a computer system architecture is considered first. \ Computer Architecture with high-level design issues. deals optimization) Computer org is concerned with the __ way hardware components are connected together to form a| computer system Tt deals with the components of a connection in a system. Computer Organization tells us how exactly all the units in the system ‘are arranged and interconnected. Whereas Organization expresses the realization of architecture. ‘An organization is done on the basis of architecture. Computer Organization deals with | low-level design issues. I || Architecture involves Logic Organization involves Physical } (Zhstruction sets, Addressing Components (Circuit design, Adders, | modes, Data types, Cache _ Signals, Peripherals) . The Central Processing Unit (CPU) contains an arithmetic and | 4 of The Input-Output devices connected to the computer include the keyboard, mouse, | manipulating data, a number of registers for storing data, and a control circuit for fetching and executing instructions. : The memory unit of a digital computer contains storage for instructions and data. The Random Access Memory (RAM) for real-time processing of the data. The Input-Output devices for generating inputs from the user and displaying the final results to the user, terminals, magnetic disk drives, and other communication devices. i = iifIn this method all the requesting components are attached se, Involves three control signals assigned as BUS request , BUS GRANT end BUG BUSY. All the bus units are connected to the bus BUS REQUEST line. When actwated,| 't indicates that one or more devices are requesting to controller responds to a BUS REQUEST only if BUS BUSY is inactive. When the bus control is given to the requesting device, it enables its physical connection ond activates the BUS BUSY. When the Th thas @ sigh bus Abita perio Hoe ig. Obbitedi tion... requesting device gets control of the bus and receives BUS s further propagation of the signals, activates BUS BUSY and ~ 8 ice receives BUS GRANT signal, it forwards the signal to request bus access, the device that is closer to the and receives the bus control, 1ed to the bus controller are of higher priority than er can odd more devices anywhere along the chain, up toa certain maximum - Pilting Method aePAGENO.—__7 owe The system connections for polling method are shown in figure above —— + This method replaces the BUS GRANT line of Daisy chain method with a set of poll ines that ane connected directly to all devices on the BUS. count ‘Similar 10 daisy chain method, devices request access to the bus via a common BUS REQUEST line, In response to a signal on BUS REQUEST.bus controller generates a = sequence of numbers on the poll count lines. Each device compares these numbers as their device address already assigned to them, when a requesting device finds that its address matches the number on the poll count lines, the device activates BUS BUSY. The bus controller responds by terminating the polling process and the device = connects to the bus ~ . Adyantages - =~. This method does not favor any particular device and processor. ~— . The method is also quite simple. ~— , Tf one device fails then entire system will not stop workings failure of a device does -_ not affect other devices, —sThe priority of a device is determined by the position of “sequence. This sequence can be programmed if the po programmble register 5 address in the polling es are connected to a ~~ Disadvantages ~ Number of devices that can share the bus is limited by the addressing capability of |} the poll lines, nod, there are separate BUS REQUEST and BUS GRANT lines for every — at are sharing the bus. In this approach, the bus controller has the capability — ‘e identifying all the requesting devices. The bus controller responds quest by determining the highest priority device that has sent ‘the bus request. This priority is programmable and is predetermined. The priority decider 0 the bus controller selects the desired request. L ‘Advantages - « This method generates fast response. ‘s Due to separate BUS REQUEST and BUS GRANT lines, the arbitration is fast. U L Disadvantages - } + Hardware cost is high as large no. of control lines are required, | ing n devicesin__ 5 approximately a Due to independent requesting, there are 2n control lines for cont contrast.daisy chaining requires two such lines, while polling requires log2n lines.PAGENO. R gests ome apa —_ ee PEN symbol Nurs Function us bits S| fo. See i = be 16 | Holds memory operand the i = ° eee a 12 ess for th 18 a = AR jememory - : : AC 16 ene 2 t £6, [oure | [ner] IR 16 Hol mn, code. ee —— ia Holds address of the instruction | ae Regist Transp targuage (i) tGnaf _trtkauetowns 4 | thot ow bei : |_ePu. The nd asie computer: sso L |.PAGE NO. owe 9 —L 1 _ || I The symbolic notation used to describe the micro-operation transfers amongst registers is called Register transfer language. ansfer means the availability of hardware logic The term register tr rm a stated micro-operation and transfer the result of circuits that can perfor the operation to the same or another register. yrammers who apply this term to The word language is borrowed from prog language is a procedure for writing ning languages. This programming program ify a given computational process. symbols to speci Following are some commonly used registers: 1. Accumulator: This is the most common register, used to store data taken out from the memory. 2, General Purpose Registers: This is used to store data intermediate ~ results during program execution. Tt can be accessed via assembly programming. |3. Special Purpose Registers: Users do not access these registers These registers are for Computer system, _ MAR: Memory Address Register are those registers that holds the ‘address for memory unit. MBR: Memory Buffer Register stores instruction and data received from the memory and sent from the memory. m Counter points to the next instruction to be executed = PG: Prograt .e instruction to be executed. IR: Instruction Register holds th registers Ina computer system, data transfer takes place between processor \s. These and memory and between processor registers and input-output system data transfer can be represented by standard notations given below:oy ee ae Pat Had each... Sebi tb bun kK 4 =a) Sa Or xem= 4 ; Mux 2 kKxJ 2 4X1 aod ts Sy oe Ate —§ log, = 4. |} Nerina nett << $$$ | 2 Goninoe copa) Fira 2 tegeak o TT —___“ dogecap 4. _ = tk n= Bick Bus — | 4) No. & Reeder 2 | a) oiat mo. 4 3 State Buln = a. z X | So gent Linas lage7 Bus Line for Bit Select = Enable —| 2x4 Decoder = fe] ‘The outputs generated by the four buffers are connected to form a single bus line. Only one buffer can be in active state at a given point of time. The control inputs to the buffers determine which of the four normal inputs will communicate with the bus line » A2* 4 decoder ensures that no more than one control input is active at ny given point of time. ns. Memory Transfer ‘ost of the standard notations used for specifying operations on memory transfer are fated below. © Thus, a read operation can be stated as: Write: M [AR] — Ri » The Write statement causes a transfer of information from register RI into the The transfer of information from a memory unit to the user end is called a Read operation. The transfer of new information to be stored in the memory is called ‘a Write operation. ‘A memory word is designated by the letter M. We must specify the address of memory word while writing the memory transfer operations. The address register is designated by AR and the data register by DR. DR MAR} The Read statement causes a transfer of information into the data register (DR) from the memory word (M) selected by the address register (AR), ‘And the corresponding write operation can be stated as: memory word (M) selected by address register (AR). in) Memory Unit l Data Out pata in Read Write 24 eAPAGE HO,-" ao Lina Shige Right Ce’) a . iss Lt tush [| kee | 4 O cho 5h Ae i | Decrement itt A= A=, ———— 2 ee Ans 3. = OO.) aeet ereLe ne Bik Biro ee eee ee Blimp Pees. c A a a Sea tt 4 Sushatlon A Si, eh aes anes peer aes Ginrenas fe F a: Bit Bibany mina A Varin 2 Ash nae _B> Bb; B @: Bo Gun Fads) eis 3 W ts es fn re | ‘a fi ¥ A 4 a Fa LFA aa. ah = ee, i Feat Hh B-O, O@4=7e° (=a we A-1, 104 = 08 i= = —eoe 3, adds one to it, and gener s3. The output carry CA will be 1 only after incrementing binary tt Note: The 4-bit binary incrementer circuit can be extended to an n-bit —+ binary incrementer by extending the circuit to include n hal + least significant bit must have one input connected to logi «| inputs receive the number to be incremented or the carry ft Fe stage. aTruth. Table oF gh —3i8.2o.! Boolean. fune __|l00@0 — fo 2 Gin” Sei i coogi. fi 3% 0 ORO Ese _ AF aie Fu Tafa se: 2 Ope a Ee REE OR + hey. Fe AVA OR, fe ary)’ _FWhen the abbreviated address is used ie TIR(RI] (Del: Content of x) large physical memory Li = canbe addressed with a relatively small soot ~ number of bits = Slow to acquire an operand because of an ~_ additional memory access =SEA = M[IR(address)] i ‘ent or Autodecrement Mode aA he register is used to access memory coeeel | When the address in tl - When the addre: L—>| gool_{ 70] _ “nthe register is incremented or decremented Py 7 EA~ Fou! a U automatically 1 900) - ____ Address specified in the instruction aregister ~ Shorter address than the memory pairs - Saving address field in the instruction - Faster to acquire an operand than the memory addressing -EA=IR(R) (IR(R): Register field of IR): tia a 4 5 [Sepa Chek aterien! Of ta potinn 4 rt Av AC =BR. than L Hee ae mm " n ell, (i - On Uns) Je : aS tt 4 ae | | Nace Ac-ap | all AC>AC+ BR (= ace ert | ~_[ Sep iigaane AC , Onuene lone fate tb Ac bo 2 HSE Of Ont, Ond lsh S Lipts Resurount St byl ¥ . ae — than goto Stepi fepp dinal senulk A i avilable in (ign. past) tok Cn (doe ra 9 ta pA HpieRe Olt SRB — -@R = 190) cen. __ ire carnplermant of 8h = BRT — aig Be old Ox a eee Onn On $e. » | a 0 al Be Se aa ao 7 oer 3, Es —_ - iO ilies a Wie 10.07 SIV eee Mn no a E +, | aS a ee 5 5 b Psbor “H00"10 ol ey Ga Chick-Qn Bnei — 41m dio 1 ae ex | __4_4 —th ot 5 ee ~ oy oshriie 1.1.0 p70 | h @) tha 04 1440 o409 1 Ona 4 Bi _ ee ye eens = isn — in nai \ Ar GR ia lq Atzncepe 0.104 0400. -. ® Tahal dol 4 ee f = fi LAC BBR aA) gol __ —}y gab 1040 101 0e cane ae “pls Eh a/ too! oll = = fp} - — © due) AO op oR ‘= nea o | hoy oidpe OO eg RO ca a ©| thuk > Sc20 i Naw Solution. =f al f- Mu L>» pool 01014 —Eq > angina Bile ~S (8), Chek lion te bow Bez IS ) ~ Loh 1) = wo0 ; Lio OT ian 4) Ooh i QR~ 3 + an : Noa, Se > 0 Solution 9 11114 04044 Gestion AC GR Onan fy SC : Dts emo Groif)__() > Hosdecary fn Borree!S Mitton. Gl thek oot | bos 601 [py AC=arste [1010 [bdo | 104ae I a SSSi ay t | asa, dnl Sipl> tomuut dial to Biraty a 7 yy), Oe P(/259-1a5). = (lovilo10}|-+ ool) = i —— a.) x E [onl ate a1-2 (Leon nico!) 2, 62 : 37 si O- |y00 oot a | oan oma PP Ryo. fy d-166 Guu d:16. E. die |_B—bik agi ain Signed. aks | Qunols vs Pe > _(35)10 =aloo0 | (oe ee. Bie 52 uous Poink Nw. = aaing= f Add © 35) ondCal)in bit — ie (1), = 9001 LL Sign bit 2Né [iy = a Sig be = — — + 1S omplerunk >= 35 ~_L Oollloo (ke | LL opens 54, 4 sey (2) LOM TOO «am -35> VIO 1 m_ a 12 [ot soHtoto Hee} tba? 4He EE AQ <= Diisiclund = +ve ——___ AO, - +e , AQ~ st Ve 1B ee eas Dithed:dhedd, be atank 10 bia = ALIA Dibtoo. = 5 be __ hue ee SaaS ae -6> Olll) 2 = oll apooco = Durdind = Ag = Lomo | > Miao. = b —, oo ‘Old10__ colo. Ce, _bke miteol_to oe — ond Co. {the Quypul > Tin Gi + jt Pie = MeO BL ~ yy Groprgation. > fi Fal +} | Qing {inattn > Oy = A bi dana Se MOC Cie oy Pea, Cat m= bit CLA 7 hae 4 B= 4 bit CLA ene ie eee Oe ; FE Th_atmoue the cluppurdensis Git on cial i ect on Lalo Ai, leer a ae > Gy + bal Go ea Cy * Gy + ma Pole Gay (G2 +hGM) Cox, = Got oC C3 = G24 (= [Gi+ PB (Go+u te 0 , for dora, |e" G 2 ee fu ad for pruating Gade Jaen. a é. oe iB bea +) The & Outputs o the diaoder an Cleatgnatiol 7 bu ae by Ni — D>. Bie iu Gpprid to Yu Conk io ae Sequence Wuntix tar Co i aes ee 0 dhroug'. tS Th Sulbts % Count dueodut indo IO EmiuAg Sigrale Te threcgln The Sequinee county, SC can be toetuenuthid oo Cherred eee Mott of Hae tire 5 Hae countix y newmuntiact to i Hae Aegis. of font signals Gut of YX16 durcdin . Oren ie all oH count. 4 cleared to 9 tauiog th next _timoy i tp be lo. + Pacun aa Le dining Uignata Bb, T., LT ond Ty i PRE Eaplain bald comficl wg” Cl _fiming, diagrason«he te reaionship ofthe contra siznals the postive transition of the ing angram figure shows lock, + SC is incremented with every posi procedures the sequence of — A basic compu tions that «particular ‘on the basis of the1 Memory «reference instruction shacks fr D3 address as an operand, =e fe struction bq = oso 40 N10 (het ini) Memory reference instructi Brae 15 18 wa 0 F241, j —- ies 4 {Opcode = 000 through 110) Fmemory is used to speci Example ~ IR register contains = 0001 ie CMA after fetch and decode cycle ws lement accumulator. it isa register reference ins Hence, AC—~AC 3 These instru za oe Saas ttifenseeo persion) I+4 employed under certain circumstances, as for ‘an instruction code specify a variety of ven addres. for choosing operands from fied by computer instruc 8. Operands ‘memory address. Operands re are executed on some data stored in er of k bits that defines one of 2" registers in the 16 processor registers RO through RIS will have a register is shown below, together withADD RI, A, B RI = MIA] + MIB] ‘ADD R2, C, D R2— M{C] + M{D] ¢ MOLX, RILR2 M[X] = RI *R2 he computer has two processor registers, RI and R2. The symbol ‘operand al memory address symbolized by A. it results in short programs when 00 many bits to nost common in commercial computers. Here a a processor register or a memory word. \ddress field can specify p io to evaluate X = (A +B) * (C + D) is as follows: MOV Ri, A Ri—MIA] ADD K (8) MOV R2,C R2—MIC] | ADD R2,D R2—R2+M{D] MOL Ri, R2 RI RI*R2 MOV X,RI MIX] — RI BRI RI + )*(C + Dp is + LOADA AC=MIAI + ADDB AC—AC+M V M{T] — AC + LOAD ¢ AC=M + ADD D AC AC+M{[D] + sTol ‘Lero-Address Instructions + A stack-organized computer docs pot use an adress field forthe instructions ADD ed an adress field to specify wing program shows how X fora stack organized computer. (TOS stands for * (C+ D) will be v top of stack.) f Instruction Cycle. A program residing in the memory unit of a computer consists of a structions are executed by the processor by going ———— ‘An instruction cycle. also known as fetch-decode- — sequence of instructions, These through a cycle for eact PUSH A TOS — 4 PUSH B TOs —B. ADD TOS — (A+B) PUSH C TOS —¢ PUSH D TOS —D ADD TOS (C+D) MOL TOS —(C+D)"(A +B) POP X MIX] — Tos Biven to this an address field in the computational ‘execute cycle is the basic operational process of a computer. This process is repeated ‘continuously by CPU from boot up to shut dawn of computer Instruction Cycle = In a basic computer, each instruction cycle consists of the fol Fetch instruction from memory. Decode the instruction. Read the effective address from memory. Execute the instruction,Hion Code An instruction code 4 specific operation. uct the computer to Hrs racking frat” [Le Ansty bo / Uertronies S0thak f ir Rondlorn. Acerss [of ndlureable Storage. [o) stemirol Mimo, — SRontoal Munson, iH ERAT PAGE. DaTE rangeably but, they arereused sometimes interchangeably but, they are — ea It supports shorter control word.a SS tend 1 ea, Ce Contal Lo Sir¢ YoY > Athabat Mune = HK eta. = Bobi si AG x “ea = tah b) Re Uti _ = a es = = Gt ae a faa = lon sng? GX aay] e_ “4 oh) ie Lotyfabubieal Cu pshish ae peal ee Se COntiina 64 eo the Si a nib Sas es % - ke ing = ee 5 = Rie at tebe ~ || Condibon : thot a ie= eae a 2 7B Bhanek Gnd ® Aagstes ay : ee Ey NABER.5 PAGENO, Stored program Organization (Fig 5.1) DATE py zak | aA| Sto ) [AR Pe] ® i + ae i j Vy IRS MOAR), Pee HL ae ze [REM [Rey] S Execute a ft, dhe uc n« When a ud oo Ans. The way flowchart sh iandled by the computer can be explained by means of the © An interrupt flip-flop R is included in the computer. R=, the computer got * IFTEN is 1, control checks the flag bits.IEN = 1, flip-flop instruction cycle ther flag is the va of andi eqs t,t ees fl LE PAGE No. ore ice program in memory starting and R is cleared to 0. from memory is in causes the yommunication Input - Output Terminal Interface Receiver ations jutput configuration for a basic computer. Computer registers & Flip Flopsae WAP_4o asda = ¥ — Sete as rockt) GG +H Ke STok eh Tes pare k| or Coad b fe Se 3 Hep That fdas Easel it | Mule a einciMEere | P| NSEC ESS EEE ee ce ee fa oe EYE , | 8ue Rr A,B = Meal - Mee) ~ | @mure ic ee Mu R.,D, 6 & <— Mon) > MCE | Gree dN T ho Ac + HLT _§ | St, Ro, fo F Res fo — ented |_ SvoREesh —_MrileAc Co Res< Miprt f Pt | puse, Ree Roe 2x rol hl aap Rk Re Ry + Ry ace Act Ry <= MCHI1e MC] | MUL Ra, H, kK pi fey Rae G Ro = Ra + Moo 7 t ——|_ Div X& 1k, aba MExl <= R, /R2 STORE Tr mir, - Miv Ra, 8 Rie Mini a | Mur Ro, © Ro < brfaink Ro + — ostiee Notatow > AR = = & +1 ue fk ,F ae (pe een Es us A, Toe>A j Mul &,c Ra = 22% MOC a! Sue Top > : fae ee pa(A-f) $$Sao eS all = aa ee eg Se To, > (DE Quan e a a lop =e a ae | | a cee x (2 e8)-P)) 5 = (CA=6) +(Ca (Dae) | Purh G = Tsp 2 { oe ea ee ee ea ea a Wisk pe Sy po —} eas Trp (G+ (419) r —}—hw —____‘Tebs ((A-8)+(0 (R36) P| Seer SA > | eo By es S-E,8&, TEN, GT (£6 x input and outpu Ko7 ht a Eaem =oPage No. eee ce consider ak” segmer mt to take *k’ cye completed in the pi a k=n=leycles =(k=n-1)Tp In the same case. for a non-pi of Non-pipelined processor As the performance of a process When the number of tasks Sn’ are significant! S=ntk/n S=k ly larger than k, that is, n> =n speed up / Max sped up = § / Sou Ime 1o complete the instructions lve oF an ideal Parallel processing can be described as a class ‘of techniques which enables the system to mrs data-processing tasks to increase the computational speed ot Computer system, Out simultaneous data-processing to achieve f le an instruction is bein, 18 Processed in the ALU component can be read from memory, computer processing caps t can be accomplished during a ving a multiplicity of fun ions simultaneously. The data ean be dst is indicated in each block ifthe diagram: ier performs the arithmetic operation with integer Point operations are separated into thre eiruits operating in parallel an be performed concurrently on different 30 one number can be shifted while —+ Integer Multiply. | acef Tp 2 k+ =) TF k:5 ' = (5 + (to0-1)\ 4O. H SEA IEO ns = dom n ' spas e { =e = Ee donna — Tp = [K+ (m-)IT beats te 7 — ns) | Spee up Baki 5 ees 4 ——|__Mag™ Shed up = k= 6 . Te eS $ — ee st = | = Bays fe Ne i ee | __ Ting > [00 ne — E = a nna 5o Th Bee Trop, Tp» 2 = S57] 22 |Top 2 kT = 50%1 X 100 > Somms 1 Tp =[k+(n-/)]T = [5+(50-) Ido - (idem = 1080 4 {| OL ok | gy a | S =. Tnp = 1" oD = U.¢s & Tsp = tak T 1080. Bi z (Ox¥(x §O = 9a na— Tp =[K + Goan eee nace—tis Wire —> Date f 6 Page No ed 13 1 en, ¥ WL Vili Ly Joo. ford he on te «|e > f __Ta_ 2 fk Ga) | Tp sheets. eee Sesh) = a ee —ni(n my Webi wt Bie (n=1) tek = Gxt + 4( aco -1) + = Dos F So, alo = having. Fae = tl = Orme Stace tire di aq CPL feild vl are used as per the system requirement. The | chip interconnection ina 128* 8 RAM chip.° ‘must be | and 0 forthe unitto operate, ~=——1y impedance sate, Thef Jn table specifies the operations of a 128 * 8 RAM chip, — cS1 €S2 RD WR | Memoryfunction | State of data bus lain Memory which is directly 1} is accessed by CPU 0) a0 Inhibit High-impedance 0 1 x x Inhibit High-impedance High-impedance Input data to RAM its capable 's applied. That means this type of memor ache Memory. Output data to RAM ‘memories are used to build C a x Inhibit High-impedance ie capacitors tend to lose over a peri their usage. The main memory is [aT] 1 ‘its similar to D T Constructed 0 4, Cons that lea! ‘ip-flops. contents as lang 3s powe! —|2.Reav 3.Expensive | The prin Sf the ive. memory may be constructed | me te dato. 4, Slows. than SRAM. 4 IM memory is used for keeping program: Scan not store many bits per chip. Faster than DRAM. 5, Can store many bits per chip. 6.Uses more power 6. Uses less power, F7,Generates more heat, tes less heat. 7.Gene! Used (or main memory: 8, Used for cacheschip — I Dab bus DO. FDO rene! td aaee RD we wae ee a zmory location. ich is represented by the MAR from memory data register (MDR) will smiory address register (MAR). a Uieddsos 04 2.5.65 r | Rams Oo00-W04F ~O O Ox xx | gam 9 O0%-mFF -O 0 f xxx Lad hat > Diov-17e -O | Ox xx Ron Oiso-OlFe 1-0, | | Xxx | fom cavo-osre [1] x X x xx| i isties are : ‘The major characterist : : ‘This memory-is accessed simultaneously and in parallel on the basis of| data content rather than by specific address or location. ‘This memory is capable of finding an empty unused location to store | the word. This memory is uniquely suited to do parallel searches by data} association. = oo Each cell must have storage capability as well as logic circuits for matching its content with an external argument. S.No.| Spatial locality Temporal locality Temporal locality refers to the tendency fora processor to access || memory locations that have been used recently. 1. | Spatial locality refers to the tendency of execution to involve a number of memory locations that are clustered. The spatial locality means | ‘The temporal locality means that II that instructions stored near- | a recently executed instruction by to the recently executed | islikely tobe executed again very || instructions are also likely to | soon. be executed soon, 3. | The spatial aspect suggests | The temporal aspect of the that instead of bringing just | locality reference suggests that | ei one item from the main| whenever information of | memory to the cache, it is | instruction and data is first wise to bring several items | needed, this information should | that reside at adjacent | be brought into cache where it | addresses as well. will hopefully remain until it is needed again, | — or related storage locations are frequently accessed, depending on the memory ‘ access pattern. __ | Example: "1 Take the example of an operating system. Ideally, we would like an . unlimited amount of main memory, instantly accessible. In practice, we have a limited amount of main memory, and because it is cheaper, a very large amount of secondary memory. However the trade-off is that secondary memory tends to be several orders of magnitude slower than primary memory. We can approach the ideal by keeping the more often used data in main memory, and everything else in secondary memory. Because of the principle of Locality of Reference, we can be sure that most memory references will be to locations already stored in main memory, thereby improving efficiency and providing a flat memory | f a small-sized type of volatile computer memory that peed data access to a processor and stores frequently used computer programs, applications and data. 1 2. Itstores and retai s data only until a computer is powered up. ~|8. Cache memory provides faster data storage and access by storing an instance of programs and data routinely accessed by the processor. [> ‘Thus, when a processor requests data that already has an instance in a model. F the cache memory, it does not need to go to the main memory or the This scheme is used in modern operating systems and is called virtual nagar Preiate memory. Virtual memory gives users the appearance of unlimited primary memory by transparently u 5. Cache memor primary ¢ Re eacdeenes can be primary or secondary cache memory, where a 4 is directly integrated or closest to the processor. |—| 6. In addition to hardware-based cache, ¢ cache, where a reserved frequently accessed che memory also can be a disk |_—_ Portion on a disk stores and provide access to applications from the diskrearrelzany nen (0 aimdry Lit xabio { Hit Ratio = Hit = Ne op Hits Het + Mian Tete Oncenrer pores ; 7 7a4 9s \ teas \ at fee (leek | i from memor: ess is used to c. ield of CPU address is compared with the as: he word read froi 512 x 12 0256 at 234s 34 52 te 4 2009 Cache memory Address = 9 bits Data = 12 bits Cache memory Index Tag __ Data {000 | 00 | 5670 777 | 00 | 7523 | 000 | 01 | 1256 01777 5azt by Heat Has tnt. Tanke Go onecache location can have m cache and the mori id 2-way set ass Cache memory @ Index Tag ooo [02 00 666 01 000 01 666 isadvantage of this technique is that it generates fic and may create a bottleneck. Write back: a, Itis another technique which minim: b. c s memory writes. With write back, updates are made only in the cache. When an update occurs, an UPDATE bit associated with the slot is set. Then, when a block is replaced it is written back to main memory ifand only ifthe UPDATE bit is set. A) The problem vocth wre bade to trot Pine of rman memory orn irwalia ord bine, Otezcaes EG (ora baal ont eiaaa i. Cache Memory, in any of thi lethe Main Memory addre: itch gives the Set No of Main Slemory lemory whose Block 0 is pre ifed Set no. is compared with the two Tags. y oF th ‘The CPU to work at its maximum efficiency, the data transfer from the other hardware must be as fast as its speed. The purpose of a cache is t ensure this smooth and fast transition of data to the CPU. As CPU speed increased to the point where the RAM is no longer able to transferring of information again become a serious problem. | h was effectively a small and extremely | fast memory, was added to the proces: from the RAM. Since the cache ru can rapidly provid any delay. r to store immediate instruction. at the same speed of the CPU, it tion to the CPU at the shortest time withoutry, reads and writes are done using bank in turn, resulting in higher memory shputs due to reduced waiting for memory banks to become ready for desired operations p bits of the addr is) and higher order m bits mory bank that is selected | tions are s cache memory increase the accessing speed of CPU, Cache memory is exactly a ‘memory unit wi size of cache vemory is less than the virtual other hand hardware ‘manages the eache memory Jk of data in the memory and I utilization of the memory system as is a memory management capability of an OS that s hardware and ow a computer to compensate for physical memory shortages by t Random Access Memory (RAM) to disk storage, Virtual address space is increased using active memory in RAM and inactive memory in Hard Disk Drives (HDDs) to form contiguous addresses that hold both the application and its data, A system using virtual memory can load larger programs or multiple programs running at the same time, allowing each one to operate as if it has infinite memory and without having to purchase more RAM. Virtual memory is a facility that allows program to address memory from local point of view, without regard to the amount of main memory: ‘A virtual memory system provides a mechanism for translating program generated addre: to correct main memory locations: This is done dynamically, while programs are being executed im the! CPU, ory block nee siemory blocks are occupied, one ahth gee) jught in while all tk as block replacy nt. snows m has to be replaced. This is known The replacement algorithms 1, Optimal replacemen: In this policy, replace ae Place the block which is no longer needed in the re given as follows : Ifall blocks curre 'e memory will be used again, replace s tly in each u E nemory W d 'e one which will not be used in the future for the longest time. ‘The optimal r¢ optimal replacement is obviously simply because when a block wi i Boke pecause when a block willbe needed in the future is usually