Central Processing Unit | |__~ This model executes only |_one single instruction ey ! at one time, but _sperates only o a a | Few pieces of date Fetched /read from memery Von Neumann architecture Von Neumann bot tle neck b Separation of memory and CPU L Interconnect determing, rate which instructions ond data are accessible Process Entities | Executsble machine language proaram 2. Memory blocks (executable code, disks, nelwork interface cards) 3 Resource descriptors by the OS (file descriptor) 4. Steutiy occess ond levels (information on accessible hardware + software resources) 5: Process stole information (ready /biocked ete)Von Neumann models modification I Caching = Collection of memory lscations = Allows CPU te access more quickly then in main memory 2 Virtual Memory 7 To resolve the size limitation in caching = Main _memarg con act as cache for secondary storage = Creates more contiguous and lorger addresable memery space for applications & The Mechanism 1+ Address Space L Programs running ° computer has own virlual address space L Divides them into pages [in smaller units) L Can be larger than octual physical RAM 2- Page Table L Maps virtual address to LEnables system to find data / instruction that program needs eorres ponding physical addresses in RAM / disk 3- Page Swapping © Occurs when L Swaps data between RAM ond disk drive program tries to access date not in RAM. Advantages: I) Efficient Memory Usage 2) Implement isolation 3) Simplified Memory Monagement3. Instruction level parallelism \+ Pipelining ~ Tasks overlapping between each other L Divides inshruchion to stages and allows mulli instructions $o be processed ot same ne L Each inshruction advances through stages in sequence 2- Mal tiple issue Simultaneously execute different instructions in a program © Runs multi instruction simultaneously in a single clock cycle L Minimizes dependencies » but requires more complex hardware Pipelining ewample: Instruction Pipelining in CPU (Stoge by Stage) Si - Instruction Fetch (iF) S1.- Instruction Decsde (10) S3- Execute (Ex) S4- Memory Access (MEM) SS- Write- Back (WB) Lv Malliple Tnsbruction: Superscalar Prscesing 1 Add RL R2, RF 2 Multiply R4, RS, Re 3. Subtmct RT, R3, RI 4 Division RIO, Ril, RI2 # Assume there are 2 mulbi issue processors, A) and A2: A [A T Me R+R | Ras Rs xRe Th Ry ~Ra-by | Po = Ru Qa